WO2018126914A1 - Procédé et dispositif de codage de code de contrôle de parité à faible densité quasi-cyclique, et support de stockage - Google Patents

Procédé et dispositif de codage de code de contrôle de parité à faible densité quasi-cyclique, et support de stockage Download PDF

Info

Publication number
WO2018126914A1
WO2018126914A1 PCT/CN2017/118105 CN2017118105W WO2018126914A1 WO 2018126914 A1 WO2018126914 A1 WO 2018126914A1 CN 2017118105 W CN2017118105 W CN 2017118105W WO 2018126914 A1 WO2018126914 A1 WO 2018126914A1
Authority
WO
WIPO (PCT)
Prior art keywords
matrix
kbset
nset
template
row
Prior art date
Application number
PCT/CN2017/118105
Other languages
English (en)
Chinese (zh)
Inventor
许进
徐俊
李立广
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201710449155.7A external-priority patent/CN108288968A/zh
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2018126914A1 publication Critical patent/WO2018126914A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Definitions

  • the present application relates to the field of communications, and in particular, to a coding method and apparatus, and a storage medium for a quasi-cyclic low-density parity check code.
  • the transmitting end of the digital communication system usually includes a source, a source encoder, a channel coder and a modulator
  • the receiving end usually includes a demodulator, a channel decoder, a source decoder and a sink.
  • the channel coder is used to introduce information bits into the information bits according to certain rules so that the receiving channel decoder can correct the errors occurring when the information is transmitted on the channel to some extent.
  • FEC Forward Error Correction
  • the commonly used FEC codes include a Turbo code, a Low Density Check Code (LDPC), a polarization code, a convolutional code, etc.; for example, in a Long-Term Evolution (LTE) system.
  • LDPC Low Density Check Code
  • LTE Long-Term Evolution
  • Turbo codes are used for data transmission; LDPC codes and convolutional codes are used in IEEE 802.11 systems.
  • the LDPC code is a linear block code based on the sparse check matrix. It is the sparsity of its check matrix that can realize the high-throughput and low-complexity codec, which makes the LDPC code practical.
  • LDPC codes have many decoding algorithms. Among them, Message Passing algorithm or Belief Propagation Algorithm (BP) is the mainstream and basic algorithm of LDPC codes. Currently, there are many improved effective decoding. algorithm.
  • the graphical representation of the LDPC parity check matrix is a bipartite graph.
  • An M*N parity check matrix H defines a constraint that each codeword having N bits satisfies M parity sets.
  • a bipartite graph includes N variable nodes and M parity nodes.
  • the bipartite graph there is no connection between any nodes of the same class, and the total number of edges in the bipartite graph is equal to the number of non-zero elements in the check matrix.
  • the parity check matrix H of this LDPC code be a (M ⁇ z) ⁇ (N ⁇ z) matrix, which is composed of M ⁇ N block matrices, each of which is a basic permutation of z ⁇ z.
  • the basic permutation matrix is a unit matrix
  • they are cyclic shifting matrices of the unit array (the default is right shift), so the structured LDPC code is also called quasi-cyclic LDPC code.
  • a block matrix is an all-zero matrix
  • the matrix is generally represented by -1, and if the cyclic shift s of the unit array is obtained, Equal to s, so all A basic check matrix Hb can be constructed.
  • z is the dimension indicating the standard permutation matrix, where z is called the spreading factor.
  • the structured LDPC code can be uniquely determined by the basic check matrix Hb and the spreading factor z.
  • the base check matrix Hb (2 rows and 4 columns) is as follows, and the expansion factor z is equal to 4:
  • the LDPC code can use hierarchical decoding, that is, a partial parallel decoding method.
  • the parity check matrix as described above has 8 rows, indicating that there are 8 parity check codes.
  • each parity check matrix needs to be decoded separately, if all 8 parity check codes are updated, For an iteration.
  • a basic matrix is used for each different spreading factor LDPC code, then for each different code length, the LDPC code codec needs to store a basic matrix, and when the code length is large, it is stored.
  • the parity check matrix H can be obtained, so that the generated codec can be applied to a case where the code length is variable.
  • the correction is to correct the non-negative value elements in the basic matrix Hb by using the spreading factors of different code lengths, and the corrected element value should be smaller than the expansion factor value under the code length.
  • correction algorithms For example, mod, scale+floor, or scale+round can be used.
  • P ij be the non-negative of the i-th row and j-th column of the basic matrix H b . 1 element, P ij ' is corrected
  • the non-negative 1 element of the i-th row and j-th column has:
  • z is the expansion factor corresponding to the current code length, that is, the number of rows or columns of the block square matrix
  • z max is the expansion factor corresponding to the maximum supported code length, or the maximum expansion factor.
  • Mod is the modulo operation
  • [ ⁇ ] is the next rounding operation
  • Round is the rounding operation.
  • the use of structured LDPC codes also has some problems in supporting flexible code lengths.
  • This method is called Shorten the code code. It can be seen that the number of padding bits for information bit sequences of different lengths is also different. When the number of bits is too large, the performance of shortening code coding will deteriorate. That is, the structured LDPC coding in the related art has a problem that the coding performance deteriorates when the length of the bit sequence to be coded continuously changes.
  • An embodiment of the present application provides a coding method and apparatus for a quasi-cyclic low-density parity check code, and a storage medium, to at least solve the problem that the coding performance of the bit sequence to be encoded is continuously changed when the length of the bit sequence to be coded is changed by using the structured LDPC code in the related art. problem.
  • a coding method of a quasi-cyclic low-density parity check code comprising: determining a spreading factor z, and a basic check matrix Hb; using the determined z and the Hb to be encoded
  • the kbset ⁇ 9,10,
  • k1 is the length of the bit sequence I to be encoded
  • the spreading factor z n*2i
  • n is a positive integer greater than 1
  • i is a non-negative integer less than 10
  • the n is determined from the second set nset.
  • a 2 j , where j is a positive integer.
  • the first function f 1 is expressed as: Where mod(x,y) represents x to y for remainder operations, and [ ⁇ ] means takes integer operations, including rounding up, rounding down, or rounding rounding.
  • the first function f 1 is expressed as: Among them, [ ⁇ ] means taking integer operations, including rounding up, rounding down, or rounding rounding.
  • the second function f 2 is expressed as: Where mod(x, y) represents x to y for remainder operations, and [ ⁇ ] means takes integer operations, including rounding up, rounding down, or rounding rounding.
  • an apparatus for encoding a quasi-cyclic low-density parity check code comprising: a determining module configured to determine a spreading factor z, and a basic check matrix Hb; and an encoding module configured to utilize Determining the z and the Hb to perform low density parity check code LDPC encoding on the encoded bit sequence I; wherein the Hb includes a block A corresponding to a mb row kb2 column of system bits and an mb corresponding to a parity bit
  • the kbset ⁇ 9,10,
  • a modifying unit configured to modify the non-negative element s in the Hb by: for a preset threshold a, when z ⁇ a, adopting the first function f1 Correcting the s in the Hb; when 0 ⁇ z ⁇ a, correcting the s in the Hb by using a
  • a storage medium is also provided.
  • the storage medium is arranged to store program code for performing the above steps.
  • the low-density parity check code LDPC encoding is performed according to the determined spreading factor z and the basic check matrix Hb, the bit sequence I to be encoded, the length of the bit sequence to be encoded using the structured LDPC encoding can be solved continuously.
  • the problem of poor coding performance at the time of change achieves the effect of improving the performance of LDPC coding.
  • FIG. 1 is a block diagram showing the hardware structure of a mobile terminal for encoding a quasi-cyclic low-density parity check code according to an embodiment of the present application
  • FIG. 2 is a flowchart of a method for encoding a quasi-cyclic low density parity check code according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of a basic parity check matrix Hb used for encoding in the specific embodiment
  • FIG. 4 is a structural block diagram of an apparatus for encoding a quasi-cyclic low-density parity check code according to an embodiment of the present application
  • FIG. 5 is a structural block diagram (1) of an encoding module 44 of an encoding apparatus for a quasi-cyclic low-density parity check code according to an embodiment of the present application;
  • FIG. 6 is a structural block diagram (2) of an encoding module 44 of an encoding apparatus for a quasi-cyclic low-density parity check code according to an embodiment of the present application.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG. 1 is a hardware structural block diagram of a mobile terminal of a quasi-cyclic low-density parity check code encoding method according to an embodiment of the present application.
  • mobile terminal 10 may include one or more (only one shown in FIG. 1) processor 102 (processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA.
  • FIG. 1 is merely illustrative and does not limit the structure of the above electronic device.
  • the mobile terminal 10 may also include more or fewer components than those shown in FIG. 1, or have a different configuration than that shown in FIG.
  • the memory 104 can be used to store software programs and modules of application software, such as program instructions/modules corresponding to the encoding method of the quasi-cyclic low-density parity check code in the embodiment of the present application, and the processor 102 runs the software stored in the memory 104. Programs and modules to perform various functional applications and data processing, that is, to implement the above methods.
  • Memory 104 may include high speed random access memory, and may also include non-volatile memory such as one or more magnetic storage devices, flash memory, or other non-volatile solid state memory.
  • memory 104 may further include memory remotely located relative to processor 102, which may be connected to mobile terminal 10 over a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • Transmission device 106 is for receiving or transmitting data via a network.
  • the network embodiment described above may include a wireless network provided by a communication provider of the mobile terminal 10.
  • the transmission device 106 includes a Network Interface Controller (NIC) that can be connected to other network devices through a base station to communicate with the Internet.
  • the transmission device 106 can be a Radio Frequency (RF) module for communicating with the Internet wirelessly.
  • NIC Network Interface Controller
  • RF Radio Frequency
  • FIG. 2 is a flowchart of a method for encoding a quasi-cyclic low density parity check code according to an embodiment of the present application. As shown in FIG. 2, the process includes the following steps. :
  • Step S202 determining an expansion factor z, and a basic check matrix Hb;
  • Step S204 performing low-density parity check code LDPC encoding on the to-be-coded bit sequence I using the determined z and the Hb; wherein the Hb includes a block A corresponding to a mb row kb2 column of system bits and a parity bit corresponding to the parity bit.
  • the low-density parity check code LDPC encoding is performed according to the determined spreading factor z and the basic check matrix Hb; the bit sequence I to be encoded, the length of the bit sequence to be encoded using the structured LDPC encoding can be solved continuously.
  • the problem of poor coding performance at the time of change achieves the effect of improving the performance of LDPC coding.
  • the execution body of the foregoing steps may be a terminal (which may be an encoder or the like), but is not limited thereto.
  • the above-described z and the above-described Hb determining the kb column are subjected to the above LDPC encoding.
  • k1 is the length of the bit sequence I to be encoded
  • the spreading factor z n*2i
  • n is a positive integer greater than 1
  • i is a non-negative integer less than 10
  • the n is determined from the second set nset.
  • a 2 j , where j is a positive integer.
  • the first function f 1 is expressed as: Where mod(x, y) represents x to y for remainder operations, and [ ⁇ ] means takes integer operations, including rounding up, rounding down, or rounding rounding.
  • the first function f 1 is expressed as: Among them, [ ⁇ ] means taking integer operations, including rounding up, rounding down, or rounding rounding.
  • the second function f 2 is expressed as: Where mod(x, y) represents x to y for remainder operations, and [ ⁇ ] means takes integer operations, including rounding up, rounding down, or rounding rounding.
  • the template matrix HBG of the basic matrix Hb is the same as the first template matrix H1BG:
  • the second template matrix has the same number of rows and columns as the first template matrix
  • the second template matrix is a template matrix as follows:
  • the first sub-matrix H1BGsub1 of the first template matrix is identical to the first sub-matrix H2BGsub1 of the second template matrix, wherein the first sub-matrix is a sub-matrix composed of the first four rows.
  • the a plurality of "0" elements in the sub-matrix H2'BGsubj of the adjusted second template matrix are a "1" elements at corresponding positions in the sub-matrix H2BGsubj before adjustment; wherein a is a positive integer.
  • the b "1" elements in the sub-matrix H2'BGsubj of the adjusted second template matrix are b "0"s at corresponding positions in the sub-matrix H2BGsubj before adjustment. Element; where b is a positive integer.
  • the set_b' of the positions of the b 1 elements in the jth submatrix H2'BGsubj of the adjusted second template matrix is the position of the 3 0 elements in the second template matrix before the adjustment (row_q, Col_q) is a subset of the set set_b; wherein the position set set_b of the three 0 elements in the second template matrix before adjustment is: ⁇ (25, 0), (21, 0), (38, 6) ⁇ ;
  • row_q and col_q represent the row index and the column index of the 0 element in the second template matrix before the adjustment.
  • b 1, or 2, or 3.
  • the g rows in the matrix consisting of the pre-kb2+w columns of the j-th sub-matrix H2'BGsubi of the adjusted second template matrix are before the j-submatrix H2BGsubi before the adjustment.
  • the 31st row in the matrix consisting of the first 14 columns of the adjusted second template matrix is the 32nd row of the second template matrix before the adjustment; the matrix of the first 14 columns of the adjusted second template matrix is The 32rd line is the 31st line of the second template matrix before the adjustment.
  • the 33rd row in the matrix consisting of the first 14 columns of the adjusted second template matrix is the 34th row in the matrix consisting of the first 14 columns of the second template matrix before the adjustment; the adjusted second template
  • the 34th line in the matrix consisting of the first 14 columns of the matrix is the 33rd line in the matrix consisting of the first 14 columns of the second template matrix before the adjustment.
  • the specific embodiment provides a method for encoding a quasi-cyclic low-density parity check code of a low-density parity check code, which specifically includes the following steps:
  • Kb takes a value in the set kbset; when the length k1 of the bit sequence I to be encoded is smaller than the size kcb of the coding block, at least kcb-k1 known bits need to be added to the coded bit sequence, and the sequence is LDPC-encoded;
  • the ratio of kcb-k1 known bits to the coding block is smaller than a preset threshold T, that is, (kcb - k1) / kcb ⁇ T; wherein, in one embodiment, the threshold T is a positive number not exceeding 0.1.
  • the value set kbset of kb is ⁇ 8, 9, 10, 11, 12 ⁇
  • the set of values n of n is ⁇ 2, 3, 4, 5, 6 ⁇ ; or, kbset is ⁇ 12 , 13, 14, 15, 16 ⁇ , and nset is ⁇ 2, 3, 4, 5 ⁇ ; or, kbset is ⁇ 8, 9, 10, 11, 12, 13, 14, 15, 16 ⁇ , and nset is ⁇ 2,3,4 ⁇ .
  • the low density parity check code encoding for the coded bit sequence I includes:
  • performing low density parity check code encoding on the coded bit sequence I further includes:
  • the remaining columns are used as the columns of the new basic check matrix, and the coded bit sequence is encoded by the new basic check matrix to obtain the LDPC code.
  • the output bit sequence of the device After deleting the kb2-kb column from the preset basic check matrix, the remaining columns are used as the columns of the new basic check matrix, and the coded bit sequence is encoded by the new basic check matrix to obtain the LDPC code.
  • the p2 known bits in the output bit sequence are deleted to obtain an encoded bit sequence.
  • the bit sequence I to be encoded can be encoded using the kb column therein; the shortened number of system columns kb is taken in the set kbset.
  • kbset can be ⁇ 8,9,10,11,12 ⁇ .
  • the length of the bit sequence input to the encoder is some discrete value.
  • these discrete values are referred to as the coding block size kcb.
  • T may be a positive number not greater than 0.1, and may of course be other values, such as T being a positive number not greater than 0.2, and T being a positive number not greater than 0.15.
  • the set kcbset of kcb may be ⁇ 32 36 40 44 48 54 60 64 66 72 80 88 90 96 100 108 110 120 128 132 144 160 176 180 192 200 216 220 240 256 264 288 320 352 360 384 400 432 440 480 512 528 576 640 704 720 768 800 864 880 960 1024 1056 1152 1280 1408 1440 1536 1600 1728 1760 1920 2048 2112 2304 2560 2816 2880 3072 3200 3456 3520 3840 4096 4224 4608 5120 5632 5760 6144 6400 6912 7040 7680 8448 9216 ⁇ , of which 86 Elements.
  • the difference between the solution of the specific embodiment and the solution of the specific embodiment 2 is that the basic check matrix used in the coding in this embodiment is different from that of the specific embodiment 2.
  • the bit sequence I to be encoded can be encoded using the kb column therein; the shortened number of system columns kb is taken in the set kbset, and in this embodiment the kbset can be ⁇ 12, 13 , 14, 15, 16 ⁇ .
  • the value set nset of another parameter n of the expansion factor z can be ⁇ 2, 3, 4, 5 ⁇ .
  • the first function f 1 can be expressed as:
  • the second function f 2 can be expressed as: Where mod(x, y) represents the remainder operation of x versus y, which means taking integer operations, including rounding up, rounding down, or rounding rounding;
  • the first function f 1 can be expressed as: Where [ ⁇ ] means taking integer operations, including rounding up, rounding down, or rounding rounding;
  • the values of kb and n can make the size of the coding block have a good granularity, so as to reduce the number of padding bits, and ensure that the length of the bit sequence to be encoded changes by 1 bit granularity, the padding bit can be controlled in one Within the lower proportion, so as to ensure that the length of the bit sequence to be encoded changes continuously, it also has better coding performance.
  • the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware, but in many cases, the former is A better implementation.
  • the technical solution of the present application which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium (such as ROM/RAM, disk,
  • the optical disc includes a number of instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the methods described in various embodiments of the present application.
  • an apparatus for encoding a quasi-cyclic low-density parity check code is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and has not been described again.
  • the term "module” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • FIG. 4 is a structural block diagram of an apparatus for encoding a quasi-cyclic low-density parity check code according to an embodiment of the present application. As shown in FIG. 4, the apparatus includes: a determining module 42 and an encoding module 44. Description:
  • FIG. 5 is a structural block diagram (1) of an encoding module 44 of an encoding apparatus for a quasi-cyclic low-density parity check code according to an embodiment of the present application. As shown in FIG. 5, the encoding module 44 is shown in FIG. The method includes: a determining unit 52 and an encoding unit 54, and the encoding module 44 is described below:
  • k1 is the length of the bit sequence I to be encoded
  • the spreading factor z n*2i
  • n is a positive integer greater than 1
  • i is a non-negative integer less than 10
  • the n is determined from the second set nset.
  • FIG. 6 is a structural block diagram (2) of an encoding module 44 of an encoding apparatus for a quasi-cyclic low-density parity check code according to an embodiment of the present application. As shown in FIG. 6, the encoding module 44 is shown in FIG. Including: a correction unit 62, the encoding module 44 is described below:
  • a 2 j , where j is a positive integer.
  • the first function f 1 is expressed as: Where mod(x, y) represents x to y for remainder operations, and [ ⁇ ] means takes integer operations, including rounding up, rounding down, or rounding rounding.
  • the first function f 1 is expressed as: Among them, [ ⁇ ] means taking integer operations, including rounding up, rounding down, or rounding rounding.
  • the second function f 2 is expressed as: Where mod(x, y) represents x to y for remainder operations, and [ ⁇ ] means takes integer operations, including rounding up, rounding down, or rounding rounding.
  • a storage medium is also provided.
  • the storage medium is arranged to store program code for performing the above steps.
  • the above embodiment is applicable to a shortened structured LDPC, and the size of the expansion factor is reasonably determined by the shortening range of the system column kb.
  • the kb and n are reasonably determined.
  • the value can be such that the size of the coding block has a good granularity to reduce the number of padding bits, and the padding bit can be controlled at a lower ratio when the length of the bit sequence to be encoded changes by 1 bit granularity. Therefore, it is also ensured that the length of the bit sequence to be encoded continuously changes when it is continuously changed.
  • Increasing the LDPC code adapts to different application scenarios, different data types, etc., and can improve the decoding performance of the LDPC code while improving flexibility.
  • Embodiments of the present application also provide a storage medium.
  • the above storage medium may be arranged to store program code for performing the above steps.
  • the storage medium may include, but is not limited to, a USB flash drive, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, and a removable hard disk.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • mobile hard disk a hard disk
  • removable hard disk a variety of media that can store program code, such as a disk or an optical disk.
  • the processor executes the above steps in accordance with the program code already stored in the storage medium.
  • modules or steps of the present application can be implemented by a general computing device, which can be concentrated on a single computing device or distributed in a network composed of multiple computing devices.
  • they may be implemented by program code executable by the computing device, such that they may be stored in the storage device for execution by the computing device, and in some cases may be performed in a different order than that illustrated herein.
  • the application is not limited to any particular combination of hardware and software.
  • the low-density parity check code LDPC encoding is performed according to the determined spreading factor z and the basic check matrix Hb; the bit sequence I to be encoded, the length of the bit sequence to be encoded using the structured LDPC encoding can be solved continuously.
  • the problem of poor coding performance at the time of change achieves the effect of improving the performance of LDPC coding.

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

L'invention concerne un procédé et un dispositif de codage d'un code de contrôle de parité à faible densité quasi-cyclique, et un support de stockage. Le procédé consiste à : déterminer un facteur d'extension z et une matrice de contrôle de base Hb ; et utiliser les z et Hb déterminés pour effectuer un codage de contrôle de parité à faible densité (LDPC) sur une séquence de bits I à coder, Hb comprenant un bloc A ayant une taille de mb rangées et de kb2 colonnes et correspondant à des bits systématiques et un bloc B ayant une taille de mb rangées et de mb colonnes et correspondant à des bits de contrôle, kb2 ＝ nb - mb, kb2 étant un nombre entier supérieur ou égal à 4, chacun des éléments parmi mb et nb étant un nombre entier.
PCT/CN2017/118105 2017-01-09 2017-12-22 Procédé et dispositif de codage de code de contrôle de parité à faible densité quasi-cyclique, et support de stockage WO2018126914A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201710014296.6 2017-01-09
CN201710014296 2017-01-09
CN201710449155.7A CN108288968A (zh) 2017-01-09 2017-06-14 准循环低密度奇偶校验码的编码方法及装置
CN201710449155.7 2017-06-14

Publications (1)

Publication Number Publication Date
WO2018126914A1 true WO2018126914A1 (fr) 2018-07-12

Family

ID=62789091

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/118105 WO2018126914A1 (fr) 2017-01-09 2017-12-22 Procédé et dispositif de codage de code de contrôle de parité à faible densité quasi-cyclique, et support de stockage

Country Status (1)

Country Link
WO (1) WO2018126914A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113541698A (zh) * 2020-04-22 2021-10-22 华为技术有限公司 编码、译码方法、装置及设备

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101005334A (zh) * 2007-01-12 2007-07-25 中兴通讯股份有限公司 一种低密度奇偶校验码的混合自动请求重传包生成方法
CN101459430A (zh) * 2007-12-14 2009-06-17 中兴通讯股份有限公司 低密度生成矩阵码的编码方法
CN101534128A (zh) * 2009-04-27 2009-09-16 东南大学 低密度奇偶校验码校验矩阵的构造方法
CN101567697A (zh) * 2009-05-25 2009-10-28 普天信息技术研究院有限公司 一种速率兼容的低密度奇偶校验码编码方法和编码器
CN102412842A (zh) * 2010-09-25 2012-04-11 中兴通讯股份有限公司 一种低密度奇偶校验码的编码方法及装置
CN104868925A (zh) * 2014-02-21 2015-08-26 中兴通讯股份有限公司 结构化ldpc码的编码方法、译码方法、编码装置和译码装置
CN107370490A (zh) * 2016-05-13 2017-11-21 中兴通讯股份有限公司 结构化ldpc的编码、译码方法及装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101005334A (zh) * 2007-01-12 2007-07-25 中兴通讯股份有限公司 一种低密度奇偶校验码的混合自动请求重传包生成方法
CN101459430A (zh) * 2007-12-14 2009-06-17 中兴通讯股份有限公司 低密度生成矩阵码的编码方法
CN101534128A (zh) * 2009-04-27 2009-09-16 东南大学 低密度奇偶校验码校验矩阵的构造方法
CN101567697A (zh) * 2009-05-25 2009-10-28 普天信息技术研究院有限公司 一种速率兼容的低密度奇偶校验码编码方法和编码器
CN102412842A (zh) * 2010-09-25 2012-04-11 中兴通讯股份有限公司 一种低密度奇偶校验码的编码方法及装置
CN104868925A (zh) * 2014-02-21 2015-08-26 中兴通讯股份有限公司 结构化ldpc码的编码方法、译码方法、编码装置和译码装置
CN107370490A (zh) * 2016-05-13 2017-11-21 中兴通讯股份有限公司 结构化ldpc的编码、译码方法及装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113541698A (zh) * 2020-04-22 2021-10-22 华为技术有限公司 编码、译码方法、装置及设备
CN113541698B (zh) * 2020-04-22 2022-07-12 华为技术有限公司 编码、译码方法、装置及设备

Similar Documents

Publication Publication Date Title
JP7152394B2 (ja) Ｌｄｐｃコードを符号化および復号化するための方法および装置
US11095317B2 (en) Efficiently decodable QC-LDPC code
JP4602418B2 (ja) 検査行列生成方法、符号化方法、復号方法、通信装置、符号化器および復号器
CN106685586B (zh) 生成用于在信道中传输的低密度奇偶校验码的方法及设备
US9432052B2 (en) Puncture-aware low density parity check (LDPC) decoding
US7934146B2 (en) Method, apparatus and computer program product providing for data block encoding and decoding
WO2017194013A1 (fr) Procédé et dispositif de codage à correction d'erreurs
KR20210032007A (ko) 구조화된 ldpc의 부호화 및 복호화 방법 및 장치
CN108988869B (zh) 一种确定校验矩阵的方法及装置、计算机存储介质
KR102303379B1 (ko) 준-순환 저밀도 패리티 체크를 위한 설계 방법 및 장치
JPWO2008016117A1 (ja) 検査行列生成方法、符号化方法、通信装置、通信システムおよび符号化器
CN113612486B (zh) 一种构建pbrl ldpc码的基矩阵方法、系统、装置及存储介质
WO2015120719A1 (fr) Procédé et dispositif de traitement d'informations
WO2021063217A1 (fr) Procédé et appareil de décodage
JP4832447B2 (ja) チャネルコードを用いた復号化装置及び方法
CN112204888A (zh) 具有高效编码和良好误码平层特性的一类qc-ldpc码
JP5789014B2 (ja) 符号化方法、符号化器、復号器
WO2018126914A1 (fr) Procédé et dispositif de codage de code de contrôle de parité à faible densité quasi-cyclique, et support de stockage
WO2017214851A1 (fr) Procédé de transfert de signal, terminal émetteur et terminal récepteur
WO2018084732A1 (fr) Codes ldpc pour schémas de harq à redondance incrémentielle (ir-harq)
WO2018149304A1 (fr) Procédé et dispositif de traitement de données, appareil de traitement de données et support de stockage informatique
WO2024103386A1 (fr) Procédé de communication sur la base d'un code ldpc et appareil de communication
JP2009177649A (ja) 符号化方法、符号化器、復号器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17889619

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17889619

Country of ref document: EP

Kind code of ref document: A1