WO2022171019A1 - 一种编码和译码方法及相关装置 - Google Patents

一种编码和译码方法及相关装置 Download PDF

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WO2022171019A1
WO2022171019A1 PCT/CN2022/074851 CN2022074851W WO2022171019A1 WO 2022171019 A1 WO2022171019 A1 WO 2022171019A1 CN 2022074851 W CN2022074851 W CN 2022074851W WO 2022171019 A1 WO2022171019 A1 WO 2022171019A1
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sub
matrix
blocks
block
encoded
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PCT/CN2022/074851
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English (en)
French (fr)
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张华滋
童文
王俊
李榕
童佳杰
王献斌
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华为技术有限公司
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Priority to EP22752180.4A priority Critical patent/EP4277132A1/en
Publication of WO2022171019A1 publication Critical patent/WO2022171019A1/zh
Priority to US18/366,757 priority patent/US20230387939A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1174—Parity-check or generator matrices built from sub-matrices representing known block codes such as, e.g. Hamming codes, e.g. generalized LDPC codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes

Definitions

  • the present application relates to the field of wireless communication technologies, and in particular, to a coding and decoding method and a related apparatus.
  • communication devices such as terminal devices, base stations, etc.
  • polar codes being included in the 5th generation mobile networks (5G) standard for wireless communication
  • the current mainstream polar code decoding methods can be divided into two categories according to their decoding timing, namely polar code timing decoding and polar code non-sequential decoding.
  • the so-called polar code timing decoding means that the decoder performs bit-by-bit decoding according to the natural timing of polar design.
  • the non-sequential decoding of polar codes means that the decoder outputs decoding results in parallel according to other structures of polar codes (such as Taner graph, Trelis graph, etc.).
  • Non-sequential decoding of polar codes is the opposite, because multiple bits can be output at one time, and the decoding delay is small, but because it does not completely match the design of polar codes, it will bring a certain loss in decoding performance.
  • an encoding method is provided, and the method can be executed by a sending device, or a chip with similar functions of the sending device.
  • the sending device may be a terminal device or a network device.
  • the sending device can obtain the first vector to be encoded.
  • the sending device may perform first encoding on the first vector to be encoded to obtain a second vector to be encoded.
  • the sending device may encode the second vector to be encoded based on the first generator matrix to obtain an encoded codeword.
  • the first generator matrix may include at least N+1 sub-matrices a, and the N sub-matrices a may be located on the main diagonal of the first generator matrix.
  • the first generator matrix may be a block upper triangular matrix, or the first generator matrix may be a block lower triangular matrix.
  • the aforementioned sub-matrix a is a polar kernel matrix with a size of 2 m * 2 m , m is a natural number, and N is a natural number.
  • the transmitting device may transmit the encoded codeword.
  • the sending device can perform the first encoding on the first to-be-encoded vector, because any code block in the first to-be-encoded vector will be affected by the previous code block when performing the first encoding, and will also affect the next code
  • the first coding is performed on the block, so that there is coupling between multiple code blocks, and coding gain is obtained.
  • the first generator matrix encodes the second to-be-coded vector
  • the first generator matrix since the first generator matrix includes N+1 sub-matrices, and the N+1 sub-matrices are located on the diagonal of the first generator matrix, and the first The matrix block triangular matrix is generated, so it is equivalent to encoding multiple short codes, and then coupling multiple short codes to obtain an encoded codeword, which can reduce the encoding complexity and improve the encoding performance.
  • the elements of the upper triangle in the block upper triangular matrix can be a
  • the elements of the lower triangle can be 0, and the elements of the lower triangle in the lower triangle matrix of the block can be a
  • the elements of the upper triangle can be 0
  • a plurality of short codes can be coupled according to the positional relationship of the sub-matrix a in the first generator matrix.
  • the first generator matrix may include K first sub-blocks, and the K first sub-blocks may be located on the main diagonal of the first generator matrix, between adjacent first sub-blocks There is partial overlap, K is an integer greater than or equal to 2, and greater than or equal to N; each first sub-block is or
  • the first generator matrix may include K first sub-blocks located on the main diagonal of the first generator matrix, and the first sub-block has two matrices with different styles, so that the first generator matrix also has two different styles, so different short codes can be coupled.
  • the overlapping portion between adjacent first sub-blocks is a.
  • the size of the overlapping portion between adjacent first sub-blocks can be the size of the sub-matrix a, so that the coupling mode between the short codes is related to the polar kernel matrix, which can reduce the coding complexity.
  • the K first sub-blocks may contain N sub-matrices a, when the first sub-block is When , one sub-matrix a is located in the upper right corner of the first generator matrix.
  • the first generator matrix may include K first sub-blocks located on the main diagonal of the first generator matrix and a sub-matrix a located in the upper right corner, so that the first sub-block a in the second to-be-coded vector There is coupling between the code block and the last code block, which can further improve the coding performance.
  • the first generator matrix may include K first sub-blocks located on the main diagonal of the first generator matrix and a sub-matrix a located in the lower left corner, which can make the first sub-block a in the second to-be-coded vector There is coupling between the code block and the last code block, which can further improve the coding performance.
  • the sending device may determine the number of second sub-blocks included in the information bits to be encoded.
  • the sending device may determine the code rate of each second subblock included in the information bits to be encoded based on the total code rate of the codeword and the number of the second subblocks; wherein the code rate of each second subblock is different.
  • the transmitting device may determine the first vector to be encoded based on the code rate of each second sub-block.
  • the first vector to be encoded may include q second sub-blocks, where q is an integer greater than 0.
  • a decoding method is provided.
  • the method can be performed by a receiving device, or a chip with similar functions of the receiving device.
  • the receiving device can receive the codeword.
  • the codeword may be encoded based on the first generator matrix.
  • the first generator matrix may include at least N+1 sub-matrices a, wherein the N sub-matrices a may be located on the main diagonal of the first generator matrix, and the first generator matrix may be a block upper triangular matrix, or the first generator matrix
  • the matrix can be a block lower triangular matrix.
  • a is a polar code polar kernel matrix of size 2 m * 2 m
  • m is a natural number
  • N is a natural number.
  • the elements of the upper triangle in the block upper triangular matrix are all a, and the elements of the lower triangle in the block lower triangular matrix are all a.
  • the first generator matrix may include K first sub-blocks, and the K first sub-blocks may be located on the main diagonal of the first generator matrix, between adjacent first sub-blocks There is a partial overlap, and K is an integer greater than or equal to 2 and greater than or equal to N.
  • Each first subblock can be or
  • the overlapping portion between adjacent first sub-blocks may be a.
  • the K first sub-blocks may contain N sub-matrices a, when the first sub-block is , one sub-matrix a is located in the lower left corner of the first generator matrix.
  • a communication apparatus may include various modules/units for implementing the first aspect or any possible implementation manner of the first aspect, or may further include a communication device for implementing the second aspect or the second aspect.
  • Each module/unit in any possible implementation of the aspect. For example, processing units and input and output units.
  • the apparatus includes, when the first aspect or each module/unit in any possible implementation manner of the first aspect is executed, the processing unit, configured to obtain the first vector to be encoded; the processing unit, is also used to perform first encoding on the first vector to be encoded to obtain a second vector to be encoded; perform second encoding on the second vector to be encoded based on the first generator matrix to obtain an encoded codeword; wherein,
  • the first generator matrix includes at least N+1 sub-matrices a, wherein the N sub-matrices a are located on the main diagonal of the first generator matrix, and the first generator matrix is a block upper triangular matrix, or the first generator matrix
  • the generator matrix is a lower block triangular matrix, wherein a is a polar code polar kernel matrix with a size of 2 m * 2 m , m is a natural number and N is a natural number; the input and output unit is used for sending the encoded codeword.
  • the elements of the upper triangle in the block upper triangular matrix are all a, and the elements of the lower triangle in the block lower triangular matrix are all a.
  • the first generator matrix includes K first sub-blocks, the K first sub-blocks are located on the main diagonal of the first generator matrix, and adjacent first sub-blocks are located on the main diagonal of the first generator matrix. There is partial overlap between sub-blocks, and K is an integer greater than or equal to 2 and greater than or equal to N; each first sub-block is or
  • the overlapping portion between adjacent first sub-blocks is a.
  • the K first sub-blocks include N sub-matrices a, when the first sub-block is , one sub-matrix a is located in the upper right corner of the first generator matrix.
  • the K first sub-blocks include N sub-matrices a, when the first sub-block is , one sub-matrix a is located at the lower left corner of the first generator matrix.
  • the processing unit is further configured to determine the number of second sub-blocks included in the information bits to be encoded; based on the total code rate of the codeword and the number of the second sub-blocks, determine the number of the second sub-blocks. the code rate of each second sub-block included in the information bits to be encoded; wherein, the code rate of each second sub-block is different; the first to-be-coded vector is determined based on the code rate of each second sub-block; the The first vector to be encoded includes q second sub-blocks, where q is an integer greater than 0.
  • the input and output unit is configured to receive a codeword; the codeword is based on the first aspect. obtained by encoding a generator matrix; the processing unit is configured to decode the codeword according to the first generator matrix.
  • the first generator matrix includes at least N+1 sub-matrices a, wherein the N sub-matrices a are located on the main diagonal of the first generator matrix, and the first generator matrix is a block upper triangular matrix, or the The first generator matrix is a block lower triangular matrix, where a is a polar code polar kernel matrix of size 2 m * 2 m , m is a natural number and N is a natural number.
  • the elements of the upper triangle in the block upper triangular matrix are all a, and the elements of the lower triangle in the block lower triangular matrix are all a.
  • the first generator matrix includes K first sub-blocks, the K first sub-blocks are located on the main diagonal of the first generator matrix, and adjacent first sub-blocks are located on the main diagonal of the first generator matrix. There is partial overlap between sub-blocks, and K is an integer greater than or equal to 2 and greater than or equal to N; each first sub-block is or
  • the overlapping portion between adjacent first sub-blocks is a.
  • the K first sub-blocks include N sub-matrices a, when the first sub-block is , one sub-matrix a is located in the upper right corner of the first generator matrix.
  • the K first sub-blocks include N sub-matrices a, when the first sub-block is , one sub-matrix a is located at the lower left corner of the first generator matrix.
  • a communication apparatus in a fourth aspect, includes a processor and a transceiver.
  • the transceiver performs the transceiving steps of the method in the first aspect or any possible implementation manner of the first aspect, or performs the transceiving steps of the method in the second aspect or any possible implementation manner of the second aspect.
  • the processor uses the hardware resources in the controller to execute processing steps other than the sending and receiving steps of the method in the first aspect or any possible implementation manner of the first aspect, or execute the second aspect or any one of the second aspect. Processing steps other than the transceiving step of the method in one possible implementation.
  • the communication device further includes a memory.
  • the memory can be located inside the device, or it can be located outside the device and connected to the device.
  • the memory may be integrated with the processor.
  • a chip in a fifth aspect, includes a logic circuit and a communication interface.
  • the logic circuit is used to obtain the first vector to be encoded, and perform first encoding on the first vector to be encoded to obtain the second vector to be encoded.
  • the second encoding is performed on the second to-be-encoded vector based on the first generator matrix to obtain an encoded codeword.
  • the communication interface is used for outputting the encoded codeword.
  • the communication interface is used to input an encoded codeword.
  • the logic circuit is configured to decode the encoded codeword according to the first generator matrix.
  • the present application provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, when the computer-readable storage medium runs on a computer, the computer executes the methods of the above aspects.
  • the present application provides a computer program product storing instructions that, when executed on a computer, cause the computer to perform the methods of the above aspects.
  • the present application provides a communication system, including at least one of the above-mentioned terminal equipment and at least one of the above-mentioned network equipment.
  • 4A is one of schematic diagrams of a shift register provided by an embodiment of the present application.
  • 5B is one of the schematic diagrams of the grouping of the first vector to be encoded according to an embodiment of the present application.
  • 5C is one of the schematic diagrams of the grouping of the first vector to be encoded according to an embodiment of the present application.
  • 5D is one of the schematic diagrams of the grouping of the first vector to be encoded according to an embodiment of the present application.
  • 5E is one of the schematic diagrams of the grouping of the first vector to be encoded according to an embodiment of the present application.
  • 6B is one of the schematic diagrams of the sub-matrix a provided by the embodiment of the present application.
  • FIG. 7A is one of the schematic diagrams of the first generator matrix provided by the embodiment of the present application.
  • FIG. 7B is one of the schematic diagrams of the first generator matrix provided by the embodiment of the present application.
  • FIG. 8A is one of schematic diagrams of decoding performance provided by an embodiment of the present application.
  • FIG. 8B is one of the schematic diagrams of decoding performance provided by an embodiment of the present application.
  • FIG. 9A is one of the schematic diagrams of the first sub-block provided by an embodiment of the present application.
  • FIG. 9B is one of the schematic diagrams of the first generator matrix provided by the embodiment of the present application.
  • FIG. 10A is one of the schematic diagrams of the first sub-block provided by an embodiment of the present application.
  • FIG. 10B is one of the schematic diagrams of the first generator matrix provided by the embodiment of the present application.
  • FIG. 11A is one of the schematic diagrams of the first generator matrix provided by the embodiment of the present application.
  • FIG. 11B is one of the schematic diagrams of the first generator matrix provided by the embodiment of the present application.
  • FIG. 12A is one of schematic diagrams of decoding performance provided by an embodiment of the present application.
  • FIG. 12B is one of the schematic diagrams of decoding performance provided by an embodiment of the present application.
  • FIG. 13A is one of the schematic diagrams of the decoding process provided by the embodiment of the present application.
  • 13B is one of the schematic diagrams of the decoding process provided by the embodiment of the present application.
  • FIG. 14 is a schematic diagram of a coupling relationship of transmitting code blocks according to an embodiment of the present application.
  • FIG. 16 is one of the schematic diagrams of an encoding device provided by an embodiment of the present application.
  • FIG. 18 is one of the schematic diagrams of the encoding apparatus provided by the embodiment of the present application.
  • FIG. 19 is a schematic diagram of a decoding apparatus provided by an embodiment of the present application.
  • Mode 1 Encode the bits to be coded by using a generator matrix.
  • N is the code length
  • N is an integer greater than or equal to 1.
  • ui is the bit before encoding
  • i is an integer between 1 and N.
  • Information bits are bits used to carry information.
  • the frozen bits are padding bits, and the frozen bits can usually be 0.
  • the coding code length corresponding to this coding diagram is 8, and each circle in each row represents a summation between the bit of the row where the circle is located and the row reached by the circle, and the bit on the right side of the circle is the summation result .
  • the first circle of the row where the first frozen bit is located refers to the sum of the frozen bit 0 of the row where the circle is located, which is the first row, and the bit 0 of the row where the circle is located, which is the second row.
  • the summation result is: 0.
  • polar coding can be strictly proved to reach the channel capacity of the channel coding scheme, it has the characteristics of high performance, low complexity, and flexible matching methods.
  • 3GPP 3rd generation partnership project
  • eMBB enhanced mobile broadband
  • the current mainstream polar code decoding methods can be divided into two categories according to their decoding timing, namely polar code timing decoding and polar code non-sequential decoding.
  • the so-called polar code timing decoding means that the decoder performs bit-by-bit decoding according to the natural timing of polar design.
  • Non-sequential decoding of polar codes is the opposite, because multiple bits can be output at one time, and the decoding delay is small, but because it does not completely match the design of polar codes, it will bring a certain loss in decoding performance. But through reasonable design, this part of the loss can be reduced as much as possible.
  • the embodiments of the present application provide an encoding and decoding method, which is used to reduce the complexity of polar encoding and decoding and improve the performance of polar encoding and decoding.
  • Various generator matrices are provided in the embodiments of the present application, which are used to encode the bits to be encoded.
  • adjacent code blocks can be coupled, and short codes can be coupled to long codes, so as to maintain low-complexity decoding on the premise of improving coding gain.
  • the communication system 200 includes a sending device 201 and a receiving device 2102 .
  • the sending device 201 may be a network device or a terminal device, and the receiving device 202 may be a network device or a terminal device.
  • the receiving device 202 may be a terminal device; when the receiving device 202 is a network device, the sending device 201 may be a terminal device.
  • the sending device 201 may include an encoder, and the sending device 201 may perform polar encoding on the bits to be encoded through the encoder, and output the encoded codeword.
  • the encoded codeword can be transmitted to the receiving device 202 on the channel after rate matching, interleaving and modulation.
  • the receiving device 202 may include a decoder, the receiving device 202 may receive and demodulate the signal from the sending device 201, and the receiving device 202 may decode the received signal through the decoder.
  • the terminal devices involved in this application include devices that provide users with voice and/or data connectivity, specifically, include devices that provide users with voice, or include devices that provide users with data connectivity, or include devices that provide users with voice and/or data connectivity.
  • device for data connectivity may include a handheld device with wireless connectivity, or a processing device connected to a wireless modem.
  • the terminal equipment may include user equipment (UE), wireless terminal equipment, mobile terminal equipment, device-to-device (D2D) terminal equipment, vehicle to everything (V2X) terminal equipment , Machine-to-machine/machine-type communications (M2M/MTC) terminal equipment, Internet of things (IoT) terminal equipment, subscriber unit (subscriber unit), subscriber station (subscriber) station), mobile station, remote station, access point (AP), remote terminal, access terminal, user terminal ), user agent, or user device, satellite, drone, balloon, airplane, etc.
  • UE user equipment
  • D2D device-to-device
  • V2X vehicle to everything
  • M2M/MTC Machine-to-machine/machine-type communications
  • IoT Internet of things
  • subscriber unit subscriber unit
  • subscriber station subscriber station
  • AP access point
  • remote terminal access terminal
  • user agent or user device, satellite, drone, balloon, airplane, etc.
  • these may include mobile telephones (or "cellular" telephones), computers with mobile terminal
  • PCS personal communication service
  • SIP session initiation protocol
  • WLL wireless local loop
  • PDA personal digital assistant
  • constrained devices such as devices with lower power consumption, or devices with limited storage capacity, or devices with limited computing power, etc.
  • the terminal device may also be a wearable device.
  • Wearable devices can also be called wearable smart devices or smart wearable devices.
  • the various terminal devices described above, if they are located on the vehicle (for example, placed in the vehicle or installed in the vehicle), can be considered as on-board terminal equipment.
  • the on-board terminal equipment is also called an on-board unit (OBU).
  • the network equipment involved in this application includes access network (AN) equipment, such as a base station (for example, an access point), which may refer to an access network that communicates with wireless terminal equipment through one or more cells over the air interface.
  • AN access network
  • the device for communication or for example, a network device in a vehicle-to-everything (V2X) technology is a roadside unit (RSU).
  • V2X vehicle-to-everything
  • RSU roadside unit
  • an exemplary flowchart of the encoding and decoding method provided by the embodiment of the present application may include the following steps:
  • Step 301 The sending device obtains a first vector to be encoded.
  • the number of bits to be encoded is 4.
  • the sub-channels with the highest reliability among the 8 sub-channels are: sub-channel 3, sub-channel 5, sub-channel 7 and sub-channel 8, then the positions corresponding to sub-channel 3, sub-channel 4, sub-channel 7 and sub-channel 8 are It is used to carry information bits, and other subchannels are used to carry frozen bits.
  • the sequence to be encoded may be 00101011, where 1 represents an information bit and 0 represents a frozen bit.
  • Step 302 The sending device performs first encoding on the first vector to be encoded to obtain a second vector to be encoded.
  • the first encoding here may include outer code encoding.
  • the outer code encoding can be expressed as the multiplication of the first vector to be encoded and the upper triangular matrix.
  • the diagonal of the upper triangular matrix is all 1s, the upper right corner of the diagonal can take any value, and the lower left corner of the diagonal is full. is 0, this unified outer code is called pre-transformation coding.
  • the sending device may use convolutional codes (CC), parity check (PC), generalized cyclic redundancy check (generalized CRC) or other block codes to perform external coding on the first to-be-coded vector. code encoding.
  • FIG. 4A a schematic diagram of a shift register is shown when a convolutional code is used to perform outer code encoding. Among them, in is interpreted as input, and out is interpreted as output.
  • the input of the position of the information bit is the i-th information bit ui, and the output is the XOR bit value.
  • the frozen bit position input is 0 and the output is the XOR bit value.
  • the position of the CRC bit here can be selected from any frozen bit position, and does not need to be at the end.
  • FIG. 4B a schematic diagram of a shift register is shown when a check code is used to perform outer code encoding. Among them, in is interpreted as input, and out is interpreted as output. The position of the information bit is input as the ith information bit ui, and the output is the ith information bit ui. The frozen bit position input is 0 and the output is the value of the 0th bit register.
  • the outer code encoding in the embodiment of the present application is to string together the information bits of all code blocks and perform outer code encoding together, so that the outer code encoding result of the current code block is affected by the previous code block and will continue to affect the next code block.
  • the outer code encoding result In order to reduce the decoding complexity, the outer code can skip all frozen bit positions before the first information bit position in each code block, and the above-mentioned shift register does not move at these positions, that is, each code All frozen bit positions before the first information bit position in the block are set to zero or any known constant.
  • the outer code encoding can be performed independently in groups. Before each group of encoding, the shift register is initialized according to the method shown above. Grouping and grouping can overlap (overlapping) or non-overlapping (non-overlapping), if overlapping, the output of the previous set of registers is used as the input of the new set of registers.
  • the first vector to be encoded includes 8 bits, which are u1, u2, u3, u4, u5, u6, u7 and u8 respectively.
  • the sending device may regard each bit in the first vector to be encoded as a group, and then perform outer code encoding on each group. As shown in FIG. 5A, the number of bits in each group is 1 and there is no overlap between groups.
  • the sending device may perform an outer code on the 8 packets to obtain the second vector to be coded including 8 bits, namely v1, v2, v3, v4, v5, v6, v7, and v8.
  • the sending device may take every two bits in the first vector to be encoded as a group, and then perform outer code encoding on each group. As shown in FIG. 5B, the number of bits in each group is 2 and there is no overlap between groups.
  • the sending device may perform an outer code on the 4 packets to obtain the second vector to be coded including 8 bits, namely v1, v2, v3, v4, v5, v6, v7, and v8.
  • the sending device may regard every two bits in the first vector to be encoded as a group, and then perform outer code encoding on each group. As shown in FIG. 5C, the number of bits in each group is 2 and there is overlap between groups.
  • the sending device can perform the outer code on the 7 packets to obtain the second vector to be coded including 8 bits, which are v1, v2, v3, v4, v5, v6, v7, and v8 respectively.
  • the sending device may take every four bits in the first vector to be encoded as a group, and then perform outer code encoding on each group. As shown in FIG. 5D, the number of bits in each group is 4 and there is overlap between groups.
  • the sending device may perform an outer code on the 2 packets to obtain a second vector to be coded including 8 bits, namely v1, v2, v3, v4, v5, v6, v7, and v8.
  • the sending device may take every 8 bits in the first vector to be encoded as a group, and then perform outer code encoding on each group. As shown in Figure 5E, the number of bits in each group is 8 and there is no overlap between groups.
  • the sending device may perform an outer code on one packet to obtain the second vector to be encoded including 8 bits, namely v1, v2, v3, v4, v5, v6, v7, and v8.
  • the first encoding may also include an interleaving operation.
  • the sending device may perform outer code encoding after interleaving the first vector to be encoded; or, the sending device may perform interleaving after encoding the outer code of the first vector to be encoded.
  • Step 303 The sending device performs second encoding on the second vector to be encoded based on the first generator matrix to obtain an encoded codeword.
  • the first generator matrix here may include at least one N+1 sub-matrix a.
  • the N sub-matrices a may be located on the main diagonal of the first generator matrix.
  • the above-mentioned first generator matrix may be a block upper triangular matrix, or may be a block lower triangular matrix.
  • a is a polar code polar kernel matrix of size 2 m * 2 m
  • m is a natural number
  • N is a natural number.
  • the sub-matrix a can contain polar kernel G N , and 0 elements.
  • the polar kernel G N can be distributed in the lower left corner of the sub-matrix a, and can be distributed in a triangle.
  • the polar nucleus GN can form the sides of the triangle.
  • the sub-matrix a is a polar kernel matrix with a size of 2*2 and a polar kernel matrix with a size of 4*4 as examples for description. It should be noted that the sub-matrix a may also be a polar kernel matrix with a size of 8*8, 16*16 or 2m * 2m .
  • the submatrix a can also be a polar kernel G N .
  • the sub-matrix a may be a 2*2 polar kernel matrix.
  • the submatrix a can be
  • the sub-matrix a may be a 4*4 polar kernel matrix.
  • the submatrix a can be
  • the first generator matrix in the embodiment of the present application will be described.
  • the first generator matrix may be divided into the following three types according to different coupling modes.
  • the first type triangular coupling.
  • the triangular coupling can be understood as the triangular distribution of the sub-matrix a in the first generator matrix. It should be understood that the sub-matrix a may cover the triangle, or may also form the sides of the above triangle. In the embodiment of the present application, the triangle a is covered with the triangle as an example for description.
  • Case 1 The first generator matrix is an upper triangular matrix.
  • the first sub-block In order to support 1-pass decoding starting from the first sub-block, the first sub-block needs to be able to be decoded independently and cannot be superimposed with other sub-block code words. Therefore, the coupled polar matrix needs to be written in an upper triangular form, as shown in Figure 7A.
  • FIG. 7A it is taken as an example that the first encoding vector includes 8 sub-blocks. Each sub-block may contain multiple information bits and multiple frozen bits.
  • the above encoding process can also be decomposed into outer code encoding, intra-sub-block encoding and inter-sub-block coupling encoding.
  • the sending device may perform outer code encoding on the subblock ui to obtain the outer code subblock vi.
  • the sending device then multiplies the outer code sub - code block vi by the polar core GN to obtain the sub-code word ci.
  • the sending device may superimpose each sub-code word ci in a coupling manner to obtain the final code word ci' of the coupled code.
  • the coupling manner may be as shown in FIG. 7A .
  • Case 2 The first generator matrix is a lower triangular matrix.
  • the processing starts from the last sub-code block first, and the first generator matrix needs to be written in a lower triangular formula, as shown in FIG. 7B .
  • the first encoding vector includes 8 sub-blocks as an example for description. Each sub-block may contain multiple information bits and multiple frozen bits.
  • the sending device may fill in the information bits and frozen bits in sequence according to the reliability of the sub-channels to obtain an M-long information vector u.
  • an M-long information vector ui can be regarded as a second sub-block.
  • the transmitting device can perform outer code encoding on the vector u, the total length of which is T*N, and the outer code word vector v whose total length is the same as T*N is obtained. Then the v vector is multiplied by the coupled polar matrix in the binary domain.
  • the sending device may encode the vector to be encoded based on the first generator matrix to obtain a codeword.
  • the codeword obtained by the encoding by the transmitting device through the above-mentioned first generator matrix multiple sub-blocks are coupled, so that a higher encoding gain of the coupled code can be obtained, and the encoding performance can be improved.
  • the sending device may first determine the number of second subblocks included in the first vector to be encoded.
  • the sending device may determine the code rate of each second subblock based on the total code rate of the codeword and the number of the second subblocks. It should be understood that the code rates of different second sub-blocks may be different.
  • the sending device may determine the first vector to be encoded based on the code rate of each second subblock and the number of second subblocks included in the first vector to be encoded.
  • each group has 4 second sub-blocks, and there is polarization between the second sub-blocks, the number of information bits of each second sub-block is different. According to the pre-stored total code rate and the first to-be-coded vector containing According to the relationship between the number of the second sub-blocks and the code rate of each second sub-block, it can be determined that the number of information bits of the 1st, 2nd, 3rd, and 4th second sub-blocks are 33, 50, 54, and 119, respectively.
  • the relationship between the total code rate, the number of second sub-blocks included in the first vector to be encoded, and the code rate of each second sub-block can be determined by the total code length, the total information length, the total code rate, the second sub-block
  • the number of blocks, the number of groups, the number of second sub-blocks in each group, and the information length of each second sub-block are determined. For details, see Table 1 to Table 9 below.
  • the encoding method of the embodiment of the present application has a gain of 0.3dB to 1dB compared to the uncoupled code.
  • FIG. 8B it is a simulation effect diagram of different encoding methods.
  • the SC decoding method is used for a picture
  • the SCL decoding method is used for the b picture.
  • the horizontal axis represents the signal to noise ratio (SNR)
  • the vertical axis represents the Block Error Rate (BLER).
  • SNR signal to noise ratio
  • BLER Block Error Rate
  • the triangular coupling matrix coding method provided by the embodiment of the present application has a significantly lower bit error rate compared with the short code, and compared with the long code The rate is not much different, but the complexity is lower than the long code.
  • the generator matrix of adjacent coupling may include K first sub-blocks.
  • K first sub-blocks are located on the main diagonal of the first generator matrix, and adjacent first sub-blocks partially overlap.
  • K is greater than or equal to 2.
  • the first sub-block can be or
  • different adjacent coupling generating matrices are introduced respectively.
  • Fig. 9A is a generator matrix of size 4*4, and the generator matrix contains submatrix a and 0 elements. As shown in FIG. 9A , the generator matrix includes three first sub-blocks. The above-mentioned three first sub-blocks are located on the main diagonal of the first generator matrix.
  • the first sub-block In order to support 1-pass decoding starting from the first sub-block, the first sub-block needs to be able to be decoded independently and cannot be superimposed with other sub-block code words. Therefore, the coupled Polar matrix needs to be written in the upper triangular form, as shown in Fig. 9B.
  • the first generator matrix includes 7 first sub-blocks.
  • the first vector to be encoded includes 8 small blocks and 7 second sub-blocks.
  • the sending device can fill in the information bits and the frozen bits in sequence according to the reliability of the sub-channels to obtain multiple M-long information vectors ui.
  • the transmitting device can perform outer code encoding on the vector u, the total length of which is T*N, and the outer code word vector v whose total length is the same as T*N is obtained. Then the v vector is multiplied by the coupled polar matrix in the binary domain.
  • the second sub-block 1 may be u1+u2
  • the second sub-block 2 may be u2+u3
  • the second sub-block 4 may be u4+u5
  • the second sub-block 4 may be u4+u5.
  • Sub-block 5 may be u5+u6, second sub-block 6 may be u6+u7, and second sub-block 7 may be u7+u8.
  • the above encoding process can also be decomposed into outer code encoding, intra-sub-block encoding and inter-sub-block coupling encoding.
  • the sending device may perform outer code encoding on the subblock ui to obtain the outer code subblock vi.
  • the sending device then multiplies the outer code sub - code block vi by the polar core GN to obtain the sub-code word ci.
  • the sending device may superimpose each sub-code word ci in a coupling manner to obtain the final code word ci' of the coupled code.
  • the coupling manner may be as shown in FIG. 9B .
  • Fig. 10A is a generator matrix of size 4*4, which contains submatrix a and 0 elements. As shown in FIG. 10A , the generator matrix includes three first sub-blocks. The above-mentioned three first sub-blocks are located on the main diagonal of the first generator matrix.
  • the processing starts from the last subcode block first, and the first generator matrix needs to be written in a lower triangular formula, as shown in FIG. 10B .
  • the first generator matrix includes 7 first sub-blocks.
  • the first vector to be encoded includes 8 small blocks and 7 second sub-blocks.
  • the sending device can fill in the information bits and the frozen bits in sequence according to the reliability of the sub-channels to obtain multiple M-long information vectors ui.
  • the transmitting device can perform outer code encoding on the vector u, the total length of which is T*N, and the outer code word vector v whose total length is the same as T*N is obtained. Then the v vector is multiplied by the coupled polar matrix in the binary domain.
  • the second sub-block 1 may be u1+u2
  • the second sub-block 2 may be u2+u3
  • the second sub-block 4 may be u4+u5
  • the second sub-block 4 may be u4+u5.
  • Sub-block 5 may be u5+u6, second sub-block 6 may be u6+u7, and second sub-block 7 may be u7+u8.
  • the above encoding process can also be decomposed into outer code encoding, intra-sub-block encoding and inter-sub-block coupling encoding.
  • the sending device may perform outer code encoding on the subblock ui to obtain the outer code subblock vi.
  • the sending device then multiplies the outer code sub - code block vi by the polar kernel GN to obtain the sub-code word ci.
  • the sending device may superimpose each sub-code word ci in a coupling manner to obtain the final code word ci' of the coupled code.
  • the coupling manner may be as shown in FIG. 10B .
  • the third type tail biting coupling
  • the tail-biting coupling here is determined based on the generating matrix of the adjacent coupling, and can be divided into the following two cases:
  • the first generator matrix is upper triangular.
  • the first generator matrix may include 7 first sub-blocks, each first sub-block includes 16 sub-matrices a, and the first generator matrix further includes 1 sub-matrix a located at the lower left corner of the first generator matrix.
  • the sending device may perform outer code encoding on multiple M-length information vectors ui, the total length of which is T*N, to obtain an outer code word vector v whose total length is the same as T*N. Then the v vector is multiplied by the coupled polar matrix in the binary domain.
  • the second sub-block 1 may be u1+u2
  • the second sub-block 2 may be u2+u3
  • the second sub-block 3 may be u3+u4
  • the second sub-block 4 may be u4+u5
  • the second sub-block 4 may be u4+u5.
  • Sub-block 5 may be u5+u6, second sub-block 6 may be u6+u7, and second sub-block 7 may be u7+u8.
  • the above encoding process can also be decomposed into outer code encoding, intra-sub-block encoding and inter-sub-block coupling encoding.
  • the sending device may perform outer code encoding on the subblock ui to obtain the outer code subblock vi.
  • the sending device then multiplies the outer code sub - code block vi by the polar core GN to obtain the sub-code word ci.
  • the sending device may superimpose each sub-code word ci in a coupling manner to obtain the final code word ci' of the coupled code.
  • the coupling manner may be as shown in FIG. 11A .
  • c1' c1+c2
  • c2' c2+c3
  • c3' c3+c4
  • c4' c4+c5
  • c5' c5+c6
  • c6' c6+c7
  • c7' c7+ c8+c1
  • the first generator matrix is a lower triangular form.
  • the first generator matrix may include 7 first sub-blocks, each first sub-block includes 16 sub-matrices a, and the first generator matrix further includes 1 sub-matrix a located in the upper right corner of the first generator matrix.
  • the sending device may perform outer code encoding on multiple M-length information vectors ui, the total length of which is T*N, to obtain an outer code word vector v whose total length is the same as T*N. Then the v vector is multiplied by the coupled polar matrix in the binary domain.
  • the second sub-block 1 may be u1+u2
  • the second sub-block 2 may be u2+u3
  • the second sub-block 3 may be u3+u4
  • the second sub-block 4 may be u4+u5
  • the second sub-block 4 may be u4+u5.
  • Sub-block 5 may be u5+u6, second sub-block 6 may be u6+u7, and second sub-block 7 may be u7+u8.
  • the above encoding process can also be decomposed into outer code encoding, intra-sub-block encoding and inter-sub-block coupled encoding.
  • the sending device may perform outer code encoding on the subblock ui to obtain the outer code subblock vi.
  • the sending device then multiplies the outer code sub - code block vi by the polar core GN to obtain the sub-code word ci.
  • the sending device may superimpose each sub-code word ci in a coupling manner to obtain the final code word ci' of the coupled code.
  • the coupling manner may be as shown in FIG. 11A .
  • the transmitting device may determine the second vector to be encoded contained in the first vector to be encoded.
  • the number of subblocks The transmitting device may determine the code rate of each second subblock based on the total code rate of the codeword and the number of the second subblocks. Wherein, the code rate of each second sub-block may be different.
  • the transmitting device may determine the first vector to be encoded based on the code rate of each second sub-block.
  • the code rates of two adjacent second sub-blocks in the first vector to be encoded may also be the same, and the first vector to be encoded includes at least two different code rates.
  • the sending device may determine the code rate of each second subblock according to the number of the second subblocks included in the first vector to be encoded and the total code rate.
  • the relationship between the total code rate and the number of second sub-blocks and the code rate of each second sub-block can be determined by the total code length, the total information length, the total code rate, the number of small blocks, the number of groups, the number of The number of sub-blocks and the information length of each small block are determined. For details, see Table 1 to Table 9 below.
  • the encoding method of the embodiment of the present application has a gain of 0.3dB to 1dB compared to the uncoupled code.
  • the reliability of each sub-channel is different, so the construction method is different from that of 1-pass.
  • the overall input reliability of the sub-block is calculated, and the code rate of each sub-block is obtained. Equivalently, the number of information bits of each sub-block can be obtained.
  • the reliability of each sub-channel in the sub-block is calculated again, which is the same as the construction method of the original Polar code.
  • Rth can be used as a boundary to determine which coupling scheme is used when the code rate is less than or equal to Rth or greater than or equal to Rth.
  • Rth can be defined as intermediate code rates such as 1/2, 7/16, 9/16, 3/8 or 5/8.
  • FIG. 12A it is a simulation effect diagram of different encoding methods.
  • the SC decoding method is used for a picture
  • the SCL decoding method is used for the b picture.
  • the horizontal axis represents the signal to noise ratio (SNR)
  • the vertical axis represents the Block Error Rate (BLER).
  • SNR signal to noise ratio
  • BLER Block Error Rate
  • the bit error rate of the long code is the lowest
  • the bit error rate of the coding method of the embodiment of the present application is slightly higher than that of the long code
  • the bit error rate of the short code is the highest.
  • the coding method provided by the embodiments of the present application can reduce the complexity and improve the coding gain.
  • the bit error rate is not much different from the bit error rate of the long code.
  • SCL decoding can further reduce the bit error rate.
  • FIG. 12B it is a simulation effect diagram of different encoding methods.
  • the SC decoding method is used for a picture
  • the SCL decoding method is used for the b picture.
  • the horizontal axis represents the signal to noise ratio (SNR)
  • the vertical axis represents the Block Error Rate (BLER).
  • SNR signal to noise ratio
  • BLER Block Error Rate
  • the bit error rate of the long code is the lowest
  • the bit error rate of the coding method of the embodiment of the present application is slightly higher than that of the long code
  • the bit error rate of the short code is the highest.
  • the coding method provided by the embodiments of the present application can reduce the complexity and improve the coding gain.
  • SCL decoding can further reduce the bit error rate.
  • the triangular coupling matrix coding method provided by the embodiment of the present application has a significantly lower bit error rate than that of the short code, and the error rate is obviously lower than that of the long code.
  • the rate is not much different, but the complexity is lower than the long code.
  • Step 304 The sending device sends the encoded codeword to the receiving device, and the corresponding receiving device receives the codeword from the sending device.
  • Step 305 The receiving device decodes the codeword.
  • the codeword when the receiving device decodes the codeword, the codeword may be decoded based on the first generator matrix.
  • the receiving device may use different first generator matrices to decode the codeword according to different encoding modes. Among them, according to the different encoding methods, the decoding will be described in the following four cases.
  • the characteristics of the 1-pass decoding of the triangular coupling matrix can include the following two characteristics:
  • the triangular coupling matrix needs to use the decoding results of all previous sub-blocks to write the LLR to be decoded of the current sub-block during hard decoupling.
  • the XOR value of the i-th bit of all previous sub-blocks is 0, the i-th channel receiving LLR of the current sub-block is directly sent to the current sub-block decoder. If the XOR value of the i-th bit of all previous sub-blocks is 1, the sign of the received LLR of the i-th channel of the current sub-block is inverted or multiplied by -1 and sent to the current sub-block decoder.
  • the decoding method may be as shown in FIG. 13A. Among them, codeword hard decoupling between sub-blocks is performed first. It should be understood that the first sub-block does not require codeword hard decoupling.
  • the meaning of the hard decoupling of codewords between sub-blocks is: using the decoding result of the previous sub-block to write the LLR to be decoded of the current sub-block.
  • the i-th value of the output LLR is lt,i, then the i-th LLR value sent to the current sub-block decoder is This goes back and forth until the last sub-block is translated.
  • the characteristics of the 1-pass decoding of the triangular coupling matrix can include the following two characteristics:
  • Polarization can be formed between sub-blocks, and part of the long code gain can be obtained as much as possible.
  • the decoding method is also different. As shown in the figure below:
  • the decoding method may be as shown in FIG. 13B .
  • the forward transfer of soft decoupling of codewords between sub-blocks is performed first. It should be understood that no codeword soft decoupling is required for the last sub-block. Assuming that the i-th codeword bit of the previous sub-block is ct-1,i, the i-th value of the forward decoupling LLR of the previous sub-block is lt-1,i, and the channel of the current sub-block receives the LLR's i-th value.
  • the channel of the next subblock receives the LLR's
  • the reverse decoupling LLR of the current sub-block is sent to the current sub-block decoder, and so on until the last sub-block is decoded.
  • the 1-pass decoding of adjacent coupling and tail-biting coupling matrices can include the following two characteristics:
  • the decoding method may be as shown in FIG. 13A. Among them, codeword hard decoupling between sub-blocks is performed first. It should be understood that the first sub-block does not require codeword soft decoupling. Assuming that the i-th bit of the previous sub-block is ci, and the i-th value of the channel output LLR of the current sub-block is li, the i-th value sent to the current sub-block decoder is This goes back and forth until the last sub-block is translated. Wherein, if the i-th bit of the previous sub-block is 0, the i-th channel receiving LLR of the current sub-block is directly sent to the current sub-code decoder. If the i-th bit of the previous sub-block is 1, the sign of the received LLR of the i-th channel of the current sub-block is inverted or multiplied by -1 and sent to the current sub-code decoder.
  • the 2-pass decoding of adjacent coupling and tail-biting coupling matrices can include the following two characteristics:
  • Polarization can be formed between sub-blocks, and part of the long code gain can be obtained as much as possible.
  • the decoding method may be as shown in FIG. 13B .
  • the reverse transfer of soft decoupling of codewords between sub-blocks is performed first. It should be understood that there is no need for soft decoupling of codewords for most of the sub-blocks.
  • the i-th value of the channel receiving LLR of the current sub-block is l't,i
  • the i-th value of the channel receiving LLR of the next sub-block is l't+1,i
  • the i-th codeword bit of the previous sub-block is ct-1,i
  • the i-th value of the channel receiving LLR of the previous sub-block is l't-1,i
  • the reverse decoupling LLR of the current sub-block is The i-th value of is lt,i
  • the forward decoupling LLR of the current sub-block is sent to the current sub-block decoder, and so on until the last sub-block is decoded.
  • the sending device and the receiving device can respectively determine the outer code type, outer code polynomial, outer code group number, coupling degree, coupling group number, coupling relationship, selection of coupling matrix, and other coupling-related parameters.
  • the coupling-related parameters may be determined by the parameters of the scene and the codeword, and the like.
  • the transmitting device or the receiving device may first determine a specific coupling scheme based on parameters such as code length or application scenarios, including coupling-related parameters such as the outer code, number of packets, coupling degree, and coupling mode shown above.
  • the sending device may negotiate the above-mentioned coupling-related parameters with the receiving device through signaling, or the sending device may indicate the coupling-related parameters to the receiving device, or the receiving device may indicate the coupling-related parameters to the sending device.
  • the coupling-related parameters may also be specified by a communication protocol, which is not specifically limited in this application. Then the sender and receiver perform codec communication according to the agreed method.
  • the sending device and the receiving device may negotiate or indicate coupling-related parameters through a radio resource control (radio resource control, RRC) message.
  • RRC radio resource control
  • a part of fields may be newly added to the RRC message to carry encoding configuration information.
  • the encoding configuration information may include the above-mentioned multiple coupling-related parameters.
  • the sending device or the receiving device may indicate coupling-related parameters through downlink control information (downlink control information, DCI).
  • DCI downlink control information
  • the format of the DCI may be as shown in Table 19 below.
  • the bits to be encoded may be divided into several groups, and each group includes a specified number of code blocks (code blocks, CBs). There may be a coupling relationship between the code blocks in each group, as shown in Figure 14.
  • code blocks code blocks
  • FIG. 14 is only an exemplary coupling mode.
  • the number B of bits to be encoded is greater than a certain threshold K cb , the B bits to be encoded are segmented, and the CRC belonging to the CB is added to each segment of information bits.
  • the CRC is L long and L>0.
  • the number of bits to be encoded after adding CRC bits is B', and the process is as follows:
  • the information vectors u 0 , u 1 ,..., u C-1 of C segments are encoded respectively, and the obtained codeword vectors are c 0 ,c 1 ,...,c C-1 , where the rth CB
  • the code rate (information bits) is first allocated to the C CBs, and the number of information bits of each sub-block is K 1 , K 2 ,...,K C , where is the number of information bits of the rth CB is Kr .
  • Kr may contain CRC bits or may not contain CRC bits.
  • K 1 +K 2 +...+K C B'.
  • c r1 ,c r2 ,...c rl are sub-blocks that have a coupling relationship with the rth CB, so the coupled codeword of the rth CB is composed of the sub-block codes of the r 1 ,r 1 ,...,r l CBs Words are generated by coupled encoding.
  • the apparatus 1500 may include a processing unit 1520 and an input-output unit 1510 .
  • a storage unit 1530 is also included; the processing unit 1520 may be connected to the storage unit 1530 and the input/output unit 1510 respectively, and the storage unit 1530 may also be connected to the input/output unit 1510 .
  • the processing unit 1520 may be integrated with the storage unit 1530 .
  • the input-output unit 1510 may also be referred to as a transceiver, a transceiver, a transceiver, or the like.
  • the processing unit 1520 may also be referred to as a processor, a processing board, a processing module, a processing device, and the like.
  • the device used to implement the receiving function in the input and output unit 1510 may be regarded as a receiving unit
  • the device used to implement the sending function in the input and output unit 1510 may be regarded as a transmitting unit, that is, the input and output unit 1510 includes a receiving unit and sending unit.
  • the input-output unit may also sometimes be referred to as a transceiver, a transceiver, or a transceiver circuit.
  • the receiving unit may also sometimes be referred to as a receiver, receiver, or receiving circuit, or the like.
  • the transmitting unit may also sometimes be referred to as a transmitter, a transmitter, or a transmitting circuit, or the like.
  • the input/output unit 1510 is configured to perform the sending and receiving operations of the sending device and the receiving device in the above method embodiments
  • the processing unit 1520 is configured to perform the sending and receiving operations on the sending device and the receiving device in the above method embodiments except for the sending and receiving operations. other operations.
  • the input-output unit 1510 is configured to perform the sending operation of the sending device and the receiving operation of the receiving device shown in step 304 in FIG. 3 .
  • the input-output unit 1510 is further configured to perform other transceiving steps of the sending device and the receiving device in the embodiments of the present application.
  • the processing unit 1520 is configured to perform the processing steps of the sending device shown in steps 301 to 303 in FIG. 3 and the processing operations of the receiving device shown in step 305, and/or the processing unit 1520 is configured to perform the processing in the embodiments of the present application. Additional processing steps for sending and receiving devices.
  • the processing unit 1520 is further configured to: determine the number of second sub-blocks included in the information bits to be encoded; The code rate of each second sub-block included in the information bits to be encoded; wherein, the code rate of each second sub-block is different; when the processing unit 1520 acquires the first to-be-coded vector, it is specifically used for: based on the The code rate of each second subblock determines the first vector to be encoded; the first vector to be encoded includes q second subblocks, and q is an integer greater than 0.
  • the memory 1602 may be independent or integrated with the processor 1601 . In some embodiments, memory 1602 may even be located outside of encoding device 1600.
  • the encoding apparatus 1600 may further include a bus 1603 for connecting the memory 1602 and the processor 1601 .
  • the apparatus 1600 may further include a transmitter.
  • the transmitter is used to transmit the encoded bits.
  • FIG. 17 it is a schematic diagram of a hardware structure of an apparatus according to an embodiment of the present application.
  • the apparatus 1700 is used to implement the function of the receiving device in the above method.
  • the device may be a receiving device, or a chip with functions similar to the receiving device, or a device that can be matched and used with the receiving device.
  • the apparatus 1700 a processor 1701 and a memory 1702.
  • the memory 1702 is used to store computer programs and can also be used to store intermediate data
  • the processor 1701 is configured to execute the computer program stored in the memory, so as to implement each step in the above encoding method. For details, refer to the relevant descriptions in the foregoing method embodiments.
  • the encoding apparatus 1700 may further include a bus 1703 for connecting the memory 1702 and the processor 1701 .
  • FIG. 18 is a schematic structural diagram of an apparatus provided by an embodiment of the present application.
  • the apparatus 1800 may include a communication interface 1801 and a logic circuit 1802 .
  • the logic circuit 1802 is configured to obtain a first vector to be encoded; perform first encoding on the first vector to be encoded to obtain a second vector to be encoded. and performing second encoding on the second vector to be encoded based on the first generator matrix to obtain an encoded codeword; wherein the first generator matrix includes at least N+1 sub-matrices a, and N sub-code blocks are located in the first On the main diagonal of a generator matrix, the first generator matrix is a block upper triangular matrix, or the first generator matrix is a block lower triangular matrix, where a is a polar code polar with a size of 2 m * 2 m Kernel matrix, m is a natural number and N is a natural number; the communication interface is used for outputting the encoded codeword.
  • the apparatus 1800 provided in this embodiment of the present application may execute the technical solutions shown in the foregoing method embodiments, and the implementation principles and beneficial effects thereof are similar to those shown in the foregoing method embodiments, and will not be repeated here.
  • the logic circuit 1902 is used for decoding the codeword.
  • the communication interface 1901 may have the function of the input and output unit 1510 in the embodiment of FIG. 15 .
  • the logic circuit 1902 may have the function of the processing unit 1520 in the embodiment of FIG. 15 .
  • the communication interface 1901 may have the function of the receiver in the embodiment of FIG. 17 .
  • the logic circuit 1902 may have the function of the processor 1701 in the embodiment of FIG. 17 .
  • the logic circuit 1902 may also perform other steps in the decoding method.
  • the apparatus 1900 provided in this embodiment of the present application may execute the technical solutions shown in the foregoing method embodiments, and the implementation principles and beneficial effects thereof are similar to those shown in the foregoing method embodiments, and will not be repeated here.
  • a computer-readable storage medium on which instructions are stored, and when the instructions are executed, the methods of the sending device and the receiving device in the above method embodiments are executed.
  • a computer program product containing instructions is provided, and when the instructions are executed, the methods of the sending device and the receiving device in the above method embodiments are executed.
  • a communication system may include the above-mentioned at least one sending device and the above-mentioned at least one receiving device.
  • processors mentioned in the embodiments of the present invention may be a central processing unit (Central Processing Unit, CPU), and may also be other general-purpose processors, digital signal processors (Digital Signal Processors, DSP), application-specific integrated circuits ( Application Specific Integrated Circuit, ASIC), off-the-shelf Programmable Gate Array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the memory mentioned in the embodiments of the present invention may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (Read-Only Memory, ROM), a programmable read-only memory (Programmable ROM, PROM), an erasable programmable read-only memory (Erasable PROM, EPROM), an electrically programmable read-only memory (Erasable PROM, EPROM). Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be Random Access Memory (RAM), which acts as an external cache.
  • RAM Static RAM
  • DRAM Dynamic RAM
  • SDRAM Synchronous DRAM
  • SDRAM double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM DDR SDRAM
  • enhanced SDRAM ESDRAM
  • synchronous link dynamic random access memory Synchlink DRAM, SLDRAM
  • Direct Rambus RAM Direct Rambus RAM
  • the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components
  • the memory storage module
  • memory described herein is intended to include, but not be limited to, these and any other suitable types of memory.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable storage medium.
  • the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution, and the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .

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Abstract

本申请实施例提供一种编码和译码方法及相关装置，用来降低编码译码的复杂度，以及提升编译码性能。该方法中，发送设备可以获取第一待编码向量。发送设备可以对第一待编码向量进行第一编码，得到第二待编码向量。发送设备可以基于第一生成矩阵对第二待编码向量进行编码，得到编码后的码字。其中，第一生成矩阵可以包括至少N+1个子矩阵a，其中的N个子矩阵a可以位于第一生成矩阵的主对角线上。其中，第一生成矩阵可以是块上三角矩阵，或者述第一生成矩阵可以是块下三角矩阵。前述子矩阵a是大小为2 m*2 m的极化码polar核矩阵，m是自然数，N是自然数。发送设备可以发送编码后的码字。

Description

一种编码和译码方法及相关装置
相关申请的交叉引用
本申请要求在2021年02月09日提交中国专利局、申请号为202110177405.2、申请名称为“一种编码和译码方法及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及无线通信技术领域，尤其涉及一种编码和译码方法及相关装置。
背景技术
在通信技术领域，通信设备(例如终端设备、基站等)可以通过极化码(polar码)的方式进行信道编码和译码。
近年来，随着polar码被列入无线通信第五代移动网络(5 th generation mobile networks，5G)标准，对polar码的译码研究成为了通信方向的热点问题。目前主流的polar码译码方法可按其译码时序分为两类，即polar码时序译码和polar码非时序译码。所谓polar码时序译码，是指译码器根据polar设计的天然时序性按比特位逐位进行译码。而polar码非时序译码，是指译码器根据polar码的其他结构(如Taner graph，Trelis graph等)并行输出译码结果。polar码时序译码的优点是和polar码的设计兼容，理论分析很方便，缺点是由于其逐位输出的特性，译码延迟较大，对实时性要求较高的通信系统不适合。polar码非时序译码则相反，因为可以一次性输出多个比特，译码延迟较小，但是因其跟polar码的设计不完全匹配，会在译码性能上带来一定的损失。
发明内容
本申请实施例提供一种编码和译码方法及相关装置，用来降低编码译码的复杂度，以及获得编译码的增益，提升编译码性能。
第一方面，提供了一种编码方法，该方法可以由发送设备执行，或者类似发送设备功能的芯片执行。其中，发送设备可以是终端设备或者网络设备。该方法中，发送设备可以获取第一待编码向量。发送设备可以对第一待编码向量进行第一编码，得到第二待编码向量。发送设备可以基于第一生成矩阵对第二待编码向量进行编码，得到编码后的码字。其中，第一生成矩阵可以包括至少N+1个子矩阵a，其中的N个子矩阵a可以位于第一生成矩阵的主对角线上。其中，第一生成矩阵可以是块上三角矩阵，或者述第一生成矩阵可以是块下三角矩阵。前述子矩阵a是大小为2 m*2 m的极化码polar核矩阵，m是自然数，N是自然数。发送设备可以发送编码后的码字。
基于上述方案，发送设备可以对第一待编码向量进行第一编码，由于第一待编码向量中任一个码块进行第一编码时会受上一个码块的影响，且也会影响下一个码块进行第一编码，可以使得多个码块之间有耦合，获得编码增益。此外，在第一生成矩阵对第二待编码向量进行编码时，由于第一生成矩阵包括了N+1个子矩阵，且N+1个子矩阵位于第一生成矩阵的对角线上，且第一生成矩阵块三角矩阵，因此相当于对多个短码进行编码，再对多个短码进行耦合，得到编码后的码字，进而可以降低编码复杂度，也可以提升编码的性 能。
在一种可能的实现方式中，块上三角矩阵中上三角的元素都是a，块下三角矩阵中下三角的元素都是a。
基于上述方案，块上三角矩阵中上三角的元素都可以是a，下三角中的元素可以是0，在块下三角矩阵中下三角的元素都可以是a，上三角的元素都可以是0，在对第二待编码向量进行编码时，可以根据第一生成矩阵中子矩阵a的位置关系，对多个短码进行耦合。
在一种可能的实现方式中，第一生成矩阵可以包含K个第一子块，K个第一子块可以位于第一生成矩阵的主对角线上，相邻的第一子块之间有部分重叠，K是大于等于2，且大于等于N的整数；每个第一子块是
Figure PCTCN2022074851-appb-000001
或
Figure PCTCN2022074851-appb-000002
基于上述方案，第一生成矩阵可以包含K个位于第一生成矩阵的主对角线上的第一子块，且第一子块有两种样式不同的矩阵，使得第一生成矩阵也具有两种不同的样式，因此可以实现对不同的短码进行耦合。
在一种可能的实现方式中，相邻的第一子块之间重叠部分为a。
基于上述方案，相邻的第一子块之间重叠部分大小可以为子矩阵a的大小，使得短码之间的耦合方式与polar核矩阵相关，可以降低编码的复杂度。
在一种可能的实现方式中，K个第一子块可以包含N个子矩阵a，当第一子块是
Figure PCTCN2022074851-appb-000003
时，1个子矩阵a位于第一生成矩阵的右上角。
基于上述方案，第一生成矩阵可以是包含K个位于第一生成矩阵的主对角线上的第一子块以及位于右上角的一个子矩阵a，可以使得第二待编码向量中第一个码块与最后一个码块之间有耦合，可以进一步提升编码性能。
在一种可能的实现方式中，K个第一子块可以包含N个子矩阵a，当第一子块是
Figure PCTCN2022074851-appb-000004
时，1个子矩阵a位于第一生成矩阵的左下角。
基于上述方案，第一生成矩阵可以是包含K个位于第一生成矩阵的主对角线上的第一子块以及位于左下角的一个子矩阵a，可以使得第二待编码向量中第一个码块与最后一个码块之间有耦合，可以进一步提升编码性能。
在一种可能的实现方式中，发送设备可以确定待编码信息比特包含的第二子块的数量。发送设备可以基于码字的总码率和第二子块的数量，确定待编码信息比特包含的每一个第二子块的码率；其中，每一个第二子块的码率不同。发送设备可以基于每一个第二子块的码率确定第一待编码向量。第一待编码向量可以包含q个第二子块，q是大于0的整数。
基于上述方案，发送设备可以获取第一待编码向量时，可以根据码字的总码率以及第二子块的数量确定第一待编码向量中每一个第二子块的码率，使得短码的长度不同，耦合码的长度也不相同，可以提升编码性能。
第二方面，提供了一种译码方法。该方法可以由接收设备执行，或者类似接收设备功能的芯片执行。该方法中，接收设备可以接收码字。码字可以是基于第一生成矩阵编码得到的。其中，第一生成矩阵可以包括至少N+1个子矩阵a，其中的N个子矩阵a可以位于第一生成矩阵的主对角线上，第一生成矩阵可以是块上三角矩阵，或者第一生成矩阵可以是块下三角矩阵。其中a是大小为2 m*2 m的极化码polar核矩阵，m是自然数N是自然数。接收设备可以对码字进行译码。
在一种可能的实现方式中，块上三角矩阵中上三角的元素都是a，块下三角矩阵中下三角的元素都是a。
在一种可能的实现方式中，第一生成矩阵可以包含K个第一子块，K个第一子块可以位于第一生成矩阵的主对角线上，相邻的第一子块之间有部分重叠，K是大于等于2，且大于等于N的整数。每个第一子块可以是
Figure PCTCN2022074851-appb-000005
或
Figure PCTCN2022074851-appb-000006
在一种可能的实现方式中，相邻的第一子块之间重叠部分可以为a。
在一种可能的实现方式中，K个第一子块可以包含N个子矩阵a，当第一子块是
Figure PCTCN2022074851-appb-000007
时，1个子矩阵a位于第一生成矩阵的右上角。
在一种可能的实现方式中，K个第一子块可以包含N个子矩阵a，当第一子块是
Figure PCTCN2022074851-appb-000008
时，1个子矩阵a位于第一生成矩阵的左下角。
第三方面，提供一种通信装置，该装置可以包括用于执行第一方面或第一方面任一种可能实现方式中的各个模块/单元，或者还可以包括用于执行第二方面或第二方面任一种可能实现方式中的各个模块/单元。比如，处理单元和输入输出单元。
示例性的，该装置包括用于执行第一方面或第一方面任一种可能实现方式中的各个模块/单元时，所述处理单元，用于获取第一待编码向量；所述处理单元，还用于对所述第一待编码向量进行第一编码，得到第二待编码向量；基于第一生成矩阵对所述第二待编码向量进行第二编码，得到编码后的码字；其中，第一生成矩阵包括至少N+1个子矩阵a，其中的N个子矩阵a位于所述第一生成矩阵的主对角线上，所述第一生成矩阵是块上三角矩阵，或者所述第一生成矩阵是块下三角矩阵，其中a是大小为2 m*2 m的极化码polar核矩阵，m是自然数N是自然数；所述输入输出单元，用于发送所述编码后的码字。
在一种可能的实现方式中，所述块上三角矩阵中上三角的元素都是a，所述块下三角矩阵中下三角的元素都是a。
在一种可能的实现方式中，所述第一生成矩阵包含K个第一子块，所述K个第一子块位于所述第一生成矩阵的主对角线上，相邻的第一子块之间有部分重叠，K是大于等于2，且大于等于N的整数；每个第一子块是
Figure PCTCN2022074851-appb-000009
或
Figure PCTCN2022074851-appb-000010
在一种可能的实现方式中，相邻的第一子块之间重叠部分为a。
在一种可能的实现方式中所述K个第一子块包含N个子矩阵a，当所述第一子块是
Figure PCTCN2022074851-appb-000011
时，1个子矩阵a位于所述第一生成矩阵的右上角。
在一种可能的实现方式中，所述K个第一子块包含N个子矩阵a，当所述第一子块是
Figure PCTCN2022074851-appb-000012
时，1个子矩阵a位于所述第一生成矩阵的左下角。
在一种可能的实现方式中，所述处理单元还用于确定待编码信息比特包含的第二子块的数量；基于码字的总码率和所述第二子块的数量，确定所述待编码信息比特包含的每一个第二子块的码率；其中，每一个第二子块的码率不同；基于所述每一个第二子块的码率确定第一待编码向量；所述第一待编码向量包含q个第二子块，q是大于0的整数。
示例性的，该装置包括用于执行第二方面或第二方面任一种可能实现方式中的各个模块/单元时，所述输入输出单元，用于接收码字；所述码字是基于第一生成矩阵编码得到的；所述处理单元，用于根据所述第一生成矩阵对所述码字进行译码。其中，第一生成矩阵包括至少N+1个子矩阵a，其中的N个子矩阵a位于所述第一生成矩阵的主对角线上，所述第一生成矩阵是块上三角矩阵，或者所述第一生成矩阵是块下三角矩阵，其中a是大小为2 m*2 m的极化码polar核矩阵，m是自然数N是自然数。
在一种可能的实现方式中，所述块上三角矩阵中上三角的元素都是a，所述块下三角矩阵中下三角的元素都是a。
在一种可能的实现方式中，所述第一生成矩阵包含K个第一子块，所述K个第一子块位于所述第一生成矩阵的主对角线上，相邻的第一子块之间有部分重叠，K是大于等于2，且大于等于N的整数；每个第一子块是
Figure PCTCN2022074851-appb-000013
或
Figure PCTCN2022074851-appb-000014
在一种可能的实现方式中，相邻的第一子块之间重叠部分为a。
在一种可能的实现方式中，所述K个第一子块包含N个子矩阵a，当所述第一子块是
Figure PCTCN2022074851-appb-000015
时，1个子矩阵a位于所述第一生成矩阵的右上角。
在一种可能的实现方式中，所述K个第一子块包含N个子矩阵a，当所述第一子块是
Figure PCTCN2022074851-appb-000016
时，1个子矩阵a位于所述第一生成矩阵的左下角。
第四方面，提供了一种通信装置，通信装置包括处理器和收发机。收发机执行第一方面或第一方面任一种可能实现方式中方法的收发步骤，或者执行第二方面或第二方面任一种可能实现方式中方法的收发步骤。控制器运行时，处理器利用控制器中的硬件资源执行第一方面或第一方面任一种可能实现方式中方法的除收发步骤以外的处理步骤，或者执行第二方面或第二方面任一种可能实现方式中方法的除收发步骤以外的处理步骤。
在一种可能的实现方式中，通信装置还包括存储器。该存储器可以位于装置内部，或者也可以位于装置外部，与所述装置相连。
在一种可能的实现方式中，存储器可以与处理器集成在一起。
第五方面，提供了一种芯片，该芯片包括逻辑电路和通信接口。
在一种设计中，逻辑电路用于获取第一待编码向量，以及对第一待编码向量进行第一编码，得到第二待编码向量。基于第一生成矩阵对第二待编码向量进行第二编码，得到编码后的码字。所述通信接口用于输出编码后的码字。
在一种设计中，所述通信接口用于输入编码后的码字。所述逻辑电路用于根据第一生成矩阵对所述编码后的码字进行译码。
第六方面，本申请提供一种计算机可读存储介质，计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各方面的方法。
第七方面，本申请提供了一种存储指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面的方法。
第八方面，本申请提供一种通信系统，包括至少一个上述的终端设备和至少一个上述的网络设备。
另外，第二方面至第八方面的有益效果可以参见如第一方面所示的有益效果。
附图说明
图1为polari编码示意图；
图2为本申请实施例提供的通信系统的示意图；
图3为本申请实施例提供的编码方法和译码方法的示例性流程图；
图4A为本申请实施例提供的移位寄存器的示意图之一；
图4B为本申请实施例提供的移位寄存器的示意图之一；
图5A为本申请实施例提供的第一待编码向量的分组示意图之一；
图5B为本申请实施例提供的第一待编码向量的分组示意图之一；
图5C为本申请实施例提供的第一待编码向量的分组示意图之一；
图5D为本申请实施例提供的第一待编码向量的分组示意图之一；
图5E为本申请实施例提供的第一待编码向量的分组示意图之一；
图6A为本申请实施例提供的子矩阵a的示意图之一；
图6B为本申请实施例提供的子矩阵a的示意图之一；
图7A为本申请实施例提供的第一生成矩阵的示意图之一；
图7B为本申请实施例提供的第一生成矩阵的示意图之一；
图8A为本申请实施例提供的译码性能示意图之一；
图8B为本申请实施例提供的译码性能示意图之一；
图9A为本申请实施例提供的第一子块的示意图之一；
图9B为本申请实施例提供的第一生成矩阵的示意图之一；
图10A为本申请实施例提供的第一子块的示意图之一；
图10B为本申请实施例提供的第一生成矩阵的示意图之一；
图11A为本申请实施例提供的第一生成矩阵的示意图之一；
图11B为本申请实施例提供的第一生成矩阵的示意图之一；
图12A为本申请实施例提供的译码性能示意图之一；
图12B为本申请实施例提供的译码性能示意图之一；
图13A为本申请实施例提供的译码过程示意图之一；
图13B为本申请实施例提供的译码过程示意图之一；
图14为本申请实施例的发送码块的耦合关系示意图；
图15为本申请实施例提供的装置的结构示意图；
图16为本申请实施例提供的编码装置示意图之一；
图17为本申请实施例提供的译码装置示意图之一；
图18为本申请实施例提供的编码装置示意图之一；
图19为本申请实施例提供的译码装置示意图之一。
具体实施方式
在通信技术领域，通信设备(例如终端设备、基站等)可以通过极化码(polar码)的方式进行信道编码。以下，通过如下两种方式对polar编码进行介绍。
方式一：通过生成矩阵对待编码比特进行编码。
其中，
Figure PCTCN2022074851-appb-000017
参阅图1，
Figure PCTCN2022074851-appb-000018
为一个行向量，
Figure PCTCN2022074851-appb-000019
N为码长，N为大于或等于1的整数。u i为编码前的比特，i为1至N之间的整数。
Figure PCTCN2022074851-appb-000020
中包括信息比特和/或冻结比特，即，u i可以为信息比特或者冻结比特。信息比特为用于携带信息的比特。冻结比特为填充比特，冻结比特通常可以为0。
G N为生成矩阵，G N为N*N的矩阵，
Figure PCTCN2022074851-appb-000021
或者
Figure PCTCN2022074851-appb-000022
其中，B N为一个N*N的转置矩阵，例如，B N可以为比特转置(bit reversal)矩阵。
Figure PCTCN2022074851-appb-000023
Figure PCTCN2022074851-appb-000024
为log 2(N)个矩阵F 2的克罗内克(kronecker)乘积。上述所涉及的加法和乘法均为二进制伽罗华域(galois field)上的操作。还可以将G N称为生成矩阵核。
方式二：通过编码示意图介绍polar编码过程。
参见图1，该编码图对应的编码码长为8，每一行中的每一个圆圈表示圆圈所在行的 比特与圆圈所达行之间的一次求和，圆圈右侧的比特即为求和结果。举例来说，第一个冻结比特所在行的第一个圆圈是指将圆圈所在行即第一行的冻结比特0，与圆圈所达行即第二行的比特0求和，求和结果为0。
目前，由于polar编码能够被严格证明达到信道容量的信道编码方案，具有高性能，较低复杂度，匹配方式灵活等特点。目前已经被第三代合作计划(3 rd generation partnership project，3GPP)确定成为5G控制信道增强移动宽带(enhanced mobile broadband，eMBB)场景控制信道编码方案。目前主流的polar码译码方法可按其译码时序分为两类，即polar码时序译码和polar码非时序译码。所谓polar码时序译码，是指译码器根据polar设计的天然时序性按比特位逐位进行译码。而polar码非时序译码，是指译码器根据polar码的其他结构(如Taner graph，Trelis graph等)并行输出译码结果。目前主要的polar码时序译码算法有逐次抵消(successive cancellation，SC)译码，逐次抵消列表(successive cancellation list，SCL)译码，连续消除堆栈(successive cancellation stack，SCS)译码和加上循环冗余校验之后的逐次抵消列表(cyclic redundancy check-aided successive cancellation list，CA-SCL)译码等。而非时序译码方法主要有置信传播译码(belief propagation，BP)译码等。就译码性能而言，SC译码最差，但是译码延迟有所提升。BP译码略好于SC译码。SCL译码较前者有很大提升，CA-SCL可以使polar码的性能低密度奇偶校验码(low density parity check code，LDPC)码和涡轮码(turbo code)更好。因此目前实际系统中主要采用SCL译码和CA-SCL译码。
polar码时序译码的优点是和polar码的设计兼容，理论分析很方便，缺点是由于其逐位输出的特性，译码延迟较大，对实时性要求较高的通信系统不适合。polar码非时序译码则相反，因为可以一次性输出多个比特，译码延迟较小，但是因其跟polar码的设计不完全匹配，会在译码性能上带来一定的损失。但通过合理的设计，可以将这部分损失尽可能的减小。
有鉴于此，本申请实施例提供了一种编码和译码方法，用来降低polar编译码的复杂度以及提升polar编译码的性能。本申请实施例中提供了多种生成矩阵，用来对待编码比特进行编码。上述多种生成矩阵中可以将邻近的码块耦合起来，将短码耦合成长码，在提升编码增益的前提下，维持低复杂度的译码。
本申请实施例可以应用于多种采用polar编码的领域，例如数据存储领域、光网络通信领域和无线通信领域等等。前述无线通信领域可以包括但不限于5G通信系统、未来的通信系统(如6G通信系统)、卫星通信系统、窄带物联网系统(narrow band-internet of things，NB-IoT)、全球移动通信系统(global system for mobile communications，GSM)、增强型数据速率GSM演进系统(enhanced data rate for GSM evolution，EDGE)、宽带码分多址系统(wideband code division multiple access，WCDMA)、码分多址2000系统(code division multiple access，CDMA2000)、时分同步码分多址系统(time division-synchronization code division multiple access，TD-SCDMA)，长期演进系统(long term evolution，LTE)以及5G移动通信系统的三大应用场景eMBB，超高可靠与低延迟的通信(ultra reliable low latency communication，URLLC)以及大规模机器通信(massive machine-type communications，mMTC)。
下面结合图2，介绍本申请实施例提供的编码和译码方法所适用的通信系统。参见图2，通信系统200包括发送设备201和接收设备2102。其中，发送设备201可以是网络设 备或者可以是终端设备，接收设备202可以是网络设备也可以是终端设备。可选的，当发送设备201是网络设备时，接收设备202可以是终端设备；当接收设备202是网络设备时，发送设备201可以是终端设备。
其中，发送设备201可以包括编码器，发送设备201可以通过编码器对待编码比特进行polar编码，并输出编码后的码字。编码后的码字经过速率匹配、交织以及调制后可以在信道上传输至接收设备202。其中，接收设备202可以包括译码器，接收设备202可以接收并解调来自发送设备201的信号，接收设备202可以通过译码器对接收信号进行译码。
本申请涉及的终端设备，包括向用户提供语音和/或数据连通性的设备，具体的，包括向用户提供语音的设备，或包括向用户提供数据连通性的设备，或包括向用户提供语音和数据连通性的设备。例如可以包括具有无线连接功能的手持式设备、或连接到无线调制解调器的处理设备。该终端设备可以包括用户设备(user equipment，UE)、无线终端设备、移动终端设备、设备到设备通信(device-to-device，D2D)终端设备、车到一切(vehicle to everything，V2X)终端设备、机器到机器/机器类通信(machine-to-machine/machine-type communications，M2M/MTC)终端设备、物联网(internet of things，IoT)终端设备、订户单元(subscriber unit)、订户站(subscriber station)，移动站(mobile station)、远程站(remote station)、接入点(access point，AP)、远程终端设备(remote terminal)、接入终端设备(access terminal)、用户终端设备(user terminal)、用户代理(user agent)、或用户装备(user device)、卫星、无人机、气球、飞机等。例如，可以包括移动电话(或称为“蜂窝”电话)，具有移动终端设备的计算机，便携式、袖珍式、手持式、计算机内置的移动装置等。例如，个人通信业务(personal communication service，PCS)电话、无绳电话、会话发起协议(session initiation protocol，SIP)话机、无线本地环路(wireless local loop，WLL)站、个人数字助理(personal digital assistant，PDA)、等设备。还包括受限设备，例如功耗较低的设备，或存储能力有限的设备，或计算能力有限的设备等。例如包括条码、射频识别(radio frequency identification，RFID)、传感器、全球定位系统(global positioning system，GPS)、激光扫描器等信息传感设备。作为示例而非限定，在本申请实施例中，该终端设备还可以是可穿戴设备。可穿戴设备也可以称为穿戴式智能设备或智能穿戴式设备等，是应用穿戴式技术对日常穿戴进行智能化设计、开发出可以穿戴的设备的总称。而如上介绍的各种终端设备，如果位于车辆上(例如放置在车辆内或安装在车辆内)，都可以认为是车载终端设备，车载终端设备例如也称为车载单元(on-board unit，OBU)。
本申请所涉及的网络设备，例如包括接入网(access network，AN)设备，例如基站(例如，接入点)，可以是指接入网中在空口通过一个或多个小区与无线终端设备通信的设备，或者例如，一种车到一切(vehicle-to-everything，V2X)技术中的网络设备为路侧单元(road side unit，RSU)。网络设备可以包括长期演进(long term evolution，LTE)系统或高级长期演进(long term evolution-advanced，LTE-A)中的演进型基站(NodeB或eNB或e-NodeB，evolutional Node B)，或者也可以包括演进的分组核心网络(evolved packet core，EPC)、第五代移动通信技术(the 5th generation，5G)、新空口(new radio，NR)系统(也简称为NR系统)中的下一代节点B(next generation node B，gNB)或者也可以包括云接入网(cloud radio access network，Cloud RAN)系统中的集中式单元(centralized unit，CU)和分布式单元(distributed unit，DU)，卫星、无人机、气球和飞机等，本申请实施例并不限定。
参阅图3，为本申请实施例提供的编码和译码方法的示例性流程图，可以包括以下步骤：
步骤301、发送设备获取第一待编码向量。
其中，第一待编码向量可以包括信息比特和冻结比特。发送设备可以根据Y个待编码比特对应的Y个子信道的可靠度，确定Y个待编码比特的位置，继而确定第一待编码向量。其中，发送设备可以在Y个待编码比特对应的多个子信道中选择可靠度最高的Y个子信道对应的位置。在确定Y个子信道的位置之后，在Y个子信道的位置填充待编码比特作为信息比特，在其它位置填充冻结比特，得到第一待编码向量。其中，第一待编码向量可以包括Y’个比特，Y’个比特可以包括Y个信息比特和Y’-Y个冻结比特。Y是正整数，且小于等于Y’，Y’是正整数。
例如，假设编码长度为8，待编码比特的数量为4。其中，假设8个子信道中可靠度最高的子信道分别为：子信道3、子信道5、子信道7和子信道8，则子信道3、子信道4、子信道7和子信道8对应的位置用于承载信息比特，其它子信道用于承载冻结比特。则待编码序列可以为00101011，其中，1表示信息比特，0表示冻结比特。
步骤302、发送设备对第一待编码向量进行第一编码，得到第二待编码向量。
这里的第一编码可以包括外码编码。广义地说，外码编码可以表示为第一待编码向量与上三角矩阵相乘，该上三角矩阵的对角线为全1，对角线右上角可任意取值，对角线左下角全为0，这种统一的外码称为预变换(pre-transformation)编码。具体地，发送设备可以采用卷积码(convolutional codes，CC)，校验码(parity check，PC)、广义循环冗余校验码(generalized CRC)或者其他分组码对第一待编码向量进行外码编码。其中，发送设备可以将第一待编码向量的信息比特和冻结比特分别通过对应的移位寄存器，从而实现对第一待编码向量进行外码编码。以下，以移位寄存器的多项式0x25为例，分别对不同的分组码进行说明。
1、卷积码外码(CC)：
参阅图4A，采用卷积码进行外码编码时，移位寄存器示意图。其中，in解释为输入，out解释为输出。信息比特的位置输入为第i个信息比特ui，输出为异或比特值。冻结比特的位置输入为0，输出为异或比特值。
2、广义CRC外码(CRC)：
参阅图4B，采用广义CRC码进行外码编码时，移位寄存器示意图。其中，in解释为输入，out解释为输出。信息比特的位置输入为第i个信息比特ui，输出为第i个信息比特ui。冻结比特的位置输入为第0位寄存器的值(reg[0])，输出为第0位寄存器的值。
需要说明的是，与普通CRC不同，这里CRC比特的位置可以在任意冻结比特位置中选取，无需在末尾。
3、校验码外码(PC)：
参阅图4B，采用校验码进行外码编码时，移位寄存器示意图。其中，in解释为输入，out解释为输出。信息比特的位置输入为第i个信息比特ui，输出为第i个信息比特ui。冻结比特的位置输入为0，输出为第0位寄存器的值。
本申请实施例中的外码编码是将所有码块的信息比特串起来，一起进行外码编码，使得当前码块的外码编码结果受前一码块影响，也会继续影响下一码块的外码编码结果。为了降低译码复杂度，外码编码可以跳过每个码块中第一个信息比特位置之前的所有冻结比 特位置，在这些位置上述移位寄存器也不移动，即等价地将每个码块中第一个信息比特位置之前的所有冻结比特位置的值置零或者任意已知的常数。
此外，外码编码可以分组独立进行，在每组编码前，按上述所示的方法初始化移位寄存器。分组和分组之间可以重叠(overlapping)，也可以不重叠(non-overlapping)，如果重叠，则前一组寄存器的输出作为新的一组寄存器的输入。
以下，通过附图5A-5E对不同的分组方式进行介绍。假设第一待编码向量包括8个比特，分别为u1，u2，u3，u4，u5，u6，u7和u8。
参阅图5A，发送设备可以将第一待编码向量中每一个比特作为一个分组，再对每一个分组进行外码编码。如图5A所示，每一个组的比特数为1且分组之间无重叠。发送设备可以对8个分组进行外码，得到第二待编码向量包括8个比特分别为v1，v2，v3，v4，v5，v6，v7，v8。
参阅图5B，发送设备可以将第一待编码向量中每两个比特作为一个分组，再对每一个分组进行外码编码。如图5B所示，每一个组的比特数为2且分组之间无重叠。发送设备可以对4个分组进行外码，得到第二待编码向量包括8个比特分别为v1，v2，v3，v4，v5，v6，v7，v8。
参阅图5C，发送设备可以将第一待编码向量中每两个比特作为一个分组，再对每一个分组进行外码编码。如图5C所示，每一个组的比特数为2且分组之间有重叠。发送设备可以对7个分组进行外码，得到第二待编码向量包括8个比特分别为v1，v2，v3，v4，v5，v6，v7，v8。
参阅图5D，发送设备可以将第一待编码向量中每四个比特作为一个分组，再对每一个分组进行外码编码。如图5D所示，每一个组的比特数为4且分组之间有重叠。发送设备可以对2个分组进行外码，得到第二待编码向量包括8个比特分别为v1，v2，v3，v4，v5，v6，v7，v8。
参阅图5E，发送设备可以将第一待编码向量中每8个比特作为一个分组，再对每一个分组进行外码编码。如图5E所示，每一个组的比特数为8且分组之间无重叠。发送设备可以对1个分组进行外码，得到第二待编码向量包括8个比特分别为v1，v2，v3，v4，v5，v6，v7，v8。
需要说明的是，第一编码还可以包括交织的操作。例如，发送设备可以对第一待编码向量交织后，进行外码编码；或者，发送设备可以对第一待编码向量外码编码后，进行交织。
步骤303、发送设备基于第一生成矩阵对第二待编码向量进行第二编码，得到编码后的码字。
这里的第一生成矩阵可以包括至少一个N+1个子矩阵a。其中，其中的N个子矩阵a可以位于第一生成矩阵的主对角线上。上述第一生成矩阵可以是块上三角矩阵，或者可以是块下三角矩阵。其中a是大小为2 m*2 m的极化码polar核矩阵，m是自然数N是自然数。以下，对子矩阵a进行解释。
子矩阵a中可以包含polar核G N，以及0元素。其中，polar核G N可以分布于子矩阵a的左下角，并且可以成三角形分布。polar核G N可以构成三角的边。以下，分别以子矩阵a为2*2大小的polar核矩阵和4*4大小的polar核矩阵为例进行说明。需要说明的是，子矩阵a还可以是8*8、16*16或2 m*2 m大小的polar核矩阵。可选的，子矩阵a也可以是 polar核G N。
参阅图6A，子矩阵a可以是2*2的polar核矩阵。子矩阵a可以是
Figure PCTCN2022074851-appb-000025
参阅图6B，子矩阵a可以是4*4的polar核矩阵。子矩阵a可以是
Figure PCTCN2022074851-appb-000026
以下，对本申请实施例中的第一生成矩阵进行说明，第一生成矩阵根据不同的耦合方式可以分为以下三种。
第一种：三角耦合。
其中，三角耦合可以是理解为第一生成矩阵中子矩阵a成三角形分布。应理解，子矩阵a可以铺满该三角形，或者也可以组成上述三角形的边。本申请实施例中，以三角形a铺满该三角形为例进行说明。
情况1：第一生成矩阵为上三角矩阵。
为了支持1-pass译码从第一个子块开始启动，第一个子块需要能独立译码，不能与其它子块码字叠加。因此耦合polar矩阵需要写成上三角形式，如图7A所示。图7A中以第一编码向量包括8个子块为例。每一个子块中可以包含多个信息比特和多个冻结比特。
其中，发送设备可以按照子信道的可靠度依次填入信息比特和冻结比特，得到多个M长信息向量ui。其中，一个M长信息向量ui可以认为是一个第二子块。其次，发送设备可以对向量u进行外码编码，其总长为T*N，得到总长同为T*N的外码码字向量v。然后再将v向量与耦合polar矩阵在二进制域进行相乘。
可选的，上述编码过程也可以分解成外码编码、子块内编码和子块间耦合编码。其中，发送设备可以将子块ui进行外码编码，得到外码子码块vi。发送设备再将外码子码块vi与polar核G N相乘，得到子码字ci。发送设备可以将每一个子码字ci按照耦合方式将子码字叠加，得到最终的耦合码的码字ci’。其中，耦合方式可以如图7A所示。具体的，c1’＝c1，c2’＝c1+c2，c3’＝c1+c2+c3，c4’＝c1+c2+c3+c4，c5’＝c1+c2+c3+c4+c5，c6’＝c1+c2+c3+c4+c5+c6，c7’＝c1+c2+c3+c4+c5+c6+c7，c8’＝c1+c2+c3+c4+c5+c6+c7+c8。
情况2：第一生成矩阵为下三角矩阵。
由于需要进行似然比(log-likelihood ratio，LLR)的软解耦，因此首先从最后一个子码块开始处理，第一生成矩阵需要写成下三角形式，如图7B所示。图7B中以第一编码向量包括8个子块为例进行说明。每一个子块中可以包含多个信息比特和多个冻结比特。
其中，发送设备可以按照子信道的可靠度依次填入信息比特和冻结比特，得到M长信息向量u。其中，一个M长信息向量ui可以认为是一个第二子块。其次，发送设备可以对向量u进行外码编码，其总长为T*N，得到总长同为T*N的外码码字向量v。然后再将v向量与耦合polar矩阵在二进制域进行相乘。
可选的，上述编码过程也可以分解成外码编码、子块内编码和子块间耦合编码。其中，发送设备可以将子块ui进行外码编码，得到外码子码块vi。发送设备再将外码子码块vi与polar核G N相乘，得到子码字ci。发送设备可以将每一个子码字ci按照耦合方式将子码字叠加，得到最终的耦合码的码字ci’。其中，耦合方式可以如图7B所示。具体的，c1’＝c1+c2+c3+c4+c5+c6+c7+c8，c2’＝c2+c3+c4+c5+c6+c7+c8，c3’＝c3+c4+c5+c6+c7+c8，c4’＝c4+c5+c6+c7+c8，c5’＝c5+c6+c7+c8，c6’＝c6+c7+c8，c7’＝c7+c8，c8’＝c8。
基于上述情况1和情况2，发送设备可以基于第一生成矩阵对待编码向量进行编码，得到码字。发送设备通过上述第一生成矩阵进行编码得到的码字中，多个子块间有耦合，可以获得较高的耦合码编码增益，可以提高编码的性能。
在一种可能的实现方式中，发送设备可以在得到第一待编码向量时，发送设备可以首先确定该第一待编码向量包含的第二子块的数量。发送设备可以基于码字的总码率和上述第二子块的数量，确定每一个第二子块的码率。应理解，不同的第二子块的码率可以是不同的。发送设备可以基于每一个第二子块的码率以及第一待编码向量包含的第二子块的数量，确定第一待编码向量。
在一个示例中，发送设备可以按照预先存储的总码率和第一待编码向量包含的第二子块的数量以及每一个第二子块的码率的关系，确定每一个第二子块的码率。例如，总码长为N＝1024的码，可以分成2组，每组分成4个第二子块，则每个第二子块的码长为128，第二子块只在组内进行三角耦合，组间的第二子块没有耦合关系。若总码率为1/2，则总信息比特数为512，每个组的信息比特数为512/2＝256。由于每个组有4个第二子块，第二子块之间存在极化，因此每个第二子块的信息比特数不同，根据按照预先存储的总码率和第一待编码向量包含的第二子块的数量以及每一个第二子块的码率的关系，可以确定第1,2,3,4个第二子块的信息比特数分别为33,50,54,119。
可选的，第一待编码向量中相邻两个第二子块的码率也可以是一致的，第一待编码向量中包括至少两种不同的码率。发送设备可以根据第一待编码向量中包含的第二子块的数量以及总码率，确定每一个第二子块的码率。
根据上例，总码率、第一待编码向量包含的第二子块的数量以及每一个第二子块的码率的关系可以由总码长，总信息长，总码率，第二子块数，分组数，每组第二子块数，每个第二子块的信息长确定。具体见下列表1-表9。
表1
Figure PCTCN2022074851-appb-000027
表2
Figure PCTCN2022074851-appb-000028
表3
Figure PCTCN2022074851-appb-000029
表4
Figure PCTCN2022074851-appb-000030
表5
Figure PCTCN2022074851-appb-000031
表6
Figure PCTCN2022074851-appb-000032
表7
Figure PCTCN2022074851-appb-000033
表8
Figure PCTCN2022074851-appb-000034
表9
Figure PCTCN2022074851-appb-000035
基于上述待编码信息比特的分组和码率匹配以及构造的第一生成矩阵，本申请实施例的编码方式相较于非耦合码有0.3dB到1dB的增益。
参阅图8A，为不同编码方式的仿真效果图。图8A中，a图采用SC译码方法，b图采用SCL译码方式。以a图为例，横轴表示信噪比(signal to noise ratio，SNR)，纵轴表示误块率(Block Error Rate，BLER)。其中，图中以EsN0即发送符号和噪声的功率比的对数形式体现，以分贝dB为单位。可见，在相同信噪比的情况下，长码的误码率最低，本申请实施例的编码方式误码率略高于长码的误码率，短码的误码率最高。然而，由于长码的复杂度较高，因此本申请实施例提供的编码方式，可以降低复杂度，也可以提升编码的增益。图8A中总码长N＝512，总信息长K＝64。SC译码和SCL译码相比，SCL译码可以进一步降低误码率。本申请实施例提供的编码方式，在通过SCL进行译码时，误码率低于长码和短码的误码率。
参阅图8B，为不同编码方式的仿真效果图。图8B中，a图采用SC译码方法，b图采用SCL译码方式。以a图为例，横轴表示信噪比(signal to noise ratio，SNR)，纵轴表示误块率(Block Error Rate，BLER)。其中，图中以EsN0即发送符号和噪声的功率比的对数形式体现，以分贝dB为单位。可见，在相同信噪比的情况下，长码的误码率最低，本申请实施例的编码方式误码率略高于长码的误码率，短码的误码率最高。然而，由于长码的复杂度较高，因此本申请实施例提供的编码方式，可以降低复杂度，也可以提升编码的增益。图8B中总码长N＝1024，总信息长K＝128。SC译码和SCL译码相比，SCL译码的误码率较高于SC译码的误码率。
通过图8A和图8B可以看出，在码率相同的情况下，本申请实施例提供的三角耦合矩阵编码方式，相较于短码误码率明显较低，而相较于长码误码率相差不大，但复杂度低于长码。
在三角耦合的1-pass矩阵中，由于只使用硬比特解耦，而不是LLR解耦，每个子块的输入LLR可靠度相同，子块的polar码构造与普通polar码也无异。
在三角耦合的2-pass矩阵中，每个子码块的可靠度不同，因此构造方法和1-pass不一样。首先计算子块的整体输入可靠度，得到每个子块的码率。等价的，可以得到每个子块 的信息比特数。其次，再计算子块中每一个子信道的可靠度，这部分与原Polar码构造方法相同。
第二种：临近耦合。
其中，临近耦合的生成矩阵可以包含K个第一子块。上述K个第一子块位于第一生成矩阵的主对角线上，相邻的第一子块之间有部分重叠。这里的K大于或等于2。其中，第一子块可以是
Figure PCTCN2022074851-appb-000036
或
Figure PCTCN2022074851-appb-000037
以下，按照第一子块的情况不同，分别介绍不同的临近耦合的生成矩阵。
情况1：第一子块是
Figure PCTCN2022074851-appb-000038
参阅图9A，对本申请实施例中的第一子块进行介绍。图9A中是4*4大小的生成矩阵，该生成矩阵包含了子矩阵a和0元素。如图9A所示，该生成矩阵中包含了3个第一子块。上述3个第一子块位于第一生成矩阵的主对角线上。
为了支持1-pass译码从第一个子块开始启动，第一个子块需要能独立译码，不能与其它子块码字叠加。因此耦合Polar矩阵需要写成上三角形式，如图9B所示。图9B中以第一生成矩阵包含7个第一子块为例。其中，第一待编码向量包含8个小块，7个第二子块。
发送设备可以按照子信道的可靠度依次填入信息比特和冻结比特，得到多个M长信息向量ui。其次，发送设备可以对向量u进行外码编码，其总长为T*N，得到总长同为T*N的外码码字向量v。然后再将v向量与耦合polar矩阵在二进制域进行相乘。图9B中，第二子块1可以是u1+u2，第二子块2可以是u2+u3，第二子块3可以是u3+u4，第二子块4可以是u4+u5，第二子块5可以是u5+u6，第二子块6可以是u6+u7，第二子块7可以是u7+u8。
可选的，上述编码过程也可以分解成外码编码、子块内编码和子块间耦合编码。其中，发送设备可以将子块ui进行外码编码，得到外码子码块vi。发送设备再将外码子码块vi与polar核G N相乘，得到子码字ci。发送设备可以将每一个子码字ci按照耦合方式将子码字叠加，得到最终的耦合码的码字ci’。其中，耦合方式可以如图9B所示。具体的，c1’＝c1，c2’＝c1+c2，c3’＝c2+c3，c4’＝c3+c4，c5’＝c4+c5，c6’＝c5+c6，c7’＝c6+c7，c8’＝c7+c8。
情况2：第一子块是
Figure PCTCN2022074851-appb-000039
参阅图10A，对本申请实施例中的第一子块进行介绍。图10A中是4*4大小的生成矩阵，该生成矩阵包含了子矩阵a和0元素。如图10A所示，该生成矩阵中包含了3个第一子块。上述3个第一子块位于第一生成矩阵的主对角线上。
由于需要进行LLR的软解耦，因此首先从最后一个子码块开始处理，第一生成矩阵需要写成下三角形式，如图10B所示。图10B中以第一生成矩阵包含7个第一子块为例。其中，第一待编码向量包含8个小块，7个第二子块。
发送设备可以按照子信道的可靠度依次填入信息比特和冻结比特，得到多个M长信息向量ui。其次，发送设备可以对向量u进行外码编码，其总长为T*N，得到总长同为T*N的外码码字向量v。然后再将v向量与耦合polar矩阵在二进制域进行相乘。图10B中，第二子块1可以是u1+u2，第二子块2可以是u2+u3，第二子块3可以是u3+u4，第二子块4可以是u4+u5，第二子块5可以是u5+u6，第二子块6可以是u6+u7，第二子块7可以是u7+u8。
可选的，上述编码过程也可以分解成外码编码、子块内编码和子块间耦合编码。其中，发送设备可以将子块ui进行外码编码，得到外码子码块vi。发送设备再将外码子码块vi 与polar核G N相乘，得到子码字ci。发送设备可以将每一个子码字ci按照耦合方式将子码字叠加，得到最终的耦合码的码字ci’。其中，耦合方式可以如图10B所示。具体的，c1’＝c1+c2，c2’＝c2+c3，c3’＝c3+c4，c4’＝c4+c5，c5’＝c5+c6，c6’＝c6+c7，c7’＝c7+c8，c8’＝c8。
基于上述情况1和情况2，发送设备通过上述第一生成矩阵进行编码得到的码字中，相邻的两个子块间有耦合，可以获得耦合码编码增益，可以提高编码的性能。
第三种：咬尾耦合
这里的咬尾耦合是基于临近耦合的生成矩阵确定的，可以分为以下两种情况：
情况1、第一生成矩阵是上三角形式。
其中，如果第一生成矩阵写成上三角形式，则有一个子矩阵a位于第一生成矩阵的左下角，如图11A所示。图11A中可以第一生成矩阵包含7个第一子块，每一个第一子块包含16个子矩阵a，第一生成矩阵还包含1个子矩阵a位于第一生成矩阵的左下角。
发送设备可以对多个M长信息向量ui进行外码编码，其总长为T*N，得到总长同为T*N的外码码字向量v。然后再将v向量与耦合polar矩阵在二进制域进行相乘。图11A中，第二子块1可以是u1+u2，第二子块2可以是u2+u3，第二子块3可以是u3+u4，第二子块4可以是u4+u5，第二子块5可以是u5+u6，第二子块6可以是u6+u7，第二子块7可以是u7+u8。
可选的，上述编码过程也可以分解成外码编码、子块内编码和子块间耦合编码。其中，发送设备可以将子块ui进行外码编码，得到外码子码块vi。发送设备再将外码子码块vi与polar核G N相乘，得到子码字ci。发送设备可以将每一个子码字ci按照耦合方式将子码字叠加，得到最终的耦合码的码字ci’。其中，耦合方式可以如图11A所示。具体的，c1’＝c1+c2，c2’＝c2+c3，c3’＝c3+c4，c4’＝c4+c5，c5’＝c5+c6，c6’＝c6+c7，c7’＝c7+c8，c8’＝c8+c1。
情况2、第一生成矩阵是下三角形式。
其中，如果第一生成矩阵写成下三角形式，则有一个子矩阵a位于第一生成矩阵的右上角，如图11B所示。图11B中可以第一生成矩阵包含7个第一子块，每一个第一子块包含16个子矩阵a，第一生成矩阵还包含1个子矩阵a位于第一生成矩阵的右上角。
发送设备可以对多个M长信息向量ui进行外码编码，其总长为T*N，得到总长同为T*N的外码码字向量v。然后再将v向量与耦合polar矩阵在二进制域进行相乘。图11B中，第二子块1可以是u1+u2，第二子块2可以是u2+u3，第二子块3可以是u3+u4，第二子块4可以是u4+u5，第二子块5可以是u5+u6，第二子块6可以是u6+u7，第二子块7可以是u7+u8。
可选的，上述编码过程也可以分解成外码编码、子块内编码和子块间耦合编码。其中，发送设备可以将子块ui进行外码编码，得到外码子码块vi。发送设备再将外码子码块vi与polar核G N相乘，得到子码字ci。发送设备可以将每一个子码字ci按照耦合方式将子码字叠加，得到最终的耦合码的码字ci’。其中，耦合方式可以如图11A所示。具体的，c1’＝c1+c8，c2’＝c1+c2，c3’＝c2+c3，c4’＝c3+c4，c5’＝c4+c5，c6’＝c5+c6，c7’＝c6+c7，c8’＝c7+c8。
在一种可能的实现方式中，基于临近耦合和咬尾耦合的生成矩阵进行编码的情况下，发送设备在得到第一待编码向量时，发送设备可以确定该第一待编码向量包含的第二子块的数量。发送设备可以基于码字的总码率和第二子块的数量，确定每一个第二子块的码率。其中，每一个第二子块的码率可以不同。发送设备可以基于每一个第二子块的码率确定第一待编码向量。
在一个示例中，发送设备可以按照预先存储的总码率和第二子块的数量以及每一个第二子块的码率的关系，确定第二子块的码率。例如，总码长为N＝1024的码，可以分成2组，每组分成4个小块，则小块的码长为128。其中，相邻的两个小块组成一个子块，子块只在组内进行邻近耦合，组间的子块没有耦合关系。若总码率为1/2，则总信息比特数为512，每个组的信息比特数为512/2＝256。由于每个组有4个小块，小块之间存在极化，因此每个小块的信息比特数不同，根据前文所述的码构造方法，可以确定第1,2,3,4个小块的信息比特数分别为12,72,80,92。那么子块1的信息比特数为12+72＝84，子块2的信息比特数为72+80＝152，子块3的信息比特数为80+92＝172。
可选的，第一待编码向量中相邻两个第二子块的码率也可以是一致的，第一待编码向量中包括至少两种不同的码率。发送设备可以根据第一待编码向量中包含的第二子块的数量以及总码率，确定每一个第二子块的码率。
根据上例，总码率和第二子块的数量以及每一个第二子块的码率的关系可以由总码长，总信息长，总码率，小块数，分组数，每组第二子块数和每个小块的信息长确定。具体见下列表1-表9。
表10
Figure PCTCN2022074851-appb-000040
表11
Figure PCTCN2022074851-appb-000041
表12
Figure PCTCN2022074851-appb-000042
表13
Figure PCTCN2022074851-appb-000043
表14
Figure PCTCN2022074851-appb-000044
表15
Figure PCTCN2022074851-appb-000045
表16
Figure PCTCN2022074851-appb-000046
表17
Figure PCTCN2022074851-appb-000047
表18
Figure PCTCN2022074851-appb-000048
基于上述待编码信息比特的分组和码率匹配以及构造的第一生成矩阵，本申请实施例的编码方式相较于非耦合码有0.3dB到1dB的增益。
在临近耦合或咬尾耦合的1-pass矩阵中，由于只使用硬比特解耦，而不是LLR解耦，每个子块的输入LLR可靠度相同，子块的polar码构造与普通polar码也无异。
在临近耦合或咬尾耦合的2-pass矩阵中，每个子信道的可靠度不同，因此构造方法和1-pass不一样。首先计算子块的整体输入可靠度，得到每个子块的码率。等价的，可以得到每个子块的信息比特数。其次，再计算子块中每一个子信道的可靠度，这部分与原Polar码构造方法相同。
在一种可能的实现方式中，邻近耦合方案在高码率区域性能较优，而三角耦合方案在低码率区域性能较优。因此，可以以Rth为界，确定码率小于等于Rth或者大于等于Rth时，分别采用哪一种耦合方案。举例来说，如码率R<Rth或R≤Rth时，可以采用三角耦合方案，码率R≥Rth或R>Rth，可以采用邻近耦合/咬尾耦合方案。其中，Rth可以定义为1/2，7/16，9/16，3/8或5/8等中间码率。
参阅图12A，为不同编码方式的仿真效果图。图12A中，a图采用SC译码方法，b图采用SCL译码方式。以a图为例，横轴表示信噪比(signal to noise ratio，SNR)，纵轴表示误块率(Block Error Rate，BLER)。其中，图中以EsN0即发送符号和噪声的功率比的对数形式体现，以分贝dB为单位。可见，在相同信噪比的情况下，长码的误码率最低，本申请实施例的编码方式误码率略高于长码的误码率，短码的误码率最高。然而，由于长码的复杂度较高，因此本申请实施例提供的编码方式，可以降低复杂度，也可以提升编码的增益。图12A中总码长N＝514，总信息长K＝448。本申请实施例提供的编码方式，在通过SCL进行译码时，误码率与长码的误码率相差不大。SC译码和SCL译码相比，SCL译码可以进一步降低误码率。
参阅图12B，为不同编码方式的仿真效果图。图12B中，a图采用SC译码方法，b图采用SCL译码方式。以a图为例，横轴表示信噪比(signal to noise ratio，SNR)，纵轴表示误块率(Block Error Rate，BLER)。其中，图中以EsN0即发送符号和噪声的功率比的对数形式体现，以分贝dB为单位。可见，在相同信噪比的情况下，长码的误码率最低，本申请实施例的编码方式误码率略高于长码的误码率，短码的误码率最高。然而，由于长码的复杂度较高，因此本申请实施例提供的编码方式，可以降低复杂度，也可以提升编码的增益。图12A中总码长N＝1024，总信息长K＝896。SC译码和SCL译码相比，SCL译码可以进一步降低误码率。
通过图12A和图12B可以看出，在码率相同的情况下，本申请实施例提供的三角耦合矩阵编码方式，相较于短码误码率明显较低，而相较于长码误码率相差不大，但复杂度低于长码。
步骤304、发送设备将编码后的码字发送给接收设备，相应的接收设备接收来自发送设备的码字。
步骤305、接收设备对码字进行译码。
其中，接收设备对码字进行译码时，可以基于第一生成矩阵对码字进行译码。可选的，接收设备可以根据编码方式的不同，采用不同的第一生成矩阵对码字进行译码。其中，根据编码方式不同，分为以下4种情况对译码进行说明。
情况1、三角耦合矩阵的1-pass译码。
其中，三角耦合矩阵的1-pass译码的特点可以包括如下两种特点：
1、无需进行总传输长度范围内的LLR传递，只需要在临近子块之间复制部分LLR。
2、支持更低时延的窗译码：一边接收LLR一边译码，复杂度更低。
三角耦合矩阵在硬解耦时需要利用所有之前子块的译码结果，写成当前子块的待译码LLR。其中，若所有之前子块的第i个比特的异或值为0，则直接将当前子块的第i个信道接收LLR送给当前子块译码器。若所有之前子块的第i个比特的异或值为1，则将当前子块的第i个信道接收LLR的符号取反或者乘以-1后送给当前子块译码器。
在一个示例中，译码方式可以如图13A所示。其中，首先进行子块间的码字硬解耦。应理解，第一个子块无需码字硬解耦。其中的子块间码字硬解耦的含义为：利用前一个子块的译码结果，写成当前子块的待译码LLR。
假设当前子块为第t个子块，之前所有子块的第i个比特的异或值为xt-1,i＝c1,i+c2,i+…+ct-1,i，当前子块的信道输出LLR的第i个值为lt,i，则送入当前子块译码器的第i个LLR值为
Figure PCTCN2022074851-appb-000049
如此往复，直到译完最后一个子块。
情况2、三角耦合矩阵的2-pass译码。
其中，三角耦合矩阵的1-pass译码的特点可以包括如下两种特点：
1、需要在总传输长度上进行LLR传递(backward-pass)，然后逐个子块的译码结果传递(forward-pass)。
2、可以在子块之间形成极化现象，尽可能拿到部分长码增益。
但是由于三角耦合矩阵与邻近耦合矩阵不同，译码的方法也不同。如下图表示：
在一个示例中，译码方式可以如图13B所示。其中，首先进行子块间的码字软解耦的正向传递。应理解，最后一个子块无需码字软解耦。假设上一个子块的第i个码字比特为ct-1,i，上一个子块的正向解耦LLR的第i个值为lt-1,i，当前子块的信道接收LLR的第i个值为l’t,i，则当前子块的正向解耦LLR的第i个值为lt,i＝g(ct-1,i,lt-1,i,l’t,i)。假设当前子块的正向解耦LLR的第i个值为lt,i＝g(ct-1,i,lt-1,i,l’t,i)，下一个子块的信道接收LLR的第i个值为l’t+1,i，则该子块的反向解耦LLR的第i个值为lt,i＝f(lt,i,l’t+1,i)。将当前子块的反向解耦LLR送入当前子块译码器，如此往复，直到译完最后一个子块。
情况3、邻近耦合和咬尾耦合矩阵的1-pass译码。
其中，邻近耦合和咬尾耦合矩阵的1-pass译码可以包括如下两种特点：
1、无需进行总传输长度范围内的LLR传递，只需要在临近子块之间复制部分LLR。
2、支持更低时延的窗译码：一边接收LLR一边译码，复杂度更低。
在一个示例中，译码方式可以如图13A所示。其中，首先进行子块间的码字硬解耦。应理解，第一个子块无需码字软解耦。假设上一个子块的第i个比特为ci，当前子块的信道输出LLR的第i个值为li，则送入当前子块译码器的第i个值为
Figure PCTCN2022074851-appb-000050
如此往复，直到译完最后一个子块。其中，若前一个子块的第i个比特为0，则直接将当前子块的第i个信道接收LLR送给当前子码译码器。若前一个子块的第i个比特为1，则将当前子块的第i个信道接收LLR的符号取反或者乘以-1后送给当前子码译码器。
情况4、邻近耦合和咬尾耦合矩阵的2-pass译码。
其中，邻近耦合和咬尾耦合矩阵的2-pass译码可以包括如下两种特点：
1、需要在总传输长度上进行LLR传递(backward-pass)，然后逐个子块的译码结果传递(forward-pass)。
2、可以在子块之间形成极化现象，尽可能拿到部分长码增益。
在一个示例中，译码方式可以如图13B所示。其中，首先进行子块间的码字软解耦的反向传递。应理解，最有一个子块无需码字软解耦。假设当前子块的信道接收LLR的第i个值为l’t,i，下一个子块的信道接收LLR的第i个值为l’t+1,i，则该子块的反向解耦LLR的第i个值为lt,i＝f(l’t,i,l’t+1,i)。假设上一个子块的第i个码字比特为ct-1,i，上一个子块的信道接收LLR的第i个值为l’t-1,i，当前子块的反向解耦LLR的第i个值为lt,i，则正向解耦LLR的第i个值为lt,i＝g(ct-1,i,l’t-1,i,lt,i)。将当前子块的正向解耦LLR送入当前子块译码器，如此往复，直到译完最后一个子块。
在一种可能的实现方式，发送设备与接收设备可以分别确定外码种类、外码多项式、外码分组数、耦合度、耦合分组数、耦合关系、耦合矩阵的选择以及其他的耦合相关参数。其中，耦合相关参数可以由场景和码字的参数等确定。
可选的，发送设备或接收设备可以首先由码长等参数或者应用场景，确定具体的耦合方案，包含前文所示的外码、分组数、耦合度和耦合方式等耦合相关参数。其中，发送设备可以与接收设备通过信令协商上述耦合相关参数，或者发送设备可以向接收设备指示耦合相关参数，或者接收设备可以向发送设备指示耦合相关参数。可选的，耦合相关参数也可以是通信协议规定的，本申请不做具体限定。然后收发双方按照约定的方式进行编译码通信。
在一个示例中，发送设备与接收设备可以通过无线资源控制(radio resource control，RRC)消息，协商或指示耦合相关参数。可选的，RRC消息可以新增一部分字段，用来承载编码配置信息。该编码配置信息中可以包含上述多个耦合相关参数。
另一个示例中，发送设备或接收设备可以通过下行控制信息(downlink control information，DCI)指示耦合相关参数。可选的，DCI的格式可以如下表19所示。
表19
Figure PCTCN2022074851-appb-000051
在一种可能的实现方式中，可以将待编码比特分成若干组，每组中包含指定数量的码块(code block，CB)。每组中的码块之间可以有耦合关系，如图14所示。其中，码块之间的耦合关系可以参见上述三种编码方式中的相关描述，图14仅是示例性的给出了一种耦合方式。
在一个示例中，如果待编码比特数量B大于某个阈值K cb，则将B个待编码比特进行分段(segmentation)，且为每段信息比特上加上属于该CB的CRC。假设CRC为L长，L>0。将添加CRC比特后的待编码比特数量为B’，其流程如下：
If B<＝K cb
CRC长度＝0
CB数量：C＝1
B’＝B
编码：B’信息比特→N码字比特
Else
CRC长度＝L
CB数量：
Figure PCTCN2022074851-appb-000052
B’＝B+CB数量×L
For r＝0:C-1
对第r个CB进行子块内编码：c r＝CB_encode(u r)
End for
For r＝0:C-1
对第r个CB进行子块间(耦合)编码：c’ r＝Couple_encode(c r,c r1,c r2,…c rl)
(其中c r1,c r2,…c rl为与第r个CB存在耦合关系的子块)
End forc'2＝couple_encode(c 2,c 1)＝c 2+c 1
End if
经过分段后，将C段信息向量u 0,u 1,…,u C-1分别编码后，得到的码字向量为c 0,c 1,…,c C-1，其中第r个CB的码字比特为c r＝[c r0,c r1,…,c r(Nr-1)]，其中Nr为第r个CB的子块码字比特数量。然后对C个CB进行子块间编码，得到的码字向量为c’ 0,c’ 1,…,c’ c-1，其中第r个CB的码字比特为c’ r＝[c’ r0,c’ r1,…,c’ r(Mr-1)]，其中Mr为第r个CB的耦合码字比特数量。其中c r1,c r2,…c rl为与第r个CB存在耦合关系的子块，因此第r个CB的耦合码字由第r 1,r 1,…,r l个CB的子块码字经过耦合编码产生。上述r大于等于1。
另一个示例中，如果待编码比特数量B大于某个阈值K cb，则将B个待编码比特进行分段(segmentation)，且为每段信息比特上加上属于该CB的CRC。假设CRC为L长，L>0。将添加CRC比特后的待编码比特数量为B’，其流程如下：
If B<＝K cb
CRC长度＝0
CB数量：C＝1
B’＝B
编码：B’信息比特→N码字比特
Else
CRC长度＝L
CB数量：
Figure PCTCN2022074851-appb-000053
B’＝B+CB数量×L
对C个CB进行码率(信息比特)分配：{K 1,K 2,…,K C}＝Rate_allocation(B’,C)
For r＝0:C-1
对第r个CB进行子块内编码：c r＝CB_encode(u r)c' 3＝couple_encode(c 3,c 2,c 1)＝c 3+c 2+c 1
End for
For r＝0:C-1
对第r个CB进行子块间(耦合)编码：c’ r＝Couple_encode(c r,c r1,c r2,…c rl)
(其中c r1,c r2,…c rl为与第r个CB存在耦合关系的子块)
End for
End if
经过分段后，首先对C个CB进行码率(信息比特)分配，得到各个子块的信息比特数量分别为K 1,K 2,…,K C，其中为第r个CB的信息比特数量为K r。其中，Kr可以包含CRC比特或者可以不包含CRC比特。K 1+K 2+…+K C＝B’。将C段信息向量u 0,u 1,…,u C-1分别编码后，得到的码字向量为c 0,c 1,…,c C-1，其中第r个CB的码字比特为c r＝[c r0,c r1,…,c r(Nr-1)]，其中Nr为第r个CB的子块码字比特数量。然后对C个CB进行子块间编码，得到的码字向量为c’ 0,c’ 1,…,c’ c-1，其中第r个CB的码字比特为c’ r＝[c’ r0,c’ r1,…,c’ r(Mr-1)]，其中Mr为第r个CB的耦合码字比特数量。其中c r1,c r2,…c rl为与第r个CB存在耦合关系的子块，因此第r个CB的耦合码字由第r 1,r 1,…,r l个CB的子块码字经过耦合编码产生。
基于与上述通信方法的同一技术构思，如图15所示，提供了一种装置1500。该装置1500可以包括处理单元1520和输入输出单元1510。可选的，还包括存储单元1530；处理单元1520可以分别与存储单元1530和输入输出单元1510相连，所述存储单元1530也可以与输入输出单元1510相连。其中，处理单元1520可以与存储单元1530集成。输入输出单元1510也可以称为收发器、收发机、收发装置等。处理单元1520也可以称为处理器，处理单板，处理模块、处理装置等。可选的，可以将输入输出单元1510中用于实现接收功能的器件视为接收单元，将输入输出单元1510中用于实现发送功能的器件视为发送单元，即输入输出单元1510包括接收单元和发送单元。输入输出单元有时也可以称为收发机、收发器、或收发电路等。接收单元有时也可以称为接收机、接收器、或接收电路等。发送单元有时也可以称为发射机、发射器或者发射电路等。
应理解，输入输出单元1510用于执行上述方法实施例中发送设备和接收设备的发送操作和接收操作，处理单元1520用于执行上述方法实施例中发送设备和接收设备上除了收发操作之外的其他操作。例如，在一种实现方式中，输入输出单元1510用于执行图3中的步骤304所示的发送设备的发送操作和接收设备的接收操作。和/或输入输出单元1510还用于执行本申请实施例中发送设备和接收设备的其他收发步骤。处理单元1520，用于执行图3中的步骤301至步骤303所示的发送设备的处理步骤和步骤305所示的接收设备的处理操作，和/或处理单元1520用于执行本申请实施例中发送设备和接收设备的其他处理步骤。
需要说明的是，本申请实施例所示的编码装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此次不再进行赘述。
所述存储单元1530，用于存储计算机程序；
示例性的，装置1500用于执行发送设备执行的步骤时，所述处理单元1520，用于获取第一待编码向量；所述处理单元1520，还用于对所述第一待编码向量进行第一编码，得到第二待编码向量；基于第一生成矩阵对所述第二待编码向量进行第二编码，得到编码后的码字；所述输入输出单元1510，用于发送所述编码后的码字。其中，第一生成矩阵可以参见如图3所示的方法实施例中的相关描述，此处不再赘述。
在一种可能的实现方式中，所述处理单元1520还用于：确定待编码信息比特包含的第二子块的数量；基于码字的总码率和所述第二子块的数量，确定所述待编码信息比特包含的每一个第二子块的码率；其中，每一个第二子块的码率不同；所述处理单元1520在获取第一待编码向量时具体用于：基于所述每一个第二子块的码率确定第一待编码向量； 所述第一待编码向量包含q个第二子块，q是大于0的整数。
示例性的，装置1500用于执行接收设备执行的步骤时，所述输入输出单元1510，用于接收码字；所述码字是基于第一生成矩阵编码得到的。所述处理单元1520，用于对所述码字进行译码。其中，第一生成矩阵可以参见如图3所示的方法实施例中的相关描述，此处不再赘述。
参阅图16，为本申请实施例提供的一种装置的硬件结构示意图。该装置1600用于实现上述方法中发送设备的功能。该装置用于实现上述方法中发送设备的功能时，该装置可以是发送设备，也可以是类似发送设备功能的芯片，或者是能够和发送设备匹配使用的装置。该装置1600：处理器1601和存储器1602。
存储器1602，用于存储计算机程序，还可以用于存储中间数据；
处理器1601，用于执行存储器存储的计算机程序，以实现上述编码方法中的各个步骤。具体可以参见前面方法实施例中的相关描述。
可选地，存储器1602既可以是独立的，也可以跟处理器1601集成在一起。在有些实施方式中，存储器1602甚至还可以位于编码装置1600之外。
当所述存储器1602是独立于处理器1601之外的器件时，所述编码装置1600还可以包括总线1603，用于连接所述存储器1602和处理器1601。
可选的，装置1600还可以进一步包括发送器。例如，发送器用于发送编码后的比特。
本实施例提供的装置1600可以为终端设备，或者也以为网络设备，可用于执行上述的编码方法，其实现方式和技术效果类似，本实施例此处不再赘述。
参阅图17，为本申请实施例提供的一种装置的硬件结构示意图。该装置1700用于实现上述方法中接收设备的功能。该装置用于实现上述方法中接收设备的功能时，该装置可以是接收设备，也可以是类似接收设备功能的芯片，或者是能够和接收设备匹配使用的装置。该装置1700：处理器1701和存储器1702。
存储器1702，用于存储计算机程序，还可以用于存储中间数据；
处理器1701，用于执行存储器存储的计算机程序，以实现上述编码方法中的各个步骤。具体可以参见前面方法实施例中的相关描述。
可选地，存储器1702既可以是独立的，也可以跟处理器1701集成在一起。在有些实施方式中，存储器1702甚至还可以位于编码装置1700之外。
当所述存储器1702是独立于处理器1701之外的器件时，所述编码装置1700还可以包括总线1703，用于连接所述存储器1702和处理器1701。
可选的，装置1700还可以进一步包括接收器。例如，接收器用于接收编码后的比特。
本实施例提供的装置1700可以为终端设备，或者也以为网络设备，可用于执行上述的编码方法，其实现方式和技术效果类似，本实施例此处不再赘述。
图18为本申请实施例提供的一种装置的结构示意图。请参见图18，该装置1800可以包括通信接口1801和逻辑电路1802。
所述逻辑电路1802用于，获取第一待编码向量；对所述第一待编码向量进行第一编码，得到第二待编码向量。以及，基于第一生成矩阵对所述第二待编码向量进行第二编码，得到编码后的码字；其中，第一生成矩阵包括至少N+1个子矩阵a，N个子码块位于所述第一生成矩阵的主对角线上，所述第一生成矩阵是块上三角矩阵，或者所述第一生成矩阵是块下三角矩阵，其中a是大小为2 m*2 m的极化码polar核矩阵，m是自然数N是自然数； 所述通信接口用于输出发送编码后的码字。
可选的，通信接口1801可以具有图15实施例中的输入输出单元1510的功能。逻辑电路1802可以具有图15实施例中的处理单元1520的功能。
可选的，逻辑电路1802可以具有图16实施例中的处理器1601的功能。逻辑电路1802还可以执行编码方法中其它的步骤。
本申请实施例提供的装置1800可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似此处不再进行赘述。
图19为本申请实施例提供的另一种装置的结构示意图。请参见图19，该装置1900可以包括通信接口1901和逻辑电路1902。
所述通信接口1901用于，输入编码后的码字；
所述逻辑电路1902用于，对所述码字进行译码。
可选的，通信接口1901可以具有图15实施例中的输入输出单元1510的功能。逻辑电路1902可以具有图15实施例中的处理单元1520的功能。
可选的，通信接口1901可以具有图17实施例中的接收器的功能。逻辑电路1902可以具有图17实施例中的处理器1701的功能。逻辑电路1902还可以执行译码方法中其它的步骤。
可选的，通信接口1901还可以输出译码结果。
本申请实施例提供的装置1900可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似此处不再进行赘述。
作为本实施例的另一种形式，提供一种计算机可读存储介质，其上存储有指令，该指令被执行时执行上述方法实施例中发送设备和接收设备的方法。
作为本实施例的另一种形式，提供一种包含指令的计算机程序产品，该指令被执行时执行上述方法实施例中发送设备和接收设备的方法。
作为本实施例的另一种形式，提供一种通信系统，该系统可以包括上述至少一个发送设备和上述至少一个接收设备。
应理解，本发明实施例中提及的处理器可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解，本发明实施例中提及的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM， SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)。
需要说明的是，当处理器为通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件时，存储器(存储模块)集成在处理器中。
应注意，本文描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应所述以权利要求的保护范围为准。

Claims (28)

  1. 一种编码方法，其特征在于，包括：
    发送设备获取第一待编码向量；
    所述发送设备对所述第一待编码向量进行第一编码，得到第二待编码向量；
    所述发送设备基于第一生成矩阵对所述第二待编码向量进行第二编码，得到编码后的码字；
    其中，所述第一生成矩阵包括至少N+1个子矩阵a，其中的N个所述子矩阵a位于所述第一生成矩阵的主对角线上，所述第一生成矩阵是块上三角矩阵，或者所述第一生成矩阵是块下三角矩阵，其中a是大小为2 m*2 m的极化码polar核矩阵，m是自然数，N是自然数；
    所述发送设备发送所述编码后的码字。
  2. 根据权利要求1所述的方法，其特征在于，所述块上三角矩阵中上三角的元素都是a，所述块下三角矩阵中下三角的元素都是a。
  3. 根据权利要求1或2所述的方法，其特征在于，所述第一生成矩阵包含K个第一子块，所述K个第一子块位于所述第一生成矩阵的主对角线上，相邻的所述第一子块之间有部分重叠，K是大于等于2，且大于等于N的整数；每个所述第一子块是
    Figure PCTCN2022074851-appb-100001
    或
    Figure PCTCN2022074851-appb-100002
  4. 根据权利要求3所述的方法，其特征在于，所述相邻的第一子块之间重叠部分为a。
  5. 根据权利要求3或4所述的方法，其特征在于，所述K个第一子块包含所述N个子矩阵a，当所述第一子块是
    Figure PCTCN2022074851-appb-100003
    时，1个所述子矩阵a位于所述第一生成矩阵的右上角。
  6. 根据权利要求3或4所述的方法，其特征在于，所述K个第一子块包含所述N个子矩阵a，当所述第一子块是
    Figure PCTCN2022074851-appb-100004
    时，1个所述子矩阵a位于所述第一生成矩阵的左下角。
  7. 根据权利要求1-5任一所述的方法，其特征在于，所述发送设备获取第一待编码向量之前，还包括：
    所述发送设备确定待编码信息比特包含的第二子块的数量；
    所述发送设备基于码字的总码率和所述第二子块的数量，确定所述待编码信息比特包含的每一个第二子块的码率；其中，每一个第二子块的码率不同；
    所述发送设备基于所述每一个第二子块的码率确定所述第一待编码向量；所述第一待编码向量包含q个第二子块，q是大于0的整数。
  8. 一种译码方法，其特征在于，包括：
    接收设备接收码字；所述码字是基于第一生成矩阵编码得到的；
    所述接收设备根据所述第一生成矩阵对所述码字进行译码；其中，所述第一生成矩阵包括至少N+1个子矩阵a，其中的N个所述子矩阵a位于所述第一生成矩阵的主对角线上，所述第一生成矩阵是块上三角矩阵，或者所述第一生成矩阵是块下三角矩阵，其中a是大小为2 m*2 m的极化码polar核矩阵，m是自然数N是自然数。
  9. 根据权利要求8所述的方法，其特征在于，所述块上三角矩阵中上三角的元素都是a，所述块下三角矩阵中下三角的元素都是a。
  10. 根据权利要求8或9所述的方法，其特征在于，所述第一生成矩阵包含K个第一子块，所述K个第一子块位于所述第一生成矩阵的主对角线上，相邻的所述第一子块之间有部分重叠，K是大于等于2，且大于等于N的整数；每个所述第一子块是
    Figure PCTCN2022074851-appb-100005
    或
    Figure PCTCN2022074851-appb-100006
  11. 根据权利要求10所述的方法，其特征在于，相邻的所述第一子块之间重叠部分为a。
  12. 根据权利要求10或11所述的方法，其特征在于，所述K个第一子块包含所述N个子矩阵a，当所述第一子块是
    Figure PCTCN2022074851-appb-100007
    时，1个所述子矩阵a位于所述第一生成矩阵的右上角。
  13. 根据权利要求10-12任一所述的方法，其特征在于，所述K个第一子块包含所述N个子矩阵a，当所述第一子块是
    Figure PCTCN2022074851-appb-100008
    时，1个所述子矩阵a位于所述第一生成矩阵的左下角。
  14. 一种通信装置，其特征在于，包括：处理单元和输入输出单元；
    所述处理单元，用于获取第一待编码向量；
    所述处理单元，还用于对所述第一待编码向量进行第一编码，得到第二待编码向量；基于第一生成矩阵对所述第二待编码向量进行第二编码，得到编码后的码字；
    其中，第一生成矩阵包括至少N+1个子矩阵a，其中的N个所述子矩阵a位于所述第一生成矩阵的主对角线上，所述第一生成矩阵是块上三角矩阵，或者所述第一生成矩阵是块下三角矩阵，其中a是大小为2 m*2 m的极化码polar核矩阵，m是自然数N是自然数；
    所述输入输出单元，用于发送所述编码后的码字。
  15. 根据权利要求14所述的装置，其特征在于，所述块上三角矩阵中上三角的元素都是a，所述块下三角矩阵中下三角的元素都是a。
  16. 根据权利要求14或15所述的装置，其特征在于，所述第一生成矩阵包含K个第一子块，所述K个第一子块位于所述第一生成矩阵的主对角线上，相邻的所述第一子块之间有部分重叠，K是大于等于2，且大于等于N的整数；每个所述第一子块是
    Figure PCTCN2022074851-appb-100009
    或
    Figure PCTCN2022074851-appb-100010
  17. 根据权利要求16所述的装置，其特征在于，所述相邻的第一子块之间重叠部分为a。
  18. 根据权利要求16或17所述的装置，其特征在于，所述K个第一子块包含所述N个子矩阵a，当所述第一子块是
    Figure PCTCN2022074851-appb-100011
    时，1个所述子矩阵a位于所述第一生成矩阵的右上角。
  19. 根据权利要求16-18任一所述的装置，其特征在于，所述K个第一子块包含所述N个子矩阵a，当所述第一子块是
    Figure PCTCN2022074851-appb-100012
    时，1个所述子矩阵a位于所述第一生成矩阵的左下角。
  20. 根据权利要求14-19任一所述的装置，其特征在于，所述处理单元在获取第一待编码向量之前，还用于：
    确定待编码信息比特包含的第二子块的数量；
    基于码字的总码率和所述第二子块的数量，确定所述待编码信息比特包含的每一个第二子块的码率；其中，每一个第二子块的码率不同；
    所述处理单元在获取第一待编码向量时具体用于：
    基于所述每一个第二子块的码率确定所述第一待编码向量；所述第一待编码向量包含q个第二子块，q是大于0的整数。
  21. 一种通信装置，其特征在于，包括：处理单元和输入输出单元；
    所述输入输出单元，用于接收码字；所述码字是基于第一生成矩阵编码得到的；
    所述处理单元，用于根据所述第一生成矩阵对所述码字进行译码；其中，所述第一生成矩阵包括至少N+1个子矩阵a，其中的N个子矩阵a位于所述第一生成矩阵的主对角线 上，所述第一生成矩阵是块上三角矩阵，或者所述第一生成矩阵是块下三角矩阵，其中a是大小为2 m*2 m的极化码polar核矩阵，m是自然数N是自然数。
  22. 根据权利要求21所述的装置，其特征在于，所述块上三角矩阵中上三角的元素都是a，所述块下三角矩阵中下三角的元素都是a。
  23. 根据权利要求21或22所述的装置，其特征在于，所述第一生成矩阵包含K个第一子块，所述K个第一子块位于所述第一生成矩阵的主对角线上，相邻的所述第一子块之间有部分重叠，K是大于等于2，且大于等于N的整数；每个所述第一子块是
    Figure PCTCN2022074851-appb-100013
    或
    Figure PCTCN2022074851-appb-100014
  24. 根据权利要求23所述的装置，其特征在于，所述相邻的第一子块之间重叠部分为a。
  25. 根据权利要求23或24所述的装置，其特征在于，所述K个第一子块包含所述N个子矩阵a，当所述第一子块是
    Figure PCTCN2022074851-appb-100015
    时，1个子矩阵a位于所述第一生成矩阵的右上角。
  26. 根据权利要求23-25任一所述的装置，其特征在于，所述K个第一子块包含所述N个子矩阵a，当所述第一子块是
    Figure PCTCN2022074851-appb-100016
    时，1个子矩阵a位于所述第一生成矩阵的左下角。
  27. 一种通信装置，其特征在于，包括：处理器和存储器；
    其中，所述存储器用于存储计算机可执行指令，当所述处理器执行部分或全部所述计算机可执行指令时，使得所述权利要求1-7中任一项所述的方法被执行，或者使得所述权利要求8-13中任一项所述的方法被执行。
  28. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机可执行指令，所述计算机可执行指令在被电子装置调用时，使所述电子装置执行如权利要求1-7中任一项所述的方法或者使所述电子装置执行如权利要求8-13任一项所述的方法。
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