WO2021209855A1 - 半導体装置、及び電子機器 - Google Patents

半導体装置、及び電子機器 Download PDF

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Publication number
WO2021209855A1
WO2021209855A1 PCT/IB2021/052804 IB2021052804W WO2021209855A1 WO 2021209855 A1 WO2021209855 A1 WO 2021209855A1 IB 2021052804 W IB2021052804 W IB 2021052804W WO 2021209855 A1 WO2021209855 A1 WO 2021209855A1
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Prior art keywords
wiring
transistor
circuit
terminal
current
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Ceased
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PCT/IB2021/052804
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English (en)
French (fr)
Japanese (ja)
Inventor
黒川義元
上妻宗広
青木健
金村卓郎
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2022514869A priority Critical patent/JP7571127B2/ja
Priority to US17/915,673 priority patent/US12376447B2/en
Priority to CN202180028372.3A priority patent/CN115427962A/zh
Publication of WO2021209855A1 publication Critical patent/WO2021209855A1/ja
Anticipated expiration legal-status Critical
Priority to JP2024177458A priority patent/JP2025003452A/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K39/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic radiation-sensitive element covered by group H10K30/00
    • H10K39/30—Devices controlled by radiation
    • H10K39/32—Organic image sensors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

Definitions

  • One aspect of the present invention relates to a semiconductor device and an electronic device.
  • one aspect of the present invention is not limited to the above technical fields.
  • the technical field of the invention disclosed in the present specification and the like relates to a product, a driving method, or a manufacturing method.
  • one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, power storage devices, image pickup devices, storage devices, signal processing devices, and sensors. , Processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods.
  • the mechanism of the brain is incorporated as an electronic circuit, and has a circuit corresponding to "neurons” and "synapses" of the human brain. Therefore, such integrated circuits are sometimes called “neuromorphic”, “brainmorphic”, “brain-inspired” and the like.
  • the integrated circuit has a non-Von Neumann architecture, and is expected to be able to perform parallel processing with extremely low power consumption as compared with the von Neumann architecture in which the power consumption increases as the processing speed increases.
  • a model of information processing that imitates a neural network having "neurons” and “synapses” is called an artificial neural network (ANN).
  • ANN artificial neural network
  • the operation of the weighted sum of the neuron outputs, that is, the product-sum operation is the main operation.
  • Non-Patent Document 1 proposes a product-sum calculation circuit using a non-volatile memory element.
  • the product-sum calculation circuit in each memory element, the operation in the sub-threshold region of the transistor having silicon in the channel formation region is used, and the data corresponding to the multiplier and the input data corresponding to the multiplicand stored in each memory element are used. Outputs the current corresponding to the multiplication with.
  • the data corresponding to the product-sum calculation is acquired by the sum of the currents output by the memory elements in each column. Since the product-sum calculation circuit has a memory element inside, it is possible to eliminate reading and writing data from an external memory in multiplication and addition. Therefore, it is expected that the number of times of data transfer due to reading and writing can be reduced, so that the power consumption can be reduced.
  • Transistors with silicon in the channel formation region tend to change transistor characteristics, field effect mobility, etc. due to temperature changes.
  • the temperature of the integrated circuit rises due to heat generated when it is driven, and the characteristics of the transistors contained in the integrated circuit change, which may make it impossible to perform correct calculation. There is.
  • the multiplication of the digital data (multiplier data) to be a multiplier and the digital data (multiplier data) to be a multiplier is executed in the digital multiplication circuit.
  • the addition of the digital data (product-sum data) obtained by the multiplication is executed by the digital addition circuit, and the digital data (product-sum data) is acquired as the result of the multiply-accumulate operation.
  • the digital multiplication circuit and the digital adder circuit have specifications that can handle multi-bit operations.
  • the circuit area since it is necessary to increase the circuit scales of the digital multiplication circuit and the digital adder circuit, the circuit area may increase and the power consumption may also increase.
  • the sensor array including the sensor is arranged above the semiconductor chip in which the arithmetic circuit is configured, it is preferable that the sensor array is arranged at the center of the semiconductor chip or near the center in the top view.
  • the drive circuit of the sensor included in the sensor array can be arranged around the sensor array.
  • the convex lens is stabilized by setting the position of the convex lens to the center or the vicinity of the center of the semiconductor chip in the top view. Can be placed.
  • the sensor array is arranged at the center or near the center of the semiconductor chip in the top view.
  • the layout of arithmetic circuits, wiring, etc. formed on the semiconductor chip needs to be designed according to the sensor array located at the center or near the center above the semiconductor chip, so that the degree of freedom of the layout may be reduced. There is.
  • One aspect of the present invention is to provide a semiconductor device capable of multiply-accumulate operation. Alternatively, one aspect of the present invention is to provide a semiconductor device having low power consumption. Alternatively, one aspect of the present invention is to provide a semiconductor device having a reduced circuit area. Alternatively, one aspect of the present invention is to provide a semiconductor device that suppresses a decrease in operating ability due to heat.
  • one aspect of the present invention is to provide a new semiconductor device or the like.
  • one aspect of the present invention is to provide an electronic device having the above-mentioned semiconductor device.
  • the problem of one aspect of the present invention is not limited to the problems listed above.
  • the issues listed above do not preclude the existence of other issues.
  • Other issues are issues not mentioned in this item, which are described below. Issues not mentioned in this item can be derived from descriptions in the description, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one aspect of the present invention solves at least one of the above-listed problems and other problems. It should be noted that one aspect of the present invention does not need to solve all of the above-listed problems and other problems.
  • One aspect of the present invention is a semiconductor device having a first layer, a second layer located above the first layer, and a third layer located above the second layer.
  • the first layer has a first cell, a first circuit, a first wiring, and a second wiring adjacent to the first wiring, and the second layer is adjacent to the third wiring and the third wiring. It has a matching fourth wire, and a third layer has an electrode and a sensor.
  • the first circuit also has a switch.
  • the sensor is electrically connected to the third wire via an electrode and a first plug.
  • the first terminal of the switch is electrically connected to the third wiring via the second plug, and the second terminal of the switch is electrically connected to the first cell via the first wiring.
  • the electrode has a region that overlaps with the sensor and a region that overlaps with the first plug. Further, the first wiring, the second wiring, the third wiring, and the fourth wiring are parallel to each other, and the distance between the wirings of the third wiring and the fourth wiring is the same as that of the first wiring. It is 0.9 times or more and 1.1 times or less the distance between the wirings of the second wiring.
  • the first layer may have a second cell.
  • the first cell has a first transistor, a second transistor, and a first capacitance
  • the second cell has a configuration having a third transistor, a fourth transistor, and a second capacitance. It is preferable to do so.
  • the gate of the first transistor is electrically connected to the first terminal of the first capacitance and the first terminal of the second transistor, and the first terminal of the first transistor is of the second transistor.
  • the second terminal of the first capacitance is electrically connected to the second terminal and is electrically connected to the second terminal of the switch via the first wiring.
  • the gate of the third transistor is electrically connected to the first terminal of the second capacitance and the first terminal of the fourth transistor, and the first terminal of the third transistor is the second terminal of the fourth transistor. It is preferable that the second terminal of the second capacitance is electrically connected to the second terminal of the switch via the first wiring.
  • the first layer may have a first current source circuit.
  • the first current source circuit has a function of passing a first current from the output terminal of the first current source circuit, and the output terminal of the first current source circuit is electrically connected to the first terminal of the first transistor. It is preferable that it is connected to.
  • the sensor has a function of passing a second current according to the information obtained by sensing, and an input corresponding to the amount of the second current to each of the second terminal of the first capacitance and the second terminal of the second capacitance. It is preferable to have a function of giving an electric potential.
  • the second cell holds the potential corresponding to the second current at the gate of the third transistor, so that the amount of current flowing between the first terminal and the second terminal of the third transistor is the amount of the second current. It is preferable to have a function to set to. Further, the first cell holds a potential corresponding to the first current at the gate of the first transistor, so that the amount of current flowing between the first terminal and the second terminal of the first transistor is the amount of the first current. When the amount of the second current flowing through the sensor changes, the amount of the first current flowing between the first terminal and the second terminal of the first transistor is adjusted according to the fluctuation amount of the input potential. , It is preferable to have a function of changing the amount of the third current.
  • the amount of the first current and the amount of the third current are the ranges of the current that flows when the first transistor operates in the subthreshold region, and the amount of the second current is the subthreshold of the second transistor.
  • the range of current that flows when operating in the region is the range of current that flows when operating in the region.
  • each of the first transistor, the second transistor, the third transistor, and the fourth transistor is metal-oxidized in the channel forming region. It may be configured to have an object.
  • the senor in any one of the above (1) to (4), may have a photodiode.
  • one aspect of the present invention is an electronic device having the semiconductor device according to any one of (1) to (5) above and a housing. Further, the semiconductor device preferably has a function of performing a product-sum calculation.
  • the semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics.
  • a semiconductor element transistor, diode, photodiode, etc.
  • the storage device, the display device, the light emitting device, the lighting device, the electronic device, and the like are themselves semiconductor devices, and may have the semiconductor device.
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display
  • One or more devices, light emitting devices, loads, etc. can be connected between X and Y.
  • the switch has a function of controlling on / off. That is, the switch is in a conducting state (on state) or a non-conducting state (off state), and has a function of controlling whether or not a current flows.
  • a circuit that enables functional connection between X and Y for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion, etc.) Circuits (digital-analog conversion circuit, analog-digital conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes the signal potential level, etc.), voltage source, current source , Switching circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, storage circuit, control circuit, etc.) It is possible to connect one or more to and from. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. do.
  • X and Y are electrically connected, it means that X and Y are electrically connected (that is, another element between X and Y). Or when they are connected with another circuit in between) and when X and Y are directly connected (that is, they are connected without sandwiching another element or another circuit between X and Y). If there is) and.
  • X and Y, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and the X, the source (or the second terminal, etc.) of the transistor are connected to each other. (1 terminal, etc.), the drain of the transistor (or the 2nd terminal, etc.), and Y are electrically connected in this order.
  • the source of the transistor (or the first terminal, etc.) is electrically connected to X
  • the drain of the transistor (or the second terminal, etc.) is electrically connected to Y
  • the X, the source of the transistor (such as the second terminal).
  • the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.
  • X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor. (Terminals, etc.), transistor drains (or second terminals, etc.), and Y are provided in this connection order.
  • the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be separated. Separately, the technical scope can be determined. Note that these expression methods are examples, and are not limited to these expression methods.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • circuit diagram shows that the independent components are electrically connected to each other, one component has the functions of a plurality of components.
  • one component has the functions of a plurality of components.
  • the term "electrically connected” as used herein includes the case where one conductive film has the functions of a plurality of components in combination.
  • the “resistance element” can be, for example, a circuit element having a resistance value higher than 0 ⁇ , wiring, or the like. Therefore, in the present specification and the like, the “resistive element” includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, a coil, and the like. Therefore, the term “resistor element” can be paraphrased into terms such as “resistance”, “load”, and “region having a resistance value”, and conversely, “resistance", “load”, and “region having a resistance value”. Can be rephrased as a term such as “resistive element”.
  • the resistance value can be, for example, preferably 1 m ⁇ or more and 10 ⁇ or less, more preferably 5 m ⁇ or more and 5 ⁇ or less, and further preferably 10 m ⁇ or more and 1 ⁇ or less. Further, for example, it may be 1 ⁇ or more and 1 ⁇ 10 9 ⁇ or less.
  • the “capacitance element” means, for example, a circuit element having a capacitance value higher than 0F, a wiring region having a capacitance value, a parasitic capacitance, a transistor gate capacitance, and the like. Can be.
  • terms such as “capacitive element”, “parasitic capacitance”, and “gate capacitance” can be paraphrased into terms such as “capacity”, and conversely, the term “capacity” means “capacitive element” and “parasitic”. It can be paraphrased into terms such as “capacity” and "gate capacitance”.
  • the term “pair of electrodes” in “capacity” can be rephrased as “pair of conductors", “pair of conductive regions", “pair of regions” and the like.
  • the value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. Further, for example, it may be 1 pF or more and 10 ⁇ F or less.
  • the transistor has three terminals called a gate, a source, and a drain.
  • the gate is a control terminal that controls the conduction state of the transistor.
  • the two terminals that function as sources or drains are the input and output terminals of the transistor.
  • One of the two input / output terminals becomes a source and the other becomes a drain depending on the high and low potentials given to the conductive type (n-channel type, p-channel type) of the transistor and the three terminals of the transistor. Therefore, in the present specification and the like, the terms source and drain can be paraphrased with each other.
  • the transistor when explaining the connection relationship of transistors, "one of the source or drain” (or the first electrode or the first terminal), “the other of the source or drain” (or the second electrode, or The notation (second terminal) is used.
  • it may have a back gate in addition to the above-mentioned three terminals.
  • one of the gate or the back gate of the transistor may be referred to as a first gate
  • the other of the gate or the back gate of the transistor may be referred to as a second gate.
  • the terms “gate” and “backgate” may be interchangeable.
  • the respective gates When the transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, and the like in the present specification and the like.
  • the circuit element may have a plurality of circuit elements.
  • one resistor when one resistor is described on the circuit diagram, it includes the case where two or more resistors are electrically connected in series.
  • one capacity when one capacity is described on the circuit diagram, it includes the case where two or more capacities are electrically connected in parallel.
  • one transistor when one transistor is described on the circuit diagram, two or more transistors are electrically connected in series, and the gates of the respective transistors are electrically connected to each other. Shall include.
  • the switch has two or more transistors, and two or more transistors are electrically connected in series, respectively. It is assumed that the case where the gates of the transistors of the above are electrically connected to each other is included.
  • a node can be paraphrased as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on a circuit configuration, a device structure, and the like.
  • terminals, wiring, etc. can be paraphrased as nodes.
  • ground potential ground potential
  • the potentials are relative, and when the reference potential changes, the potential given to the wiring, the potential applied to the circuit or the like, the potential output from the circuit or the like also changes.
  • the terms “high level potential” and “low level potential” do not mean a specific potential.
  • both of the two wires “function as a wire that supplies a high level potential”
  • the high level potentials provided by both wires do not have to be equal to each other.
  • both of the two wires are described as “functioning as a wire that supplies a low level potential”
  • the low level potentials given by both wires do not have to be equal to each other. ..
  • the "current” is a charge transfer phenomenon (electrical conduction).
  • the description “electrical conduction of a positively charged body is occurring” means “electrical conduction of a negatively charged body in the opposite direction”. Is happening. " Therefore, in the present specification and the like, “current” refers to a charge transfer phenomenon (electrical conduction) accompanying the movement of carriers, unless otherwise specified.
  • the carrier here include electrons, holes, anions, cations, complex ions, and the like, and the carriers differ depending on the system in which the current flows (for example, semiconductor, metal, electrolytic solution, vacuum, etc.).
  • the "current direction” in the wiring or the like shall be the direction in which the carriers having a positive charge move, and shall be described as a positive current amount.
  • the direction in which the carriers that become negative charges move is opposite to the direction of the current, and is expressed by the amount of negative current. Therefore, in the present specification and the like, if there is no notice about the positive or negative of the current (or the direction of the current), the description such as “current flows from element A to element B” means “current flows from element B to element A” or the like. It can be paraphrased as. Further, the description such as “a current is input to the element A” can be rephrased as "a current is output from the element A” or the like.
  • the ordinal numbers “first”, “second”, and “third” are added to avoid confusion of the components. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. For example, the component referred to in “first” in one of the embodiments of the present specification and the like may be the component referred to in “second” in another embodiment or in the claims. There can also be. Further, for example, the component mentioned in “first” in one of the embodiments of the present specification and the like may be omitted in another embodiment or in the claims.
  • the terms “above” and “below” do not limit the positional relationship of the components directly above or below and in direct contact with each other.
  • the expression “electrode B on the insulating layer A” it is not necessary that the electrode B is formed in direct contact with the insulating layer A, and another configuration is formed between the insulating layer A and the electrode B. Do not exclude those that contain elements.
  • membrane and layer can be interchanged with each other depending on the situation.
  • the terms “insulating layer” and “insulating film” may be changed to the term "insulator”.
  • Electrode may be used as part of a “wiring” and vice versa.
  • the terms “electrode” and “wiring” include the case where a plurality of “electrodes” and “wiring” are integrally formed.
  • a “terminal” may be used as part of a “wiring” and / or an “electrode” and vice versa.
  • the term “terminal” includes a case where a plurality of "electrodes", “wiring”, “terminals” and the like are integrally formed.
  • the "electrode” can be a part of the “wiring” or the “terminal”, and for example, the “terminal” can be a part of the “wiring” or the “electrode”.
  • terms such as “electrode”, “wiring”, and “terminal” may be replaced with terms such as "area” in some cases.
  • terms such as “wiring”, “signal line”, and “power supply line” can be interchanged with each other in some cases or depending on the situation.
  • the reverse is also true, and it may be possible to change terms such as “signal line” and “power supply line” to the term “wiring”.
  • a term such as “power line” may be changed to a term such as "signal line”.
  • terms such as “signal line” may be changed to terms such as "power line”.
  • the term “potential” applied to the wiring may be changed to a term such as “signal” in some cases or depending on the situation.
  • the reverse is also true, and terms such as “signal” may be changed to the term “potential”.
  • semiconductor impurities refer to, for example, components other than the main components constituting the semiconductor layer.
  • an element having a concentration of less than 0.1 atomic% is an impurity.
  • the inclusion of impurities may result in, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, a decrease in crystallinity, and the like.
  • the impurities that change the characteristics of the semiconductor include, for example, group 1 element, group 2 element, group 13 element, group 14 element, group 15 element, and other than the main component.
  • transition metals and the like and in particular, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like.
  • the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements, and the like (however, oxygen, Does not contain hydrogen).
  • the switch means a switch that is in a conductive state (on state) or a non-conducting state (off state) and has a function of controlling whether or not a current flows.
  • the switch means a switch having a function of selecting and switching a path through which a current flows.
  • an electric switch, a mechanical switch, or the like can be used. That is, the switch is not limited to a specific switch as long as it can control the current.
  • Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, and MIS (Metal Insulator Semiconductor) diodes. , A diode-connected transistor, etc.), or a logic circuit that combines these.
  • transistors for example, bipolar transistors, MOS transistors, etc.
  • diodes for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, and MIS (Metal Insulator Semiconductor) diodes. , A diode-connected transistor, etc.
  • the "conducting state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited.
  • the "non-conducting state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically cut off.
  • the polarity (conductive type) of the transistor is not particularly limited.
  • An example of a mechanical switch is a switch that uses MEMS (Micro Electro Mechanical System) technology.
  • the switch has an electrode that can be moved mechanically, and the movement of the electrode controls conduction and non-conduction.
  • parallel means a state in which two straight lines are arranged at an angle of -10 ° or more and 10 ° or less. Therefore, the case of ⁇ 5 ° or more and 5 ° or less is also included.
  • substantially parallel or approximately parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 ° or more and 30 ° or less.
  • vertical means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included.
  • substantially vertical or “approximately vertical” means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.
  • a semiconductor device capable of product-sum calculation.
  • a semiconductor device having low power consumption can be provided.
  • a novel semiconductor device or the like can be provided by one aspect of the present invention.
  • an electronic device having the above semiconductor device can be provided.
  • the effect of one aspect of the present invention is not limited to the effects listed above.
  • the effects listed above do not preclude the existence of other effects.
  • the other effects are the effects not mentioned in this item, which are described below. Effects not mentioned in this item can be derived from those described in the description, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one aspect of the present invention has at least one of the above-listed effects and other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.
  • FIG. 1 is a schematic perspective view showing a configuration example of a semiconductor device.
  • FIG. 2 is a schematic perspective view showing a configuration example of a semiconductor device.
  • FIG. 3 is a schematic perspective view showing a configuration example of a semiconductor device.
  • FIG. 4 is a top view showing an example of wiring routing included in the semiconductor device.
  • 5A and 5B are diagrams showing an example of the shape of the wiring included in the semiconductor device.
  • FIG. 6 is a schematic perspective view showing a configuration example of a semiconductor device.
  • FIG. 7 is a block diagram showing a configuration example of the semiconductor device.
  • 8A to 8C are block diagrams showing a configuration example of a circuit included in the semiconductor device.
  • 9A to 9D are circuit diagrams showing a configuration example of a circuit included in the semiconductor device.
  • FIG. 10A to 10C are circuit diagrams showing a configuration example of a circuit included in the semiconductor device.
  • FIG. 11 is a block diagram showing a configuration example of the semiconductor device.
  • FIG. 12 is a timing chart showing an operation example of the semiconductor device.
  • FIG. 13 is a timing chart showing an operation example of the semiconductor device.
  • FIG. 14 is a block diagram showing a configuration example of the semiconductor device.
  • 15A to 15C are circuit diagrams showing a configuration example of a circuit included in the semiconductor device.
  • FIG. 16 is a block diagram showing a configuration example of a circuit included in the semiconductor device.
  • FIG. 17A is a circuit diagram showing a configuration example of a circuit included in the semiconductor device
  • FIG. 17B is a block diagram showing a configuration example of a circuit included in the semiconductor device.
  • FIGS. 18A and 18B are block diagrams showing a configuration example of a circuit included in the semiconductor device
  • FIGS. 18C and 18D are circuit diagrams showing a configuration example of the circuit included in the semiconductor device.
  • FIG. 19 is a circuit diagram showing a configuration example of a circuit included in the semiconductor device.
  • FIG. 20 is a circuit diagram showing a configuration example of a circuit included in the semiconductor device.
  • 21A is a block diagram showing a configuration example of a semiconductor device
  • FIGS. 21B and 21C are circuit diagrams showing an example of a circuit included in the semiconductor device.
  • 22A and 22B are block diagrams showing a configuration example of a circuit included in the semiconductor device.
  • 23A and 23B are timing charts showing operation examples of the semiconductor device.
  • FIG. 24A and 24B are diagrams illustrating a hierarchical neural network.
  • FIG. 25 is a block diagram showing a configuration example of the semiconductor device.
  • FIG. 26 is a block diagram showing a configuration example of the semiconductor device.
  • FIG. 27 is a schematic cross-sectional view showing a configuration example of the semiconductor device.
  • FIG. 28 is a schematic cross-sectional view showing a configuration example of the semiconductor device.
  • 29A to 29C are schematic cross-sectional views showing a configuration example of a transistor.
  • 30A and 30B are schematic cross-sectional views showing a configuration example of a transistor.
  • FIG. 31A is a top view showing a configuration example of the capacitance element
  • FIGS. 31B and 31C are cross-sectional perspective views showing a configuration example of the capacitance element.
  • FIG. 32A is a top view showing a configuration example of the capacitance element
  • FIG. 32B is a cross-sectional view showing a configuration example of the capacitance
  • FIG. 32C is a cross-sectional perspective view showing a configuration example of the capacitance element.
  • FIG. 33 is a schematic cross-sectional view showing a configuration example of the semiconductor device.
  • FIG. 34A is a diagram for explaining the classification of the crystal structure of IGZO
  • FIG. 34B is a diagram for explaining the XRD spectrum of crystalline IGZO
  • FIG. 34C is a diagram for explaining the microelectron diffraction pattern of crystalline IGZO.
  • .. 35A is a perspective view showing an example of a semiconductor wafer
  • FIG. 35A is a perspective view showing an example of a semiconductor wafer
  • FIG. 35B is a perspective view showing an example of a chip
  • FIGS. 35C and 35D are perspective views showing an example of an electronic component.
  • 36A to 36F are perspective views of a package and a module containing an imaging device.
  • FIG. 37 is a perspective view showing an example of an electronic device.
  • 38A to 38C are perspective views showing an example of an electronic device.
  • 39A to 39C are schematic views showing an example of an electronic device.
  • the synaptic connection strength can be changed by giving existing information to the neural network.
  • the process of giving existing information to the neural network and determining the coupling strength may be called "learning”.
  • new information can be output based on the coupling strength.
  • the process of outputting new information based on the given information and the connection strength may be referred to as “inference” or "cognition”.
  • Examples of the neural network model include a Hopfield type and a hierarchical type.
  • a neural network having a multi-layer structure may be referred to as a “deep neural network” (DNN), and machine learning by a deep neural network may be referred to as “deep learning”.
  • DNN deep neural network
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is contained in the channel forming region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel forming region of a transistor having at least one of an amplification action, a rectifying action, and a switching action, the metal oxide is referred to as a metal oxide semiconductor. be able to. Further, when describing as an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.
  • a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.
  • the configuration shown in each embodiment can be appropriately combined with the configuration shown in other embodiments to form one aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.
  • the content (may be a part of the content) described in one embodiment is the other content (may be a part of the content) described in the embodiment and one or more other implementations. It is possible to apply, combine, or replace at least one content with the content described in the form of (may be a part of the content).
  • figure (which may be a part) described in one embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more other figures.
  • the figure (which may be a part) described in the embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more other figures.
  • more figures can be formed.
  • FIG. 1 shows a configuration example of a semiconductor device capable of performing a product-sum calculation of a plurality of first data and a plurality of second data.
  • the semiconductor device SDV shown in FIG. 1 has a layer PDL, a layer ERL, and a layer CCL.
  • the semiconductor device SDV shown in FIG. 1 has a three-dimensional structure, arrows indicating the x direction, the y direction, and the z direction are attached to FIG.
  • the x-direction, y-direction, and z-direction here are shown as, as an example, directions orthogonal to each other.
  • one of the x direction, the y direction, and the z direction may be referred to as a "first direction” or a "first direction”.
  • the other one may be referred to as a "second direction” or a "second direction”.
  • the remaining one may be referred to as a "third direction” or a "third direction”.
  • the layer ERL is located above the layer CCL, and the layer PDL is located above the layer ERL. That is, the layer CCL, the layer ERL, and the layer PDL are stacked in this order in the z direction.
  • the layer PDL has a sensor array SCA as an example.
  • the sensor array SCA has a plurality of electrodes and a plurality of sensors, and in FIG. 1, as an example, the electrodes DNK [1] to the electrodes DNK [m] (where m is 1 or more) are used as the plurality of electrodes. It is an integer.) And the sensor SNC [1] to the sensor SNC [m] as a plurality of sensors are shown in the figure. Further, as an example, m electrodes DNK are arranged in a matrix in the layer PDL, and sensors SNC [1] to sensor SNC [1] are placed on the respective electrodes DNK [1] to DNK [m]. m] is provided.
  • the electrode DNK [1] and the electrode DNK [i] (i here is an integer of 1 or more and m or less).
  • the electrode DNK [m] are excerpted and shown.
  • the symbols of the sensor SNC [1], the sensor SNC [i], and the sensor SNC [m] are extracted from the sensor SNC [1] to the sensor SNC [m]. Is shown.
  • the sensor SNC [1] to the sensor SNC [m] have a function of converting the sensed information into a current amount and outputting the current amount. Further, each of the electrode DNK [1] to the electrode DNK [m] functions as a terminal for outputting the current amount in the sensor SNC [1] to the sensor SNC [m].
  • an optical sensor can be applied as the sensor SNC [1] to the sensor SNC [m].
  • the layer PDL can be a part of the image sensor. In that case, it is desirable that the range of the light intensity that can be sensed by the optical sensor includes the intensity of the light emitted in the environment in which the optical sensor is used.
  • FIG. 2 also shows a semiconductor device SDV to which a sensor SNC having a photodiode PD is applied as an optical sensor.
  • the circuit configuration of the sensor SNC [i] one of the input terminal or the output terminal of the photodiode PD included in the sensor SNC [i] is wired EIL [i] via the electrode DNK [i]. ] May be electrically connected.
  • the circuit configuration of the sensor SNC [i] may be configured to include a switch or the like for shutting off the power supply in order to temporarily stop the sensor SNC [i].
  • the sensor SNC [i] may include a circuit, an element, or the like having another function.
  • a pressure sensor for example, a pressure sensor, a gyro sensor, an acceleration sensor, an auditory sensor, a temperature sensor, a humidity sensor and the like can be used. ..
  • the sensor SNC [1] to the sensor SNC [m] are preferably provided in a region close to the outside world, for example, in order to sense information in the outside world. That is, as shown in FIG. 1, the layer PDL is preferably provided above, for example, the layer CCL and the layer ERL.
  • the layer ERL has wiring EIL [1] to wiring EIL [m].
  • the symbols of the wiring EIL [1], the wiring EIL [i], and the wiring EIL [m] are extracted from the wiring EIL [1] to the wiring EIL [m]. Is shown.
  • the wiring EIL [1] is electrically connected to the electrode DNK [1] of the layer PDL. Further, the wiring EIL [i] is electrically connected to the electrode DNK [i] of the layer PDL. Further, the wiring EIL [m] is electrically connected to the electrode DNK [m] of the layer PDL.
  • each of the electrodes DNK [1] to DNK [m] is wired.
  • a plug (sometimes called a contact hole or the like) or the like is provided at a position intersecting the EIL [1] to the wiring EIL [m], and each of the electrodes DNK [1] to the electrode DNK [m] and the wiring EIL [m] are provided. 1] to each of the wiring EIL [m] are electrically connected.
  • the area of each of the electrode DNK [1] to the electrode DNK [m] may be increased.
  • the wiring EIL [1] to the wiring EIL [m] are the sensor SNC [1] to the sensor SNC [m] when information is sensed in each of the sensor SNC [1] to the sensor SNC [m]. ] Each functions as a path through which an amount of current corresponding to the information output is flowing.
  • the layer PDL has a configuration in which each of the sensors SNC [1] and the sensor SNC [m] sequentially performs sensing, and a current can be sequentially passed through each of the wiring EIL [1] to the wiring EIL [m].
  • the layer PDL is configured to be provided with a signal line for selecting the sensor SNC [1] to the sensor SNC [m], and signals or the like are sequentially transmitted to the signal line to be sequentially transmitted to the sensor SNC [1] to the sensor.
  • the SNC [m] may be operated sequentially.
  • the layer PDL of the semiconductor device SDV is, for example, an output terminal (cathode) of the photodiode on the electrode DNK. Can be configured to be electrically connected.
  • the input terminal (anode) of the photodiode may be electrically connected to the electrode DNK.
  • the sensor SNC [1] to the sensor SNC [m] is an optical sensor composed of a photodiode or the like, for example, only one sensor SNC among the sensor SNC [1] to the sensor SNC [m] can be used.
  • the sensor SNC [1] to the sensor SNC [m] can be sequentially operated. Since there are m sensor SNCs, there are m types of filters that irradiate only one sensor SNC with light. In addition to these, when a filter that does not irradiate any of the sensor SNC [1] to the sensor SNC [m] with light is prepared, the number of filters is m + 1.
  • the sensor SNC [1] to the sensor SNC [m] can sequentially perform sensing by sequentially switching such filters.
  • the semiconductor device SDV is individually provided for each of the sensor SNC [1] to the sensor SNC [m]. May be configured to irradiate light. By individually irradiating light, the sensors SNC [1] to SNC [m] are sequentially irradiated with light, and the sensors SNC [1] to SNC [m] are sequentially sensed. It can be performed.
  • the layer CCL has an arithmetic circuit.
  • the arithmetic circuit has, for example, a cell array CA, a circuit PTC, a circuit XCS, a circuit WCS, a circuit WSD, a circuit ITS, a circuit SWS1, and a circuit SWS2.
  • the cell array CA has a plurality of cells. As will be described in detail later, the plurality of cells included in the cell array CA have a function of holding the first data for performing the product-sum operation, a function of multiplying the first data and the second data, and the like. Have.
  • the cell array CA is electrically connected to a plurality of wirings.
  • the cell array CA includes wiring WCL [1] to wiring WCL [n] (where n is an integer of 1 or more) and wiring WSL [1] to wiring WSL. [M] and the configuration electrically connected to the wiring XCL [1] to the wiring XCL [m] are shown.
  • the wiring WCL [1] to the wiring WCL [n] are wirings that electrically connect the circuit SWS1 and the circuit SWS2. That is, it can be said that the circuit SWS1 is electrically connected to the circuit SWS2 by the wiring WCL [1] to the wiring WCL [n] via the cell array CA.
  • the wiring WSL [1] to the wiring WSL [m] and the wiring XCL [1] to the wiring XCL [m] extend in the x direction, and the wiring WCL [1] to the wiring WCL [n] extends in the y direction.
  • one of the plurality of cells of the cell array CA includes any one of the wiring WCL [1] to the wiring WCL [n], any one of the wiring WSL [1] to the wiring WSL [m], and the wiring XCL [1]. ] To the wiring XCL [m], and each of them is electrically connected. Therefore, the plurality of cells included in the cell array CA are arranged in a matrix of at least m rows and n columns.
  • the circuit WCS has a function of supplying an amount of current corresponding to the first data to the wiring WCL [1] to the wiring WCL [n]. Therefore, the circuit WCS is electrically connected to each of the wiring WCL [1] to the wiring WCL [n] via the circuit SWS1.
  • the circuit SWS1 has a function of setting a conductive state or a non-conducting state between the circuit WCS and the wiring WCL [1] to the wiring WCL [n], respectively.
  • the circuit WSD is electrically connected to the wiring WSL [1] to the wiring WSL [m].
  • the circuit WSD becomes a write destination of the first data by supplying a predetermined signal to the wiring WSL [1] to the wiring WSL [m] when writing the first data to the cell included in the cell array CA. It has a function of selecting a row of the cell array CA. That is, the wiring WSL [1] to the wiring WSL [m] function as a writing word line.
  • the circuit XCS is electrically connected to the wiring XCL [1] to the wiring XCL [m].
  • the circuit XCS has a function of passing a current corresponding to the reference data described later or a current corresponding to the second data to the wiring XCL [1] to the wiring XCL [m].
  • the circuit PTC has a circuit PTR [1] to a circuit PTR [m]. Further, the first terminal of the circuit PTR [1] is electrically connected to the wiring XCL [1], and the first terminal of the circuit PTR [i] is electrically connected to the wiring XCL [i]. The first terminal of [m] is electrically connected to the wiring XCL [m].
  • the second terminal of the circuit PTR [1] is electrically connected to the wiring EIL [1] of the layer ERL
  • the second terminal of the circuit PTR [i] is electrically connected to the wiring EIL [i] of the layer ERL
  • the second terminal of the circuit PTR [m] is electrically connected to the wiring EIL [m] of the layer ERL.
  • the second terminals of the circuits PTR [1] to the circuit PTR [m] intersect each of the wiring EIL [1] to the wiring EIL [m].
  • a plug or the like is provided at a location to electrically connect the second terminal of each of the circuit PTR [1] to the circuit PTR [m] and each of the wiring EIL [1] to the wiring EIL [m].
  • the circuit PTR [1] has a function of setting a conductive state or a non-conducting state between the wiring EIL [1] and the wiring XCL [1].
  • the circuit PTR [i] has a function of making the wiring EIL [i] and the wiring XCL [i] conductive or non-conducting
  • the circuit PTR [m] has the wiring EIL [m].
  • the wiring XCL [m] have a function of making a conductive state or a non-conducting state. That is, each of the circuit PTR [1] to the circuit PTR [m] has a function as a switching element.
  • the circuit ITS has a function of acquiring the amount of current flowing through the wiring WCL [1] to the wiring WCL [n] and outputting the result according to the amount of the current to the wiring OL [1] to the wiring OL [n]. .. Therefore, the circuit ITS is electrically connected to each of the wiring WCL [1] to the wiring WCL [n] via the circuit SWS2. Further, the circuit ITS is electrically connected to each of the wiring OL [1] to the wiring OL [n].
  • the circuit SWS2 has a function of setting a conductive state or a non-conducting state between the circuit ITS and the wiring WCL [1] to the wiring WCL [n], respectively.
  • the layer CCL is provided with a circuit PTC, a circuit XCS, a circuit WCS, a circuit WSD, a circuit ITS, a circuit SWS1, and a circuit SWS2 as peripheral circuits of the cell array CA.
  • a circuit PTC a circuit XCS
  • a circuit WCS a circuit WCS
  • a circuit WSD a circuit ITS
  • a circuit SWS1 a circuit SWS2
  • SWS2 circuit SWS2
  • the configuration of one aspect of the present invention may be a semiconductor device SDV having a layer PDL, a layer ERL, a layer CCL, and a layer PHL.
  • the layer PDL is located above the layer ERL
  • the layer ERL is located above the layer CCL
  • the layer CCL is located above the layer PHL.
  • the semiconductor device SDV of FIG. 3 has a layer PHL, a circuit XCS corresponding to a peripheral circuit of the cell array CA, a circuit WCS, a circuit WSD, a circuit ITS, a circuit SWS1, and a circuit SWS2. It differs from the semiconductor device SDV of FIG. 1 in that it is provided in the PHL.
  • the configuration of one aspect of the present invention includes a circuit XCS in which the cell array CA corresponds to a peripheral circuit of the cell array CA, a circuit WCS, a circuit WSD, a circuit ITS, a circuit SWS1, and a circuit SWS2. It may be configured to be located above.
  • FIG. 3 shows a configuration in which the layer PHL is located below the cell array CA
  • the layer PHL may be located above the cell array CA and below the layer ERL (not shown).
  • the wiring EIL [1] to the wiring EIL [m] are preferably extended along the x direction as an example. That is, the direction in which the wiring EIL [1] to the wiring EIL [m] is extended is preferably substantially parallel to the wiring XCL [1] to the wiring XCL [m] in the line of sight in the y direction, for example. , More preferably parallel. Further, for example, the wiring EIL [1] to the wiring EIL [m] is preferably substantially parallel to the wiring XCL [1] to the wiring XCL [m] included in the layer CCL, and is parallel to the wiring EIL [1] to the wiring EIL [m]. Is more preferable.
  • the wiring EIL [1] to the wiring EIL [m] are extended so as to be substantially parallel or parallel to the row direction (x direction) of the cell array CA in the top view.
  • the width of the wiring of the wiring EIL [1] to the wiring EIL [m] is 0.7 times or more, 0.8 times or more the width of the wiring of the wiring XCL [1] to the wiring XCL [m].
  • it is preferably 0.9 times or more, and preferably 1.1 times or less, 1.2 times or less, 1.3 times or less, 1.5 times or less, or 2 times or less.
  • the distance between the adjacent wirings in the wiring EIL [1] to the wiring EIL [m] is 0.1 times or more, 0.5 times or more the distance between the adjacent wirings in the wiring XCL [1] to the wiring XCL [m]. It is preferably times or more, 0.7 times or more, 0.8 times or more, or 0.9 times or more, and 1.1 times or less, 1.2 times or less, 1.3 times or less, or 1.5 times. It is preferably 2 times or less.
  • the above-mentioned lower limit value and upper limit value can be combined.
  • the process of forming the wiring EIL [1] to the wiring EIL [m] is ,
  • the process of forming the wiring XCL [1] to the wiring XCL [m] may be the same.
  • a photomask for forming the wiring XCL [1] to the wiring XCL [m] may be applied.
  • FIG. 4 is a top view (viewed from the z direction) showing an example of wiring the wiring XCL [1] to the wiring XCL [m] and the wiring EIL [1] to the wiring EIL [m] in the semiconductor device SDV.
  • FIG. 4 shows that the angle formed by the wiring XCL [1] to the wiring XCL [m] and the wiring EIL [1] to the wiring EIL [m] is larger than 0 degrees in the top view. It may be large.
  • the wiring EIL [1] to the wiring EIL can be set to 0 degrees or more.
  • the degree of freedom in the position of the sensor array SCA electrically connected to each of [m] can be increased.
  • the layer ERL preferably has a region in which at least two wires of the wiring EIL [1] to the wiring EIL [m] are parallel to each other, and the wiring EIL [1] to the wiring EIL [m] of each other. It is more preferable to have a region where the wiring is parallel.
  • the wiring EIL [1] to the wiring EIL [m] is designed so as not to be in a conductive state between the wirings (current, signal, etc. do not flow), the wiring EIL [1] to the wiring EIL [m]
  • the shape is not particularly limited.
  • the wiring EIL [1] to the wiring EIL [m] may be a wiring having an angle as shown in FIG. 5A, a wiring having a curved portion as shown in FIG. 5B, or the like.
  • the wiring EIL [1] to the wiring EIL [m] may be a wiring in which the shapes as shown in FIGS. 5A and 5B are combined.
  • the wiring EIL [1] to the wiring EIL [m] do not have to be parallel to each other.
  • the wiring interval of the wiring EIL [1] to the wiring EIL [m] is the same as, for example, the wiring XCL [1] to the wiring XCL [m].
  • the region formed by the layer PDL above the layer ERL can be freely determined along the one direction.
  • the sensor array SCA in the layer PDL is in the direction in which the wiring EIL [1] to the wiring EIL [m] is extended in the layer ERL (direction of the black arrow in FIG. 6). If so, the arrangement can be freely decided.
  • the location of the sensor array SCA can be almost freely determined on the semiconductor chip constituting the arithmetic circuit (layer CCL). Therefore, for example, the sensor array SCA can be arranged at the center or near the center in the top view of the semiconductor chip. Further, since the layout of the arithmetic circuit included in the layer CCL does not depend on the installation location of the sensor array SCA, the degree of freedom in layout of the arithmetic circuit and the wiring around it can be increased.
  • FIG. 7 shows a configuration example of an arithmetic circuit that performs a product-sum operation of positive or “0” first data and positive or “0” second data
  • the layer CCL of FIG. 1 is It can be an arithmetic circuit having.
  • the arithmetic circuit MAC1 shown in FIG. 7 performs a product-sum calculation of the first data corresponding to the potential held in each cell and the input second data, and is activated by using the result of the product-sum calculation. It is a circuit that performs function operations.
  • the first data and the second data can be analog data or multi-valued data (discrete data) as an example.
  • the arithmetic circuit MAC1 has a circuit WCS, a circuit XCS, a circuit WSD, a circuit PTC, a circuit SWS1, a circuit SWS2, a circuit ITS, and a cell array CA, similarly to the layer CCL of FIG.
  • the cell array CA has cell IM [1,1] to cell IM [m, n] and cell IMref [1] to cell IMref [m].
  • Each of the cell IM [1,1] to the cell IM [m, n] has a function of holding a potential corresponding to the amount of current according to the first data
  • the cell IMref [1] to the cell IMref [m] Has a function of supplying the retained potential and the potential corresponding to the second data required for performing the product-sum calculation to the wiring XCL [1] to the wiring XCL [m].
  • the cell array CA in FIG. 7 has cells arranged in a matrix of m rows and n + 1 columns, but the cell array CA has a configuration in which cells are arranged in a matrix of one row or more and two or more columns. good.
  • Each of the cell IM [1,1] to the cell IM [m, n] has a transistor F1, a transistor F2, and a capacitance C5 as an example, and the cell IMref [1] to the cell IMref [m].
  • Each has, as an example, a transistor F1m, a transistor F2m, and a capacitance C5m.
  • the sizes of the transistors F1 (for example, channel length, channel width, transistor configuration, etc.) included in each of the cells IM [1,1] to the cells IM [m, n] are equal to each other.
  • the sizes of the transistors F2 included in each of the cells IM [1,1] to the cells IM [m, n] are equal to each other.
  • the transistors F1m included in each of the cell IMref [1] to the cell IMref [m] have the same size, and the transistors included in each of the cell IMref [1] to the cell IMref [m].
  • the sizes of F2m are equal to each other.
  • the sizes of the transistor F1 and the transistor F1m are preferably equal to each other, and the sizes of the transistor F2 and the transistor F2m are preferably equal to each other.
  • each of the cells IM [1,1] to the cells IM [m, n] can perform substantially the same operation under the same conditions. ..
  • the same conditions include, for example, the potential of the source, drain, gate, etc. of the transistor F1, the potential of the source, drain, gate, etc.
  • the size of the transistor F1m contained in each of the cell IMref [1] to the cell IMref [m] is made equal, and the size of the transistor F2m contained in each of the cell IMref [1] to the cell IMref [m] is made equal.
  • the cells IMref [1] to the cells IMref [m] can make the operation and the result of the operation substantially the same. Almost the same operation can be performed under the same conditions.
  • the same conditions here are, for example, input to the potentials of the source, drain, gate, etc. of the transistor F1m, the potentials of the source, drain, gate, etc. of the transistor F2m, and the cell IMref [1] to cell IMref [m], respectively. Refers to the voltage that is being used.
  • the transistor F1 and the transistor F1m include the case where they finally operate in the linear region when they are in the ON state. That is, it is assumed that the gate voltage, the source voltage, and the drain voltage of each of the above-mentioned transistors are appropriately biased to the voltage in the range of operation in the linear region.
  • the transistor F1 and the transistor F1m may operate in the saturation region when they are in the ON state, and may operate in the linear region and may operate in the saturation region in a mixed manner.
  • the transistor F2 and the transistor F2m are more preferably operated in the subthreshold region (that is, in the transistor F2 or the transistor F2m, when the gate-source voltage is lower than the threshold voltage.
  • Shall include (when the drain current increases exponentially with respect to the gate-source voltage). That is, it is assumed that the gate voltage, the source voltage, and the drain voltage of each of the above-mentioned transistors are appropriately biased to the voltage in the range of operation in the subthreshold region. Therefore, the transistor F2 and the transistor F2m include a case where the transistor F2m operates so that an off-current flows between the source and the drain.
  • the transistor F1 and / or the transistor F1m is preferably an OS transistor as an example.
  • the channel forming region of the transistor F1 and / or the transistor F1m is more preferably an oxide containing at least one of indium, gallium, and zinc.
  • indium and element M includes, for example, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, etc.
  • the transistor F1 and / or the transistor F1m has the structure of the transistor described in the fifth embodiment.
  • the leakage current of the transistor F1 and / or the transistor F1m can be suppressed, so that the power consumption of the arithmetic circuit can be reduced.
  • the leakage current from the holding node to the writing word line can be made very small, so that the potential refreshing operation of the holding node can be performed. Can be reduced.
  • the power consumption of the arithmetic circuit can be reduced.
  • the leakage current from the holding node to the wiring WCL or the wiring XCL very small, the cell can hold the potential of the holding node for a long time, so that the calculation accuracy of the calculation circuit can be improved.
  • the OS transistor for the transistor F2 and / or the transistor F2m, it is possible to operate in a wide current range in the subthreshold region, so that the current consumption can be reduced.
  • the transistor F2 and / or the transistor F2m can also be manufactured at the same time as the transistor F1 and the transistor F1m by using the OS transistor, so that the manufacturing process of the arithmetic circuit may be shortened. ..
  • the transistor F2 and / or the transistor F2m can be a transistor containing silicon in the channel forming region (hereinafter, referred to as a Si transistor) other than the OS transistor.
  • amorphous silicon sometimes referred to as hydrogenated amorphous silicon
  • microcrystalline silicon microcrystalline silicon
  • polycrystalline silicon single crystal silicon and the like
  • the first terminal of the transistor F1 is electrically connected to the gate of the transistor F2.
  • the first terminal of the transistor F2 is electrically connected to the wiring VE.
  • the first terminal of the capacitance C5 is electrically connected to the gate of the transistor F2.
  • the first terminal of the transistor F1m is electrically connected to the gate of the transistor F2m.
  • the first terminal of the transistor F2m is electrically connected to the wiring VE.
  • the first terminal having a capacitance of C5 m is electrically connected to the gate of the transistor F2 m.
  • a back gate is shown for the transistor F1, the transistor F2, the transistor F1m, and the transistor F2m, and the connection configuration of the back gate is not shown. It can be decided at the design stage.
  • the gate and the back gate may be electrically connected in order to increase the on-current of the transistor. That is, for example, the gate of the transistor F1 and the back gate may be electrically connected, or the gate of the transistor F1m and the back gate may be electrically connected.
  • the back gate of the transistor and an external circuit are electrically connected in order to fluctuate the threshold voltage of the transistor or to reduce the off current of the transistor.
  • a wiring for connection may be provided, and a potential may be applied to the back gate of the transistor by the external circuit or the like.
  • the transistor F1 and the transistor F2 shown in FIG. 7 have a back gate, but the semiconductor device according to one aspect of the present invention is not limited thereto.
  • the transistor F1 and the transistor F2 shown in FIG. 7 may have a configuration that does not have a back gate, that is, a transistor having a single gate structure. Further, some transistors may have a back gate, and some other transistors may not have a back gate.
  • the transistor F1 and the transistor F2 shown in FIG. 7 are n-channel transistors, but the semiconductor device according to one aspect of the present invention is not limited thereto.
  • the transistor F1 and a part or all of the transistor F2 may be replaced with a p-channel type transistor.
  • transistor F1 and the transistor F2 are not limited to the transistor F1 and the transistor F2.
  • the wiring VE is between the first terminal and the second terminal of each transistor F2 of the cell IM [1,1], the cell IM [m, 1], the cell IM [1, n], and the cell IM [m, n]. It is a wiring for passing a current through the cell IMref [1], and also functions as a wiring for passing a current between the first terminal and the second terminal of the respective transistors F2 of the cell IMref [1] and the cell IMref [m].
  • the wiring VE functions as a wiring for supplying a constant voltage.
  • the constant voltage can be, for example, a low level potential, a ground potential, or the like.
  • the second terminal of the transistor F1 is electrically connected to the wiring WCL [1]
  • the gate of the transistor F1 is electrically connected to the wiring WSL [1].
  • the second terminal of the transistor F2 is electrically connected to the wiring WCL [1]
  • the second terminal of the capacitance C5 is electrically connected to the wiring XCL [1].
  • the connection point between the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitance C5 is a node NN [1,1]. ..
  • the second terminal of the transistor F1 is electrically connected to the wiring WCL [1]
  • the gate of the transistor F1 is electrically connected to the wiring WSL [m].
  • the second terminal of the transistor F2 is electrically connected to the wiring WCL [1]
  • the second terminal of the capacitance C5 is electrically connected to the wiring XCL [m].
  • the connection point between the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitance C5 is a node NN [m, 1]. ..
  • the second terminal of the transistor F1 is electrically connected to the wiring WCL [n]
  • the gate of the transistor F1 is electrically connected to the wiring WSL [1].
  • the second terminal of the transistor F2 is electrically connected to the wiring WCL [n]
  • the second terminal of the capacitance C5 is electrically connected to the wiring XCL [1].
  • the connection point between the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitance C5 is a node NN [1, n]. ..
  • the second terminal of the transistor F1 is electrically connected to the wiring WCL [n]
  • the gate of the transistor F1 is electrically connected to the wiring WSL [m].
  • the second terminal of the transistor F2 is electrically connected to the wiring WCL [n]
  • the second terminal of the capacitance C5 is electrically connected to the wiring XCL [m].
  • the connection point between the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitance C5 is a node NN [m, n]. ..
  • the second terminal of the transistor F1m is electrically connected to the wiring XCL [1]
  • the gate of the transistor F1m is electrically connected to the wiring WSL [1].
  • the second terminal of the transistor F2m is electrically connected to the wiring XCL [1]
  • the second terminal of the capacitance C5 is electrically connected to the wiring XCL [1].
  • the connection point between the first terminal of the transistor F1m, the gate of the transistor F2m, and the first terminal of the capacitance C5 is a node NNref [1].
  • the second terminal of the transistor F1m is electrically connected to the wiring XCL [m]
  • the gate of the transistor F1m is electrically connected to the wiring WSL [m].
  • the second terminal of the transistor F2m is electrically connected to the wiring XCL [m]
  • the second terminal of the capacitance C5 is electrically connected to the wiring XCL [m].
  • the connection point between the first terminal of the transistor F1m, the gate of the transistor F2m, and the first terminal of the capacitance C5 is a node NNref [m].
  • node NN [1,1] to the node NN [m, n] and the node NNref [1] to the node NNref [m] function as holding nodes for their respective cells.
  • the transistor F2 has a diode connection configuration.
  • the constant voltage given by the wiring VE as the ground potential (GND)
  • the gate (node NN) of the transistor F2 is determined according to the amount of current I. Since the transistor F1 is in the ON state, the potential of the second terminal of the transistor F2 is ideally equal to the gate (node NN) of the transistor F2.
  • the transistor F2 can flow a current having a current amount I corresponding to the ground potential of the first terminal of the transistor F2 and the potential of the gate (node NN) of the transistor F2 between the source and drain of the transistor F2.
  • such an operation is referred to as "setting (programming) the amount of current flowing between the source and drain of the transistor F2 of the cell IM to I" and the like.
  • the circuit PTC has a circuit PTR [1] to a circuit PTR [m]. Further, each of the circuit PTR [1] to the circuit PTR [m] has a switch SA [1] to a switch SA [m] as an example.
  • the switch SA [1] to the switch SA [m] for example, an analog switch, an electric switch such as a transistor, or the like can be applied.
  • the transistor can be a transistor having the same structure as the transistor F1 and the transistor F2.
  • a mechanical switch may be applied.
  • the first terminal of the switch SA [1] is electrically connected to the wiring XCL [1], and the control terminal of the switch SA [1] is electrically connected to the wiring SWLA.
  • the second terminal of the switch SA [1] is electrically connected to the wiring EIL [1] of the layer ERL of the semiconductor device SDV of FIG. 1 as an example.
  • the first terminal of the switch SA [m] is electrically connected to the wiring XCL [m]
  • the control terminal of the switch SA [m] is electrically connected to the wiring SWLA.
  • the second terminal of the switch SA [m] is electrically connected to the wiring EIL [m] of the layer ERL of the semiconductor device SDV of FIG. 1 as an example.
  • the wiring SWLA functions as wiring for switching between the on state and the off state of each of the switch SA [1] to the switch SA [m]. Therefore, a high level potential or a low level potential is supplied to the wiring SWLA.
  • the circuit SWS1 has a transistor F3 [1] to a transistor F3 [n] as an example.
  • the first terminal of the transistor F3 [1] is electrically connected to the wiring WCL [1]
  • the second terminal of the transistor F3 [1] is electrically connected to the circuit WCS, and the gate of the transistor F3 [1].
  • the first terminal of the transistor F3 [n] is electrically connected to the wiring WCL [n]
  • the second terminal of the transistor F3 [n] is electrically connected to the circuit WCS, and the gate of the transistor F3 [n]. Is electrically connected to the wiring SWL1.
  • the wiring SWL1 functions as wiring for switching between the on state and the off state of each of the transistors F3 [1] to F3 [n]. Therefore, a high level potential or a low level potential is supplied to the wiring SWL1.
  • each of the transistors F3 [1] to F3 [n] for example, a transistor applicable to the transistor F1 and / or the transistor F2 can be used.
  • an OS transistor as each of the transistors F3 [1] to F3 [n].
  • an electric switch such as an analog switch, a mechanical switch, or the like may be applied.
  • the circuit SWS1 functions as a circuit that puts the circuit WCS and each of the wiring WCL [1] to the wiring WCL [n] in a conductive state or a non-conducting state. That is, the circuit SWS1 uses the transistors F3 [1] to F3 [n] as switching elements, so that the circuit WCS and the wiring WCL [1] to the wiring WCL [n] are in a conductive state or non-conducting. The state is being switched.
  • the circuit SWS2 has a transistor F4 [1] to a transistor F4 [n] as an example.
  • the first terminal of the transistor F4 [1] is electrically connected to the wiring WCL [1]
  • the second terminal of the transistor F4 [1] is electrically connected to the input terminal of the conversion circuit ITRZ [1] described later.
  • the gate of the transistor F4 [1] is electrically connected to the wiring SWL2.
  • the first terminal of the transistor F4 [n] is electrically connected to the wiring WCL [n]
  • the second terminal of the transistor F4 [n] is electrically connected to the input terminal of the conversion circuit ITRZ [n] described later.
  • the gate of the transistor F4 [n] is electrically connected to the wiring SWL2.
  • the wiring SWL2 functions as wiring for switching between the on state and the off state of each of the transistors F4 [1] to F4 [n]. Therefore, a high level potential or a low level potential is supplied to the wiring SWL2.
  • each of the transistors F4 [1] to F4 [n] for example, a transistor applicable to the transistor F1 and / or the transistor F2 can be used.
  • an OS transistor as each of the transistors F4 [1] to F4 [n].
  • an electric switch such as an analog switch, a mechanical switch, or the like may be applied.
  • the circuit SWS2 has a function of making the wiring WCL [1] or the wiring WCL [n] and the circuit ITS conductive or non-conducting. That is, the circuit SWS1 uses the transistors F4 [1] to F4 [n] as switching elements, so that the circuit ITS and the wiring WCL [1] to the wiring WCL [n] are in a conductive state or non-conducting. The state is being switched.
  • the circuit WCS has a function of supplying the wiring WCL [1] to the wiring WCL [n] with an amount of current corresponding to the first data. That is, the circuit WCS supplies the first data to be stored in each cell of the cell array CA when the transistor F3 [1] to the transistor F3 [n] is in the ON state.
  • the circuit XCS has a function of passing an amount of current according to the reference data described later or an amount of current according to the second data to the wiring XCL [1] to the wiring XCL [m]. That is, in the arithmetic circuit MAC1 of FIG. 7, the circuit XCS converts each of the cell IMref [1] to the cell IMref [m] of the cell array CA into an amount of current corresponding to the reference data or second data. Apply the corresponding amount of current.
  • the circuit WSD supplies a predetermined signal to the wiring WSL [1] to the wiring WSL [m] when writing the first data to the cell IM [1,1] to the cell IM [m, n].
  • This has a function of selecting the row of the cell array CA to which the first data is written.
  • the circuit WSD supplies a high level potential to the wiring WSL [1] and supplies a low level potential to the wiring WSL [2] (not shown) to the wiring WSL [m] to supply the wiring WSL [1]. It is possible to turn on the transistor F1 having a gate electrically connected and turn off the transistor F1 having a gate electrically connected to each of the wiring WSL [2] to the wiring WSL [m]. can.
  • the circuit WSD is electrically connected to the wiring SWL1 and the wiring SWL2 as an example.
  • the circuit WSD has a function of making a predetermined signal between the circuit WCS and the cell array CA in a conductive state or a non-conducting state by supplying a predetermined signal to the wiring SWL1, and supplies a predetermined signal to the wiring SWL2, which will be described later. It has a function of setting a conduction state or a non-conduction state between the conversion circuit ITRZ [1] or the conversion circuit ITRZ [n] and the cell array CA.
  • the circuit ITS has a conversion circuit ITRZ [1] to a conversion circuit ITRZ [n].
  • Each of the conversion circuit ITRZ [1] and the conversion circuit ITRZ [n] has an input terminal and an output terminal as an example.
  • the output terminal of the conversion circuit ITRZ [1] is electrically connected to the wiring OL [1]
  • the output terminal of the conversion circuit ITRZ [n] is electrically connected to the wiring OL [n].
  • Each of the conversion circuit ITRZ [1] and the conversion circuit ITRZ [n] has a function of converting into a voltage corresponding to the amount of current input to the input terminal and outputting it from the output terminal.
  • the voltage may be, for example, an analog voltage, a digital voltage, or the like.
  • each of the conversion circuit ITRZ [1] to the conversion circuit ITRZ [n] may have a function-based arithmetic circuit. In this case, for example, the converted voltage may be used to perform a function calculation by the calculation circuit, and the result of the calculation may be output to the wiring OL [1] to the wiring OL [n].
  • a sigmoid function for example, a tanh function, a softmax function, a ReLU function, a threshold function, or the like can be used as the above-mentioned functions.
  • Circuit WCS Circuit XCS
  • circuit WCS Circuit XCS
  • FIG. 8A is a block diagram showing an example of the circuit WCS. Note that FIG. 8A also shows the circuit SWS1, the transistor F3, the wiring SWL1, and the wiring WCL in order to show the electrical connection with the circuits around the circuit WCS.
  • the circuit WCS has, for example, as many circuits WCSa as there are wiring WCLs. That is, the circuit WCS has n circuits WCSa.
  • circuit SWS1 also has the same number of transistors F3 as the number of wiring WCLs. That is, the circuit SWS1 also has n transistors F3.
  • the transistor F3 shown in FIG. 8A can be any one of the transistor F3 [1] to the transistor F3 [n] included in the arithmetic circuit MAC1 of FIG. 7.
  • the wiring WCL can be any one of the wiring WCL [1] and the wiring WCL [n] included in the arithmetic circuit MAC1 of FIG. 7.
  • a separate circuit WCSa is electrically connected to each of the wiring WCL [1] to the wiring WCL [n] via a separate transistor F3.
  • the circuit WCSa shown in FIG. 8A has a switch SWW as an example.
  • the first terminal of the switch SWW is electrically connected to the second terminal of the transistor F3, and the second terminal of the switch SWW is electrically connected to the wiring VINIL1.
  • the wiring VINIL1 functions as a wiring that gives a potential for initialization to the wiring WCL, and the potential for initialization can be a ground potential (GND), a low level potential, a high level potential, or the like.
  • the switch SWW is turned on only when a potential for initialization is applied to the wiring WCL, and is turned off at other times.
  • the switch SWW for example, an analog switch, an electric switch such as a transistor, or the like can be applied.
  • the transistor can be a transistor having the same structure as the transistor F1 and the transistor F2.
  • a mechanical switch may be applied.
  • the circuit WCSa of FIG. 8A has a plurality of current sources CS as an example.
  • the circuit WCSa has a function of outputting the first data of K bits (2 K value) (K is an integer of 1 or more) as a current amount, and in this case, the circuit WCSa has 2 K- 1 pieces.
  • the circuit WCSa has one current source CS that outputs information corresponding to the value of the first bit as a current, and has two current source CSs that output information corresponding to the value of the second bit as a current.
  • it has 2K-1 current sources CS that output information corresponding to the K-bit value as a current.
  • each current source CS has a terminal T1 and a terminal T2.
  • the terminal T1 of each current source CS is electrically connected to the second terminal of the transistor F3 included in the circuit SWS1.
  • the terminal T2 of the one current source CS is electrically connected to the wiring DW [1]
  • each of the terminals T2 of the two current sources CS is electrically connected to the wiring DW [2]
  • 2 K -Each of the terminals T2 of one current source CS is electrically connected to the wiring DW [K].
  • Each of the plurality of current source CSs included in the circuit WCSa has a function of outputting the same constant current I Wut from the terminal T1.
  • the error of the constant current I Wut output from each of the terminals T1 of the plurality of current sources CS is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, it is assumed that there is no error in the constant current I Wut output from the terminals T1 of the plurality of current sources CS included in the circuit WCSa.
  • the wiring DW [1] to the wiring DW [K] function as wiring for transmitting a control signal for outputting a constant current I Wut from the electrically connected current source CS.
  • the current source CS electrically connected to the wiring DW [1] uses I Wut as a constant current of the transistor F3.
  • the current source CS electrically connected to the wiring DW [1] does not output I Wut.
  • the two current sources CS electrically connected to the wiring DW [2] when a high level potential is applied to the wiring DW [2], the two current sources CS electrically connected to the wiring DW [2] generate a constant current of a total of 2I Wut in the transistor F3.
  • the current source CS electrically connected to the wiring DW [2] draws a total constant current of 2I Wut. Do not output.
  • the current source CS electrically connected to the wiring DW [K] is Does not output a constant current of 2 K-1 I Wut in total.
  • the current flowing through one current source CS electrically connected to the wiring DW [1] corresponds to the value of the first bit
  • the two currents electrically connected to the wiring DW [2] corresponds to the value of the second bit
  • the amount of current flowing through the K current source CS electrically connected to the wiring DW [K] corresponds to the value of the K bit.
  • I Wut flows from the circuit WCSa to the second terminal of the transistor F3 of the circuit SWS1 as a constant current. Further, for example, when the value of the first bit is "0" and the value of the second bit is "1", a low level potential is given to the wiring DW [1] and a high level potential is given to the wiring DW [2]. Is given. At this time, 2I Wut flows from the circuit WCSa to the second terminal of the transistor F3 of the circuit SWS1 as a constant current. Further, for example, when the value of the first bit is "1" and the value of the second bit is "1", a high level potential is given to the wiring DW [1] and the wiring DW [2].
  • 3I Wut flows from the circuit WCSa to the second terminal of the transistor F3 of the circuit SWS1 as a constant current. Further, for example, when the value of the first bit is "0" and the value of the second bit is "0", a low level potential is given to the wiring DW [1] and the wiring DW "2". At this time, a constant current does not flow from the circuit WCSa to the second terminal of the transistor F3 of the circuit SWS1.
  • FIG. 8A illustrates the circuit WCSa when K is an integer of 3 or more, but when K is 1, the circuit WCSa of FIG. 8A is connected to the wiring DW [2] to the wiring DW [K].
  • the current source CS that is electrically connected to the device may not be provided.
  • the circuit WCSa of FIG. 8A may be configured so as not to provide the current source CS electrically connected to the wiring DW [3] to the wiring DW [K].
  • the current source CS1 shown in FIG. 9A is a circuit applicable to the current source CS included in the circuit WCSa of FIG. 8A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.
  • the first terminal of the transistor Tr1 is electrically connected to the wiring VDDL, and the second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. It is connected.
  • the second terminal of the transistor Tr2 is electrically connected to the terminal T1, and the gate of the transistor Tr2 is electrically connected to the terminal T2. Further, the terminal T2 is electrically connected to the wiring DW.
  • the wiring DW is any one of the wiring DW [1] to the wiring DW [n] of FIG. 8A.
  • Wiring VDDL functions as wiring that applies a constant voltage.
  • the constant voltage can be, for example, a high level potential.
  • the constant voltage given by the wiring VDDL is set to a high level potential
  • a high level potential is input to the first terminal of the transistor Tr1.
  • the potential of the second terminal of the transistor Tr1 is set to a potential lower than the high level potential.
  • the first terminal of the transistor Tr1 functions as a drain
  • the second terminal of the transistor Tr1 functions as a source.
  • the gate-source voltage of the transistor Tr1 is 0V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current (drain current) in the current range of the subthreshold region flows between the first terminal and the second terminal of the transistor Tr1.
  • the amount of the current is preferably 1.0 ⁇ 10-8 A or less, and more preferably 1.0 ⁇ 10-12 A or less. Further, it is more preferably 1.0 ⁇ 10 -15 A or less. Further, for example, it is more preferable that the current is in a range where the current increases exponentially with respect to the gate-source voltage. That is, the transistor Tr1 functions as a current source for passing a current in the current range when operating in the subthreshold region. Note that the current is equivalent to I Wut, or later to I Xut described above.
  • the transistor Tr2 functions as a switching element.
  • the first terminal of the transistor Tr2 functions as a drain and the second terminal of the transistor Tr2 functions as a source.
  • the back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are electrically connected, the voltage between the back gate and the source is 0 V. Therefore, when the threshold voltage of the transistor Tr2 is within an appropriate range, the transistor Tr2 is turned on by inputting a high level potential to the gate of the transistor Tr2, and the gate of the transistor Tr2 is low. When the level potential is input, the transistor Tr2 is turned off.
  • the current in the current range of the subthreshold region described above flows from the second terminal of the transistor Tr1 to the terminal T1, and when the transistor Tr2 is in the off state, the current is the transistor Tr1. It is assumed that the current does not flow from the second terminal to the terminal T1.
  • the circuit applicable to the current source CS included in the circuit WCSa of FIG. 8A is not limited to the current source CS1 of FIG. 9A.
  • the current source CS1 has a configuration in which the back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are electrically connected, but the back gate of the transistor Tr2 is electrically connected to another wiring. It may be configured as such.
  • An example of such a configuration is shown in FIG. 9B.
  • the current source CS2 shown in FIG. 9B has a configuration in which the back gate of the transistor Tr2 is electrically connected to the wiring VTHL.
  • the threshold voltage of the transistor Tr2 can be changed.
  • the off-current of the transistor Tr2 can be reduced by increasing the threshold voltage of the transistor Tr2.
  • the current source CS1 has a configuration in which the back gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected, but the back gate of the transistor Tr2 and the second terminal are connected to each other.
  • the voltage may be held by the capacity.
  • FIG. 9C An example of such a configuration is shown in FIG. 9C.
  • the current source CS3 shown in FIG. 9C has a transistor Tr3 and a capacitance C6 in addition to the transistor Tr1 and the transistor Tr2.
  • the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 are electrically connected via the capacitance C6, and the back gate of the transistor Tr1 and the first terminal of the transistor Tr3 are electrically connected.
  • the current source CS3 has a configuration in which the second terminal of the transistor Tr3 is electrically connected to the wiring VTL, and the gate of the transistor Tr3 is electrically connected to the wiring VWL.
  • the current source CS3 can bring the wiring VTL and the back gate of the transistor Tr1 into a conductive state by applying a high level potential to the wiring VWL to turn on the transistor Tr3.
  • a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr1.
  • the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 can be maintained by the capacitance C6. That is, the threshold voltage of the transistor Tr1 can be changed by determining the voltage given to the back gate of the transistor Tr1 by the wiring VTL, and the threshold voltage of the transistor Tr1 is fixed by the transistor Tr3 and the capacitance C6. can do.
  • the circuit applicable to the current source CS included in the circuit WCSa of FIG. 8A may be the current source CS4 shown in FIG. 9D.
  • the current source CS4 has a configuration in which the back gate of the transistor Tr2 is electrically connected to the wiring VTHL instead of the second terminal of the transistor Tr2 in the current source CS3 of FIG. 9C. That is, the current source CS4 can change the threshold voltage of the transistor Tr2 according to the potential given by the wiring VTHL, similarly to the current source CS2 of FIG. 9B.
  • the current source CS4 when a large current flows between the first terminal and the second terminal of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to allow the current to flow from the terminal T1 to the outside of the current source CS4. ..
  • the current source CS4 applies a high level potential to the wiring VTHL, lowers the threshold voltage of the transistor Tr2, and raises the on-current of the transistor Tr2, thereby increasing the on-current of the transistor Tr1.
  • a large current flowing between the terminals can be passed from the terminal T1 to the outside of the current source CS4.
  • the circuit WCSa By applying the current sources CS1 to CS4 shown in FIGS. 9A to 9D as the current source CS included in the circuit WCSa of FIG. 8A, the circuit WCSa outputs a current corresponding to the first data of K bits. can do. Further, the amount of the current can be, for example, the amount of current flowing between the first terminal and the second terminal within the range in which the transistor F1 operates in the subthreshold region.
  • the circuit WCSa of FIG. 8A has a configuration in which one current source CS of FIG. 9A is connected to each of the wiring DW [1] to the wiring DW [K]. Further, when the channel width of the transistor Tr1 [1] is w [1], the channel width of the transistor Tr1 [2] is w [2], and the channel width of the transistor Tr1 [K] is w [K], each channel is used.
  • the circuit WCSa shown in FIG. 8B corresponds to the first data of K bits like the circuit WCSa of FIG. 8A. It can output current.
  • the transistor Tr1 (including the transistor Tr1 [1] to the transistor Tr1 [K]), the transistor Tr2 (including the transistor Tr2 [1] to the transistor Tr2 [K]), and the transistor Tr3 are, for example, the transistor F1 and / Alternatively, a transistor applicable to the transistor F2 can be used.
  • an OS transistor may be used as the transistor Tr1 (including the transistor Tr1 [1] to the transistor Tr1 [K]), the transistor Tr2 (including the transistor Tr2 [1] to the transistor Tr2 [K]), and the transistor Tr3. preferable.
  • FIG. 8C is a block diagram showing an example of the circuit XCS. Note that FIG. 8C also shows the wiring XCL in order to show the electrical connection with the circuits around the circuit XCS.
  • the circuit XCS has, for example, as many circuits XCSa as there are wiring XCLs. That is, the circuit XCS has m circuits XCSa.
  • the wiring XCL shown in FIG. 8C can be any one of the wiring XCL [1] and the wiring XCL [m] included in the arithmetic circuit MAC1 of FIG. Therefore, a separate circuit XCSa is electrically connected to each of the wiring XCL [1] to the wiring XCL [m].
  • the circuit XCSa shown in FIG. 8C has a switch SWX as an example.
  • the first terminal of the switch SWX is electrically connected to the second terminal of the transistor F4, and the second terminal of the switch SWX is electrically connected to the wiring VINIL2.
  • the wiring VINIL2 functions as a wiring that gives an initialization potential to the wiring XCL, and the initialization potential can be a ground potential (GND), a low level potential, a high level potential, or the like. Further, the initialization potential given by the wiring VINIL2 may be equal to the potential given by the wiring VINIL1.
  • the switch SWX is turned on only when a potential for initialization is applied to the wiring XCL, and is turned off at other times.
  • the switch SWX can be, for example, a switch applicable to the switch SWW.
  • the circuit configuration of the circuit XCSa of FIG. 8C can be substantially the same as that of the circuit WCSa of FIG. 9A.
  • the circuit XCSa has a function of outputting reference data as a current amount and a function of outputting second data of L bits (2 L value) (L is an integer of 1 or more) as a current amount.
  • the circuit XCSa has 2 L- 1 current source CS.
  • the circuit XCSa has one current source CS that outputs information corresponding to the value of the first bit as a current, and has two current source CSs that output information corresponding to the value of the second bit as a current. It has 2 L-1 current sources CS that output information corresponding to the value of the L-th bit as a current.
  • the value of the first bit can be "1" and the value of the second and subsequent bits can be "0".
  • the terminal T2 of one current source CS is electrically connected to the wiring DX [1], and each of the terminals T2 of the two current source CS is electrically connected to the wiring DX [2]. 2 L-1 Each of the terminals T2 of the current source CS is electrically connected to the wiring DX [L].
  • the plurality of current source CSs included in the circuit XCSa each have a function of outputting IXut from the terminal T1 as the same constant current.
  • the wiring DX [1] to the wiring DX [L] function as wiring for transmitting a control signal for outputting the IXut from the electrically connected current source CS. That is, the circuit XCSa has a function of passing an amount of current corresponding to the information of the L bits sent from the wiring DX [1] to the wiring DX [L] to the wiring XCL.
  • 2I Xut flows from the circuit XCSa to the wiring XCL as a constant current.
  • a high level potential is given to the wiring DX [1] and the wiring DX [2].
  • 3I Xut flows from the circuit XCSa to the wiring XCL as a constant current.
  • a low level potential is given to the wiring DX [1] and the wiring DX [2].
  • no constant current flows from the circuit XCSa to the wiring XCL.
  • a current having a current amount of zero flows from the circuit XCSa to the wiring XCL.
  • the current amount zero, I Xut , 2I Xut , 3I Xut, etc. output by the circuit XCSa can be used as the second data output by the circuit XCSa, and in particular, the current amount I Xut output by the circuit XCSa is a circuit. It can be the reference data output by XCSa.
  • the constant current I Xut output from each of the terminals T1 of the plurality of current source CSs is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, it is assumed that there is no error in the constant current I Xut output from the terminals T1 of the plurality of current sources CS included in the circuit XCSa.
  • any of the current sources CS1 to CS4 of FIGS. 9A to 9D can be applied as in the current source CS of the circuit WCSa.
  • the wiring DW shown in FIGS. 9A to 9C may be replaced with the wiring DX.
  • the circuit XCSa can pass a current in the current range of the subthreshold region to the wiring XCL as reference data or second data of the L bit.
  • the same circuit configuration as the circuit WCSa shown in FIG. 8B can be applied.
  • the circuit WCSa shown in FIG. 8B is replaced with the circuit XCSa
  • the wiring DW [1] is replaced with the wiring DX [1]
  • the wiring DW [2] is replaced with the wiring DX [2]
  • the wiring DW [K] is wired. It may be considered by replacing DX [L], replacing the switch SWW with the switch SWX, and replacing the wiring VINIL1 with the wiring VINIL2.
  • the conversion circuit ITRZ1 shown in FIG. 10A is an example of a circuit that can be applied to the conversion circuit ITRZ [1] to the conversion circuit ITRZ [n] of FIG.
  • FIG. 10A also shows the circuit SWS2, the wiring WCL, the wiring SWL2, and the transistor F4 in order to show the electrical connection with the circuits around the conversion circuit ITRZ1.
  • the wiring WCL is any one of the wiring WCL [1] and the wiring WCL [n] included in the arithmetic circuit MAC1 of FIG. 7, and the transistor F4 is included in the arithmetic circuit MAC1 of FIG. It is any one of the transistor F4 [1] to the transistor F4 [n].
  • the conversion circuit ITRZ1 of FIG. 10A is electrically connected to the wiring WCL via the transistor F4. Further, the conversion circuit ITRZ1 is electrically connected to the wiring OL.
  • the conversion circuit ITRZ1 has a function of converting the amount of current flowing from the conversion circuit ITRZ1 to the wiring WCL or the amount of current flowing from the wiring WCL to the conversion circuit ITRZ1 into an analog voltage and outputting the analog voltage to the wiring OL. That is, the conversion circuit ITRZ1 has a current-voltage conversion circuit.
  • the conversion circuit ITRZ1 of FIG. 10A has a resistor R5 and an operational amplifier OP1 as an example.
  • the inverting input terminal of the operational amplifier OP1 is electrically connected to the first terminal of the resistor R5 and the second terminal of the transistor F4.
  • the non-inverting input terminal of the operational amplifier OP1 is electrically connected to the wiring VRL.
  • the output terminal of the operational amplifier OP1 is electrically connected to the second terminal of the resistor R5 and the wiring OL.
  • Wiring VRL functions as wiring that gives a constant voltage.
  • the constant voltage can be, for example, a ground potential (GND), a low level potential, or the like.
  • the conversion circuit ITRZ1 has the configuration shown in FIG. 10A, so that the amount of current flowing from the wiring WCL to the conversion circuit ITRZ1 via the transistor F4, or the current flowing from the conversion circuit ITRZ1 to the wiring WCL via the transistor F4.
  • the amount can be converted into an analog voltage and output to the wiring OL.
  • the inverting input terminal of the operational amplifier OP1 becomes virtual ground, so the analog voltage output to the wiring OL is based on the ground potential (GND). It can be a voltage.
  • the conversion circuit ITRZ1 of FIG. 10A is configured to output an analog voltage, but the circuit configuration applicable to the conversion circuit ITRZ [1] to the conversion circuit ITRZ [n] of FIG. 7 is not limited to this.
  • the conversion circuit ITRZ1 may have a configuration having an analog-digital conversion circuit ADC as shown in FIG. 10B.
  • the input terminal of the analog-digital conversion circuit ADC is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, and the analog-digital conversion circuit ADC has.
  • the output terminal is electrically connected to the wiring OL.
  • the conversion circuit ITRZ2 of FIG. 10B can output a digital signal to the wiring OL.
  • the conversion circuit ITRZ2 when the digital signal output to the wiring OL is 1 bit (binary value), the conversion circuit ITRZ2 may be replaced with the conversion circuit ITRZ3 shown in FIG. 10C.
  • the conversion circuit ITRZ3 of FIG. 10C has a configuration in which a comparator CMP1 is provided in the conversion circuit ITRZ1 of FIG. 10A. Specifically, in the conversion circuit ITRZ3, the first input terminal of the comparator CMP1 is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, and the second input terminal of the comparator CMP1 is the wiring VRL2. The output terminal of the comparator CMP1 is electrically connected to the wiring OL.
  • the wiring VRL2 functions as a wiring that gives a potential for comparison with the potential of the first terminal of the comparator CMP1.
  • the conversion circuit ITRZ3 of FIG. 10C has a magnitude of the voltage converted from the amount of current flowing between the source and drain of the transistor F4 by the current-voltage conversion circuit and the voltage given by the wiring VRL2.
  • a low level potential or a high level potential can be output to the wiring OL.
  • the conversion circuit ITRZ [1] to the conversion circuit ITRZ [n] applicable to the arithmetic circuit MAC1 in FIG. 7 is not limited to the conversion circuit ITRZ1 to the conversion circuit ITRZ3.
  • the conversion circuit ITRZ1 to the conversion circuit ITRZ3 have a functional arithmetic circuit.
  • the arithmetic circuit of the function system can be an arithmetic circuit such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold value function.
  • the operation circuit MAC1 can change the circuit configuration depending on the situation.
  • the arithmetic circuit MAC1 may be changed to a configuration in which the circuit SWS1 is not provided, as shown in the arithmetic circuit MAC1A shown in FIG.
  • the circuit SWS1 can stop the current flowing from the circuit WCS to the wiring WCL [1] to the wiring WCL [n], but in the case of the arithmetic circuit MAC1A, the circuit WCS can stop the current flowing from the circuit WCS to the wiring WCL.
  • the current flowing through [1] to the wiring WCL [n] may be stopped.
  • the circuit WCSa of FIG. 8A is applied as the circuit WCSa included in the circuit WCS of the arithmetic circuit MAC1A and the current source CS1 of FIG. 9A is applied as the current source CS
  • the wiring DW [1] to the wiring A low level potential may be input to each of the DW [K], and the switch SWW may be turned off.
  • the circuit WCSa By operating the circuit WCSa in this way, the current flowing from the circuit WCS to the wiring WCL [1] to the wiring WCL [n] can be stopped. In this way, by stopping the current flowing from the circuit WCS to the wiring WCL [1] to the wiring WCL [n], the calculation can be performed using the calculation circuit MAC1A instead of the calculation circuit MAC1.
  • FIG. 12 shows a timing chart of an operation example of the arithmetic circuit MAC1.
  • wiring SWL1, wiring SWL2, wiring SWLA, and wiring WSL [i] (i is an integer of 1 or more and m-1 or less) between the time T11 and the time T23 and in the vicinity thereof. )
  • Wiring WSL [i + 1] Wiring XCL [i]
  • Wiring XCL [i + 1] Node NN [i, j] (j is an integer of 1 or more and n-1 or less)
  • Node NN [i + 1, j] Node NNref [i]
  • node NNref [i + 1 Node NNref [i + 1
  • cell IM [i, j] the first terminal of the transistor F2 contained in the - amount of the current flowing between the second terminal I F2 [i, j] and the cell IMref [i ],
  • the current amount I F2 [i + 1, j ] that flows between the cells IMref first terminal of the transistor F2m contained in [i + 1] - current amount I F2m flowing between the second terminal [i + 1], each variation in Is also shown.
  • the circuit WCS of FIG. 8A is applied as the circuit WCS of the arithmetic circuit MAC1, and the circuit XCS of FIG. 8C is applied as the circuit XCS of the arithmetic circuit MAC1.
  • the potential of the wiring VE is the ground potential GND.
  • the potentials of the node NN [i, j], the node NN [i + 1, j], the node NNref [i], and the node NNref [i + 1] are set to the ground potential GND as initial settings. It is assumed that it is.
  • the potential for initialization of the wiring VINIL1 in FIG. 8A is set to the ground potential GND, and is included in the switch SWW, the transistor F3, and the cell IM [i, j] and the cell IM [i + 1, j].
  • the potentials of the nodes NN [i, j] and the nodes NN [i + 1, j] can be set to the ground potential GND.
  • the potential for initialization of the wiring VINIL2 in FIG. 8C is set to the ground potential GND, and the switch SWX and the respective transistors F1m included in the cell IMref [i, j] and the cell IMref [i + 1, j] are used.
  • the potentials of the nodes NNref [i, j] and the nodes NNref [i + 1, j] can be set to the ground potential GND.
  • each of the switch SA [1] to the switch SA [m] is turned on when a high level potential is input to the control terminal, and is turned off when a low level potential is input to the control terminal. It shall be. Further, the potential given by the wiring SWLA is always a low level potential (denoted as Low in FIG. 12). Therefore, in this operation example, the switch SA [1] to the switch SA [m] are always in the off state.
  • a high level potential (denoted as High in FIG. 12) is applied to the wiring SWL1 and a low level potential (denoted as Low in FIG. 12) is applied to the wiring SWL2. Is applied.
  • a high level potential is applied to each gate of the transistor F3 [1] to the transistor F3 [n]
  • each of the transistor F3 [1] to the transistor F3 [n] is turned on
  • the transistor F4 [1] is turned on.
  • a low level potential is applied to each of the gates of the transistors F4 [n] to turn off each of the transistors F4 [1] to F4 [n].
  • a low level potential is applied to the wiring WSL [i] and the wiring WSL [i + 1].
  • the gate of the transistor F1 included in the cell IM [i, 1] to the cell IM [i, n] in the i-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref [i] And, a low level potential is applied to, and each transistor F1 and transistor F1m are turned off.
  • a low level potential is applied to, and the respective transistors F1 and F1m are turned off.
  • the ground potential GND is applied to the wiring XCL [i] and the wiring XCL [i + 1].
  • the initialization potential of the wiring VINIL2 is set to the ground potential GND, and the switch SWX is set.
  • the potentials of the wiring XCL [i] and the wiring XCL [i + 1] can be set to the ground potential GND.
  • wiring is performed in the circuit WCSa of FIG. 8A, which is electrically connected to the wiring WCL [1] to the wiring WCL [n] via separate transistors F3.
  • the first data is not input to the DW [1] to the wiring DW [K].
  • the circuit WCSa of FIG. 8A it is assumed that a low level potential is input to each of the wiring DW [1] and the wiring DW [K].
  • a high level potential is applied to the wiring WSL [i] between time T12 and time T13.
  • the gate of the transistor F1 included in the cell IM [i, 1] to the cell IM [i, n] in the i-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref [i] A high level potential is applied to and, and the respective transistors F1 and F1m are turned on.
  • a low level potential is applied to the wiring WSL [1] to the wiring WSL [m] other than the wiring WSL [i], and the cells other than the i-th row of the cell array CA are applied.
  • the transistor F1 included in the IM [1,1] to the cell IM [m, n] and the transistor F1m included in the cell IMref [1] to the cell IMref [m] other than the i-th row are in the off state. It is assumed that it is.
  • ground potential GND is continuously applied to the wiring XCL [1] to the wiring XCL [m] from before the time T12.
  • a current of a current amount I 0 [i, j] flows from the circuit WCS to the cell array CA via the transistor F3 [j] as the first data.
  • the wiring WCL shown in FIG. 8A is the wiring WCL [j]
  • a signal corresponding to the first data is input to each of the wiring DW [1] to the wiring DW [K].
  • Current I 0 [i, j] flows from the circuit WCSa to the second terminal of the transistor F3 [j].
  • the first terminal of the transistor F1 included in the cell IM [i, j] in the i-th row of the cell array CA and the wiring WCL [j] are in a conductive state.
  • the transistor F1 included in the cell IM [i, j] when the transistor F1 included in the cell IM [i, j] is turned on, the transistor F2 included in the cell IM [i, j] has a diode connection configuration. Therefore, when a current flows from the wiring WCL [j] to the cell IM [i, j], the potentials of the gate of the transistor F2 and the second terminal of the transistor F2 become substantially equal. The potential is determined by the amount of current flowing from the wiring WCL [j] to the cell IM [i, j], the potential of the first terminal of the transistor F2 (here, GND), and the like.
  • the potential of the gate (node NN [i, j]) of the transistor F2 is caused by the current of the current amount I 0 [i, j] flowing from the wiring WCL [j] to the cell IM [i, j].
  • the threshold voltage of the transistor F2 is Vth [i, j]
  • the amount of current I 0 [i, j] when the transistor F2 operates in the subthreshold region is described by the following equation. can.
  • I a is the drain current when V g [i, j] is V th [i, j], and J is a correction coefficient determined by the temperature, device structure, and the like.
  • the circuit XCS, the wiring XCL [i], the current of the current amount I ref0 flows as reference data.
  • the wiring XCL shown in FIG. 8C is the wiring XCL [i]
  • the wiring DX [1] has a high level potential
  • the wiring DX [2] to the wiring DX [K] have a low level potential.
  • Is input, and the current I ref0 flows from the circuit XCSa to the wiring XCL [i]. That is, I ref0 I Xut .
  • the first terminal of the transistor F1m included in the cell IMref [i] and the wiring XCL [i] are in a conductive state, so that the wiring XCL [i] to the cell IMref current of the current amount I ref0 flows [i].
  • the transistor F2m included in the cell IMref [i] has a diode connection configuration. .. Therefore, when a current flows from the wiring XCL [i] to the cell IMref [i], the potentials of the gate of the transistor F2m and the second terminal of the transistor F2m become substantially equal. The potential is determined by the amount of current flowing from the wiring XCL [i] to the cell IMref [i], the potential of the first terminal of the transistor F2m (here, GND), and the like.
  • the gate of the transistor F2 (node NNref [i]) is assumed to be V gm [i]
  • the potential of the wiring XCL [i] at this time is also set to V gm [i]. That is, in the transistor F2m, the gate-source voltage becomes V gm [i] -GND, and the current amount I ref 0 is set as the current flowing between the first terminal and the second terminal of the transistor F2m.
  • the current amount I ref0 when transistor F2m operates in the subthreshold region can be described as the following equation.
  • the correction coefficient J is the same as that of the transistor F2 included in the cell IM [i, j].
  • the device structure and size (channel length, channel width) of the transistors are the same.
  • the correction coefficient J of each transistor varies due to manufacturing variation, it is assumed that the variation is suppressed to the extent that the discussion described later holds with practically sufficient accuracy.
  • the weighting coefficient w [i, j], which is the first data is defined as follows.
  • equation (1.1) can be rewritten as the following equation.
  • the capacitance C5 has the potential of the gate (node NN [i, j]) of the transistor F2 and the wiring XCL [i]. The difference between the potential and V g [i, j] -V gm [i] is retained. Further, when the transistor F1 included in the cell IMref [i] is turned off, the potential of the gate (node NNref [i]) of the transistor F2m and the potential of the wiring XCL [i] are added to the capacitance C5m. 0, which is the difference between, is retained.
  • the voltage held by the capacitance C5m is a voltage that is not 0 (here, for example, V ds ) depending on the transistor characteristics of the transistor F1m and / or the transistor F2m in the operation from the time T13 to the time T14.
  • V ds the potential of the node NNref [i] may be considered as the potential obtained by adding V ds to the potential of the wiring XCL [i].
  • GND is applied to the wiring XCL [i] between the time T15 and the time T16.
  • the wiring XCL shown in FIG. 8C is the wiring XCL [i]
  • the wiring is performed by setting the initial potential of the wiring VINIL2 to the ground potential GND and turning on the switch SWX.
  • the potential of XCL [i] can be set to the ground potential GND.
  • the nodes NN [i, 1] to the nodes NN [i, n] are combined by the capacitance C5 included in each of the cell IM [i, 1] to the cell IM [i, n] in the i-th row.
  • the potential of the node NNref [i] changes due to capacitive coupling by the capacitance C5m contained in the cell IMref [i].
  • the amount of change in the potential of the nodes NN [i, 1] to the node NN [i, n] is the amount of change in the potential of the wiring XCL [i], and each cell IM [i, 1] included in the cell array CA.
  • the potential is multiplied by the capacitive coupling coefficient determined by the configuration of the cell IM [i, n].
  • the capacitive coupling coefficient is calculated from the capacitance of the capacitance C5, the gate capacitance of the transistor F2, the parasitic capacitance, and the like.
  • the potential of the node NNref [i] also changes due to the capacitance coupling by the capacitance C5m included in the cell IMref [i].
  • the capacitive coupling coefficient due to the capacitance C5m is p as in the capacitance C5
  • the potential of the node NNref [i] of the cell IMref [i] is p (V gm [V gm] from the potential between the time T14 and the time T15. i] -GND) Decrease.
  • p 1 is set as an example. Therefore, the potential of the node NNref [i] between the time T15 and the time T16 becomes GND.
  • a high level potential is applied to the wiring WSL [i + 1] between time T16 and time T17.
  • a high level potential is applied to and, and the respective transistors F1 and F1m are turned on.
  • a low level potential is applied to the wiring WSL [1] to the wiring WSL [m] other than the wiring WSL [i + 1], and the cells other than the i + 1th row of the cell array CA.
  • the transistor F1 included in the IM [1,1] to the cell IM [m, n] and the transistor F1m included in the cell IMref [1] to the cell IMref [m] other than the i + 1th row are in the off state. It is assumed that it is.
  • ground potential GND is continuously applied to the wiring XCL [1] to the wiring XCL [m] from before the time T16.
  • a current of current amount I 0 [i + 1, j] flows from the circuit WCS to the cell array CA via the transistor F3 [j] as the first data.
  • the wiring WCL shown in FIG. 8A is the wiring WCL [j + 1]
  • a signal corresponding to the first data is input to each of the wiring DW [1] to the wiring DW [K].
  • Current I 0 [i + 1, j] flows from the circuit WCSa to the second terminal of the transistor F3 [j].
  • the first terminal of the transistor F1 included in the cell IM [i + 1, j] in the i + 1th row of the cell array CA and the wiring WCL [j] are in a conductive state, and the i + 1 of the cell array CA is in a conductive state.
  • Wiring because the first terminal of the transistor F1 included in the cells IM [1, j] to cell IM [m, j] other than the row and the wiring WCL [j] are in a non-conducting state.
  • a current with a current amount of I 0 [i + 1, j] flows from the WCL [j] to the cell IM [i + 1, j].
  • the transistor F1 included in the cell IM [i + 1, j] when the transistor F1 included in the cell IM [i + 1, j] is turned on, the transistor F2 included in the cell IM [i + 1, j] has a diode connection configuration. Therefore, when a current flows from the wiring WCL [j] to the cell IM [i + 1, j], the potentials of the gate of the transistor F2 and the second terminal of the transistor F2 become substantially equal. The potential is determined by the amount of current flowing from the wiring WCL [j] to the cell IM [i + 1, j], the potential of the first terminal of the transistor F2 (here, GND), and the like.
  • the potential of the gate (node NN [i + 1, j]) of the transistor F2 is caused by the current of the current amount I 0 [i + 1, j] flowing from the wiring WCL [j] to the cell IM [i + 1, j].
  • the threshold voltage of the transistor F2 is Vth [i + 1, j]
  • the amount of current I 0 [i + 1, j] when the transistor F2 operates in the subthreshold region is described by the following equation. can.
  • the correction coefficient is J, which is the same as the transistor F2 included in the cell IM [i, j] and the transistor F2m included in the cell IMref [i].
  • the circuit XCS current of the current amount I ref0 flows as reference data in the line XCL [i + 1].
  • the wiring DX [1] has a high level potential and the wiring DX [2].
  • the first terminal of the transistor F1m included in the cell IMref [i + 1] and the wiring XCL [i + 1] are in a conductive state, so that the wiring XCL [i + 1] to the cell IMref A current with a current amount of I ref0 flows through [i + 1].
  • the transistor F1m included in the cell IMref [i + 1] is turned on, so that the transistor F2m included in the cell IMref [i + 1, j] is connected by a diode. It becomes. Therefore, when a current flows from the wiring XCL [i + 1] to the cell IMref [i + 1], the potentials of the gate of the transistor F2m and the second terminal of the transistor F2m become substantially equal. The potential is determined by the amount of current flowing from the wiring XCL [i + 1] to the cell IMref [i + 1], the potential of the first terminal of the transistor F2m (here, GND), and the like.
  • the gate (node NNref [i + 1]) of the transistor F2 becomes V gm [i + 1] by the current of the current amount I ref0 flowing from the wiring XCL [i + 1] to the cell IMref [i + 1]. Further, the potential of the wiring XCL [i + 1] at this time is also set to V gm [i + 1]. That is, in the transistor F2m, the gate-source voltage becomes V gm [i + 1] -GND, and the current amount I ref 0 is set as the current flowing between the first terminal and the second terminal of the transistor F2m.
  • the current amount I ref0 when transistor F2m operates in the subthreshold region can be described as the following equation.
  • the correction coefficient J is the same as that of the transistor F2 included in the cell IM [i + 1, j].
  • the weighting coefficient w [i + 1, j], which is the first data is defined as follows.
  • equation (1.5) can be rewritten as the following equation.
  • a low level potential is applied to the wiring WSL [i + 1] between time T18 and time T19.
  • a low level potential is applied to, and each transistor F1 and transistor F1m are turned off.
  • the capacitance C5 When the transistor F1 included in the cell IM [i + 1, j] is turned off, the capacitance C5 has the potential of the gate (node NN [i + 1, j]) of the transistor F2 and the wiring XCL [i + 1]. The difference between the potential and V g [i + 1, j] -V gm [i + 1] is retained. Further, when the transistor F1 included in the cell IMref [i + 1] is turned off, the potential of the gate (node NNref [i + 1]) of the transistor F2m and the potential of the wiring XCL [i + 1] are added to the capacitance C5m. 0, which is the difference between, is retained.
  • the voltage held by the capacitance C5m is a voltage that is not 0 depending on the transistor characteristics of the transistor F1m and / or the transistor F2m in the operation from the time T18 to the time T19 (here, for example, V ds ). ) May be.
  • the potential of the node NNref [i + 1] may be considered as the potential obtained by adding V ds to the potential of the wiring XCL [i + 1].
  • the ground potential GND is applied to the wiring XCL [i + 1].
  • the wiring XCL shown in FIG. 8C is the wiring XCL [i + 1]
  • the wiring is made by setting the initial potential of the wiring VINIL2 to the ground potential GND and turning on the switch SWX.
  • the potential of XCL [i + 1] can be set to the ground potential GND.
  • the nodes NN [i, 1] to the nodes NN [i + 1, n] are combined by the capacitance C5 included in each of the cell IM [i + 1,1] to the cell IM [i + 1, n] in the i + 1 row.
  • the potential of the node NNref [i + 1] changes due to the capacitive coupling by the capacitance C5m contained in the cell IMref [i + 1].
  • the amount of change in the potential of the node NN [i + 1,1] to the node NN [i + 1,n] is the amount of change in the potential of the wiring XCL [i + 1], and each cell IM [i + 1,1] included in the cell array CA.
  • the potential is multiplied by the capacitive coupling coefficient determined by the configuration of the cell IM [i + 1, n].
  • the capacitive coupling coefficient is calculated from the capacitance of the capacitance C5, the gate capacitance of the transistor F2, the parasitic capacitance, and the like.
  • the potential of the node NNref [i + 1] also changes due to the capacitance coupling by the capacitance C5m included in the cell IMref [i + 1].
  • the capacitive coupling coefficient due to the capacitance C5m is p as in the capacitance C5
  • the potential of the node NNref [i + 1] of the cell IMref [i + 1] is p (V) from the potential at the time point between the time T18 and the time T19.
  • gm [i + 1] -GND decreases.
  • a low level potential is applied to the wiring SWL1 between the time T20 and the time T21.
  • a low level potential is applied to the gates of the transistors F3 [1] to F3 [n], and each of the transistors F3 [1] to F3 [n] is turned off.
  • a high level potential is applied to the wiring SWL2 between the time T21 and the time T22.
  • a high level potential is applied to the respective gates of the transistors F4 [1] to F4 [n], and each of the transistors F4 [1] to F4 [n] is turned on.
  • a current of x [i] I ref0 which is x [i] times the current amount I ref0 , flows from the circuit XCS to the wiring XCL [i] as the second data.
  • the wiring XCL shown in FIG. 8C is the wiring XCL [i]
  • each of the wiring DX [1] to the wiring DX [K] is subjected to the value of x [i].
  • x [i] corresponds to the value of the second data.
  • the potential of the wiring XCL [i] changes from 0 to V gm [i] + ⁇ V [i].
  • the node is coupled by the capacitance C5 included in each of the cell IM [i, 1] to the cell IM [i, n] in the i-th row of the cell array CA.
  • the potentials of NN [i, 1] to node NN [i, n] also change. Therefore, the potential of the node NN [i, j] of the cell IM [i, j] is V g [i, j] + p ⁇ V [i].
  • the potential of the node NNref [i] in the cell IMref [i] is V gm [i] + p ⁇ V [i].
  • the quantity I ref1 [i, j] can be described as follows.
  • the amount of current flowing between the first terminal and the second terminal of the transistor F2 included in the cell IM [i, j] is the first data w [i, j] and the second data x [i]. Is proportional to the product of.
  • a current of x [i + 1] I ref0 which is x [i + 1] times the current amount I ref0 , flows from the circuit XCS to the wiring XCL [i + 1] as the second data.
  • the wiring XCL shown in FIG. 8C is the wiring XCL [i + 1]
  • each of the wiring DX [1] to the wiring DX [K] is subjected to the value of x [i + 1].
  • x [i + 1] I ref0 x [i + 1] I Xut flows from the circuit XCSa to the wiring XCL [i + 1] as a current amount.
  • x [i + 1] corresponds to the value of the second data.
  • the potential of the wiring XCL [i + 1] changes from 0 to V gm [i + 1] + ⁇ V [i + 1].
  • the node is coupled by the capacitance C5 included in each of the cell IM [i + 1,1] to the cell IM [i + 1,n] in the i + 1th row of the cell array CA.
  • the potentials of NN [i + 1,1] to node NN [i + 1,n] also change. Therefore, the potential of the node NN [i + 1, j] of the cell IM [i + 1, j] is V g [i + 1, j] + p ⁇ V [i + 1].
  • the potential of the node NNref [i + 1] in the cell IMref [i + 1] is V gm [i + 1] + p ⁇ V [i + 1].
  • the amount of current flowing between the first terminal and the second terminal of the transistor F2 included in the cell IM [i + 1, j] is w [i + 1, j] which is the first data and x which is the second data. It is proportional to the product of [i + 1].
  • the amount of current output from the conversion circuit ITRZ [j] is the weighting coefficients w [i, j] and w [i + 1, j], which are the first data, and the signal value x [of the neuron, which is the second data.
  • the amount of current is proportional to the sum of products of i] and x [i + 1].
  • the arithmetic circuit MAC1 uses one of the plurality of columns as a cell that holds I ref0 and xI ref0 as the amount of current, so that the product-sum operation processing can be performed simultaneously for the number of the remaining columns among the plurality of columns. Can be executed. That is, by increasing the number of columns in the memory cell array, it is possible to provide a semiconductor device that realizes high-speed product-sum calculation processing.
  • FIG. 13 shows a timing chart of an operation example of the arithmetic circuit MAC1. Similar to the timing chart of FIG. 12, the timing chart of FIG. 13 shows the wiring SWL1, the wiring SWL2, the wiring SWLA, and the wiring WSL [i] (i is 1 or more) between the time T11 and the time T23 and in the vicinity thereof. (M-1 or less integer.), Wiring WSL [i + 1], Wiring XCL [i], Wiring XCL [i + 1], Node NN [i, j] (j is an integer of 1 or more and n-1 or less.
  • the operation example of the timing chart of FIG. 13 is different from the timing chart of FIG. 12 in that a high level potential is input to the wiring SWLA at a predetermined timing. That is, the operation example of the timing chart of FIG. 13 is different from the timing chart of FIG. 12 in that the sensor SNC [1] to the sensor SNC [m] are used. Therefore, in the description of the operation example of the timing chart of FIG. 13, the contents of the operation example of the timing chart of FIG. 12 will be taken into consideration, and the parts different from the operation example of the timing chart of FIG. 12 will be mainly described.
  • the operation is the same as that of the timing chart of FIG. 12 before the time T11 and between the time T11 and the time T13.
  • each of the switch SA [1] to the switch SA [m] having a control terminal electrically connected to the wiring SWLA is turned on.
  • I ref0 flows as the current amount of wiring XCL [i] via the wiring EIL [i] from the sensor SNC [i] layer PDL.
  • the I ref0 can be, for example, the amount of the current (sometimes referred to as the reference current) that is output by sensing the first information that is the reference by the sensor SNC [i] of FIG.
  • the potential of the wiring XCL [i] becomes, for example, V gm [i].
  • the sensor SNC [1] to the sensor SNC [m] other than the sensor SNC [i] may or may not perform sensing.
  • the circuit XCS all the switches SWX included in the circuit XCSa other than the i-th line are turned on, and the wiring XCL [1] to the wiring XCL [m] other than the wiring XCL [i] are respectively turned on. It is preferable that the potential of is set to the ground potential.
  • I ref0 flows as a current from the sensor SNC [i + 1] of the layer PDL to the wiring XCL [i + 1].
  • the I ref0 can be, for example, a reference current for sensing and outputting the first information to which the sensor SNC [i] in FIG. 1 serves as a reference.
  • the first information may be the same as or different from the first information sensed by the sensor SNC [i] between the time T13 and the time T15 in the timing chart of FIG. good.
  • the circuit XCS by turning off the switch SWX of the circuit XCSa on the i + 1 line, the potential of the wiring XCL [i + 1] becomes, for example, V gm [i + 1].
  • the sensor SNC [1] to the sensor SNC [m] other than the sensor SNC [i + 1] may or may not perform sensing.
  • the circuit XCS all the switches SWX included in the circuit XCSa other than the i-th line are turned on, and the wiring XCL [1] to the wiring XCL [m] other than the wiring XCL [i] are respectively turned on. It is preferable that the potential of is set to the ground potential.
  • the current x [i] I ref0 can be, for example, a current that the sensor SNC [i] of FIG. 1 senses and outputs the second information. That is, in the sensor SNC [i], the output current corresponding to the second information corresponds to x [i] times the output current corresponding to the first information. Further, in the circuit XCS, by turning off the switch SWX of the circuit XCSa on the i-th line, the potential of the wiring XCL [i] is changed to, for example, V gm [i] + ⁇ V [i].
  • the current x [i + 1] I ref0 can be, for example, a current that the sensor SNC [i + 1] of FIG. 1 senses and outputs the second information. That is, in the sensor SNC [i + 1], the output current corresponding to the second information corresponds to x [i + 1] times the output current corresponding to the first information.
  • the potential of the wiring XCL [i + 1] is changed to, for example, V gm [i + 1] + ⁇ V [i + 1].
  • the amount of current flowing between the conversion circuit ITRZ [j] and the wiring WCL [j] is determined by the first terminal of the transistor F2 of the cell IM [i, j]. the amount of current flowing between the two terminals I 1 [i, j] and the cell IM first terminal of the transistor F2 of [i + 1, j] - the amount of current I 1 flowing between the second terminal [i + 1, j], the sum of (Corresponds to equation (1.17).) Therefore, the amount of current output from the conversion circuit ITRZ [j] to the wiring WCL [j] is the first data, the weighting coefficients w [i, j] and w [i + 1, j], and the second data.
  • the semiconductor device SDV shown in FIG. 1 can perform operations from the first layer (input layer) to the second layer (intermediate layer) of a hierarchical neural network, for example. That is, the information (value) obtained by sensing by the sensor SNC [1] to the sensor SNC [m] corresponds to a signal transmitted from the neuron in the first layer to the neuron in the second layer. Further, by holding the weighting coefficient between the neuron of the first layer and the neuron of the second layer in the cell IM [1, j] to the cell IM [m, j], the arithmetic circuit MAC1 can perform the information. The sum of products of (value) and the weighting coefficient can be calculated.
  • the hierarchical neural network will be described in detail in the fourth embodiment.
  • the operation example of the semiconductor device SDV described above is suitable for calculating the sum of products of positive first data and positive second data.
  • An operation example for calculating will be described in the second embodiment.
  • the transistor included in the semiconductor device SDV includes, for example, a transistor in which Ge and the like are included in the channel forming region, and a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, and SiGe in the channel forming region.
  • Transistors, transistors in which carbon nanotubes are contained in the channel forming region, transistors in which organic semiconductors are contained in the channel forming region, and the like can be used.
  • FIG. 14 shows a configuration example of an arithmetic circuit that performs the sum of products of the first data of positive, negative, or “0” and the second data of positive, or “0”.
  • the arithmetic circuit MAC2 shown in FIG. 14 has a configuration in which the arithmetic circuit MAC1 of FIG. 7 is modified. Therefore, in the arithmetic circuit MAC2, the description of the part that overlaps with the explanation of the arithmetic circuit MAC1 will be omitted.
  • the cell array CA shown in FIG. 14 has a circuit CES [1, j] to a circuit CES [m, j], and the circuit CES [1, j] has a cell IM [1, j] and a cell IMr [1, j], and the circuit CES [m, j] has cells IM [m, j] and cells IMr [m, j].
  • the circuit CES [1, j] and the circuit CES [m, j] are shown, and the other circuit CES will be omitted.
  • [m, n] and the like attached to each reference numeral may be omitted.
  • the cell IM can have the same configuration as the cell IM [1,1] to the cell IM [m, n] included in the cell array CA of the arithmetic circuit MAC1 shown in FIG.
  • the cell IMr can have the same configuration as the cell IM.
  • the cell IMr of FIG. 14 is illustrated as an example having the same configuration as the cell IM.
  • "r" is added to the reference numerals indicating the transistors and capacitances contained in the cell IMr so that the transistors and capacitances contained in the cell IM and the cell IMr can be distinguished from each other.
  • the cell IMr has a transistor F1r, a transistor F2r, and a capacitance C5r.
  • the transistor F1r corresponds to the transistor F1 of the cell IM
  • the transistor F2r corresponds to the transistor F2 of the cell IM
  • the capacitance C5r corresponds to the capacitance C5 of the cell IM. Therefore, for the electrical connection configurations of the transistor F1r, the transistor F2r, and the capacitance C5r, the description of the IM [1,1] to the cell IM [m, n] of the first embodiment will be taken into consideration.
  • connection point between the first terminal of the transistor F1r, the gate of the transistor F2r, and the first terminal of the capacitance C5r is a node NNr.
  • the second terminal of the capacitance C5 is electrically connected to the wiring XCL [1]
  • the gate of the transistor F1 is electrically connected to the wiring WSL [1]
  • the transistor F1 The second terminal and the second terminal of the transistor F2 are electrically connected to the wiring WCL [j].
  • the second terminal of the capacitance C5r is electrically connected to the wiring XCL [1]
  • the gate of the transistor F1r is electrically connected to the wiring WSL [1]
  • the second terminal of the transistor F1r and the transistor F2r are connected.
  • the second terminal is electrically connected to the wiring WCLr [j].
  • the second terminal of the capacitance C5 is electrically connected to the wiring XCL [m]
  • the gate of the transistor F1 is electrically connected to the wiring WSL [m].
  • the second terminal of the transistor F1 and the second terminal of the transistor F2 are electrically connected to the wiring WCL [j].
  • the second terminal of the capacitance C5r is electrically connected to the wiring XCL [m]
  • the gate of the transistor F1r is electrically connected to the wiring WSL [m]
  • the second terminal of the transistor F1r and the transistor F2r are connected.
  • the second terminal is electrically connected to the wiring WCLr [j].
  • Each of the wiring WCL [j] and the wiring WCLr [j] is included in the circuit CES from the circuit WCS as an example, similarly to the wiring WCL [1] to the wiring WCL [n] described in the first embodiment. It functions as a wiring for passing a current through the cell IM and the cell IMr. Further, as an example, it functions as a wiring for passing a current from the conversion circuit ITRZD [j] to the cell IM and the cell IMr included in the circuit CES.
  • the circuit SWS1 has a transistor F3 [j] and a transistor F3r [j].
  • the first terminal of the transistor F3 [j] is electrically connected to the wiring WCL [j]
  • the second terminal of the transistor F3 [j] is electrically connected to the circuit WCS
  • the gate of the transistor F3 [j]. Is electrically connected to the wiring SWL1.
  • the first terminal of the transistor F3r [j] is electrically connected to the wiring WCLr [j]
  • the second terminal of the transistor F3r [j] is electrically connected to the circuit WCS, and the transistor F3r [j] is connected.
  • the gate of is electrically connected to the wiring SWL1.
  • the circuit SWS2 has a transistor F4 [j] and a transistor F4r [j].
  • the first terminal of the transistor F4 [j] is electrically connected to the wiring WCL [j]
  • the second terminal of the transistor F4 [j] is electrically connected to the conversion circuit ITRZD [j]
  • the transistor F4 [j] is connected.
  • the gate of [j] is electrically connected to the wiring SWL2.
  • the first terminal of the transistor F4r [j] is electrically connected to the wiring WCLr [j]
  • the second terminal of the transistor F4r [j] is electrically connected to the conversion circuit ITRZD [j].
  • the gate of F4r [j] is electrically connected to the wiring SWL2.
  • the circuit ITS has a conversion circuit ITRZD [j].
  • the conversion circuit ITRZD [j] is a circuit corresponding to the conversion circuit ITRZ [j] in the arithmetic circuit MAC1.
  • the amount of current flowing from the conversion circuit ITRZD [j] to the wiring WCL [j] and the conversion circuit ITRZD It has a function of generating a voltage corresponding to the difference between the amount of current flowing from [j] to the wiring WCLr [j] and outputting it to the wiring OL [j].
  • FIG. 15A A specific configuration example of the conversion circuit ITRZD [j] is shown in FIG. 15A.
  • the conversion circuit ITRZD1 shown in FIG. 15A is an example of a circuit applicable to the conversion circuit ITRZD [j] of FIG.
  • FIG. 15A also shows the circuit SWS2, the wiring WCL, the wiring WCLr, the wiring SWL2, the transistor F4, and the transistor F4r in order to show the electrical connection with the circuits around the conversion circuit ITRZD1.
  • each of the wiring WCL and the wiring WCLr is, as an example, the wiring WCL [j] and the wiring WCLr [j] included in the arithmetic circuit MAC2 of FIG. 14, and the transistor F4 and the transistor F4r are, as an example, FIG.
  • the transistor F4 [j] and the transistor F4r [j] included in the arithmetic circuit MAC2 of the above can be used.
  • the conversion circuit ITRZD1 of FIG. 15A is electrically connected to the wiring WCL via the transistor F4. Further, the conversion circuit ITRZD1 is electrically connected to the wiring WCLr via the transistor F4r. Further, the conversion circuit ITRZD1 is electrically connected to the wiring OL.
  • the conversion circuit ITRZD1 has a function of converting the amount of current flowing from the conversion circuit ITRZD1 to the wiring WCL or the amount of current flowing from the wiring WCL to the conversion circuit ITRZD1 to the first voltage, and the amount of current flowing from the conversion circuit ITRZD1 to the wiring WCLr, or It has a function of converting the amount of current flowing from the wiring WCLr to the conversion circuit ITRZD1 into a second voltage, and a function of outputting an analog voltage corresponding to the difference between the first voltage and the second voltage to the wiring OL.
  • the conversion circuit ITRZD1 of FIG. 15A has, for example, a resistor RP, a resistor RM, an operational amplifier OPP, an operational amplifier OPM, and an operational amplifier OP2.
  • the inverting input terminal of the operational amplifier OPP is electrically connected to the first terminal of the resistor RP and the second terminal of the transistor F4.
  • the non-inverting input terminal of the operational amplifier OPP is electrically connected to the wiring VRPL.
  • the output terminal of the operational amplifier OPP is electrically connected to the second terminal of the resistor RP and the non-inverting input terminal of the operational amplifier OP2.
  • the inverting input terminal of the operational amplifier OPM is electrically connected to the first terminal of the resistor RM and the second terminal of the transistor F4r.
  • the non-inverting input terminal of the operational amplifier OPM is electrically connected to the wiring VRML.
  • the output terminal of the operational amplifier OPM is electrically connected to the second terminal of the resistor RM and the inverting input terminal of the operational amplifier OP2.
  • the output terminal of the operational amplifier OP2 is electrically connected to the wiring OL.
  • Wiring VRPL functions as wiring that gives a constant voltage.
  • the constant voltage can be, for example, a ground potential (GND), a low level potential, or the like.
  • the wiring VRML functions as a wiring that applies a constant voltage.
  • the constant voltage can be, for example, a ground potential (GND), a low level potential, or the like.
  • the constant voltages given by the wiring VRPL and the wiring VRML may be equal to each other or different from each other. In particular, by setting the constant voltage given by each of the wiring VRPL and the wiring VRML to the ground potential (GND), each of the inverting input terminal of the operational amplifier OPP and the inverting input terminal of the operational amplifier OPM can be virtually grounded.
  • the conversion circuit ITRZD1 has the configuration shown in FIG. 15A, so that the amount of current flowing from the wiring WCL to the conversion circuit ITRZD1 via the transistor F4, or the current flowing from the conversion circuit ITRZD1 to the wiring WCL via the transistor F4.
  • the quantity can be converted to a first voltage.
  • the amount of current flowing from the wiring WCLr to the conversion circuit ITRZD1 via the transistor F4r, or the amount of current flowing from the conversion circuit ITRZD1 to the wiring WCLr via the transistor F4r can be converted into a second voltage. can.
  • an analog voltage corresponding to the difference between the first voltage and the second voltage can be output to the wiring OL.
  • the conversion circuit ITRZD1 of FIG. 15A has a configuration of outputting an analog voltage, but the circuit configuration applicable to the conversion circuit ITRZD [j] of FIG. 14 is not limited to this.
  • the conversion circuit ITRZD1 may have an analog-digital conversion circuit ADC as shown in FIG. 15B, as in FIG. 10B.
  • the input terminal of the analog-digital conversion circuit ADC is electrically connected to the output terminal of the operational amplifier OP2, and the output terminal of the analog-digital conversion circuit ADC is electrically connected to the wiring OL. It has a structure that is. With such a configuration, the conversion circuit ITRZD2 of FIG. 15B can output a digital signal to the wiring OL.
  • the conversion circuit ITRZ2 when the digital signal output to the wiring OL is 1 bit (binary value), the conversion circuit ITRZ2 may be replaced with the conversion circuit ITRZD3 shown in FIG. 15C. Similar to FIG. 10C, the conversion circuit ITRZ3 of FIG. 15C has a configuration in which the comparator CMP2 is provided in the conversion circuit ITRZD1 of FIG. 15A. Specifically, in the conversion circuit ITRZD3, the first input terminal of the comparator CMP2 is electrically connected to the output terminal of the operational amplifier OP2, the second input terminal of the comparator CMP2 is electrically connected to the wiring VRL3, and the comparator CMP2 The output terminal is electrically connected to the wiring OL.
  • the wiring VRL3 functions as a wiring that gives a potential for comparison with the potential of the first terminal of the comparator CMP2.
  • the conversion circuit ITRZD3 of FIG. 15C converts the first voltage converted from the amount of current flowing between the source and drain of the transistor F4 and the amount of current flowing between the source and drain of the transistor F4r.
  • a low level potential or a high level potential can be output to the wiring OL depending on the magnitude of the difference between the second voltage and the voltage given by the wiring VRL3.
  • the circuit CES can use two circuits, the cell IM and the cell IMr, for holding the first data. That is, the circuit CES can set two current amounts and hold the potentials corresponding to the respective current amounts in the cell IM and the cell IMr. Therefore, the first data can be represented by the amount of current set in the cell IM and the amount of current set in the cell IMr.
  • the positive first data, the negative first data, or the first data of "0" held in the circuit CES is defined as follows.
  • the cell IM [1, j] When positive first data is held in the circuit CES [1, j], the cell IM [1, j] has, for example, between the first terminal and the second terminal of the transistor F2 of the cell IM [1, j].
  • the amount of current corresponding to the absolute value of the positive first data value is set to flow.
  • the gate of the transistor F2 (node NN [1, j]) holds a potential corresponding to the amount of current.
  • the cell IMr [1, j] is set so that no current flows between the first terminal and the second terminal of the transistor F2r of the cell IMr [1, j] as an example.
  • the gate of the transistor F2r (node NNr [1, j]) may hold the potential given by the wiring VE, the initial potential given by the wiring VINIL1 of the circuit WCSa of FIG. 8A, and the like.
  • the cell IMr [1, j] When the circuit CES [1, j] holds the negative first data, the cell IMr [1, j] has the negative first data as an example, and the transistor F2r of the cell IMr [1, j] has the negative first data.
  • the gate of the transistor F2r (node NNr [1, j]) holds a potential corresponding to the amount of current.
  • the cell IM [1, j] is set so that no current flows through the transistor F2 of the cell IM [1, j] as an example.
  • the gate of the transistor F2 (node NN [1, j]) may hold the potential given by the wiring VE, the potential for initialization given by the wiring VINIL1 of the circuit WCSa of FIG. 8A, and the like.
  • the transistor F2 of the cell IM [1, j] and the transistor F2r of the cell IMr [1, j] are respectively. Is set so that no current flows. Specifically, the potential given by the wiring VE and the wiring VINIL1 of the circuit WCSa of FIG. 8A are connected to the gate of the transistor F2 (node NN [1, j]) and the gate of the transistor F2r (node NNr [1, j]). It suffices if the initialization potential to be given is maintained.
  • the cell IMr is between the cell IM and the wiring WCL as in the circuit CES [1, j] described above.
  • a current amount corresponding to the first data is set to flow between the cell IM and the wiring WCLr, and a current flows between the cell IM and the wiring WCL, and between the cell IMr and the wiring WCLr, and the other. You can set it so that it does not flow.
  • the first data of "0" is held in another circuit CES, similarly to the circuit CES [1, j] described above, between the cell IM and the wiring WCL, and between the cell IMr and the wiring WCLr. It may be set so that no current flows between them.
  • the first data is circuit CES.
  • the first data "+3”, “+2”, “+1”, “0”, “-1”, “-2”, “-3” can be defined as shown in the following table, for example.
  • the first data is held in each of the circuit CES [1, j] to the circuit CES [m, j], and each of the wiring XCL [1] to the wiring XCL [m] has the first data.
  • the second data is input.
  • a low level potential is applied to the wiring SWL1 to turn off the transistor F3 [j] and the transistor F3r [j].
  • a high level potential is applied to the wiring SWL2 to turn off the transistor F3 [j] and the transistor F4r. Turn on [j].
  • the conversion circuit ITRZD [j] and the wiring WCL [j] are in a conductive state, so that a current may flow from the conversion circuit ITRZD [j] to the wiring WCL [j]. Further, since the conversion circuit ITRZD [j] and the wiring WCLr [j] are in a conductive state, a current may flow from the conversion circuit ITRZD [j] to the wiring WCLr [j].
  • Converter ITRZD the sum of the amount of current flowing from [j] to the wiring WCL [j] and I S [j]
  • converting circuit ITRZD the sum of the amount of current flowing from [j] to the wiring WCLr [j] I Sr [j as, when referred to the operation example of the arithmetic circuit MAC1 described in the first embodiment, I S [j] and I Sr [j] can be expressed by the following equation.
  • w [i, j] shown in the formula (2.1) is the value of the first data written in the cell IM [i, j], and w r [i, j] shown in the formula (2.2). ] Is the value of the first data written in the cell IMr [i, j].
  • w [i, j] or w r [i, j] is a value other than "0"
  • the other of w [i, j] or w r [i, j] is "0".
  • Converter ITRZD [j] for example, the sum I S of the amount of current flowing through the wiring WCL [j] is converted to a first voltage, the sum of the amount of current flowing through the wiring WCLr I Sr [j] a second voltage Convert to. Then, the conversion circuit ITRZD [j] can output a voltage corresponding to the difference between the first voltage and the second voltage to the wiring OL.
  • the conversion circuits ITRZD1 to ITRZD3 shown in FIGS. 15A to 15C have a circuit configuration for outputting a voltage to the wiring OL, but one aspect of the present invention is not limited to this.
  • the conversion circuit ITRZD [j] included in the arithmetic circuit MAC2 of FIG. 14 may have a circuit configuration for outputting a current.
  • the conversion circuit ITRZD4 shown in FIG. 16 is a circuit that can be applied to the conversion circuit ITRZD [j] included in the calculation circuit MAC2 of FIG. It has a circuit configuration that outputs as.
  • FIG. 16 also shows the circuit SWS2, the wiring WCL, the wiring WCLr, the wiring OL, the transistor F4, and the transistor F4r in order to show the electrical connection with the circuits around the conversion circuit ITRZD4.
  • each of the wiring WCL and the wiring WCLr is, as an example, the wiring WCL [j] and the wiring WCLr [j] included in the arithmetic circuit MAC2 of FIG. 14, and the transistor F4 and the transistor F4r are, as an example, FIG.
  • the transistor F4 [j] and the transistor F4r [j] included in the arithmetic circuit MAC2 of the above can be used.
  • the conversion circuit ITRZD4 of FIG. 16 is electrically connected to the wiring WCL via the transistor F4. Further, the conversion circuit ITRZD4 is electrically connected to the wiring WCLr via the transistor F4r. Further, the conversion circuit ITRZD4 is electrically connected to the wiring OL.
  • the conversion circuit ITRZD4 has one of the amount of current flowing from the conversion circuit ITRZD4 to the wiring WCL or the amount of current flowing from the wiring WCL to the conversion circuit ITRZD4, and the amount of current flowing from the conversion circuit ITRZD4 to the wiring WCLr, or from the wiring WCLr to the conversion circuit ITRZD4. It has a function of acquiring the difference current between one of the flowing currents and the current. Further, it has a function of passing the difference current between the conversion circuit ITRZD4 and the wiring OL.
  • the conversion circuit ITRZD4 of FIG. 16 has a transistor F5, a current source CI, a current source CIr, and a current mirror circuit CM1 as an example.
  • the second terminal of the transistor F4 is electrically connected to the first terminal of the current mirror circuit CM1 and the output terminal of the current source CI, and the second terminal of the transistor F4r is connected to the second terminal of the current mirror circuit CM1.
  • the output terminal of the current source CIr and the first terminal of the transistor F5 are electrically connected.
  • the input terminal of the current source CI is electrically connected to the wiring VHE, and the input terminal of the current source CIr is electrically connected to the wiring VHE.
  • the third terminal of the current mirror circuit CM1 is electrically connected to the wiring VSE, and the fourth terminal of the current mirror circuit CM1 is electrically connected to the wiring VSE.
  • the second terminal of the transistor F5 is electrically connected to the wiring OL, and the gate of the transistor F5 is electrically connected to the wiring OEL.
  • the current mirror circuit CM1 applies a current amount corresponding to the potential of the first terminal of the current mirror circuit CM1 between the first terminal and the third terminal of the current mirror circuit CM1 and the second terminal of the current mirror circuit CM1. It has a function of flowing between the terminal and the fourth terminal.
  • the wiring VHE functions as, for example, wiring that applies a constant voltage.
  • the constant voltage can be a high level potential or the like.
  • the wiring VSE functions as, for example, wiring that applies a constant voltage.
  • the constant voltage can be a low level potential, a ground potential, or the like.
  • the wiring OEL functions as wiring for transmitting a signal for switching the transistor F5 to the on state or the off state, for example. Specifically, for example, a high level potential or a low level potential may be input to the wiring OEL.
  • the current source CI has a function of passing a constant current between the input terminal and the output terminal of the current source CI. Further, the current source CIr has a function of passing a constant current between the input terminal and the output terminal of the current source CIr. In the conversion circuit ITRZD4 of FIG. 16, it is preferable that the magnitude of the current flowing through the current source CI and the magnitude of the current flowing through the current source CIr are equal to each other.
  • the amount of current flowing from the converter ITRZD4 wiring WCL through the transistor F4 and I S the amount of current flowing from the converter ITRZD4 wiring WCLr through the transistor F4r and I Sr. Further, the amount of current flowing through each of the current source CI and the current source CIr is defined as I 0 .
  • I S is the arithmetic circuit MAC2 of Fig. 14, for example, cell IM located j-th column [1, j] to the cell IM [m, j] is the sum of the amount of current flowing through the.
  • I Sr in the arithmetic circuit MAC2 of Fig. 14, for example, cells IMR located j-th column [1, j] to the cell IMR [m, j] is the sum of the amount of current flowing through the.
  • the transistor F4 and the transistor F4r are turned on. Therefore, the amount of current flowing from the first terminal of the current mirror circuit CM1 the third terminal becomes I 0 -I S. Also, the current mirror circuit CM1, flows the current amount of I 0 -I S to the second terminal from the second terminal of the current mirror circuit CM1.
  • the above example of retention of the first data is taken into consideration.
  • the cell IM [i, j] when positive first data is held in the circuit CES [i, j], the cell IM [i, j] is located between the first terminal and the second terminal of the transistor F2 of the cell IM [i, j].
  • the amount of current corresponding to the absolute value of the positive first data value is set to flow, and the cell IMr [i, j] is connected to the first terminal and the second terminal of the transistor F2r of the cell IMr [i, j]. Set so that no current flows between them.
  • negative first data is held in the circuit CES [i, j]
  • the cell IM [i, j] is located between the first terminal and the second terminal of the transistor F2 of the cell IM [i, j].
  • the second data is input to each of the wiring XCL [1] to the wiring XCL [m] of the arithmetic circuit MAC2 of FIG. 14, the first terminal-2nd of the transistor F2 of the cell IM [i, j].
  • the amount of current flowing between the terminals and the amount of current flowing between the first terminal and the second terminal of the transistor F2 of the cell IMr [i, j] are each proportional to the second data.
  • I S is the sum of the amount of current flowing in the cell IM [1, j] to the cell IM [m, j] which is located j-th column. Therefore, I S is the circuit CES [1, j] to the circuit CES [m, j] of the positive first data is included in the circuit CES held, equal to the total amount of current flowing through the cell IM , For example, it can be expressed in the same manner as in the equation (2.1). That, I S corresponds to the result of product-sum operation of the positive absolute value and the second data of the first data. Also, I Sr is the sum of the amount of current flowing in the cell IMR [1, j] to the cell IMR [m, j] which is located j-th column.
  • I Sr is circuit CES [1, j] to the circuit CES [m, j] of the negative first data is included in the held circuit CES, becomes the sum of the amount of current flowing through the cell IMr , For example, it can be expressed in the same manner as in the equation (2.2). That is, ISr corresponds to the result of the product-sum operation of the absolute value of the negative first data and the second data.
  • the conversion circuit ITRZD4 can be regarded as acting as, for example, a ReLU function.
  • the ReLU function can be used, for example, as an activation function of a neural network.
  • the product of the value of each signal of the neurons in the previous layer for example, it can be the second data
  • the corresponding weighting coefficient for example, it can be the first data. It is necessary to calculate the sum.
  • the hierarchical neural network will be described later in the fourth embodiment.
  • the conversion circuit ITRZD4 shown in FIG. 17A is an example of the conversion circuit ITRZD4 shown in FIG. Specifically, FIG. 17A shows an example of each configuration of the current mirror circuit CM1, the current source CI, and the current source CIr.
  • the current mirror circuit CM1 has a transistor F6 and a transistor F6r as an example
  • the current source CI has a transistor F7 as an example
  • the current source CIr is an example.
  • the transistor F6, the transistor F6r, the transistor F7, and the transistor F7r are n-channel transistors.
  • the first terminal of the current mirror circuit CM1 is electrically connected to the first terminal of the transistor F6, the gate of the transistor F6, and the gate of the transistor F6r, and the third terminal of the current mirror circuit CM1 is a transistor. It is electrically connected to the second terminal of F6. Further, the second terminal of the current mirror circuit CM1 is electrically connected to the first terminal of the transistor F6r, and the fourth terminal of the current mirror circuit CM1 is electrically connected to the second terminal of the transistor F6r.
  • the output terminal of the current source CI is electrically connected to the first terminal of the transistor F7 and the gate of the transistor F7, and the input terminal of the current source CI is electrically connected to the second terminal of the transistor F7. It is connected to the.
  • the output terminal of the current source CIr is electrically connected to the first terminal of the transistor F7r and the gate of the transistor F7r, and the input terminal of the current source CIr is electrically connected to the second terminal of the transistor F7r. It is connected to the.
  • each of the transistor F7 and the transistor F7r the gate and the first terminal are electrically connected, and the second terminal and the wiring VHE are electrically connected. Therefore, the gate-source voltage of each of the transistor F7 and the transistor F7r is 0V, and when the threshold voltage of each of the transistor F7 and the transistor F7r is within an appropriate range, the transistor F7 and the transistor F7r are respectively.
  • a constant current flows between the first terminal and the second terminal of. That is, each of the transistor F7 and the transistor F7r functions as a current source.
  • the configuration of the current source CI and the current source CIr included in the conversion circuit ITRZD4 of FIG. 16 is not limited to the current source CI and the current source CIr shown in FIG. 17A.
  • the configurations of the current source CI and the current source CIr included in the conversion circuit ITRZD4 may be changed depending on the situation.
  • each of the current source CI and the current source CIr included in the conversion circuit ITRZD4 of FIG. 16 may be the current source CI (current source CIr) shown in FIG. 17B.
  • the current source CI (current source CIr) of FIG. 17B has a plurality of current sources CSA as an example. Further, each of the plurality of current sources CSA has a transistor F7, a transistor F7s, a terminal U1, a terminal U2, and a terminal U3.
  • the current source CSA has a function of passing ICSA as an amount of current between the terminal U2 and the terminal U1. Further, when the current source CI (current source CIr) has, for example, 2 P- 1 (P is an integer of 1 or more) current source CSA, the current source CI (current source CIr) is As the amount of current, s ⁇ I CSA (s is an integer of 0 or more and 2 P -1 or less) can be passed through the output terminal.
  • the error of the constant current ICSA output from each of the terminals U1 of the plurality of current sources CSA is preferably within 10%, more preferably within 5%, and even more preferably within 1%.
  • the error of the constant current I CSA output from the terminal U1 of the plurality of current sources CSA contained in the current source CI will be described as no.
  • the first terminal of the transistor F7s is electrically connected to the terminal U1
  • the gate of the transistor F7s is electrically connected to the terminal U3.
  • the first terminal of the transistor F7 is electrically connected to the gate of the transistor F7 and the second terminal of the transistor F7s.
  • the second terminal of the transistor F7 is electrically connected to the terminal U2.
  • Each terminal U1 of the plurality of current sources CSA is electrically connected to the output terminal of the current source CI (current source CIr). Further, each terminal U2 of the plurality of current sources CSA is electrically connected to the input terminal of the current source CI (current source CIr). That is, there is continuity between each terminal U2 of the plurality of current sources CSA and the wiring VHE.
  • terminal U3 of one current source CSA is electrically connected to the wiring CL [1], and each of the terminals U3 of the two current source CSA is electrically connected to the wiring CL [2], 2P.
  • each -1 current sources CS terminal U3 are electrically connected to the wiring CL [P].
  • Wiring CL [1] to the wiring CL [P] serves as a wiring for transmitting a control signal for outputting a constant current I CSA from the current source CSA that are electrically connected.
  • the current source CSA electrically connected to the wiring CL [1] sends the ICSA to the terminal U1 as a constant current.
  • the current source CSA electrically connected to the wiring CL [1] does not output the ICSA when the low level potential is applied to the wiring CL [1].
  • the two current sources CSA electrically connected to the wiring CL [2] have a total of 2I CSA as a constant current at the terminal U1.
  • the current source CSA electrically connected to the wiring CL [2] does not output a constant current of a total of 2I CSA.
  • the wiring CL [P] electrically connected to 2 and P-1 single current source CSA the total 2 P-1 I
  • the total current source CSA electrically connected to the wiring CL [P] is 2 P-. 1 Does not output the constant current of ICSA.
  • the current source CI applies a high level potential to one or more wires selected from the wiring CL [1] to the wiring CL [P], thereby causing the current source CI (current source CIr).
  • a current can be passed through the output terminal of.
  • the amount of the current can be determined by a combination of one or more wires selected from the wiring CL [1] to the wiring CL [P] for inputting a high level potential. For example, when a high level potential is applied to the wiring CL [1] and the wiring CL [2] and a low level potential is applied to the wiring CL [3] to the wiring CL [P], the current source CI (current source CIr) is applied. ) Can pass a total current of 3I CSA to the output terminal of the current source CI (current source CIr).
  • the amount of current flowing through the output terminal by the current source CI can be changed depending on the situation.
  • the conversion circuit ITRZD4 of FIG. 17A As the conversion circuit ITRZD4 of FIG. 16, all the transistors included in the conversion circuit ITRZD4 can be used as OS transistors. Further, since the cell array CA, the circuit WCS, the circuit XCS, etc. of the arithmetic circuit MAC2 can be configured only by the OS transistor, the conversion circuit ITRZD4 can be manufactured at the same time as the cell array CA, the circuit WCS, the circuit XCS, and the like. Therefore, it may be possible to shorten the manufacturing process of the arithmetic circuit MAC2. This also applies to the case where the current source CI (current source CIr) of FIG. 17B is applied to the current source CI and the current source CIr of the conversion circuit ITRZD4 of FIG. 17A.
  • the current source CI current source CI
  • each of the current source CI and the current source CIr included in the conversion circuit ITRZD4 of FIG. 16 needs to pass the same current to each other, each of the current source CI and the current source CIr is replaced with a current mirror circuit. May be good.
  • the conversion circuit ITRZD4 shown in FIG. 18A has a configuration in which each of the current source CI and the current source CIr included in the conversion circuit ITRZD4 of FIG. 16 is replaced with the current mirror circuit CM2.
  • the current mirror circuit CM2 has a transistor F8 and a transistor F8r as an example.
  • the transistor F8 and the transistor F8r are p-channel transistors.
  • the first terminal of the transistor F8 is electrically connected to the gate of the transistor F8, the gate of the transistor F8r, the second terminal of the transistor F4, and the first terminal of the current mirror circuit CM1.
  • the second terminal of the transistor F8 is electrically connected to the wiring VHE.
  • the first terminal of the transistor F8r is electrically connected to the second terminal of the transistor F4r and the second terminal of the current mirror circuit CM1.
  • the second terminal of the transistor F8r is electrically connected to the wiring VHE.
  • the conversion circuit ITRZD4 of FIG. 18A by replacing each of the current source CI and the current source CIr included in the conversion circuit ITRZD4 of FIG. 16 with the current mirror circuit CM2, the second terminal of the transistor F4 and the current mirror circuit CM1 A current amount substantially equal to each other can be passed through the connection point with the first terminal and the connection point between the second terminal of the transistor F4r, the second terminal of the current mirror circuit CM1, and the first terminal of the transistor F5.
  • the current mirror circuit CM2 is shown in FIG. 18A as a configuration including a transistor F8 and a transistor F8r, the circuit configuration of the current mirror circuit CM2 is not limited to this.
  • the current mirror circuit CM2 may have a configuration in which the transistors included in the current mirror circuit CM2 are cascode-connected, as in FIG. 18C described later.
  • the circuit configuration of the current mirror circuit CM2 of FIG. 18A may be changed depending on the situation.
  • the conversion circuit ITRZD4 shown in FIG. 18A may not be provided with the current mirror circuit CM1 as shown in the conversion circuit ITRZD4 shown in FIG. 18B.
  • the conversion circuit ITRZD4 shown in FIG. 18B includes the amount of current flowing from the first terminal of the current mirror circuit CM2 to the second terminal of the transistor F4, the second terminal of the current mirror circuit CM2 to the second terminal of the transistor F4r, the wiring VSE, and the transistor.
  • the amount of current flowing through the connection point with the first terminal of F5 can be made substantially equal to each other. Therefore, when I S is greater than I Sr, the amount of current I out flowing through the wire OL in FIG. 18B may be similar to I S -I Sr conversion circuit ITRZD4 in FIG.
  • the conversion circuit ITRZD4 of FIG. 18B is configured not to provide the current mirror circuit CM1, the circuit area can be reduced as compared with the conversion circuit ITRZD4 of FIG. 18A. Further, since the steady current flowing from the current mirror circuit CM2 to the current mirror circuit CM1 is eliminated, the conversion circuit ITRZD4 of FIG. 18B can reduce the power consumption as compared with the conversion circuit ITRZD4 of FIG. 18A.
  • the transistor F8 and the transistor F8r are not shown, and the current mirror circuit CM2 is shown as a block diagram. Therefore, the configuration of the current mirror circuit CM2 of FIG. 18B can be determined according to the situation, similarly to the current mirror circuit CM2 of FIG. 18A.
  • the current mirror circuit CM2 included in the conversion circuit ITRZD4 of FIG. 18B may be the current mirror circuit CM2 shown in FIG. 18C.
  • a transistor F8s and a transistor F8sr which are p-channel transistors, are further provided in the current mirror circuit CM2 shown in FIG. It has a configuration in which it is cascode-connected with F8sr.
  • the operation of the current mirror circuit can be made more stable by cascode-connecting the transistors included in the current mirror circuit.
  • the current mirror circuit CM1 included in the conversion circuit ITRZD4 of FIG. 16 is not limited to the current mirror circuit CM1 shown in FIG. 17A.
  • the configuration of the current mirror circuit CM1 included in the conversion circuit ITRZD4 of FIG. 17A may be changed depending on the situation.
  • the current mirror circuit CM1 included in the conversion circuit ITRZD4 of FIG. 16 may be the current mirror circuit CM1 shown in FIG. 18D.
  • an n-channel transistor F6s and a transistor F6sr are further provided in the current mirror circuit CM1 shown in FIG. 17A, and the transistor F6 and the transistor F6s are cascode-connected, and the transistor F6r and the transistor are connected. It has a configuration in which it is cascode-connected with F6sr.
  • the operation of the current mirror circuit can be made more stable by cascode-connecting the transistors included in the current mirror circuit.
  • one aspect of the present invention is not limited to the circuit configuration of the arithmetic circuit MAC2 described in the present embodiment.
  • the operation circuit MAC2 can change the circuit configuration depending on the situation.
  • the capacitance C5 and the capacitance C5r included in the arithmetic circuit MAC2 can be the gate capacitance of the transistor (not shown).
  • the arithmetic circuit MAC2 when the parasitic capacitances of the node NN, the node NNr, and the node NNref and the peripheral wiring are large, each of the capacitance C5, the capacitance C5r, and the capacitance C5m does not necessarily have to be provided.
  • FIG. 19 shows a configuration example of the arithmetic circuit MAC3A that performs the sum of products of the first data of positive or “0” and the second data of “1” or “0” (two values, one bit digital value). Is shown.
  • the cell IM has the transistor F1, the transistor F2, the transistor F9, and the capacitance C5, and the second terminal of the capacitance C5 is electrically connected to the wiring VE2. It differs from the arithmetic circuit MAC1 in FIG. 7 in that it is different from the arithmetic circuit MAC1 in FIG. Further, the cell array CA shown in FIG. 19 may not be provided with the cell IMref included in the cell array CA shown in FIG. 7.
  • transistor F9 for example, a transistor applicable to the transistor F1 can be used.
  • the cell array CA in FIG. 19 has m ⁇ n cell IMs, and the cell IMs are arranged in an m ⁇ n matrix.
  • the cell IM in row i and column j is referred to as cell IM [i, j].
  • the gate of the transistor F2 is electrically connected to the first terminal of the capacitance C5 and the first terminal of the transistor F1.
  • the second terminal of the transistor F1 is electrically connected to the wiring WCL, and the gate of the transistor F1 is electrically connected to the wiring WSL.
  • the second terminal of the capacitance C5 is electrically connected to the wiring VE2.
  • the first terminal of the transistor F2 is electrically connected to the wiring VE1, and the second terminal of the transistor F2 is electrically connected to the first terminal of the transistor F9.
  • the second terminal of the transistor F9 is electrically connected to the wiring WCL, and the gate of the transistor F9 is electrically connected to the wiring XCL.
  • the wiring VE1 is a wiring for passing a current between the first terminal and the second terminal of the transistor F2, and functions as a wiring for supplying a constant voltage.
  • the constant voltage can be, for example, a low level potential, a ground potential, or the like.
  • the wiring VE2 functions as a wiring for supplying a constant voltage.
  • the constant voltage can be, for example, a high level potential, a low level potential, a ground potential, or the like.
  • the transistor F1 and the transistor F9 are turned on, the potential corresponding to the current amount is written to the gate of the transistor F2, and then the transistor F1 is turned off.
  • the potential of the gate of the transistor F2 is held at the first terminal of the capacitance C5.
  • the cell IM can hold the first data sent from the wiring WCL.
  • the second data is input to the cell IM.
  • a high level potential is given to the wiring XCL
  • a low level potential is given to the wiring XCL.
  • the transistor F9 is turned on, so that the drain current of the transistor F2 can flow from the second terminal of the transistor F2 to the wiring WCL.
  • the transistor F9 is turned off, so that the drain current of the transistor F2 does not flow from the second terminal of the transistor F2 to the wiring WCL.
  • a current with a current amount of zero flows from the second terminal of the transistor F2 to the wiring WCL.
  • an amount (including zero) of current corresponding to the product of the first data and the second data can be passed from the second terminal of the transistor F2 to the wiring WCL.
  • Switching between the ON state and the OFF state of the transistor F1 can be performed by the same operation as the circuit WSD shown in FIG. Therefore, it is preferable to use the same circuit WSD shown in FIG. 19 as the circuit WSD shown in FIG. 7.
  • the wiring WSL [1] to the wiring WSL [m] of FIG. 19 are electrically connected to the circuit WSD shown in FIG.
  • the wiring XCL [1] to the wiring XCL [m] has a function not only as a wiring for inputting the second data but also as a wiring for selecting the cell IM. Therefore, the circuit electrically connected to the wiring XCL [1] to the wiring XCL [m] has the function of inputting the second data to each of the wiring XCL [1] to the wiring XCL [m], and the first data. It has a function of inputting a selection signal for selecting a cell IM to write.
  • the current output by the sensor SNC is converted into a voltage by a current-voltage conversion circuit or the like, and further converted into a voltage by an analog-digital conversion circuit, a comparator circuit or the like. It is preferable that the voltage is binarized and input to the wiring XCL [1] to the wiring XCL [m]. Further, the current-voltage conversion circuit, the analog-digital conversion circuit, and the like for that purpose may be included in the layer CCL. Specifically, for example, the circuit AC [1] to the circuit AC [m] shown in FIG. 19 includes the circuit PTR shown in FIG.
  • the first terminal of the circuit AC [1] is electrically connected to the wiring XCL [1]
  • the second terminal of the circuit AC [1] is electrically connected to the wiring EIL [1].
  • the first terminal of the circuit AC [m] is electrically connected to the wiring XCL [m]
  • the second terminal of the circuit AC [m] is electrically connected to the wiring EIL [m].
  • one aspect of the present invention is not limited to the circuit configuration of the arithmetic circuit MAC3A shown in FIG. 19 described in the present embodiment.
  • the operation circuit MAC3A of FIG. 19 can change the circuit configuration depending on the situation.
  • one aspect of the present invention may be the circuit configuration of the arithmetic circuit MAC3B shown in FIG.
  • the arithmetic circuit MAC3B shown in FIG. 20 is provided with a point in which the second terminal of the transistor F9 included in each of the cell IMs is electrically connected to the wiring RCL instead of the wiring WCL, and the circuit SWS1 and the circuit SWS2 are provided. It differs from the arithmetic circuit MAC3A of FIG. 19 in that the circuit SWS3 is provided.
  • the circuit SWS3 has a switch SB [1] to a switch SB [n].
  • a switch SB [1] to the switch SB [n] for example, a switch applicable to the switch SA [1] to the switch SA [m] can be used.
  • the first terminal of the switch SB is electrically connected to the wiring WCL [1], and the second terminal of the switch SB is electrically connected to the wiring RCL [1]. Further, the control terminal of the switch SB is electrically connected to the wiring SWLB.
  • the wiring SWLB functions as wiring for switching between the on state and the off state of each of the switch SB [1] to the switch SB [n]. Therefore, a high level potential or a low level potential is supplied to the wiring SWLB.
  • the wiring RCL [1] to the wiring RCL [n] are electrically connected to the circuit ITS.
  • the transistor F1 and the transistor F9 are turned on, the switch SB is turned on, the potential corresponding to the current amount is written to the gate of the transistor F2, and then the transistor is used.
  • the potential of the gate of the transistor F2 is held at the first terminal of the capacitance C5.
  • the cell IM can hold the first data sent from the wiring WCL.
  • the switch SB When inputting the second data to the cell IM, the switch SB is turned off in advance. After that, by inputting "1" (high level potential) or "0" (low level potential) as the second data in the wiring XCL, an amount (including zero) corresponding to the product of the first data and the second data is included. ) Can be passed from the second terminal of the transistor F2 to the wiring RCL.
  • the voltage in the range in which the transistor F2 operates in the subthreshold region is input to the wiring RCL.
  • the voltage is not input to the second terminal of the transistor F1. Therefore, when a current is passed from the cell IM to the circuit ITS via the wiring RCL, the electrical load applied between the source and drain of the transistor F1 can be reduced.
  • the transistor F9 is interposed between the second terminal of the transistor F2 and the wiring RCL, the voltage lowered by the transistor F9 is input to the second terminal of the transistor F2. That is, by providing the transistor F9, the effect of suppressing the input of an overvoltage to the second terminal of the transistor F2 can also be obtained.
  • the product of the first data of positive or “0” and the second data of “1” or “0”. can perform sum operation.
  • FIG. 21A An example of the circuit configuration shown in FIG. 21A shows a circuit LGC and a circuit LS for transmitting a signal corresponding to the second data to the circuit XCS.
  • FIG. 21A shows the circuit XCS, the circuit PTC and the cell array CA included in the layer CCL, and the sensor SNC [1] included in the layer PDL. ] To the sensor SNC [m].
  • the circuit LGC and the circuit LS are included in the layer CCL as an example.
  • the degree of freedom of the current input from the wiring XCL [1] to the wiring XCL [m] to the cell array CA can be increased.
  • the degree of freedom of the current for example, the current corresponding to the reference data or the second data described in the first embodiment can be set according to the situation.
  • the circuit LGC is electrically connected to the circuit LS by the wiring LXS [1] to the wiring LXS [m]. Further, the circuit LS is electrically connected to the circuit XCS by the wiring DXS [1] to the wiring DXS [m].
  • the circuit XCS has a function of passing a current amount according to the reference data or a current amount according to the second data to each of the wiring XCL [1] to the wiring XCL [m].
  • the configuration of the circuit XCS shown in FIG. 8C can be applied to the circuit XCS.
  • the amount of current flowing through one of the wiring XCL [1] to the wiring XCL [m] is the amount of the current flowing through the wiring XCSa of the circuit XCSa electrically connected to the wiring. It is determined according to the combination of potentials input to the wiring DX [1] to the wiring DX [L].
  • FIG. 8C the amount of current flowing through one of the wiring XCL [1] to the wiring XCL [m] is the amount of the current flowing through the wiring XCSa of the circuit XCSa electrically connected to the wiring.
  • the wiring DXS [1] is the wiring DX [1] to the wiring DX [L] of the circuit XCSa electrically connected to the wiring XCL [1]
  • the wiring DXS [m] is Let the wiring DX [1] to the wiring DX [L] of the circuit XCSa electrically connected to the wiring XCL [m]. That is, one of the wiring DXS [1] to the wiring DXS [m] can be a bus wiring for transmitting a digital signal.
  • the circuit LS has a function of level-shifting the input potential to a desired potential. Specifically, the circuit LS level-shifts the potential input from the wiring LXS [1] to a desired potential, and outputs the level-shifted potential to the wiring DXS [1]. Therefore, the number of wires of the wiring LXS [1] can be the same as that of the wiring DXS [1]. Similarly, the circuit LS level-shifts the potential input from the wiring LXS [m] to a desired potential, and outputs the level-shifted potential to the wiring DXS [m]. Therefore, the number of wirings of the wiring LXS [m] can be the same as that of the wiring DXS [m]. Further, one of the wiring LXS [1] to the wiring LXS [m] can be a bus wiring for transmitting a digital signal.
  • the circuit LGC has a function of sequentially holding data DTs input to the circuit LGC and outputting the data DTs to the wiring LXS [1] to the wiring LXS [m] at a desired timing simultaneously or sequentially in parallel.
  • the data DT here may be, for example, reference data input to the wiring XCL [1] to the wiring XCL [m], or second data. That is, the circuit LGC receives from the outside of the circuit LGC in order to allow the current amount according to the reference data or the current amount according to the second data to flow through the wiring XCL [1] to the wiring XCL [m] shown in FIG. 21A.
  • the reference data or the second data is retained, and the reference data or the second data is output to each of the wiring LXS [1] to the wiring LXS [m] at a predetermined timing.
  • a specific circuit configuration example of the circuit LGC will be described later.
  • the circuit LS is not provided in the circuit configuration shown in FIG. 21A, and the wiring LXS [1] to the wiring LXS [m] and the wiring DXS are not provided. Each of [1] to the wiring DXS [m] may be electrically connected.
  • the sensor SNC [1] to the sensor SNC [m] are configured as an optical sensor including a photodiode PD, and a method of inputting a current flowing from the wiring XCL [1] to the wiring XCL [m] to the cell array CA.
  • the configuration of the sensor SNC included in the layer PDL is such that the input terminal of the photodiode PD is electrically connected to the wiring VANL, and the output terminal of the photodiode PD is the wiring. It is assumed that it is electrically connected to the EIL.
  • the wiring VANL functions as a wiring that applies a constant voltage, and the constant voltage can be a low level potential, a ground potential, a negative potential, or the like. Therefore, when the photodiode PD is irradiated with light, a current flows from the output terminal of the photodiode PD to the wiring VANL via the input terminal.
  • the switch SA [1] ] To There is a mode in which the switch SA [m] is turned off. By turning off the switch SA [1] to the switch SA [m], the current generated by the photodiode PD does not flow to the wiring XCL [i]. Therefore, the current flowing from the wiring XCL [i] to the cell array CA can be the current corresponding to the reference data generated by the circuit XCS or the second data.
  • a switch is used as one of the modes of inputting the current from the wiring XCL [i] to the cell array CA in the circuit configuration of FIG. 21A in which the sensor SNC [1] to the sensor SNC [m] are configured in FIG. 21B.
  • a switch is used.
  • the SA [1] to the switch SA [m] are turned on.
  • the current flowing from the wiring XCL [i] to the cell array CA is the desired current generated by the circuit XCS and the current generated by the photodiode PD. And, it can be the difference current.
  • the input terminal and the output terminal of the photodiode PD of FIG. 21B may be exchanged.
  • the sensor SNC has a configuration in which the input terminal of the photodiode PD is electrically connected to the wiring EIL and the output terminal of the photodiode PD is electrically connected to the wiring VANL. It has become.
  • the constant voltage given by the wiring VANL is a high level potential or the like. Therefore, when the photodiode PD is irradiated with light, a current flows from the output terminal of the photodiode PD to the input terminal. Therefore, when the photodiode PD is irradiated with light, a current flows from the wiring VANL to the input terminal via the output terminal of the photodiode PD.
  • the switch SA [ 1] As one of the modes of inputting the current from the wiring XCL [i] to the cell array CA in the circuit configuration of FIG. 21A in which the sensor SNC [1] to the sensor SNC [m] are configured in FIG. 21C, for example, the switch SA [ 1] There is a mode in which the switch SA [m] is turned off. By operating in this mode, the switch SA [1] to the switch SA [m] can be turned off in the circuit configuration of FIG. 21A in which the sensor SNC [1] to the sensor SNC [m] are configured in FIG. 21B.
  • the current generated by the photodiode PD can be prevented from flowing to the wiring XCL [i], and the current flowing from the wiring XCL [i] to the cell array CA can be referred to as reference data or second data generated by the circuit XCS.
  • the current can be set according to.
  • the amount of current flowing from the circuit XCS to the wiring XCL [i] is set to 0, that is, the current is not supplied from the circuit XCS to the wiring SCL [i], so that the wiring XCL [i] is not supplied. ]
  • the current flowing through the cell array CA can be only the current generated by the photodiode PD.
  • the degree of freedom of the current input from the wiring XCL [1] to the wiring XCL [m] to the cell array CA can be increased. It can be increased, and the current corresponding to the reference data or the second data described in the first embodiment can be set according to the situation.
  • the switches SA [1] to SA [m] of the circuit PTC are turned off.
  • a current corresponding to the reference data or the second data may be generated by the circuit XCS, and the current may be passed through the wiring XCL [1] to the wiring XCL [m].
  • the switches SA [1] to SA [m] of the circuit PTC are turned on.
  • the current generated by the sensor SNC may be passed through the wiring XCL [1] to the wiring XCL [m].
  • the amount of current flowing from the circuit XCS to the wiring XCL [1] to the wiring XCL [m] may be a desired amount or 0.
  • the circuit is between time T13 and time T14 and between time T17 and time T19.
  • the switch SA [1] to the switch SA [m] included in the PTC may be turned off, and a current corresponding to the reference data may be passed from the circuit XCS to the wiring XCL [1] to the wiring XCL [m].
  • the amount of current flowing from the circuit XCS to the wiring XCL [1] to the wiring XCL [m] is set to 0, and the switches SA [1] to the switch included in the circuit PTC are included.
  • the SA [m] may be turned on and the current generated by the sensor SNC may be passed through the wiring XCL [1] to the wiring XCL [m].
  • the current generated by the circuit XCS and the current generated by the sensor SNC are used.
  • the total current (or differential current) of the above may be passed through the wiring XCL [1] to the wiring XCL [m] as reference data or second data.
  • the sensor SNC is configured to include the photodiode PD shown in FIG. 21B or FIG. 21C, the current flowing through the wiring XCL [1] to the wiring XCL [m] depends on the data captured by the photodiode PD. It becomes a diode.
  • the correction data for the captured data is generated as a current flowing from the circuit XCS to the wiring XCL [1] to the wiring XCL [m]
  • the wiring XCL [1] to the wiring XCL [m] is transferred to the cell array CA.
  • a current can be passed according to the corrected imaging data. Examples of the correction include color tone correction for adding strength to a specific color.
  • circuit LGC configuration example Next, a specific circuit configuration example of the circuit LGC will be described.
  • the data DT reference data and the second data
  • the circuit LGC can be configured as a logic circuit.
  • the circuit LGC can have the circuit configuration shown in FIG. 22A as an example.
  • the circuit LGC shown in FIG. 22A includes a shift register SR, a latch circuit LTA [1] to a latch circuit LTA [m], a latch circuit LTD [1] to a latch circuit LTD [m], and a switch SW [1] to a switch. It has SW [m].
  • the shift register SR is electrically connected to the wiring SPL, the wiring SCL, and the wiring SEL [1] to the wiring SEL [m].
  • Wiring SEL [1] to wiring SEL [m] are electrically connected to the respective control terminals (sometimes called clock input terminal, enable signal input terminal, etc.) of the latch circuit LTA [1] to the latch circuit LTA [m].
  • the wiring LAT is electrically connected to each control terminal of the latch circuit LTD [1] to the latch circuit LTD [m].
  • each input terminal D of the latch circuit LTA [1] to the latch circuit LTA [m] is electrically connected to the wiring DAT, and each output terminal of the latch circuit LTA [1] to the latch circuit LTA [m] is electrically connected.
  • Q is electrically connected to each of the wiring DL [1] to the wiring DL [m].
  • Each input terminal D of the latch circuit LTD [1] to the latch circuit LTD [m] is electrically connected to the wiring DL [1] to the wiring DL [m], and is electrically connected to the latch circuit LTD [1] to the latch circuit LTD [m].
  • Each output terminal Q of [m] is electrically connected to each first terminal of the switch SW [1] to the switch SW [m].
  • the second terminals of the switch SW [1] to the switch SW [m] are electrically connected to each of the wiring LXS [1] to the wiring LXS [m], and the switch SW [1] to the switch SW [m] are connected to each other.
  • Each control terminal of is electrically connected to each of the wiring SWL [1] to the wiring SWL [m].
  • the switch SW [1] to the switch SW [m] for example, an electric switch such as an analog switch or a transistor can be applied. Further, as the switch SW [1] to the switch SW [m], for example, a mechanical switch may be applied. When a transistor is applied to the switch SW [1] to the switch SW [m], the transistor can be an OS transistor or a Si transistor.
  • each of the switch SW [1] to the switch SW [m] shown in FIG. 22A is turned on when a high level potential is input to the control terminal, and is turned off when a low level potential is input to the control terminal. It becomes a state.
  • the wiring SWL [1] to the wiring SWL [m] function as wiring for switching between the conductive state and the non-conducting state of the switch SW [1] to the switch SW [m] as an example.
  • the wiring SPL functions as a wiring for transmitting a start pulse signal to the shift register SR as an example.
  • the wiring SCL functions as a wiring for transmitting a clock signal to the shift register SR as an example.
  • the wiring DAT functions as a wiring for transmitting data DT to the circuit LGC as an example.
  • Each of the wiring SEL [1] to the wiring SEL [m], the wiring DL [1] to the wiring DL [m], and the wiring DAT can be wirings for transmitting a digital signal. Therefore, each of the wiring SEL [1] to the wiring SEL [m], the wiring DL [1] to the wiring DL [m], and the wiring DAT can be bus wiring. Further, the wiring SWL can also be a bus wiring.
  • the shift register SR has a function of sequentially outputting a high level potential to the wiring SEL [1] to the wiring SEL [m] according to the change of the potential input to the wiring SPL and the wiring SCL.
  • the shift register SR cannot output a high level potential to two or more of the wiring SEL [1] to the wiring SEL [m], and any one of the wiring SEL [1] to the wiring SEL [m]. Is outputting a high level potential, the remaining wires of the wiring SEL [1] to the wiring SEL [m] are assumed to output a low level potential.
  • the wiring SEL [1] when a high level potential is input to the wiring SPL as a start pulse signal and the potential rises from a low level potential to a high level potential with a clock signal from the wiring SCL, the wiring SEL [1] has a high level. Output the potential. Subsequently, when the low level potential is input to the wiring SPL and the potential rises from the low level potential to the high level potential again by the clock signal from the wiring SCL, the wiring SEL [1] has a low level potential. Is output, and the wiring SEL [2] outputs a high level potential.
  • the wiring SEL [1] and the wiring SEL [ 2] outputs a low level potential
  • wiring SEL [3] outputs a high level potential
  • the shift register SR sequentially outputs a high-level potential to one of the wiring SEL [1] to the wiring SEL [m]. It is possible to output a low level potential to wiring other than.
  • Each of the latch circuit LTA [1] to the latch circuit LTA [m] and the latch circuit LTD [1] to the latch circuit LTD [m] is enabled when a high level potential is input to the control terminal, for example. , Has a function of holding the data input to the input terminal D and outputting the data to the output terminal Q.
  • each of the latch circuit LTA [1] to the latch circuit LTA [m] and the latch circuit LTD [1] to the latch circuit LTD [m] is selected, for example, when a low level potential is input to the control terminal. It is in the disabled state, does not hold the data input to the input terminal D, and does not output the data to the output terminal Q.
  • FIG. 23A is a timing chart showing an operation example of the circuit LGC.
  • the timing chart includes wiring SPL, wiring SCL, wiring SEL [1], wiring SEL [2], wiring SEL [m-1], wiring SEL [m], wiring SWL [1] to wiring SWL [m], and It shows the change of the potential in the wiring LAT, and is input to the wiring DAT, the wiring LXS [1], the wiring LXS [2], the wiring LXS [3], the wiring LXS [m-1], and the wiring LXS [m]. Shows the data.
  • wiring SPL wiring SCL, wiring SEL [1], wiring SEL [2], wiring SEL [m-1], wiring SEL [m] wiring SWL [1] to wiring SWL [m], and wiring LAT
  • the high level potential is described as High, and the low level potential is described as Low.
  • the timing chart of FIG. 23A shows an operation example in which the circuit LGC simultaneously outputs data DT to each of the wiring LXS [1] to the wiring LXS [m] at a time between the time T31 and the time T40 and in the vicinity thereof. Is shown. As an example of this operation, for example, it is assumed that the operation is performed between the time T21 and the time T23 in the timing chart of FIG.
  • a low level potential is input to the wiring LAT and a low level potential is input to each of the wiring SWL [1] to the wiring SWL [m] at a time before the time T31. Further, it is assumed that the shift register SR outputs a low level potential to each of the wiring SEL [1] to the wiring SEL [m].
  • a high level potential is input to the wiring SPL as a start pulse signal. Further, a pulse voltage is input to the wiring SCL as a clock signal.
  • the shift register SR acquires a high level potential which is a start pulse signal input to the wiring SPL by inputting the rising edge of the pulse voltage of the clock signal.
  • Data DT [1] is input to the wiring DAT between the time T32 and the time T33. Further, a second pulse voltage is input to the wiring SCL as a clock signal.
  • the shift register SR outputs a high level potential to the wiring SEL [1] when the rising edge of the second pulse voltage of the clock signal is input.
  • the latch circuit LTD [1] since the latch circuit LTA [1] is in the enabled state, the data DT [1] input to the input terminal D is held and the data DT [1] is output to the output terminal Q.
  • the data DT [1] is input to the input terminal D of the latch circuit LTD [1].
  • the latch circuit LTD [1] since a low level potential is input to the control terminal of the latch circuit LTD [1], the latch circuit LTD [1] is the data DT input to the input terminal D of the latch circuit LTD [1]. It does not hold [1] and does not output the data DT [1] input to the output terminal Q of the latch circuit LTD [1].
  • Data DT [2] is input to the wiring DAT between the time T33 and the time T34. Further, a third pulse voltage is input to the wiring SCL as a clock signal.
  • the shift register SR outputs a low level potential to the wiring SEL [1] and outputs a high level potential to the wiring SEL [2] when the rising edge of the pulse voltage of the clock signal is input for the third time.
  • the latch circuit LTA [1] since the latch circuit LTA [1] is disabled, the data DT [2] input to the input terminal D of the latch circuit LTA [1] is not held. Further, the latch circuit LTA [1] continues to hold the data DT [1] from before the time T33, and outputs the data DT [1] from the output terminal Q.
  • the latch circuit LTA [2] since the latch circuit LTA [2] is in the enabled state, the data DT [2] input to the input terminal D is held, and the data DT [2] is output to the output terminal Q.
  • the data DT [2] is input to the input terminal D of the latch circuit LTD [2].
  • the latch circuit LTD [2] since a low level potential is input to the control terminal of the latch circuit LTD [2], the latch circuit LTD [2] is the data DT input to the input terminal D of the latch circuit LTD [2]. [2] is not held, and the data DT [2] input to the output terminal Q of the latch circuit LTD [2] is not output.
  • the data DT [3] to DT [m-2] are sequentially input to the wiring DAT, and the wiring SEL [3] to the wiring SEL [m-2] are sequentially input by the shift register SR. High level potentials are sequentially input to.
  • the data DT [3] to the data DT [m-2] are held in the latch LTA [3] to the latch circuit LTA [m-2], respectively.
  • the data DT [3] to the data DT [m-2] are output from the respective output terminals Q of the latch LTA [3] to the latch circuit LTA [m-2].
  • Data DT [m-1] is input to the wiring DAT between the time T35 and the time T36. Further, the m-th pulse voltage is input to the wiring SCL as a clock signal.
  • the shift register SR outputs a low level potential to the wiring SEL [m-2] and outputs a high level potential to the wiring SEL [m-1] when the rising edge of the mth pulse voltage of the clock signal is input. do.
  • the latch circuit LTA [m-2] since the latch circuit LTA [m-2] is disabled, the data DT [m-1] input to the input terminal D of the latch circuit LTA [m-2] is not held. Further, the latch circuit LTA [m-2] continues to hold the data DT [m-2] from before the time T35, and outputs the data DT [m-2] from the output terminal Q.
  • the latch circuit LTA [m-1] since the latch circuit LTA [m-1] is in the enabled state, the data DT [m-1] input to the input terminal D is held and the data DT [m-1] is output to the output terminal Q. .. The data DT [m-1] is input to the input terminal D of the latch circuit LTD [m-1]. At this time, since a low level potential is input to the control terminal of the latch circuit LTD [m-1], the latch circuit LTD [m-1] is the input terminal D of the latch circuit LTD [m-1]. The data DT [m-1] input to is not retained, and the data DT [m-1] input to the output terminal Q of the latch circuit LTD [m-1] is not output.
  • Data DT [m] is input to the wiring DAT between the time T36 and the time T37. Further, the m + 1th pulse voltage is input to the wiring SCL as a clock signal.
  • the shift register SR outputs a low level potential to the wiring SEL [m-1] and outputs a high level potential to the wiring SEL [m] when the rising edge of the m + 1th pulse voltage of the clock signal is input.
  • the latch circuit LTA [m-1] since the latch circuit LTA [m-1] is disabled, the data DT [m] input to the input terminal D of the latch circuit LTA [m-1] is not held. Further, the latch circuit LTA [m-1] continues to hold the data DT [m-1] from before the time T36, and outputs the data DT [m-1] from the output terminal Q.
  • the latch circuit LTD [m] since the latch circuit LTA [m] is in the enabled state, the data DT [m] input to the input terminal D is held and the data DT [m] is output to the output terminal Q.
  • the data DT [m] is input to the input terminal D of the latch circuit LTD [m].
  • the latch circuit LTD [m] since a low level potential is input to the control terminal of the latch circuit LTD [m], the latch circuit LTD [m] is the data DT input to the input terminal D of the latch circuit LTD [m]. It does not hold [m] and does not output the data DT [m] input to the output terminal Q of the latch circuit LTD [m].
  • a high level potential is input to the wiring LAT between the time T38 and the time T39.
  • a high level potential is input to the respective control terminals of the latch circuit LTD [1] to the latch circuit LTD [m], so that each of the latch circuit LTD [1] to the latch circuit LTD [m] is in the enabled state. It becomes. Therefore, the latch circuit LTD [1] to the latch circuit LTD [m] hold the data DT [1] to the data DT [m] input to the respective input terminals D, and from the respective output terminals Q.
  • the data DT [1] to the data DT [m] are output.
  • a high level potential is input to the wiring SWL [1] to the wiring SWL [m] between the time T39 and the time T40.
  • the switch SW [1] to the switch SW [m] are turned on, and the output terminals Q and the wiring LXS [1] to the wiring LXS [m] of the latch circuit LTD [1] to the latch circuit LTD [m] are turned on. It becomes a conductive state between and. Therefore, the circuit LGC can simultaneously output data DT [1] to data DT [m] from each of the wiring LXS [1] to the wiring LXS [m].
  • the circuit LGC performs the operation of the timing chart shown in FIG. 23A to simultaneously wire the data DT [1] to the data DT [m] sequentially input to the circuit LGC in parallel to the wiring LXS [1] to the wiring LXS. It can be output to [m]. Thereby, for example, a desired current can be simultaneously supplied to the wiring XCL [1] to the wiring XCL [m] of the arithmetic circuit shown in FIG. 21 between the time T21 and the time T23 in the timing chart of FIG. can.
  • the circuit LGC shows the wiring LXS [1] to the wiring.
  • Data DT may be output sequentially to each of the LXS [m].
  • the timing chart of FIG. 23B shows an operation example in which the circuit LGC sequentially outputs data DT to each of the wiring LXS [1] and the wiring LXS [m].
  • the operation before the time T39 in the timing chart of FIG. 23B it is assumed that the operation example from before the time T31 to the time T39 in the timing chart of FIG. 23A is performed.
  • the timing chart of FIG. 23B shows changes in potential in wiring SWL [1], wiring SWL [2], wiring SWL [m-1], and wiring SWL [m], and wiring LXS [1], wiring LXS [1]. 2], the wiring LXS [m-1], and the data input to the wiring LXS [m] are shown.
  • the high level potential is described as High and the low level potential is described as Low. There is.
  • a high level potential is input to the wiring SWL [1] between the time T39 and the time T40.
  • the switch SW [1] is turned on, and the output terminal Q of the latch circuit LTD [1] and the wiring LXS [1] are in a conductive state. Therefore, the output of the latch circuit LTD to the wiring LXS [1] is output.
  • the data DT [1] output from the terminal Q is transmitted.
  • the output terminal Q of the latch circuit LTD [m-1] and the wiring LXS [m-1] are in a conductive state, they are output to the wiring LXS [m-1] from the output terminal Q of the latch circuit LTD.
  • the data DT [m-1] is transmitted.
  • the circuit LGC operates until time T39 in the timing chart shown in FIG. 23A, and then performs the operation of the timing chart shown in FIG. 23B, so that the data DT [1] to sequentially input to the circuit LGC are performed.
  • the data DT [m] can be sequentially output to the wiring LXS [1] to the wiring LXS [m].
  • the switches SWL [1] to SWL [m] are sequentially turned on, and the data DT [1] to the data DT [m] are wired LXS [1]. ] To the wiring LXS [m], but the switch SWL [1] to the switch SWL [m] is selected to be turned on, and the wiring LXS [1] to the wiring LXS [m] is selected.
  • the operation may be an operation of outputting the data DT to the wiring selected from.
  • the wiring XCL [1] to the wiring XCL [1] of the arithmetic circuit MAC1 of FIG. A desired current can be supplied to any one of [m].
  • the circuit LGC of FIG. 21A provided in the semiconductor device of one aspect of the present invention is not the circuit LGC shown in FIG. 22A, but the circuit configuration of the circuit LGC of FIG. 22A may be changed depending on the situation.
  • the circuit LGC of FIG. 22A has a buffer circuit between each of the switches SW [1] to SW [m] shown in FIG. 22A and each of the wiring LXS [1] to the wiring LXS [m]. It may be provided.
  • the circuit LGC shown in FIG. 22B has a buffer circuit BF [1] to a buffer circuit BF between each of the switch SW [1] to the switch SW [m] and each of the wiring LXS [1] to the wiring LXS [m]. The configuration is provided with [m].
  • the electric signal (potential) output from the circuit LGC to the wiring LXS [1] to the wiring LXS [m]. Can be stabilized.
  • the current generated by the circuit XCS and / or the current generated by the sensor SNC can be input to the cell array CA as the reference data or the current corresponding to the second data. can.
  • a hierarchical neural network has one input layer, one or a plurality of intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers.
  • the hierarchical neural network 100 shown in FIG. 24A shows an example thereof, and the neural network 100 has a first layer to an R layer (R here can be an integer of 4 or more). ing.
  • R can be an integer of 4 or more
  • the first layer corresponds to the input layer
  • the R layer corresponds to the output layer
  • the other layers correspond to the intermediate layer.
  • FIG. 24A shows the (k-1) th layer and the kth layer (k here is an integer of 3 or more and R-1 or less) as intermediate layers, and other intermediate layers. Is not shown.
  • Each layer of the neural network 100 has one or more neurons.
  • layer 1 has neurons N 1 (1) to neuron N p (1) (where p is an integer greater than or equal to 1), and layer (k-1) is neuron N 1. (K-1) to neuron N m (k-1) (m here is an integer of 1 or more), and the k-th layer has neurons N 1 (k) to neurons N n (k) ( Here, n is an integer of 1 or more), and the R layer has neurons N 1 (R) to neurons N q (R) (q here is an integer of 1 or more). ..
  • FIG 24B a neuron N j of the k-th layer (k), shows the signal which is input to the neuron N j (k), a signal output from the neuron N j (k), the.
  • z 1 (k-1) to z m (k- ), which are output signals of neurons N 1 (k-1) to N m (k-1) in the (k-1) layer, respectively. 1) is output toward the neuron Nj (k).
  • the neuron N j (k) is, z 1 (k-1) to z m (k-1) to generate a z j (k) in response to, the z j (k) is an output signal (k + 1 ) Output to each neuron in the layer (not shown).
  • the degree of signal transmission of signals input from neurons in the previous layer to neurons in the next layer is determined by the strength of synaptic connections (hereinafter referred to as weighting factors) that connect these neurons.
  • weighting factors the strength of synaptic connections that connect these neurons.
  • the signal output from the neurons in the previous layer is multiplied by the corresponding weighting factor and input to the neurons in the next layer.
  • i an integer 1 or m
  • the signal input to the neuron N j (k) in the k-th layer can be expressed by the equation (4.1).
  • the result of the sum of products may be biased as a bias.
  • the bias is b
  • the equation (4.2) can be rewritten as the following equation.
  • the neuron N j (k) produces an output signal z j (k) in response to u j (k).
  • the output signal z j (k) from the neuron N j (k) is defined by the following equation.
  • the function f (u j (k) ) is an activation function in a hierarchical neural network, and a step function, a linear ramp function, a sigmoid function, or the like can be used.
  • the activation function may be the same or different in all neurons.
  • the activation function of neurons may be the same or different in each layer.
  • the signal output by the neurons in each layer, the weighting coefficient w, or the bias b may be an analog value or a digital value.
  • the digital value may be, for example, a binary value or a ternary value. A value with a larger number of bits may be used.
  • an analog value for example, a linear ramp function, a sigmoid function, or the like may be used as the activation function.
  • binary digital values for example, a step function with an output of -1 or 1 or 0 or 1 may be used.
  • the signal output by the neurons in each layer may have three or more values.
  • the activation function has three values, for example, a step function in which the output is -1, 0, or 1, or 0, 1, or 2.
  • a step function or the like may be used.
  • a step function of -2, -1, 0, 1, or 2 may be used.
  • the neural network 100 When the input signal is input to the first layer (input layer), the neural network 100 is sequentially input from the front layer in each layer from the first layer (input layer) to the last layer (output layer). Based on the signal, an output signal is generated using Eqs. (4.1), Eq. (4.2) (or Eq. (4.3)), and Eq. (4.4), and the output signal is used as the next layer. The operation to output to is performed. The signal output from the last layer (output layer) corresponds to the result calculated by the neural network 100.
  • the weighting coefficients w s [k-1] (k-1) s [k] (k) (s [k-1]) are An integer of 1 or more and m or less, and s [k] is an integer of 1 or more and n or less) is used as the first data, and the amount of current corresponding to the first data is sequentially stored in each cell IM in the same column.
  • the value of the activation function is used as a signal, and the output signal z s [k] of the neurons N s [k] (k) in the k-th layer is used. It can be (k).
  • the weighting coefficients w s [R-1] (R-1) s [R] (R) (s [R-1]. ] Is an integer of 1 or more, and s [R] is an integer of 1 or more and q or less) as the first data, and the amount of current corresponding to the first data is sequentially stored in each cell IM in the same column.
  • the input layer described in the present embodiment may function as a buffer circuit that outputs an input signal to the second layer.
  • the conversion circuit ITRZD4 is configured to output the amount of current corresponding to the value, for example, the neurons N s [k] of the k-th layer, which are input to a plurality of neurons of the (k + 1) layer, are input.
  • the output signal z s in (k) [k] (k ) may be a current. That is, when the arithmetic circuit MAC2 is applied as the hidden layer of the (k + 1) layer, the output signal z s [k] of the neurons N s [k] (k) of the kth layer input to the wiring XCL of the arithmetic circuit MAC2.
  • K can be the current output from the conversion circuit ITRZD4 of the arithmetic circuit MAC2 of the hidden layer of the k-th layer, which is not generated by the circuit XCS.
  • the arithmetic circuit of FIG. 25 is an arithmetic circuit MAC2-1 having the same configuration as the arithmetic circuit MAC2 of FIG. 14, and an arithmetic circuit MAC2 of FIG. It has a circuit MAC2-2 and.
  • m ⁇ n circuit CES are arranged in a matrix in the cell array CA of the arithmetic circuit MAC2-1, and n ⁇ t (t is an integer of 1 or more) in the cell array CA of the arithmetic circuit MAC2-2.
  • the circuit CES of) is arranged in a matrix.
  • each of the wiring OL [1] to the wiring OL [n] of the arithmetic circuit MAC2-1 is electrically connected to the wiring XCL [1] to the wiring XCL [n] of the arithmetic circuit MAC2-2.
  • the weighting coefficient between the neurons of the (k-1) layer and the neurons of the kth layer is used as the first data, and the circuits CES [1,1] to the cell array CA are used as the first data.
  • the output signals z s [k-1] (k-1) from the neurons N s [k-1] (k-1) in the layer (k-1) are held in the circuit CES [m, n].
  • As 2 data by passing a current amount corresponding to the second data from the circuit XCS to the wiring XCL of each line, the neurons N 1 (k) of the kth layer from each of the wiring OL [1] to the wiring OL [n].
  • the weight coefficient between the neurons of the k-th layer and the neurons of the (k + 1) layer is used as the first data
  • the circuit CES [1,1] to the circuit of the cell array CA is used as the first data.
  • any one of FIGS. 16, 17A, 18A to 18C is attached to the conversion circuit ITRZD4 [1] to the conversion circuit ITRZD4 [n] of the arithmetic circuit MAC2-1 of FIG.
  • the conversion circuit ITRZD4 of the above act as a ReLU function. Therefore, for example, when the result of the product-sum operation in the circuit CES [1, j] to the circuit CES [m, j] is "negative", the amount of current flowing from the conversion circuit ITRZD4 to the wiring OL [j] is ideal. Is preferably 0. However, in reality, a minute amount of current may flow from the conversion circuit ITRZD4 to the wiring OL [j], or a minute amount of current may flow from the wiring OL [j] to the conversion circuit ITRZD4.
  • FIG. 26 shows a configuration example of the arithmetic circuit MAC2-2 for appropriately performing the operations after the next layer of the hierarchical neural network.
  • the arithmetic circuit MAC2-2 shown in FIG. 26 changes the circuit CES arranged in the cell array CA in the arithmetic circuit MAC2 of FIG. 14 from an m ⁇ n matrix shape to an n ⁇ t matrix shape, and changes the circuit XCS. It is not provided. Further, since the circuit CES of the cell array CA of the arithmetic circuit MAC2-2 is arranged in an n ⁇ t matrix, it is added to the reference numerals of the wiring, the circuit, etc. shown in FIG. 26 in []. The values such as the coordinates described are also changed.
  • wiring TM [1], wiring TM [n], and wiring TH [1, h] (h is an integer of 1 or more and t or less) are used in the arithmetic circuit MAC2-2.
  • An example of a circuit configuration in which wiring TH [n, h], wiring THr [1, h], and wiring THr [n, h] are provided is shown.
  • the wiring TM [1] is electrically connected to the back gate of the transistor F2m of the cell IMref [1]
  • the wiring TM is connected to the back gate of the transistor F2m of the cell IMref [n].
  • wiring TH [1, h] is electrically connected to the back gate of the transistor F2 of the cell IM [1, h]
  • the transistor F2r of the cell IMr [1, h] is electrically connected.
  • the wiring TH [1, h] is electrically connected to the back gate
  • the wiring TH [n, h] is electrically connected to the back gate of the transistor F2 of the cell IM [n, h].
  • the wiring THr [n, h] is electrically connected to the back gate of the transistor F2r of n, h].
  • the configuration of the arithmetic circuit MAC2-2 of FIG. 26 may be applied to the arithmetic circuit MAC2-1 of FIG. With such a configuration, the threshold voltages of the transistor F2, the transistor F2r, and the transistor F2m included in the arithmetic circuit MAC2-1 can be changed as in the arithmetic circuit MAC2-2. ..
  • the wiring TM [1], the wiring TM [n], the wiring TH [1, h], the wiring TH [n, h], the wiring THr [1, h], and the wiring THr [n, h] are shown.
  • wiring TM [1], wiring TH [1, h], and wiring THr [1, h] are combined into one wiring and wiring.
  • the TM [n], the wiring TH [n, h], and the wiring THr [n, h] may be combined into one wiring.
  • the value (current amount) of the output signal of the neuron output by the arithmetic circuit MAC2-1 can be used as it is in the arithmetic circuit MAC2-2. Since it can be input to, the operation of the hierarchical neural network can be continuously performed from the first layer as an example. Further, since it is not necessary to temporarily store the output signal output from the wiring OL [1] to the wiring OL [n] of the arithmetic circuit MAC2-1 by an external circuit or the like, a storage device required for temporary storage is separately provided. It does not have to be provided. That is, by configuring the arithmetic circuit of FIG. 25, the circuit area can be reduced, and the power required for data transmission for temporary storage can be reduced.
  • FIG. 27 shows, as an example, the semiconductor device SDV described in the first embodiment, in which a photoelectric conversion element is applied as a photodiode to the sensor SNC.
  • the semiconductor device shown in FIG. 27 has a layer LY1, a layer LY2, and a layer LY3, and the layer LY1 includes a transistor 300, a transistor 500, and a capacitance element 600, and the layer LY3.
  • the layer LY1 includes a transistor 300, a transistor 500, and a capacitance element 600, and the layer LY3.
  • FIG. 29A shows a cross-sectional view of the transistor 500 in the channel length direction
  • FIG. 29B shows a cross-sectional view of the transistor 500 in the channel width direction
  • FIG. 29C shows a cross-sectional view of the transistor 300 in the channel width direction.
  • the transistor 500 is a transistor (OS transistor) having a metal oxide in the channel forming region.
  • the transistor 500 has a characteristic that the off-current is small and the field effect mobility does not easily change even at a high temperature.
  • a semiconductor device for example, a transistor included in the arithmetic circuit MAC1, the arithmetic circuit MAC1A, the arithmetic circuit MAC2, the arithmetic circuit MAC3A, the arithmetic circuit MAC3B, etc. described in the above embodiment, it is possible to operate even at a high temperature. It is possible to realize a semiconductor device that does not easily decrease.
  • the transistor 500 to the transistor F1 and the transistor F1m by utilizing the characteristic that the off-current is small, the potential written in the cell IM, the cell IMref, etc. can be held for a long time.
  • layer LY1 will be described. On the layer LY1, for example, a circuit included in the layer CCL in the semiconductor device SDV of FIG. 1 can be formed. Further, in the layer LY1, for example, a circuit included in the layer CCL and the layer PHL in the semiconductor device of FIG. 3 can be formed.
  • LY1 may be paraphrased as, for example, a circuit layer or a structure.
  • the transistor 500 is provided above the transistor 300, for example, and the capacitive element 600 is provided above the transistor 300 and the transistor 500, for example.
  • the photoelectric conversion element 700 is provided above the capacitive element 600, for example.
  • the capacitance element 600 can be a capacitance included in the arithmetic circuit MAC1, the arithmetic circuit MAC1A, the arithmetic circuit MAC2, the arithmetic circuit MAC3A, the arithmetic circuit MAC3B, etc. described in the above embodiment.
  • the capacitive element 600 shown in FIG. 27 may not necessarily be provided.
  • the transistor 300 is provided on the substrate 310, and has an element separation layer 312, a conductor 316, an insulator 315, a semiconductor region 313 composed of a part of the substrate 310, a low resistance region 314a that functions as a source region or a drain region, and a low resistance region 314a. It has a resistance region 314b.
  • the transistor 300 can be applied to, for example, a transistor included in the arithmetic circuit MAC1, the arithmetic circuit MAC1A, the arithmetic circuit MAC2, the arithmetic circuit MAC3A, the arithmetic circuit MAC3B, etc. described in the above embodiment.
  • FIG. 27 shows a configuration in which the gate of the transistor 300 is electrically connected to one of the source and drain of the transistor 500 via a pair of electrodes of the capacitive element 600.
  • the arithmetic circuit MAC1A, the arithmetic circuit MAC2, the arithmetic circuit MAC3A, the arithmetic circuit MAC3B, etc. one of the source or drain of the transistor 300 is one of the source or drain of the transistor 500 via the pair of electrodes of the capacitive element 600.
  • each terminal of the transistor 300 may be configured not to be electrically connected to each terminal of the transistor 500 and each terminal of the capacitive element 600.
  • the substrate 310 it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate).
  • a semiconductor substrate for example, a single crystal substrate or a silicon substrate.
  • the transistor 300 is covered with the conductor 316 on the upper surface of the semiconductor region 313 and the side surface in the channel width direction via the insulator 315.
  • the on-characteristics of the transistor 300 can be improved by increasing the effective channel width. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristic of the transistor 300 can be improved.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like.
  • It preferably contains crystalline silicon.
  • it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like.
  • a configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used.
  • the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs or the like.
  • an element that imparts n-type conductivity such as arsenic and phosphorus, or a p-type conductivity such as boron is imparted.
  • the conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy that contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.
  • a material or a conductive material such as a metal oxide material can be used.
  • the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.
  • the element separation layer 312 is provided to separate a plurality of transistors formed on the substrate 310.
  • the device separation layer can be formed by using, for example, a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a mesa separation method, or the like.
  • LOCOS Local Oxidation of Silicon
  • STI Shallow Trench Isolation
  • the transistor 300 shown in FIG. 27 is an example, and the transistor 300 is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration, driving method, and the like.
  • the transistor 300 may have a planar type structure instead of the FIN type shown in FIG. 29C.
  • the configuration of the transistor 300 may be the same as that of the transistor 500 using an oxide semiconductor, as shown in FIG. 28. The details of the transistor 500 will be described later.
  • the transistor 300 is provided on the substrate 310A.
  • a semiconductor substrate may be used in the same manner as the substrate 310 of the semiconductor device of FIG. 27.
  • the substrate 310A includes, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel still foil, a tungsten substrate, and a tungsten foil.
  • a substrate, a flexible substrate, a laminated film, a paper containing a fibrous material, a base film, or the like can be used.
  • glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass.
  • the flexible substrate, the laminated film, the base film and the like are as follows.
  • plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE).
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyether sulfone
  • PTFE polytetrafluoroethylene
  • polypropylene polyester, polyvinyl fluoride, polyvinyl chloride and the like.
  • polyamide, polyimide, aramid epoxy resin, inorganic vapor-deposited film, papers and the like.
  • the transistor 300 shown in FIG. 27 is provided with an insulator 320, an insulator 322, an insulator 324, and an insulator 326 stacked in this order from the substrate 310 side.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride, aluminum nitride and the like can be used. Just do it.
  • silicon oxide refers to a material having a higher oxygen content than nitrogen as its composition
  • silicon nitride as its composition means a material having a higher nitrogen content than oxygen as its composition. Is shown.
  • aluminum nitride refers to a material whose composition has a higher oxygen content than nitrogen
  • aluminum nitride refers to a material whose composition has a higher nitrogen content than oxygen. Is shown.
  • the insulator 322 may have a function as a flattening film for flattening a step caused by the insulator 320 and the transistor 300 covered with the insulator 322.
  • the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • the insulator 324 it is preferable to use a film having a barrier property such that hydrogen, impurities, etc. do not diffuse in the region where the transistor 500 is provided from the substrate 310, the transistor 300, or the like.
  • a film having a barrier property against hydrogen for example, silicon nitride formed by the CVD method can be used.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, so that the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300.
  • the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.
  • the amount of hydrogen desorbed can be analyzed using, for example, a heated desorption gas analysis method (TDS).
  • TDS heated desorption gas analysis method
  • the amount of hydrogen desorbed from the insulator 324 is such that the amount desorbed in terms of hydrogen atoms is converted per area of the insulator 324 when the surface temperature of the film is in the range of 50 ° C. to 500 ° C. It may be 10 ⁇ 10 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • the insulator 326 has a lower dielectric constant than the insulator 324.
  • the relative permittivity of the insulator 326 is preferably less than 4, more preferably less than 3.
  • the relative permittivity of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative permittivity of the insulator 324.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitance element 600, a conductor 328 connected to the transistor 500, a conductor 330, and the like.
  • the conductor 328 and the conductor 330 have a function as a plug or wiring.
  • a conductor having a function as a plug or wiring may collectively give a plurality of structures the same reference numerals.
  • the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • each plug and wiring As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or laminated. be able to. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are provided in this order above the insulator 326 and the conductor 330.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 has a function as a plug or wiring for connecting to the transistor 300.
  • the conductor 356 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 350 it is preferable to use an insulator having a barrier property against impurities such as hydrogen and water, similarly to the insulator 324.
  • the insulator 352 and the insulator 354 it is preferable to use an insulator having a relatively low relative permittivity in order to reduce the parasitic capacitance generated between the wirings, similarly to the insulator 326.
  • the conductor 356 preferably contains a conductor having a barrier property against impurities such as hydrogen and water.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen.
  • the conductor having a barrier property against hydrogen for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen has a structure in contact with the insulator 350 having a barrier property against hydrogen.
  • the insulator 360, the insulator 362, and the insulator 364 are laminated in this order on the insulator 354 and the conductor 356.
  • the insulator 360 it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similarly to the insulator 324 and the like. Therefore, as the insulator 360, for example, a material applicable to the insulator 324 and the like can be used.
  • the insulator 362 and the insulator 364 have a function as an interlayer insulating film and a flattening film. Further, as the insulator 362 and the insulator 364, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similarly to the insulator 324. Therefore, as the insulator 362 and / or the insulator 364, a material applicable to the insulator 324 can be used.
  • an opening is formed in a region of each of the insulator 360, the insulator 362, and the insulator 364 that overlaps with a part of the conductor 356, and the conductor 366 is provided so as to fill the opening.
  • the conductor 366 may also be formed on a part of the insulator 362.
  • the conductor 366 has a function as a plug or wiring for connecting to the transistor 300.
  • the conductor 366 can be provided by using the same material as the conductor 328 and the conductor 330.
  • Insulator 510, insulator 512, insulator 513, insulator 514, and insulator 516 are laminated in this order on the insulator 364 and the conductor 366.
  • any one of the insulator 510, the insulator 512, the insulator 513, the insulator 514, and the insulator 516 it is preferable to use a substance having a barrier property against oxygen, hydrogen and the like.
  • the insulator 510 and the insulator 514 have a barrier property such that hydrogen, impurities, etc. do not diffuse from the region where the substrate 310 or the transistor 300 is provided to the region where the transistor 500 is provided. It is preferable to use a membrane. Therefore, the same material as the insulator 324 can be used.
  • Silicon nitride formed by the CVD method can be used as an example of a film having a barrier property against hydrogen.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, so that the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300.
  • the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.
  • metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.
  • aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • the insulator 513 it is preferable to use a film having a barrier property so that impurities such as water and hydrogen do not diffuse, like the insulator 510 and the insulator 514.
  • the insulator 513 functions as a film for sealing the transistor 500 together with the insulator 576 described later. Therefore, it is preferable to use a material applicable to the insulator 576 as the insulator 513. Further, as the insulator 513, a material applicable to the insulator 510 or the insulator 514 may be used.
  • the same material as the insulator 320 can be used for the insulator 512 and the insulator 516. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 512 and the insulator 516.
  • the insulator 510, the insulator 512, the insulator 513, the insulator 514, and the insulator 516 include the conductor 518 and the conductors constituting the transistor 500 (for example, the conductors shown in FIGS. 29A and 29B). 503) etc. are embedded.
  • the conductor 518 has a function as a plug or wiring for connecting to the capacitance element 600 or the transistor 300.
  • the conductor 518 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having a barrier property against oxygen, hydrogen, and water.
  • the transistor 300 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.
  • a transistor 500 is provided above the insulator 516.
  • the transistor 500 includes a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, and an insulator arranged on the insulator 516 and the insulator 503.
  • the insulator 524 arranged on the insulator 522, the oxide 530a arranged on the insulator 524, the oxide 530b arranged on the oxide 530a, and the oxide 530b.
  • the insulator 542a and the conductor 542b arranged apart from each other, and the insulator 580 arranged on the conductor 542a and the conductor 542b and having an opening formed by overlapping between the conductor 542a and the conductor 542b.
  • the conductor 542a and the conductor 542b are collectively referred to as the conductor 542.
  • the insulator 544 is arranged between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b, and the insulator 580.
  • the conductor 560 includes a conductor 560a provided inside the insulator 550, a conductor 560b provided so as to be embedded inside the conductor 560a, and the conductor 560b. It is preferable to have.
  • the insulator 574 is arranged on the insulator 580, the conductor 560, and the insulator 550.
  • oxide 530a, oxide 530b, and oxide 530c may be collectively referred to as oxide 530.
  • the transistor 500 shows a configuration in which three layers of oxide 530a, oxide 530b, and oxide 530c are laminated in a region where a channel is formed and in the vicinity thereof.
  • One aspect of the present invention is this. It is not limited to.
  • a single layer of oxide 530b, a two-layer structure of oxide 530b and oxide 530a, a two-layer structure of oxide 530b and oxide 530c, or a laminated structure of four or more layers may be provided.
  • the conductor 560 is shown as a two-layer laminated structure, but one aspect of the present invention is not limited to this.
  • the conductor 560 may have a single-layer structure or a laminated structure of three or more layers.
  • the transistor 500 shown in FIGS. 27, 29A, and 29B is an example, and the transistor 500 is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method.
  • the conductor 560 functions as a gate electrode of the transistor, and the conductor 542a and the conductor 542b function as a source electrode or a drain electrode, respectively.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
  • the arrangement of the conductor 560, the conductor 542a and the conductor 542b is self-aligned with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing the alignment margin, the occupied area of the transistor 500 can be reduced. As a result, the semiconductor device can be miniaturized and highly integrated.
  • the conductor 560 is formed in a region between the conductor 542a and the conductor 542b in a self-aligned manner, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Therefore, the switching speed of the transistor 500 can be improved and a high frequency characteristic can be provided.
  • the conductor 560 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode.
  • the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560 without interlocking with the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be made larger than 0 V, and the off-current can be reduced. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when it is not applied.
  • the conductor 503 is arranged so as to overlap the oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected to cover the channel forming region formed in the oxide 530. Can be done.
  • the structure of the transistor that electrically surrounds the channel formation region by the electric fields of the first gate electrode and the second gate electrode is referred to as a surroundd channel (S-channel) structure.
  • the conductor 503 has the same configuration as the conductor 518, and the conductor 503a is formed in contact with the inner wall of the opening of the insulator 514 and the insulator 516, and the conductor 503b is further formed inside.
  • the transistor 500 shows a configuration in which the conductor 503a and the conductor 503b are laminated, one aspect of the present invention is not limited to this.
  • the conductor 503 may be provided as a single layer or a laminated structure having three or more layers.
  • a conductive material for the conductor 503a which has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate).
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one oxygen atom, oxygen molecule, etc.
  • the function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.
  • the conductor 503a since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 503b from being oxidized and the conductivity from being lowered.
  • the conductor 503 also functions as a wiring
  • the conductor 503a does not necessarily have to be provided.
  • the conductor 503b is shown as a single layer, it may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.
  • the insulator 522 and the insulator 524 have a function as a second gate insulating film.
  • the insulator 524 in contact with the oxide 530 it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition. That is, it is preferable that the insulator 524 is formed with an excess oxygen region.
  • oxygen deficiency in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.
  • the oxygen deficiency in the metal oxide and V O (oxygen vacancy) sometimes called the oxygen deficiency in the metal oxide and V O (oxygen vacancy).
  • Transistors using metal oxides are likely to fluctuate in electrical characteristics and may be unreliable if impurities or oxygen deficiencies (VO ) are present in the region where channels are formed in the metal oxide.
  • the oxygen-deficient (V O) in the vicinity of hydrogen, oxygen vacancy (V O) containing hydrogen defects (hereinafter sometimes referred to as V O H.) Is formed, to generate electrons serving as carriers In some cases. Therefore, if oxygen deficiency is contained in the region where the channel is formed in the oxide semiconductor, the transistor has normal-on characteristics (the channel exists even if no voltage is applied to the gate electrode, and the current is applied to the transistor. Flowing characteristics).
  • the region in which the channel is formed in the oxide semiconductor is preferably i-type (intrinsicized) or substantially i-type with a reduced carrier concentration.
  • an oxide material in which a part of oxygen is desorbed by heating is an oxide having a desorption amount of oxygen converted into oxygen atoms of 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis.
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
  • the insulator having the excess oxygen region and the oxide 530 may be brought into contact with each other to perform one or more of heat treatment, microwave treatment, or RF treatment.
  • heat treatment microwave treatment, or RF treatment.
  • water or hydrogen in the oxide 530 can be removed.
  • reactions occur which bonds VoH is disconnected, when other words happening reaction of "V O H ⁇ V O + H", can be dehydrogenated.
  • the hydrogen generated as oxygen combines with H 2 O, it may be removed from the oxide 530 or oxide 530 near the insulator.
  • a part of hydrogen may be diffused or captured (also referred to as gettering) in the conductor 542a and the conductor 542b.
  • the microwave processing for example, it is preferable to use an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side.
  • an apparatus having a power source for generating high-density plasma for example, by using a gas containing oxygen and using a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be generated.
  • the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more.
  • oxygen and argon are used as the gas to be introduced into the apparatus for performing microwave treatment, and the oxygen flow rate ratio (O 2 / (O 2 + Ar)) is 50% or less, preferably 10% or more and 30. It is better to do it at% or less.
  • the heat treatment may be performed, for example, at 100 ° C. or higher and 450 ° C. or lower, more preferably 350 ° C. or higher and 400 ° C. or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment is preferably performed in an oxygen atmosphere.
  • oxygen can be supplied to the oxide 530 to reduce oxygen deficiency (VO ).
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas. good.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of the oxidizing gas, and then the heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.
  • the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate).
  • oxygen for example, oxygen atom, oxygen molecule, etc.
  • the insulator 522 has a function of suppressing the diffusion of oxygen, impurities, etc., the oxygen contained in the oxide 530 does not diffuse to the conductor 503 and the insulator 516, which is preferable. Further, it is possible to suppress the conductor 503 from reacting with the oxygen contained in the insulator 524 and / or the oxide 530.
  • the insulator 522 may be, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconate oxide, lead zirconate titanate (PZT), strontium titanate (SrTIO 3 ), or It is preferable to use an insulator containing a so-called high-k material such as (Ba, Sr) TiO 3 (BST) in a single layer or in a laminated state. As transistors become finer and more integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as a gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • a so-called high-k material such as (Ba, Sr) TiO 3 (BST)
  • an insulator containing oxides of one or both of aluminum and hafnium which are insulating materials having a function of suppressing diffusion of impurities and oxygen (the above oxygen is difficult to permeate).
  • the insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.
  • the insulator 522 is formed by using such a material, the insulator 522 suppresses the release of oxygen from the oxide 530 and the mixing of impurities such as hydrogen into the oxide 530 from the peripheral portion of the transistor 500. Functions as a layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated on the above insulator.
  • an insulator 522 and an insulator 524 are shown as a second gate insulating film having a two-layer laminated structure, but the second gate insulating film is , It may have a single layer, or a laminated structure of three or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • oxide 530 a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel forming region.
  • oxide 530 In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium). , Hafnium, tantalum, tungsten, magnesium, etc. (one or more) and the like may be used.
  • the In-M-Zn oxide that can be applied as the oxide 530 is preferably CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) and CAC-OS (Cloud-Aligned Compound Semiconductor).
  • CAAC-OS C-Axis Aligned Crystalline Oxide Semiconductor
  • CAC-OS Cloud-Aligned Compound Semiconductor
  • In—Ga oxide, In—Zn oxide, In oxide and the like may be used as the oxide 530.
  • a metal oxide having a low carrier concentration for the transistor 500 it is preferable to use a metal oxide having a low carrier concentration for the transistor 500.
  • the impurity concentration in the metal oxide may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • impurities in the metal oxide include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon and the like.
  • hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency in the metal oxide.
  • oxygen vacancies and hydrogen combine to form a V O H.
  • V O H acts as a donor, sometimes electrons serving as carriers are generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using a metal oxide containing a large amount of hydrogen tends to have a normally-on characteristic.
  • the metal oxide since hydrogen in the metal oxide is easily moved by stress such as heat and electric field, if the metal oxide contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.
  • the highly purified intrinsic or substantially highly purified intrinsic it is preferable that the highly purified intrinsic or substantially highly purified intrinsic.
  • the impurities such as hydrogen (dehydration, may be described as dehydrogenation.) It is important to supply oxygen to the metal oxide to compensate for the oxygen deficiency (sometimes referred to as dehydrogenation treatment).
  • the metal oxide impurities is sufficiently reduced such V O H By using the channel formation region of the transistor, it is possible to have stable electrical characteristics.
  • a defect containing hydrogen in an oxygen deficiency can function as a donor of a metal oxide.
  • the carrier concentration may be evaluated instead of the donor concentration. Therefore, in the present specification and the like, as a parameter of the metal oxide, a carrier concentration assuming a state in which an electric field is not applied may be used instead of the donor concentration. That is, the "carrier concentration" described in the present specification and the like may be paraphrased as the "donor concentration".
  • the hydrogen concentration obtained by secondary ion mass spectrometry is less than 1 ⁇ 10 20 atoms / cm 3 , preferably 1 ⁇ 10 19 atoms / cm. It is less than 3, more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the metal oxide is a semiconductor having a high band gap and is intrinsic (also referred to as type I) or substantially intrinsic, and has a channel forming region.
  • the carrier concentration of the metal oxide is preferably less than 1 ⁇ 10 18 cm -3 , more preferably less than 1 ⁇ 10 17 cm -3 , and further preferably less than 1 ⁇ 10 16 cm -3. It is preferably less than 1 ⁇ 10 13 cm -3 , even more preferably less than 1 ⁇ 10 12 cm -3.
  • the lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but may be, for example, 1 ⁇ 10 -9 cm -3 .
  • the oxygen in the oxide 530 diffuses to the conductor 542a and the conductor 542b due to the contact between the conductor 542a and the conductor 542b and the oxide 530, and the conductor The 542a and the conductor 542b may be oxidized. It is highly probable that the conductivity of the conductor 542a and the conductor 542b will decrease due to the oxidation of the conductor 542a and the conductor 542b.
  • the diffusion of oxygen in the oxide 530 to the conductor 542a and the conductor 542b can be rephrased as the conductor 542a and the conductor 542b absorbing the oxygen in the oxide 530.
  • the three-layer structure of the conductor 542a or the conductor 542b, the different layer, and the oxide 530b can be regarded as a three-layer structure composed of a metal-insulator-semiconductor, and MIS (Metal-Insulator-). It may be referred to as a Semiconductor) structure, or it may be referred to as a diode junction structure mainly composed of a MIS structure.
  • the different layer is not limited to being formed between the conductor 542a and the conductor 542b and the oxide 530b.
  • the different layer is formed between the conductor 542a and the conductor 542b and the oxide 530c. May be formed in.
  • the oxide 530 can suppress the diffusion of impurities into the oxide 530b from the structure formed below the oxide 530a. Further, by having the oxide 530c on the oxide 530b, it is possible to suppress the diffusion of impurities into the oxide 530b from the structure formed above the oxide 530c.
  • the oxide 530 preferably has a laminated structure due to a plurality of oxide layers having different atomic number ratios of each metal atom.
  • the atomic number ratio of the element M in the constituent elements is larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used in the oxide 530b. Is preferable.
  • the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 530b.
  • the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a.
  • the oxide 530c a metal oxide that can be used for the oxide 530a or the oxide 530b can be used.
  • the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a is smaller than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530b
  • In-Ga-Zn oxide having a composition of 3 or its vicinity can be used.
  • a metal oxide having a composition in the vicinity of any one can be used.
  • oxides 530a, oxides 530b, and oxides 530c so as to satisfy the above-mentioned atomic number ratio relationship.
  • the above composition indicates the atomic number ratio in the oxide formed on the substrate or the atomic number ratio in the sputter target.
  • the composition of the oxide 530b by increasing the ratio of In, the on-current of the transistor, the mobility of the field effect, and the like can be increased, which is preferable.
  • the energy at the lower end of the conduction band of the oxide 530a and the oxide 530c is higher than the energy at the lower end of the conduction band of the oxide 530b.
  • the electron affinity of the oxide 530a and the oxide 530c is smaller than the electron affinity of the oxide 530b.
  • the energy level at the lower end of the conduction band changes gently.
  • the energy level at the lower end of the conduction band at the junction of the oxide 530a, the oxide 530b, and the oxide 530c is continuously changed or continuously bonded.
  • the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) other than oxygen, so that a mixed layer having a low defect level density is formed.
  • a common element (main component) other than oxygen so that a mixed layer having a low defect level density is formed.
  • the oxide 530b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide or the like may be used as the oxide 530a and the oxide 530c.
  • the main path of the carrier is oxide 530b.
  • the defect level density at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.
  • a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided on the oxide 530b.
  • the conductors 542a and 542b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium.
  • Iridium, strontium, lanthanum, or an alloy containing the above-mentioned metal element as a component, or an alloy in which the above-mentioned metal element is combined is preferably used.
  • tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are used. Is preferable.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.
  • the conductor 542a and the conductor 542b are shown as a single-layer structure, but a laminated structure of two or more layers may be used.
  • a tantalum nitride film and a tungsten film may be laminated.
  • the titanium film and the aluminum film may be laminated.
  • a two-layer structure in which an aluminum film is laminated on a tungsten film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a tungsten film. It may have a two-layer structure in which copper films are laminated.
  • a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed on the aluminum film or the copper film.
  • a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.
  • a region 543a and a region 543b may be formed as a low resistance region at the interface of the oxide 530 with the conductor 542a (conductor 542b) and its vicinity.
  • the region 543a functions as one of the source region or the drain region
  • the region 543b functions as the other of the source region or the drain region.
  • a channel forming region is formed in a region sandwiched between the region 543a and the region 543b.
  • the oxygen concentration in the region 543a (region 543b) may be reduced. Further, in the region 543a (region 543b), a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the component of the oxide 530 may be formed. In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.
  • the insulator 544 is provided so as to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided so as to cover each side surface of the oxide 530 and the insulator 524 so as to be in contact with the insulator 522.
  • insulator 544 a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium and the like. Can be used. Further, as the insulator 544, silicon nitride oxide, silicon nitride or the like can also be used.
  • the insulator 544 it is preferable to use aluminum or an oxide containing one or both oxides of hafnium, such as aluminum oxide, hafnium oxide, aluminum, and an oxide containing hafnium (hafnium aluminate). ..
  • hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in the subsequent step.
  • the conductors 542a and 542b are made of a material having oxidation resistance, or if the conductivity does not significantly decrease even if oxygen is absorbed, the insulator 544 is not an indispensable configuration. It may be appropriately designed according to the desired transistor characteristics.
  • the insulator 544 By having the insulator 544, it is possible to prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b via the oxide 530c and the insulator 550. Further, it is possible to suppress the oxidation of the conductor 560 due to the excess oxygen contained in the insulator 580.
  • the insulator 550 functions as a first gate insulating film.
  • the insulator 550 is preferably arranged in contact with the inside (upper surface and side surface) of the oxide 530c.
  • the insulator 550 is preferably formed by using an insulator that contains excess oxygen and releases oxygen by heating.
  • silicon oxide having excess oxygen silicon oxide, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, carbon, silicon oxide to which nitrogen is added, and vacancies are used.
  • Silicon oxide having can be used.
  • silicon oxide and silicon nitride nitride are preferable because they are stable against heat.
  • oxygen is effectively applied from the insulator 550 through the oxide 530c to the channel forming region of the oxide 530b. Can be supplied. Further, similarly to the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced.
  • the film thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.
  • a metal oxide may be provided between the insulator 550 and the conductor 560.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560.
  • the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to the oxide 530.
  • oxidation of the conductor 560 due to excess oxygen can be suppressed.
  • a material that can be used for the insulator 544 may be used.
  • the insulator 550 may have a laminated structure as in the case of the second gate insulating film.
  • an insulator that functions as a gate insulating film is made of a high-k material and heat.
  • the conductor 560 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 29A and 29B, but may have a single-layer structure or a laminated structure of three or more layers.
  • Conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), conductive having a function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 560b from being oxidized by the oxygen contained in the insulator 550 and the conductivity from being lowered.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b into a film by a sputtering method, the electric resistance value of the conductor 560a can be lowered to form a conductor. This can be referred to as an OC (Oxide Conductor) electrode.
  • the conductor 560b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductor 560b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 560b may have a laminated structure, for example, titanium or a laminated structure of titanium nitride and the conductive material.
  • the insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544.
  • the insulator 580 preferably has an excess oxygen region.
  • silicon, resin, or the like silicon oxide and silicon oxide nitride are preferable because they are thermally stable.
  • silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later step.
  • the insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating in contact with the oxide 530c, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. It is preferable that the concentration of impurities such as water and hydrogen in the insulator 580 is reduced.
  • the opening of the insulator 580 is formed so as to overlap the region between the conductor 542a and the conductor 542b.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
  • the conductor 560 When miniaturizing a semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. Therefore, if the film thickness of the conductor 560 is increased, the conductor 560 may have a shape having a high aspect ratio. In the present embodiment, since the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a shape having a high aspect ratio, the conductor 560 is formed without collapsing during the process. Can be done.
  • the insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550.
  • an excess oxygen region can be provided in the insulator 550 and the insulator 580. Thereby, oxygen can be supplied into the oxide 530 from the excess oxygen region.
  • the insulator 574 use one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like. Can be done.
  • aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, the aluminum oxide formed by the sputtering method can have a function as a barrier film for impurities such as hydrogen as well as an oxygen supply source.
  • An opening is formed by removing a part of the insulator 574, the insulator 580, the insulator 544, the insulator 522, the insulator 516, and the insulator 514 so as to surround the transistor 500 and expose the insulator 513. Then, an insulator 576 having a high barrier property against hydrogen or water is formed. Therefore, each side surface of the insulator 574, the insulator 580, the insulator 544, the insulator 522, the insulator 516, and the insulator 514 is in contact with the insulator 576. As a result, it is possible to prevent moisture and hydrogen from entering the transistor 500 from the outside.
  • the insulator 513 and the insulator 576 preferably have a high function of suppressing the diffusion of hydrogen (for example, at least one hydrogen atom, hydrogen molecule, etc.) or water molecule.
  • hydrogen for example, at least one hydrogen atom, hydrogen molecule, etc.
  • the insulator 513 and the insulator 576 it is preferable to use silicon nitride or silicon nitride oxide, which is a material having a high hydrogen barrier property.
  • silicon nitride or silicon nitride oxide which is a material having a high hydrogen barrier property.
  • the insulator 581 that functions as an interlayer film and a flattening film on the insulator 576.
  • the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.
  • An insulator 582 is provided on the insulator 581.
  • the insulator 582 it is preferable to use a substance having a barrier property against oxygen, hydrogen and the like. Therefore, the same material as the insulator 514 can be used for the insulator 582.
  • a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.
  • aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • an insulator 586 is provided on the insulator 582.
  • the same material as the insulator 320 can be used. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 586.
  • an insulator 552 is provided on the side surface of the insulator 586, the insulator 582, the insulator 581, the insulator 576, the insulator 574, the insulator 580, and the opening formed in the insulator 544. Then, the conductor 540a and the conductor 540b are provided so as to be in contact with the side surface of the insulator 552 and the bottom surface of the opening. In FIG. 29A, the conductor 540a and the conductor 540b are provided so as to face each other with the conductor 560 interposed therebetween. The conductor 540a and the conductor 540b have the same configuration as the conductor 546 described later.
  • the insulator 552 is provided in contact with, for example, the insulator 581, the insulator 576, the insulator 574, the insulator 580, and the insulator 544.
  • the insulator 552 preferably has a function of suppressing the diffusion of hydrogen or water molecules.
  • an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide, which is a material having a high hydrogen barrier property.
  • silicon nitride is a material having a high hydrogen barrier property, it is suitable to be used as an insulator 552.
  • the insulator 552 By using a material having a high hydrogen barrier property as the insulator 552, it is possible to suppress the diffusion of impurities such as water or hydrogen from the insulator 580 or the like to the oxide 530 through the conductor 540a and the conductor 540b. Further, it is possible to prevent the oxygen contained in the insulator 580 from being absorbed by the conductor 540a and the conductor 540b. As described above, the reliability of the semiconductor device according to one aspect of the present invention can be enhanced.
  • each of the conductor 540a and the conductor 540b has a laminated structure of two or more layers, and impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms are diffused in the first layer in contact with the insulator 552.
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms are diffused in the first layer in contact with the insulator 552.
  • the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586 are embedded with the insulator 552, the conductor 546, and the like. ..
  • the conductor 546 has a function as a plug or wiring for connecting to the capacitance element 600, the transistor 500, or the transistor 300.
  • the conductor 546 can be provided by using the same material as the conductor 540a and the conductor 540b.
  • the transistor 500 shown in FIGS. 30A and 30B may have its transistor configuration changed depending on the situation.
  • the transistor 500 of FIGS. 30A and 30B can be changed to the transistor shown in FIGS. 30A and 30B as a modification.
  • FIG. 30A is a cross-sectional view of the transistor in the channel length direction
  • FIG. 30B is a cross-sectional view of the transistor in the channel width direction.
  • the transistors shown in FIGS. 30A and 30B differ from the transistors shown in FIGS. 30A and 30B in that the oxide 530c has a two-layer structure of an oxide 530c1 and an oxide 530c2.
  • the oxide 530c1 is in contact with the side surface of the insulator 524, the side surface of the oxide 530a, the upper surface and the side surface of the oxide 530b, the side surface of the conductor 542a and the conductor 542b, the side surface of the insulator 544, and the side surface of the insulator 580.
  • the oxide 530c2 is in contact with the insulator 550.
  • In-Zn oxide can be used as the oxide 530c1.
  • the same material as the material that can be used for the oxide 530c when the oxide 530c has a one-layer structure can be used.
  • Metal oxides can be used.
  • the oxide 530c By having the oxide 530c have a two-layer structure of the oxide 530c1 and the oxide 530c2, the on-current of the transistor can be increased as compared with the case where the oxide 530c has a one-layer structure. Therefore, the transistor can be applied as, for example, a power MOS transistor.
  • the oxide 530c contained in the transistors having the configurations shown in FIGS. 29A and 29B can also have a two-layer structure of oxide 530c1 and oxide 530c2.
  • the transistors having the configurations shown in FIGS. 30A and 30B can be applied to, for example, the transistors 300 shown in FIGS. 27 and 28.
  • the transistor 300 is a semiconductor device described in the above embodiment, for example, the arithmetic circuit MAC1, the arithmetic circuit MAC1A, the arithmetic circuit MAC2, the arithmetic circuit MAC3A, and the arithmetic circuit MAC3B described in the above embodiment. It can be applied to the transistors included in the above.
  • the transistors shown in FIGS. 30A and 30B can also be applied to transistors other than the transistors 300 and 500 included in the semiconductor device of one aspect of the present invention.
  • a capacitance element 600 and wiring or a plug are provided above the transistor 500.
  • the capacitive element 600 has, for example, a conductor 610, a conductor 620, and an insulator 630.
  • a conductor 610 is provided on the conductor 546 and the insulator 586, while the conductor 540a or the conductor 540b is provided.
  • the conductor 610 has a function as one of a pair of electrodes of the capacitive element 600.
  • the conductor 612 is provided on the insulator 586 and the conductor 546 on the other side of the conductor 540a or the conductor 540b.
  • the conductor 612 has a function as a plug, a wiring, a terminal, or the like for electrically connecting the transistor 500 and the photoelectric conversion element 700 above.
  • the conductor 612 can be the wiring WCL in the arithmetic circuit MAC1 described in the first embodiment.
  • the conductor 612 and the conductor 610 may be formed at the same time.
  • the conductor 612 and the conductor 610 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned elements as components.
  • a metal nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film and the like can be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply a conductive material such as indium tin oxide.
  • the conductor 612 and the conductor 610 have a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used.
  • a conductor having a barrier property and a conductor having a high adhesion to a conductor having a high conductivity may be formed between a conductor having a barrier property and a conductor having a high conductivity.
  • An insulator 630 is provided on the insulator 586 and the conductor 610.
  • the insulator 630 functions as a dielectric sandwiched between a pair of electrodes of the capacitive element 600.
  • Examples of the insulator 630 include silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium nitride, and hafnium nitride. Zirconium oxide or the like may be used, and it can be provided in a laminated or single layer.
  • the capacitive element 600A can secure a sufficient capacitance by having an insulator having a high dielectric constant (high-k), and by having an insulator having a large dielectric strength, the dielectric strength is improved and the capacitance is improved. Electrostatic destruction of the element 600 can be suppressed.
  • the insulator of the high dielectric constant (high-k) material material having a high specific dielectric constant
  • the insulator 630 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba, Sr) TiO 3 (BST). Insulators containing high-k material may be used in single layers or in layers. Further, as the insulator 630, a compound containing hafnium and zirconium may be used. As semiconductor devices become finer and more integrated, problems such as leakage current of transistors or capacitive elements may occur due to the thinning of the gate insulator and the dielectric used for the capacitive element.
  • the gate insulator and the insulator that functions as a dielectric used for the capacitive element By using a high-k material for the gate insulator and the insulator that functions as a dielectric used for the capacitive element, it is possible to reduce the gate potential during transistor operation and secure the capacitance of the capacitive element while maintaining the physical film thickness. It will be possible.
  • the conductor 620 is provided so as to overlap with the conductor 610 via the insulator 630.
  • the conductor 610 has a function as one of a pair of electrodes of the capacitive element 600. Further, for example, the conductor 620 can be the wiring XCL in the arithmetic circuit MAC1 described in the first embodiment.
  • a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When it is formed at the same time as another structure such as a conductor, Cu (copper), Al (aluminum), or the like, which are low resistance metal materials, may be used. Further, for example, as the conductor 620, a material applicable to the conductor 610 can be used. Further, the conductor 620 may have a laminated structure of two or more layers instead of a single layer structure.
  • An insulator 640 is provided on the conductor 620 and the insulator 630.
  • the insulator 640 for example, it is preferable to use a film having a barrier property so that hydrogen and impurities do not diffuse in the region where the transistor 500 is provided. Therefore, the same material as the insulator 324 can be used.
  • An insulator 650 is provided on the insulator 640.
  • the insulator 650 can be provided by using the same material as the insulator 320. Further, the insulator 650 may function as a flattening film that covers the uneven shape below the insulator 650. Therefore, the insulator 650 can be, for example, a material applicable to the insulator 324.
  • the capacitive element 600 is composed of the conductor 610, the conductor 620, and the insulator 630. Further, in FIGS. 27 and 28, the capacitance element 600 is shown as a planar type.
  • the capacitance element 600A shown in FIGS. 31A to 31C is a planar type capacitance element applicable to the capacitance element of the semiconductor device shown in FIGS. 27 and 28.
  • 31A is a top view of the capacitive element 600A
  • FIG. 31B is a perspective view showing a cross section of the capacitive element 600A at the alternate long and short dash line L3-L4
  • FIG. 31C shows a cross section of the capacitive element 600A at the alternate long and short dash line W3-L4. It is a perspective view.
  • the conductor 610 functions as one of the pair of electrodes of the capacitance element 600A, and the conductor 620 functions as the other of the pair of electrodes of the capacitance element 600A. Further, the insulator 630 functions as a dielectric material sandwiched between the pair of electrodes.
  • the capacitive element 600 is electrically connected to the conductor 546 at the lower part of the conductor 610. Further, although not shown in FIG. 31, as shown in the semiconductor devices shown in FIGS. 27 and 28, the capacitive element 600 is electrically connected to either the conductor 540a or the conductor 540b.
  • the conductor 546 functions as a plug or wiring for connecting to another circuit element.
  • the insulator 586 in which the conductor 546 is embedded, the insulator 640 covering the conductor 620 and the insulator 630, and the insulator 650 are omitted. There is.
  • the capacitive element 600 shown in FIGS. 27, 28, 31A, 31B, and 31C is a planar type, but the shape of the capacitive element is not limited to this.
  • the capacitance element 600 may be the cylinder type capacitance element 600B shown in FIGS. 32A to 32C.
  • FIG. 32A is a top view of the capacitive element 600B
  • FIG. 32B is a cross-sectional view taken along the alternate long and short dash line L3-L4 of the capacitive element 600B
  • FIG. 32C is a perspective view showing a sectional view taken along the alternate long and short dash line W3-L4 of the capacitive element 600B. be.
  • the capacitive element 600B includes a pair of an insulator 631 on an insulator 586 in which a conductor 546 is embedded, an insulator 651 having an opening, and a conductor 610 that functions as one of a pair of electrodes. It has a conductor 620 that functions as the other of the electrodes of the above.
  • the insulator 586, the insulator 650, and the insulator 651 are omitted in order to clearly show the figure.
  • the same material as the insulator 586 can be used.
  • the conductor 611 is embedded so as to be electrically connected to the conductor 546.
  • the conductor 611 for example, the same material as the conductor 330 and the conductor 518 can be used.
  • the same material as the insulator 586 can be used.
  • the insulator 651 has an opening, and the opening is superimposed on the conductor 611.
  • the conductor 610 is formed on the bottom portion and the side surface of the opening. That is, the conductor 610 is superposed on the conductor 611 and is electrically connected to the conductor 611.
  • an opening is formed in the insulator 651 by an etching method or the like, and then the conductor 610 is formed by a sputtering method, an ALD method or the like. After that, the conductor 610 formed on the insulator 651 may be removed, leaving the conductor 610 formed on the opening by the CMP method or the like.
  • the insulator 630 is located on the insulator 651 and on the forming surface of the conductor 610.
  • the insulator 630 functions as a dielectric sandwiched between a pair of electrodes in the capacitive element.
  • the conductor 620 is formed on the insulator 630 so as to fill the opening of the insulator 651.
  • the insulator 650 is formed so as to cover the insulator 630 and the conductor 620.
  • the cylinder-type capacitive element 600B shown in FIG. 32 can have a higher capacitance value than the planar type capacitive element 600A.
  • the layer LY2 located above the capacitance element 600 will be described.
  • the layer LY2 can form the wiring included in the layer ERL in the semiconductor device SDV shown in FIGS. 1 and 3. That is, the layer LY2 functions as a wiring layer.
  • LY2 may be paraphrased as, for example, a wiring layer or a structure.
  • the insulator 411, the insulator 412, and the insulator 413 are laminated in this order above the insulator 650. Further, a conductor 416 is embedded in the insulator 411, the insulator 412, and the insulator 413.
  • the conductor 416 has a function as a plug or wiring for connecting to the transistor 500.
  • the conductor 416 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the conductor 416 can be the wiring EIL [1] to the wiring EIL [m] of the semiconductor device SDV described in the first embodiment.
  • the insulator 411 it is preferable to use an insulator having a barrier property against impurities such as hydrogen and water, similarly to the insulator 324.
  • the insulator 412 and the insulator 413 it is preferable to use an insulator having a relatively low relative permittivity in order to reduce the parasitic capacitance generated between the wirings, similarly to the insulator 326.
  • the conductor 416 preferably contains a conductor having a barrier property against impurities such as hydrogen and water.
  • a conductor having a barrier property against hydrogen is formed in the openings of the insulator 411, the insulator 412, and the insulator 413 having a barrier property against hydrogen.
  • An insulator 414 is provided on the insulator 413 and the conductor 416.
  • the insulator 414 for example, like the insulator 324, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen. Therefore, as the insulator 414, for example, a material applicable to the insulator 324 and the like can be used.
  • the layer LY3 provided above the capacitance element 600 in FIGS. 27 and 28, and the photoelectric conversion element 700 included in the layer LY3 will be described.
  • a sensor array SCA using the sensor SNC as an optical sensor which is included in the layer PDL in the semiconductor device SDV of FIGS. 1 and 3, can be formed.
  • LY3 may be paraphrased as, for example, a sensor layer and a structure.
  • the photoelectric conversion element 700 has, for example, a layer 767a, a layer 767b, a layer 767c, a layer 767d, and a layer 767e.
  • the photoelectric conversion element 700 shown in FIGS. 27 and 28 is an example of an organic photoconductive film, in which layer 767a is a lower electrode and layer 767e is a translucent upper electrode, and layers 767b, 767c, and 767d. Corresponds to the photoelectric conversion unit.
  • a pn junction type photodiode, an avalanche photodiode, or the like may be used.
  • the layer 767a which is the lower electrode, can be one of the anode and the cathode
  • the layer 767b which is the upper electrode, can be the other of the anode and the cathode.
  • the layer 767a is used as a cathode
  • the layer 767b is used as an anode.
  • the lower electrode of the layer 767a can be, for example, the electrode DNK in the layer PDL described in the first embodiment.
  • the layer 767a is preferably a low resistance metal layer, for example.
  • a low resistance metal layer for example.
  • the layer 767a for example, aluminum, titanium, tungsten, tantalum, silver or a laminate thereof can be used.
  • the layer 767e for example, it is preferable to use a conductive layer having high translucency with respect to visible light.
  • a conductive layer having high translucency with respect to visible light.
  • indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like is used. Can be done.
  • the layer 767e may be omitted.
  • One of the layers 767b and 767d of the photoelectric conversion unit can be a hole transport layer and the other can be an electron transport layer. Further, the layer 767c can be a photoelectric conversion layer.
  • the hole transport layer for example, molybdenum oxide or the like can be used.
  • the electron transport layer for example, fullerenes such as C 60 and C 70 , or derivatives thereof and the like can be used.
  • a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.
  • an insulator 750 is provided above the insulator 414. Further, an opening is provided in a region overlapping the insulator 414, the insulator 750, and the conductor 416 of the insulator 751, and the conductor 740 is provided so as to fill the opening.
  • An insulator 751 is provided on the insulator 650, and a layer 767a is provided on the insulator 751 and the conductor 740.
  • an insulator 752 is provided on the insulator 751 and on the layer 767a. Further, a layer 767b is provided on the insulator 752 and on the layer 767a.
  • a layer 767c, a layer 767d, a layer 767e, and an insulator 753 are laminated in this order.
  • the insulator 751 functions as an interlayer insulating film as an example.
  • the conductor 740 has a function as a plug or wiring for electrically connecting the photoelectric conversion element 700 and the conductor 416.
  • the conductor 740 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 752 functions as an element separation layer as an example. Although not shown, the insulator 752 is provided to prevent a short circuit with another photoelectric conversion element located adjacent to the insulator 752. As the insulator 752, for example, it is preferable to use an organic insulator or the like.
  • the insulator 753 functions as a translucent flattening film as an example.
  • a material such as silicon oxide, silicon oxide nitride, silicon nitride oxide, or silicon nitride can be used.
  • a light-shielding layer 771 As an example, a light-shielding layer 771, an optical conversion layer 772, and a microlens array 773 are provided.
  • the light-shielding layer 771 provided on the insulator 753 can suppress the inflow of light to adjacent pixels.
  • a metal layer such as aluminum or tungsten can be used for the light-shielding layer 771. Further, the metal layer and a dielectric film having a function as an antireflection film may be laminated.
  • a color filter can be used for the optical conversion layer 772 provided on the insulator 753 and the light shielding layer 771.
  • a color image can be obtained by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filter for each pixel.
  • a wavelength cut filter is used for the optical conversion layer 772, it can be used as an image pickup device that can obtain images in various wavelength regions.
  • the optical conversion layer 772 uses a filter that blocks light below the wavelength of visible light, it can be used as an infrared imaging device. Further, if the optical conversion layer 772 uses a filter that blocks light having a wavelength of near infrared rays or less, a far infrared ray imaging device can be obtained. Further, if the optical conversion layer 772 uses a filter that blocks light having a wavelength equal to or higher than that of visible light, it can be used as an ultraviolet imaging device.
  • a scintillator is used for the optical conversion layer 772, it can be used as an imaging device for obtaining an image that visualizes the intensity of radiation used in an X-ray imaging device or the like.
  • radiation such as X-rays transmitted through a subject
  • a scintillator When radiation such as X-rays transmitted through a subject is incident on a scintillator, it is converted into light (fluorescence) such as visible light and ultraviolet light by a photoluminescence phenomenon. Then, the image data is acquired by detecting the light with the photoelectric conversion element 700.
  • an imaging device having the above configuration may be used as a radiation detector or the like.
  • the scintillator contains a substance that absorbs the energy of radiation such as X-rays and gamma rays and emits visible light and ultraviolet light.
  • Gd 2 O 2 S Tb
  • Gd 2 O 2 S Pr
  • Gd 2 O 2 S Eu
  • BaFCl Eu
  • NaI, CsI, CaF 2 , BaF 2 , CeF 3 LiF, LiI, ZnO, etc.
  • Those dispersed in resin, ceramics, etc. can be used.
  • a microlens array 773 is provided on the light-shielding layer 771 and on the optical conversion layer 772. Light passing through the individual lenses of the microlens array 773 passes through the optical conversion layer 772 directly below and irradiates the photoelectric conversion element 700. By providing the microlens array 773, the focused light can be incident on the photoelectric conversion element 700, so that photoelectric conversion can be performed efficiently.
  • the microlens array 773 is preferably formed of a resin or glass having high translucency with respect to visible light.
  • FIGS. 27 and 28 show a configuration of a semiconductor device in which a transistor 300 and a photoelectric conversion element 700 using an organic photoconductive film are provided above the transistor 500, which is an aspect of the present invention.
  • Semiconductor devices are not limited to this.
  • the semiconductor device according to one aspect of the present invention may be configured to provide a back-illuminated pn junction type photoelectric conversion element instead of the photoelectric conversion element 700.
  • FIG. 33 shows a configuration example of a semiconductor device in which a back-illuminated pn junction type photoelectric conversion element 700A is provided above the transistor 300 and the transistor 500.
  • the semiconductor device shown in FIG. 33 has a configuration in which a layer LY4 having a photoelectric conversion element 700A is bonded above a substrate 310 provided with a transistor 300, a transistor 500, and a capacitance element 600.
  • the layer LY4 is a modification of the layer LY3 described above, and the layer LY4 uses the sensor SNC included in the layer PDL in the semiconductor device SDV of FIGS. 1 and 3 as an optical sensor.
  • a sensor array SCA can be formed.
  • LY4 may be paraphrased as, for example, a sensor layer and a structure.
  • the layer LY4 includes a light-shielding layer 771, an optical conversion layer 772, and a microlens array 773, and the above description is taken into consideration for these explanations.
  • the photoelectric conversion element 700A is a pn junction type photodiode formed on a silicon substrate, and has a layer 765b corresponding to a p-type region and a layer 765a corresponding to an n-type region.
  • the photoelectric conversion element 700A is an embedded photodiode, and a thin p-shaped region (a part of the layer 765b) provided on the surface side (current extraction side) of the layer 765a can suppress dark current and reduce noise. can.
  • the insulator 701, the conductor 741, and the conductor 742 have a function as a bonding layer.
  • the insulator 754 has a function as an interlayer insulating film and a flattening film.
  • the insulator 755 has a function as an element separation layer.
  • the insulator 756 has a function of suppressing the outflow of carriers.
  • the silicon substrate is provided with a groove for separating pixels, and the insulator 756 is provided on the upper surface of the silicon substrate and the groove.
  • the insulator 756 By providing the insulator 756, it is possible to prevent the carriers generated in the photoelectric conversion element 700A from flowing out to the adjacent pixels.
  • the insulator 756 also has a function of suppressing the intrusion of stray light. Therefore, the insulator 756 can suppress color mixing.
  • An antireflection film may be provided between the upper surface of the silicon substrate and the insulator 756.
  • the element separation layer can be formed by using the LOCOS method. Alternatively, it may be formed by using an STI (Shallow Trench Isolation) method or the like.
  • STI Shallow Trench Isolation
  • the insulator 756 may have a multi-layer structure.
  • the layer 765a (n-type region, corresponding to the cathode) of the photoelectric conversion element 700A is electrically connected to the conductor 741.
  • the layer 765b (p-type region, corresponding to the anode) is electrically connected to the conductor 742.
  • the conductor 741 and the conductor 742 have a region embedded in the insulator 701. Further, the surfaces of the insulator 701, the conductor 741, and the conductor 742 are flattened so that their heights match.
  • the layer 765b is electrically connected to the conductor 744, which will be described later, via the conductor 742. That is, the semiconductor device of FIG. 33 has a configuration in which a current or a voltage is applied to the anode of the photoelectric conversion element 700A from the layers LY2 and LY1 (not shown).
  • the semiconductor device shown in FIG. 33 is different from the semiconductor device shown in FIG. 27 in the configuration of the insulator, the conductor, etc. provided above the insulator 414.
  • the insulator 492 and the insulator 493 are laminated in this order on the insulator 414.
  • an opening is provided in a region overlapping the insulator 492 and the conductor 416 of the insulator 493, and the conductor 743 is formed so as to fill the opening.
  • an opening is also provided at a place other than the region, and the conductor 744 is formed so as to fill the opening.
  • the conductor 416 is electrically connected to the layer 765a via the conductor 743 and the conductor 741.
  • the conductor 416 corresponding to the wiring EIL is electrically connected to the layer 765b (input terminal (anode) of the photodiode) via the conductor 744 and the conductor 742. It may be configured as a diode.
  • the conductor 741 can be, for example, the electrode DNK included in the layer PDL described in the first embodiment.
  • the conductor 743 can be, for example, a plug that electrically connects the wiring EIL described in the first embodiment and the sensor SNC.
  • insulator 492 for example, a material applicable to the insulator 650 can be used.
  • the insulator 493 functions as a part of the bonding layer like the insulator 701. Further, the conductor 743 and the conductor 744 also function as a part of the bonding layer in the same manner as the conductor 741 and the conductor 742.
  • the insulator 493 and the insulator 701 for example, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, titanium nitride and the like can be used.
  • the insulator 493 and the insulator 701 are composed of the same components.
  • the conductor 741, the conductor 742, the conductor 743, and the conductor 744 for example, copper, aluminum, tin, zinc, tungsten, silver, platinum, gold, or the like can be used.
  • copper, aluminum, tungsten, or gold is preferably used in order to facilitate bonding between the conductor 741 and the conductor 743, and the conductor 742 and the conductor 744.
  • the conductor 741, the conductor 742, the conductor 743, and the conductor 744 may have a multi-layer structure including a plurality of layers.
  • the first conductor is formed on the side surface of the opening provided with the conductor 741, the conductor 742, the conductor 743, or the conductor 744, and then the second conductor is formed so as to fill the opening. You may.
  • a conductor having a barrier property against hydrogen such as tantalum nitride
  • the second conductor for example, tungsten having high conductivity can be used.
  • the surfaces of the insulator 493, the conductor 743, and the conductor 744 are high on the substrate 310 side, respectively. Flattening is performed so that the values match. Similarly, on the layer LY4 side, the surfaces of the insulator 701, the conductor 741 and the conductor 742 are flattened so that their heights match.
  • the surfaces that have been subjected to hydrophilic treatment with oxygen plasma or the like are brought into contact with each other after giving high flatness by polishing or the like. It is possible to use a hydrophilic bonding method or the like in which temporary bonding is performed and then main bonding is performed by dehydration by heat treatment. Since the hydrophilic bonding method also causes bonding at the atomic level, it is possible to obtain mechanically excellent bonding.
  • the oxide film on the surface and the adsorption layer of impurities are subjected to sputtering treatment.
  • a surface-activated bonding method can be used in which the surfaces are removed by contact with each other, cleaned and activated, and then bonded to each other.
  • a diffusion bonding method or the like in which surfaces are bonded to each other by using both temperature and pressure can be used. In both cases, bonding at the atomic level occurs, so that excellent bonding can be obtained not only electrically but also mechanically.
  • the conductor 743 and the conductor 744 on the substrate 310 side can be electrically connected to the conductor 741 and the conductor 742 on the layer LY4 side. Further, it is possible to obtain a connection having mechanical strength between the insulator 493 on the substrate 310 side and the insulator 701 on the layer LY4 side.
  • an insulating layer and a metal layer are mixed on each bonding surface, so for example, a surface activation bonding method and a hydrophilic bonding method may be combined.
  • a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an antioxidant treatment, and then a hydrophilic treatment is performed to join the metal layer.
  • the surface of the metal layer may be made of a refractory metal such as gold and subjected to hydrophilic treatment.
  • a joining method other than the above-mentioned method may be used.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium, tin and the like are contained. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like. ..
  • FIG. 34A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (metal oxides containing In, Ga, and Zn).
  • IGZO metal oxides containing In, Ga, and Zn
  • oxide semiconductors are roughly classified into “Amorphous”, “Crystalline”, and “Crystal”.
  • Amorphous includes complete amorphous.
  • “Crystalline” includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite) (exclusion single crystal and crystal).
  • CAAC c-axis-aligned crystalline
  • nc nanocrystalline
  • CAC Cloud-Aligned Composite
  • single crystal, poly crystal, and single crystal amorphous are excluded from the classification of "Crystalline”.
  • “Crystal” includes single crystal and poly crystal.
  • the structure in the thick frame shown in FIG. 34A is an intermediate state between "Amorphous” and “Crystal", and belongs to a new boundary region (New crystal phase). .. That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous” and "Crystal".
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum.
  • XRD X-ray diffraction
  • FIG. 34B the XRD spectrum obtained by GIXD (Glazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" is shown in FIG. 34B (horizontal axis is 2 ⁇ [deg.], And vertical axis is intensity. (Intensity) is expressed in an arbitrary unit (au)).
  • the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum obtained by the GIXD measurement shown in FIG. 34B will be simply referred to as an XRD spectrum.
  • a peak showing clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film.
  • the crystal structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a microelectron diffraction pattern) observed by a micro electron diffraction method (NBED: Nano Beam Electron Diffraction).
  • the diffraction pattern of the CAAC-IGZO film is shown in FIG. 34C.
  • FIG. 34C is a diffraction pattern observed by the NBED in which the electron beam is incident parallel to the substrate.
  • electron diffraction is performed with the probe diameter set to 1 nm.
  • oxide semiconductors may be classified differently from FIG. 34A.
  • oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS.
  • the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.
  • CAAC-OS CAAC-OS
  • nc-OS nc-OS
  • a-like OS the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.
  • CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions are oriented in a specific direction on the c-axis.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
  • the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region in which the lattice arrangement is aligned. Further, the CAAC-OS has a region in which a plurality of crystal regions are connected in the ab plane direction, and the region may have distortion.
  • the strain refers to a region in which a plurality of crystal regions are connected in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another grid arrangement is aligned. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and not clearly oriented in the ab plane direction.
  • Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the size of the crystal region may be about several tens of nm.
  • CAAC-OS has indium (In) and oxygen. It tends to have a layered crystal structure (also referred to as a layered structure) in which a layer (hereinafter, In layer) and a layer having elements M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are laminated. There is. Indium and element M can be replaced with each other. Therefore, the (M, Zn) layer may contain indium. In addition, the In layer may contain the element M. The In layer may contain Zn.
  • the layered structure is observed as a lattice image in, for example, a high-resolution TEM image.
  • the position of the peak indicating the c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.
  • a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film.
  • a certain spot and another spot are observed at point-symmetrical positions with the spot of the incident electron beam passing through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit lattice is not limited to a regular hexagon and may be a non-regular hexagon. Further, in the above strain, it may have a lattice arrangement such as a pentagon or a heptagon.
  • a clear grain boundary cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS allows distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction, the metal atoms are replaced, and the bond distance between the atoms changes. It is thought that it can be done.
  • CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
  • a configuration having Zn is preferable.
  • In-Zn oxide and In-Ga-Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries. Further, since the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities, the generation of defects, etc., CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures (so-called thermal budgets) in the manufacturing process. Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • nc-OS has tiny crystals. Since the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also referred to as a nanocrystal.
  • nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
  • nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductor depending on the analysis method. For example, when a structural analysis is performed on an nc-OS film using an XRD apparatus, a peak indicating crystallinity is not detected in the Out-of-plane XRD measurement using a ⁇ / 2 ⁇ scan. Further, when electron beam diffraction (also referred to as limited field electron diffraction) using an electron beam having a probe diameter larger than that of nanocrystals (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is performed. Is observed.
  • electron beam diffraction also referred to as limited field electron diffraction
  • nanocrystals for example, 50 nm or more
  • electron diffraction also referred to as nanobeam electron diffraction
  • an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
  • An electron diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be acquired.
  • the a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. In addition, a-like OS has a higher hydrogen concentration in the membrane than nc-OS and CAAC-OS.
  • CAC-OS relates to the material composition.
  • CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the mixed state is also called a mosaic shape or a patch shape.
  • CAC-OS has a structure in which the material is separated into a first region and a second region to form a mosaic shape, and the first region is distributed in the film (hereinafter, also referred to as a cloud shape). It says.). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
  • the atomic number ratios of In, Ga, and Zn with respect to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
  • the first region is a region in which [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region in which [Ga] is larger than [Ga] in the composition of the CAC-OS film.
  • the first region is a region in which [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
  • the first region is a region in which indium oxide, indium zinc oxide, or the like is the main component.
  • the second region is a region in which gallium oxide, gallium zinc oxide, or the like is the main component. That is, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
  • a region containing In as a main component (No. 1) by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region (1 region) and the region containing Ga as a main component (second region) have a structure in which they are unevenly distributed and mixed.
  • EDX Energy Dispersive X-ray spectroscopy
  • CAC-OS When CAC-OS is used for a transistor, the conductivity caused by the first region and the insulating property caused by the second region act in a complementary manner to switch the switching function (On / Off function). Can be added to CAC-OS. That is, the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS as a transistor, high on-current (I on ), high field effect mobility ( ⁇ ), and good switching operation can be realized.
  • I on on-current
  • ⁇ high field effect mobility
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one aspect of the present invention has two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. You may.
  • the oxide semiconductor as a transistor, a transistor with high field effect mobility can be realized. Moreover, a highly reliable transistor can be realized.
  • the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm -3 or less, preferably 1 ⁇ 10 15 cm -3 or less, more preferably 1 ⁇ 10 13 cm -3 or less, more preferably 1 ⁇ 10 11 cm ⁇ . It is 3 or less, more preferably less than 1 ⁇ 10 10 cm -3 , and more than 1 ⁇ 10 -9 cm -3.
  • the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon, carbon, etc. near the interface with the oxide semiconductor are determined. , 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, and more preferably 1 ⁇ 10 18 atoms / cm 3 or less. , More preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency.
  • oxygen deficiency When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , and more preferably 5 ⁇ 10 18 atoms / cm. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • This embodiment shows an example of a semiconductor wafer on which the semiconductor device and the like shown in the above embodiment are formed, and an electronic component in which the semiconductor device is incorporated.
  • the semiconductor wafer 4800 shown in FIG. 35A has a wafer 4801 and a plurality of circuit units 4802 provided on the upper surface of the wafer 4801.
  • the portion without the circuit portion 4802 is the spacing 4803, which is a dicing region.
  • the semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 by the previous process. Further, after that, the surface on the opposite side on which the plurality of circuit portions 4802 of the wafer 4801 are formed may be ground to reduce the thickness of the wafer 4801. By this step, the warp of the wafer 4801 can be reduced and the size of the wafer can be reduced.
  • a dicing process is performed. Dicing is performed along the scribing line SCL1 and the scribing line SCL2 (sometimes referred to as a dicing line or a cutting line) indicated by an alternate long and short dash line.
  • the spacing 4803 is provided so that a plurality of scribe lines SCL1 are parallel to each other and a plurality of scribe lines SCL2 are parallel to each other in order to facilitate the dicing process. It is preferable to provide them so as to be vertical.
  • the chip 4800a as shown in FIG. 35B can be cut out from the semiconductor wafer 4800.
  • the chip 4800a has a wafer 4801a, a circuit unit 4802, and a spacing 4803a.
  • the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between the adjacent circuit units 4802 may be substantially the same as the cutting margin of the scribe line SCL1 or the cutting margin of the scribe line SCL2.
  • the shape of the element substrate of one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in FIG. 35A.
  • the shape of the element substrate can be appropriately changed depending on the process of manufacturing the device and the device for manufacturing the device.
  • FIG. 35C shows a perspective view of a substrate (mounting substrate 4704) on which the electronic component 4700 and the electronic component 4700 are mounted.
  • the electronic component 4700 shown in FIG. 35C has a chip 4800a in the mold 4711. As shown in FIG. 35C, the chip 4800a may have a configuration in which circuit units 4802 are laminated. In FIG. 35C, a part is omitted in order to show the inside of the electronic component 4700.
  • the electronic component 4700 has a land 4712 on the outside of the mold 4711. The land 4712 is electrically connected to the electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a by a wire 4714.
  • the electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected to each other on the printed circuit board 4702 to complete the mounting board 4704.
  • FIG. 35D shows a perspective view of the electronic component 4730.
  • the electronic component 4730 is an example of SiP (System in package) or MCM (Multi Chip Module).
  • an interposer 4731 is provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.
  • the electronic component 4730 has a semiconductor device 4710.
  • the semiconductor device 4710 can be, for example, the semiconductor device described in the above embodiment, a wideband memory (HBM: High Bandwidth Memory), or the like.
  • HBM High Bandwidth Memory
  • an integrated circuit semiconductor device such as a CPU, GPU, FPGA, or storage device can be used.
  • the package substrate 4732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 4731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or multiple layers.
  • the interposer 4731 has a function of electrically connecting the integrated circuit provided on the interposer 4731 to the electrode provided on the package substrate 4732.
  • the interposer may be referred to as a "rewiring board” or an "intermediate board”.
  • a through electrode may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode.
  • a TSV Through Silicon Via
  • interposer 4731 It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide an active element in the silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with a resin interposer.
  • the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer on which the HBM is mounted.
  • the reliability is unlikely to decrease due to the difference in the expansion coefficient between the integrated circuit and the interposer. Further, since the surface of the silicon interposer is high, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
  • a heat sink heat dissipation plate
  • the heights of the integrated circuits provided on the interposer 4731 are the same.
  • the heights of the semiconductor device 4710 and the semiconductor device 4735 are the same.
  • an electrode 4733 may be provided on the bottom of the package substrate 4732.
  • FIG. 35D shows an example in which the electrode 4733 is formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Further, the electrode 4733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 4730 can be mounted on another substrate by using various mounting methods, not limited to BGA and PGA.
  • BGA Band-GPU
  • PGA Stimble Pin Grid Array
  • LGA Land-GPU
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN QuadFN
  • FIG. 36A is an external perspective view of the upper surface side of the package containing the image sensor chip.
  • the package has a package substrate 4510 for fixing the image sensor chip 4550 (see FIG. 36C), a cover glass 4520, an adhesive 4530 for adhering the two, and the like.
  • FIG. 36B is an external perspective view of the lower surface side of the package.
  • BGA Ball grid array
  • solder balls are bumps 4540.
  • LGA Land grid array
  • PGA Peripheral Component Interconnect
  • FIG. 36C is a perspective view of the package shown by omitting a part of the cover glass 4520 and the adhesive 4530.
  • An electrode pad 4560 is formed on the package substrate 4510, and the electrode pad 4560 and the bump 4540 are electrically connected via a through hole.
  • the electrode pad 4560 is electrically connected to the image sensor chip 4550 by a wire 4570.
  • FIG. 36D is an external perspective view of the upper surface side of the camera module in which the image sensor chip is housed in a lens-integrated package.
  • the camera module has an image sensor chip 4551 (a package substrate 4511 for fixing FIG. 36F, a lens cover 4521, a lens 4535, and the like. Further, an image pickup device drive circuit and an image sensor chip 4551 are located between the package substrate 4511 and the image sensor chip 4551.
  • An IC chip 4590 having a function such as a signal conversion circuit (FIG. 36F is also provided, and has a configuration as a SiP (Sensem in package)).
  • FIG. 36E is an external perspective view of the lower surface side of the camera module.
  • the package substrate 4511 has a QFN (Quad flat no-lead package) configuration in which a land 4541 for mounting is provided on the lower surface and the side surface thereof.
  • QFN Quad flat no-lead package
  • the configuration is an example, and QFP (Quad flat package) or the above-mentioned BGA may be provided.
  • FIG. 36F is a perspective view of the module shown by omitting a part of the lens cover 4521 and the lens 4535.
  • the land 4541 is electrically connected to the electrode pad 4651, and the electrode pad 4651 is electrically connected to the image sensor chip 4551 or the IC chip 4590 by a wire 4571.
  • the image sensor chip By housing the image sensor chip in the above-mentioned package, it becomes easy to mount it on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.
  • FIG. 37 illustrates how the electronic component 4700 having the semiconductor device is included in each electronic device.
  • the information terminal 5500 shown in FIG. 37 is a mobile phone (smartphone) which is a kind of information terminal.
  • the information terminal 5500 has a housing 5510 and a display unit 5511, and as an input interface, a touch panel is provided in the display unit 5511 and buttons are provided in the housing 5510.
  • the information terminal 5500 can execute an application using artificial intelligence by applying the semiconductor device described in the above embodiment.
  • Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5511, and recognizes characters and figures input by the user on the touch panel provided in the display unit 5511. Examples thereof include an application displayed on the display unit 5511 and an application for performing biometric authentication such as fingerprints and voice prints.
  • FIG. 37 shows a wristwatch-type information terminal 5900 as an example of a wearable terminal.
  • the information terminal 5900 includes a housing 5901, a display unit 5902, an operation button 5903, an operator 5904, a band 5905, and the like.
  • the wearable terminal can execute an application using artificial intelligence by applying the semiconductor device described in the above embodiment.
  • applications using artificial intelligence include an application that manages the health condition of a person wearing a wearable terminal, a navigation system that selects and guides the optimum route by inputting a destination, and the like.
  • FIG. 37 shows a desktop information terminal 5300.
  • the desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can execute an application using artificial intelligence by applying the semiconductor device described in the above embodiment.
  • applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. Further, by using the desktop type information terminal 5300, it is possible to develop a new artificial intelligence.
  • smartphones, desktop information terminals, and wearable terminals are taken as examples of electronic devices, respectively, as shown in FIG. 37, but information terminals other than smartphones, desktop information terminals, and wearable terminals can be applied.
  • Examples of information terminals other than smartphones, desktop information terminals, and wearable terminals include PDA (Personal Digital Assistant), notebook type information terminals, and workstations.
  • FIG. 37 shows an electric freezer / refrigerator 5800 as an example of an electric appliance.
  • the electric freezer / refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric freezer / refrigerator 5800 having artificial intelligence can be realized.
  • the electric freezer / refrigerator 5800 has a function of automatically generating a menu based on the foodstuffs stored in the electric freezer / refrigerator 5800, the expiration date of the foodstuffs, etc., and the foodstuffs stored in the electric freezer / refrigerator 5800. It can have a function of automatically adjusting the temperature according to the above.
  • an electric refrigerator / freezer has been described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH (Induction Heating) cooker, a water server, and an air conditioner.
  • air conditioners including conditioners, washing machines, dryers, and audiovisual equipment.
  • FIG. 37 shows a portable game machine 5200, which is an example of a game machine.
  • the portable game machine 5200 has a housing 5201, a display unit 5202, a button 5203, and the like.
  • FIG. 37 shows a stationary game machine 7500, which is an example of a game machine.
  • the stationary game machine 7500 has a main body 7520 and a controller 7522.
  • the controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 can be provided with a display unit for displaying a game image, a touch panel serving as an input interface other than buttons, a stick, a rotary knob, a slide type knob, and the like.
  • the controller 7522 is not limited to the shape shown in FIG. 37, and the shape of the controller 7522 may be variously changed according to the genre of the game.
  • a controller shaped like a gun can be used by using a trigger as a button.
  • a controller having a shape imitating a musical instrument, a music device, or the like can be used.
  • the stationary game machine may be in a form in which a controller is not used, and instead, a camera, a depth sensor, a microphone, and the like are provided and operated by the gesture and / or voice of the game player.
  • the video of the game machine described above can be output by a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • the semiconductor device described in the above embodiment By applying the semiconductor device described in the above embodiment to the portable game machine 5200, it is possible to realize the portable game machine 5200 with low power consumption. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • the portable game machine 5200 having artificial intelligence can be realized.
  • expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are defined by the program that the game has, but by applying artificial intelligence to the handheld game machine 5200, .
  • Expressions that are not limited to game programs are possible. For example, it is possible to express what the player asks, the progress of the game, the time, and the behavior of the characters appearing in the game.
  • the game player can be constructed anthropomorphically by artificial intelligence. Therefore, by setting the opponent as a game player by artificial intelligence, even one player can play the game. You can play games.
  • FIG. 37 illustrates a portable game machine as an example of a game machine
  • the electronic device of one aspect of the present invention is not limited to this.
  • Examples of the electronic device of one aspect of the present invention include a stationary game machine for home use, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), and a pitching machine for batting practice installed in a sports facility. Machines and the like.
  • the semiconductor device described in the above embodiment can be applied to an automobile which is a moving body and around the driver's seat of the automobile.
  • FIG. 37 shows an automobile 5700 as an example of a moving body.
  • an instrument panel that can display speedometer, tachometer, mileage, fuel gauge, gear status, air conditioner settings, etc. Further, a display device for displaying such information may be provided around the driver's seat.
  • the semiconductor device described in the above embodiment can be applied as a component of artificial intelligence, for example, the semiconductor device can be used in an automatic driving system of an automobile 5700. Further, the semiconductor device can be used in a system for performing road guidance, danger prediction, and the like.
  • the display device may be configured to display information such as road guidance and danger prediction.
  • the automobile is described as an example of the moving body, but the moving body is not limited to the automobile.
  • moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the semiconductor device of one aspect of the present invention is applied to these moving objects. Then, a system using artificial intelligence can be provided.
  • FIG. 37 shows a digital camera 6240, which is an example of an imaging device.
  • the digital camera 6240 has a housing 6241, a display unit 6242, an operation button 6243, a shutter button 6244, and the like, and a removable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 has a configuration in which the lens 6246 can be removed from the housing 6241 and replaced here, the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured so that a strobe device, a viewfinder, and the like can be separately attached.
  • a low power consumption digital camera 6240 can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • the digital camera 6240 having artificial intelligence can be realized.
  • the digital camera 6240 has a function of automatically recognizing a subject such as a face or an object, a function of focusing according to the subject, a function of automatically firing a flash according to the environment, and an captured image. It can have a function of toning.
  • Video camera The semiconductor device described in the above embodiment can be applied to a video camera.
  • FIG. 37 shows a video camera 6300, which is an example of an imaging device.
  • the video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation key 6304, a lens 6305, a connection unit 6306, and the like.
  • the operation key 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302.
  • the first housing 6301 and the second housing 6302 are connected by a connecting portion 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connecting portion 6306. be.
  • the image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 on the connecting unit 6306.
  • the video camera 6300 can perform pattern recognition by artificial intelligence at the time of encoding. By this pattern recognition, it is possible to calculate the difference data of people, animals, objects, etc. included in the continuous captured image data and compress the data.
  • the semiconductor device described in the above embodiment can be applied to a computer such as a PC (Personal Computer) and an expansion device for an information terminal.
  • a computer such as a PC (Personal Computer) and an expansion device for an information terminal.
  • FIG. 38A shows, as an example of the expansion device, an expansion device 6100 externally attached to a PC, which is equipped with a portable chip capable of arithmetic processing.
  • the expansion device 6100 can perform arithmetic processing by the chip by connecting to a PC by, for example, USB (Universal Serial Bus) or the like.
  • USB Universal Serial Bus
  • FIG. 38A illustrates a portable expansion device 6100, but the expansion device according to one aspect of the present invention is not limited to this, and is relatively equipped with, for example, a cooling fan. It may be a large form of expansion device.
  • the expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104.
  • the substrate 6104 is housed in the housing 6101.
  • the substrate 6104 is provided with a circuit for driving the semiconductor device or the like described in the above embodiment.
  • a chip 6105 for example, a semiconductor device, an electronic component 4700, a memory chip, etc. described in the above embodiment
  • a controller chip 6106 are attached to the substrate 6104.
  • the USB connector 6103 functions as an interface for connecting to an external device.
  • the expansion device 6100 such as a PC
  • the arithmetic processing capacity of the PC can be increased.
  • even a PC having insufficient processing capacity can perform calculations such as artificial intelligence and moving image processing.
  • FIG. 38B schematically shows data transmission in a broadcasting system. Specifically, FIG. 38B shows a route for a radio wave (broadcast signal) transmitted from a broadcasting station 5680 to reach a television receiving device (TV) 5600 in each home.
  • the TV 5600 includes a receiving device (not shown), and the broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the receiving device.
  • the antenna 5650 illustrates a UHF (Ultra High Frequency) antenna, but as the antenna 5650, a BS / 110 ° CS antenna, a CS antenna, or the like can also be applied.
  • UHF Ultra High Frequency
  • Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and the radio tower 5670 amplifies the received radio waves 5675A and transmits the radio waves 5675B.
  • the terrestrial broadcasting can be viewed on the TV 5600.
  • the broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 38B, and may be satellite broadcasting using artificial satellites, data broadcasting using optical lines, or the like.
  • the above-mentioned broadcasting system may be a broadcasting system using artificial intelligence by applying the semiconductor device described in the above embodiment.
  • the broadcasting data is transmitted from the broadcasting station 5680 to the TV 5600 of each household, the broadcasting data is compressed by the encoder, and when the antenna 5650 receives the broadcasting data, the decoder of the receiving device included in the TV 5600 compresses the broadcasting data. Restoration is done.
  • artificial intelligence for example, in motion compensation prediction, which is one of the compression methods of an encoder, it is possible to recognize a display pattern included in a display image. In-frame prediction using artificial intelligence can also be performed. Further, for example, when receiving broadcast data having a low resolution and displaying the broadcast data on the TV 5600 having a high resolution, image interpolation processing such as up-conversion can be performed in the restoration of the broadcast data by the decoder.
  • the above-mentioned broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcasting data increases.
  • UHDTV ultra-high definition television
  • a recording device having artificial intelligence may be provided on the TV5600.
  • the recording device can be made to learn the user's preference by artificial intelligence, so that a program suitable for the user's preference can be automatically recorded.
  • FIG. 38C shows a palm print authentication device, which has a housing 6431, a display unit 6432, a palm print reading unit 6433, and wiring 6434.
  • FIG. 38C shows how the palm print authentication device acquires the palm print of the hand 6435.
  • the acquired palm print is subjected to pattern recognition processing using artificial intelligence, and it is possible to determine whether or not the palm print belongs to the person himself / herself. This makes it possible to construct a system that performs highly secure authentication.
  • the authentication system according to one aspect of the present invention is not limited to the palm print authentication device, but is a device that acquires biometric information such as fingerprints, veins, faces, irises, voice prints, genes, and physique to perform biometric authentication. May be good.
  • FIG. 39A illustrates the alarm 6900, which has a detector 6901, a receiver 6902, and a transmitter 6903.
  • the sensor 6901 has a sensor circuit 6904, a vent 6905, an operation key 6906, and the like.
  • the detection object that has passed through the vent 6905 is sensed by the sensor circuit 6904.
  • the sensor circuit 6904 can be, for example, a detector whose detection target is water leakage, electric leakage, gas leakage, fire, water level of a river that may be flooded, seismic intensity of an earthquake, radiation, or the like.
  • the sensor circuit 6904 detects an object to be detected that exceeds a specified value
  • the sensor 6901 sends the information to the receiver 6902.
  • the receiver 6902 has a display unit 6907, an operation key 6908, an operation key 6909, a wiring 6910, and the like.
  • the receiver 6902 controls the operation of the transmitter 6903 according to the information from the sensor 6901.
  • the transmitter 6903 includes a speaker 6911, a lighting device 6912, and the like.
  • the transmitter 6903 has a function of transmitting an alarm in accordance with a command from the transmitter 6903.
  • 39A shows an example in which the transmitter 6903 performs both a voice alarm using the speaker 6911 and a light alarm using a lighting device 6912 such as a red light, but only one of them is alarmed or The transmitter 6903 may issue other alarms.
  • the receiver 6902 may send a command to the fire prevention equipment such as a shutter to perform a predetermined operation in accordance with the transmission of the alarm.
  • the fire prevention equipment such as a shutter to perform a predetermined operation in accordance with the transmission of the alarm.
  • FIG. 39A the case where the signal is transmitted / received wirelessly between the receiver 6902 and the sensor 6901 is illustrated, but the signal may be transmitted / received via wiring or the like.
  • the case where the signal is transmitted from the receiver 6902 to the transmitter 6903 via the wiring 6910 is illustrated, but the signal may be transmitted wirelessly.
  • FIG. 39B shows an example of a robot.
  • the robot 6140 has tactile sensors 6141a to tactile sensors 6141e, respectively.
  • the robot 6140 can grab an object by using the tactile sensor 6141a to the tactile sensor 6141e.
  • the tactile sensor 6141a to the tactile sensor 6141e have, for example, a function of flowing a current through the object according to the ground contact area when the object is touched, and the robot 6140 grabs the object from the amount of the flowing current. You can recognize that you are out.
  • FIG. 39C shows an example of an industrial robot.
  • the industrial robot preferably has a plurality of drive shafts in order to finely control the drive range.
  • the industrial robot 6150 shows an example including a functional unit 6151, a control unit 6152, a drive shaft 6153, a drive shaft 6154, and a drive shaft 6155. It is preferable that the functional unit 6151 has a sensor such as an image detection module.
  • the functional unit 6151 has one or a plurality of functions such as grasping, cutting, welding, applying, and pasting an object. As the responsiveness of the industrial robot 6150 improves, the productivity increases proportionally. Further, in order for the industrial robot 6150 to perform a precise operation, it is preferable to provide a sensor or the like for detecting a minute current.

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