WO2021208364A1 - 一种高纯半导体单晶的热等静压连接方法 - Google Patents

一种高纯半导体单晶的热等静压连接方法 Download PDF

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WO2021208364A1
WO2021208364A1 PCT/CN2020/117591 CN2020117591W WO2021208364A1 WO 2021208364 A1 WO2021208364 A1 WO 2021208364A1 CN 2020117591 W CN2020117591 W CN 2020117591W WO 2021208364 A1 WO2021208364 A1 WO 2021208364A1
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single crystal
crystal
block
semiconductor
cutting line
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PCT/CN2020/117591
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English (en)
French (fr)
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王书杰
孙聂枫
孙同年
刘惠生
徐森锋
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中国电子科技南湖研究院
中国电子科技集团公司第十三研究所
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Priority to EP20931372.5A priority Critical patent/EP4108813A4/en
Publication of WO2021208364A1 publication Critical patent/WO2021208364A1/zh

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/06—Joining of crystals

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  • the invention belongs to the field of semiconductor material preparation, and specifically relates to a method for preparing large-sized single crystals by realizing solid-state connection between crystals through hot isostatic pressing.
  • Compound semiconductor materials are one of the important basic supporting technologies for the development of the electronic information industry technology system. They are widely used in optical fiber communications, mobile communications, navigation, detection and other fields, and have become a hot spot for development in various countries.
  • the compound semiconductor single crystal substrate is the basis for the preparation of various electronic devices. The larger the size of the semiconductor single crystal, the lower the cost of the prepared device. The size of the semiconductor single crystal substrate reflects the competitiveness of the development of the national semiconductor industry.
  • the size of the crucible will increase accordingly. In order to establish a temperature gradient, the temperature at the edge of the crucible will become higher and higher, which will cause the crucible to reduce its strength or even tolerate high temperatures and contaminate the melt. At the same time, the energy utilization rate will be reduced accordingly. Therefore, from the perspective of equipment and consumables, there are more and more problems in increasing the size of heat preservation and heater, crucible size and furnace body size only by unlimitedly increasing the furnace body.
  • Chinese patent application CN 110541199 A discloses a method for preparing high-quality SiC seed crystals with a diameter of 8 inches and above.
  • the spliced SiC seed crystals are spliced using an external grinder.
  • This application represents a technical idea of connecting them together by epitaxial growth.
  • the epitaxial growth requires the epitaxial gas to be deposited at the joints through physical and chemical processes.
  • the hot isostatic pressing method is basically used to control the growth environment to complete the crystal growth, such as Chinese patent application 201210003909.3 (a high-temperature and high-pressure crystal growth equipment), Chinese patent application 201910263191.3 (a suitable ammonia thermal method to generate gallium nitride Hot isostatic pressing device for single crystal products).
  • the present invention proposes a new idea of connecting multiple small-size single crystals in solid state through a hot isostatic pressing connection method to prepare large-size high-purity semiconductor single crystals.
  • the technical solution adopted by the present invention is a hot isostatic pressing method for high-purity semiconductor single crystals, which includes the following steps:
  • Material selection select semiconductor single crystal blocks with similar overall physical properties and basically consistent splicing plane orientation accuracy.
  • Splicing surface processing Orientation, polishing and pickling treatment of the splicing surface of the semiconductor single crystal block
  • Single crystal assembly connect the processed single crystal block, the splicing surface and the splicing surface, and assemble them into a whole
  • Single crystal connection Place the assembled single crystal block in a hot isostatic pressing furnace body for heating and pressurizing treatment to complete the solid state connection between the single crystal blocks.
  • the roughness of the splicing surface is 0.3nm-10nm, the flatness is 1-10 microns, and the crystal orientation difference between the splicing surfaces is less than 0.05°.
  • the semiconductor ingot is obtained by cutting a single crystal ingot or a plurality of crystal ingots.
  • the realization principle of the present invention is: the assembled single crystal block is processed by hot isostatic pressing, and at a certain pressure and temperature, according to the consistency of the crystal lattice, the single crystal block is mutually diffused through solid atoms for a long time.
  • the splicing surface between the atoms is connected under high temperature and high pressure, and all the single crystal blocks are connected in a solid state to form a large single crystal.
  • FIG. 1 Schematic diagram of the assembly of single crystals connected by hot isostatic pressing
  • FIG. 1 Schematic diagram of crystal splicing assembly
  • FIG. 3 Schematic diagram of precision splicing and assembly of multiple single crystals
  • FIG. 4 Schematic diagram of the ingot and its plan to cut the position of the ingot
  • Figure 5 is a schematic diagram of a single crystal block cut by an ingot with twin crystals and polycrystals
  • Figure 6 shows the splicing combination of single crystal blocks cut on the same ingot
  • Figure 7 is a schematic diagram of cutting and splicing single crystal blocks on different crystal ingots.
  • Fig. 8 is a schematic diagram of cutting single crystal blocks from single crystal blocks on different crystal ingots.
  • 21 single crystal block
  • 22 fastening clamp ring
  • 23 cover upper cover
  • 23-1 cover edge sealing of cover cover
  • 23-2 suction hole
  • 24 clamp
  • 26 Semiconductor powder layer
  • 27 Covering protective layer
  • 28 Covering main body
  • 28-1 Covering main body edge sealing
  • 29 Fastening clamp ring protective layer
  • 30 Splicing surface
  • 31 Substrate
  • 32 Filler block.
  • the present invention is completed by the following steps.
  • the overall similar physical properties means that the crystal growth thermal field and growth conditions are the same, and the dopant concentration and crystal shape in the melt are similar.
  • a suitable single crystal block can be selected from the single crystals that have been cut.
  • the invention provides a method of directly cutting and obtaining a single crystal block from the crystal ingot.
  • Figure 4 shows three crystal ingots: two LEC crystal ingots and one VGF crystal ingot 2.
  • the crystal ingots have twins and polycrystalline macroscopic defects.
  • Twin boundaries 4 and polycrystalline boundaries 5 represent the location of the defects. There are also defects in the ingot 3 cut from the ingot.
  • the cylinder is the crystal rod 3 (not shown in the figure), and the left and right parts represent crystal rods with two different macroscopic (twin or polycrystalline) defects at different positions.
  • the overall physical properties of a crystal ingot are the same; because the cutting surface is the splicing surface, it can ensure that the splicing surfaces of the two single crystal blocks have the same crystal orientation and the splicing accuracy is high.
  • Cutting methods include:
  • the resin block 6 is not cut through, and the crystal rod 3 and the resin block are in an integral state, and then the resin block 6 is removed by boiling.
  • Steps A3 and A4 are in no particular order.
  • the single crystal block I3-1 and the single crystal block II3-2 can be assembled into a complete circle; in order to obtain a single crystal block with a uniform height, it can be Height, process another single crystal block.
  • the single crystal block I3-1 and the single crystal block II3-2 are spliced through the splicing surface 3-3 to keep the [def] crystal orientation of the two crystals the same.
  • the present invention provides two methods.
  • the crystal orientation accuracy of the splicing surface is basically the same, and the utilization rate of the material must be considered.
  • Cutting methods include:
  • the single crystal block I3-4 and the single crystal block II3-5 can be assembled into a cylinder; The height of another single crystal block is processed.
  • Method 2 cut multiple single crystal blocks from multiple crystal ingots, and combine the single crystal blocks into a cuboid or cube, see Figure 8.
  • the crystal orientation accuracy of the splicing surface is basically the same, and the utilization rate of the material must be considered.
  • Cutting methods include:
  • Step C2 ensures that the cutting positions on the ingot 3 are consistent.
  • Splicing surface processing Orienting, polishing and pickling the splicing surface of the semiconductor single crystal block.
  • the crystal block cut by the above method does not need to be oriented.
  • the single crystal is oriented by measuring the crystal orientation.
  • the selected crystal block or the cut crystal block is polished and pickled on the splicing surface, so that the roughness of the splicing surface is 0.3nm-10nm, the flatness is 1-10 microns, and the crystal orientation difference between the splicing surfaces is less than 0.05°.
  • Single crystal assembly connect the processed single crystal block, the splicing surface and the splicing surface, and assemble them into a whole.
  • the single crystal block I3-1 and the single crystal block II3-2 are spliced through the splicing surface 3-3 to keep the [def] crystal orientation of the two crystals the same.
  • the single crystal block III3-4 and the single crystal block IV3-5 are spliced through the splicing surface II3-6, which can ensure the electrical uniformity and symmetry of the single crystal substrate processed after the entire spliced ingot is connected. High sex.
  • the single crystal blocks cut in Figure 8 are spliced as shown in the middle figure 2 or Figure 3.
  • the single crystal blocks are spliced, ensure that the [mno] crystal orientation is connected to the splicing surface of the [-mno] crystal orientation of the other single crystal block.
  • the [pqr] crystal orientation is connected with the splicing plane of the [-pqr] crystal orientation of another single crystal block.
  • the connection of a larger number of single crystal blocks can be realized, and the splicing method can ensure continuous uniformity distribution between the chips.
  • this embodiment uses an assembly structure to complete the single crystal assembly, and the assembly process is as follows:
  • the single crystal block 21 and its splicing surface 30 are processed, and the splicing surface 30 of the two single crystal blocks 21 connected to each other is the common crystal plane of the two single crystal blocks 21, and any two different crystal orientations are maintained on the crystal surface. It is basically the same (the crystal orientation difference is less than 0.05°), and the periodicity of the overall lattice arrangement on different single crystal blocks is approximately the same.
  • the splicing surface 30 is subjected to mechanical chemical polishing, and the surface roughness of the splicing surface 30 is 0.3 nm-10 nm, and the flatness is 1-10 microns.
  • a card slot is processed on the single crystal block 21 and a fixture 24 is processed.
  • the size of the fixture 24 is determined according to the combined size of the multiple single crystal blocks 21.
  • the clamp 24 is cut from the semiconductor material of the same material as the wafer 1 and assembled with the single crystal wafer 21 to prevent stress defects caused by different thermal expansion coefficients of different materials.
  • the position of the processing slot should ensure that the direction of the clamp 24 is perpendicular to the direction of the splicing surface 30 to ensure that the direction of the force of the clamp 4 is perpendicular to the splicing surface 30.
  • clamps 24 to connect the single crystal blocks 21 together. As shown in FIG. 2, clamps 24 are respectively arranged at the upper and lower positions of the single crystal block 21 combination, which ensures the accuracy of the connection and ensures that the splicing surface 30 is not easy to be heated. Relative movement under isostatic pressure.
  • FIG. 2 is a schematic diagram of splicing two single crystal blocks 21 together.
  • FIG. 3 is another embodiment, a schematic diagram of splicing a plurality of single crystal blocks 21 together.
  • the outermost single crystal block 21 is filled with a filling block 32 to make the overall shape suitable for wrapping.
  • the filling block 32 is cut using a semiconductor material of the same material as the crystal block 21.
  • the substrate 31 uses the same semiconductor material as the crystal block 1, which can be a single crystal or a polycrystalline material. .
  • Quartz cloth or quartz fiber thread is washed with organic solvent and high-temperature vacuum treatment to remove oil stains on the surface. At the same time, it is vibrated and purged to remove the easily falling quartz filaments. The effect is to prevent pollution and prevent liquid and other impurities from entering the splicing surface.
  • the assembled and fixed single crystal block 21 is tightly wrapped with the quartz coating 25.
  • the fastening clip 22 has a fastening clip protection layer 29, and the surface of the fastening clip 22 has a boron oxide coating with a thickness of 0.5-1mm, and a boron oxide coating It can prevent metals from contaminating semiconductor materials.
  • the ingot unit is placed in the sheath body 28, and the surrounding area is filled with semiconductor material powder of the same quality as the single crystal ingot 21 to form a semiconductor powder layer 26, so that the ingot unit is located in the center of the sheath body 28 (not required to be precise, approximately Just in the center), compact the semiconductor powder, as shown in Figure 1.
  • the sheath protective layer 27 is a boron oxide coating with a thickness of 0.5-1 mm, and there is no boron oxide coating at the top cover sealing edge 23-1 and the sheath body sealing edge 28-1.
  • the sealing edge 23-1 of the cover upper cover and the sealing edge 28-1 of the cover main body are welded by laser or electron beam to complete the structural assembly.
  • Pretreatment the crystal assembly is completed, the suction hole 23-2 through the entire sheath is evacuated to 10 -3 to 10 - 6 Pa, and 0.5 to 5 hours at a temperature of preheated 400 °C.
  • the main function of heat treatment is to remove the oxide layer on the crystal surface.
  • the exhaust hole 23-2 is squeezed, and then the exhaust hole 23-2 is sealed by laser or electron beam welding for leak detection.
  • Single crystal connection Place the assembled and pretreated single crystal block in a hot isostatic pressing furnace body for heating and pressurization to complete the solid state connection between the single crystal blocks.
  • the boron oxide material is relatively brittle in a low temperature environment. If pressure is applied at a low temperature, the pressure may cause deformation of the HIP sheath, causing the boron oxide layer to break, fall off or move, and expose the sheath body 28 or the sheath.
  • the metal layer of the cover 23 causes the diffusion of metal atoms and contaminates the semiconductor material.
  • the protective gas is discharged, the temperature is slowly lowered to room temperature, the metal sheath is removed by wire cutting, and then the semiconductor polycrystalline area formed by the semiconductor powder layer 26 under high pressure is cut by a wire saw, the quartz coating layer 25, the fixture 24, The filling block 32 and the homogeneous semiconductor substrate 31 are connected to obtain large-size crystal blocks.
  • the welding position of the sealing edge 23-1 of the cover cover and the sealing edge 28-1 of the cover body is as far away as possible from the cover body 28, and the seam welding position of the exhaust hole 23-2
  • the distance from the hot isostatic pressing body 28 is at least 5 mm.
  • the assembly structure is always placed in the hot isostatic pressing furnace in the direction that the single crystal block 1 is located above the homogeneous semiconductor substrate 11.

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  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

一种高纯半导体单晶的热等静压连接方法，将多块小尺寸单晶通过热等静压方式实现晶体间的固态连接制备成大尺寸单晶。包括以下步骤：选取物理特性整体相近且拼接面(30)晶向精度基本一致的半导体单晶块(21)；对拼接面(30)进行定向、抛光、酸洗处理；拼接面(30)与拼接面(30)对接，装配成一体，放置于热等静压炉体中进行加热和加压处理，完成单晶块(21)间的固态连接。可以实现将小尺寸的单晶块(21)连接制备成大尺寸的单晶，设备简单，制备过程中不必考虑位错、孪晶、多晶化等在传统单晶生长过程中需要注意的问题，理论上可以制备任意尺寸的单晶。

Description

一种高纯半导体单晶的热等静压连接方法 技术领域
本发明属于半导体材料制备领域，具体涉及将多块小尺寸单晶通过热等静压方式实现晶体间的固态连接，制备成大尺寸单晶的方法。
背景技术
化合物半导体材料是电子信息产业技术体系发展的重要基础支撑技术之一，其广泛应用于光纤通信、移动通信、导航、探测等领域，已经成为各国竞相发展的热点。化合物半导体单晶衬底是是制备各类电子器件的基础，半导体单晶的尺寸越大，所制备器件的成本就越低，半导体单晶衬底的尺寸体现了国家半导体行业发展的竞争力。
但是，半导体单晶衬底的尺寸越大，使用传统方法制备的难度也越大：单晶炉设备的尺寸大，单晶生长温度场的稳定性和对称性要求高，对设备的仪器的要求高。同时坩埚的尺寸也会相应的增加，为了建立温度梯度，坩埚边缘的温度也就越来越高，这会导致坩埚强度降低甚至不能承受高温而污染熔体。同时，能源的利用率也会相应的降低。因此，从设备和耗材的角度来说，仅仅靠无限制的增大炉体，增大保温及加热器的尺寸、坩埚尺寸及炉体尺寸遇到了越来越多的问题。
位错及夹杂物等微观缺陷会严重影响后续器件的质量及产率，化合物半导体中的孪晶和多晶化是不可接收的宏观缺陷。位错和孪晶及多晶化是一对矛盾，位错的降低需要降温温度梯度，但是温度梯度的降低会增加孪晶的几率和多晶化的形成。因此，从生长角度来说，制备高品质低缺陷的大尺寸单晶的难度也越来越大。
中国专利申请CN 110541199 A公开了一种直径8英寸及以上尺寸的高质量SiC籽晶制备方法，通过切割拼接比目标籽晶尺寸小的SiC晶片或晶体，采用外圆磨床将拼接的SiC籽晶加工成完整晶圆形状，并在拼接SiC籽晶的生长面先进行侧向外延生长，填充籽晶拼接裂缝；随后在籽晶生长面进行同质外延，最终获得表面总厚度变化小、无裂缝、缺陷密度少的直径8英寸及以上尺寸的高质量SiC籽晶。该申请代表了一个技术思路，即通过外延生长将其连接在一起。
采用这种方式，需要控制还原生长环境，通过外延生长将其连接在一起。外延生长需要外延气体通过物理化学沉积在接缝处。
采用热等静压方式，目前基本上都是控制生长环境，完成晶体生长，如中国专利申请201210003909.3(一种高温高压晶体生长设备)、中国专利申请201910263191.3(一种适 合氨热法生成氮化镓单晶制品的热等静压装置)。
发明内容
本发明提出了一种新的思路，通过热等静压连接方法，将多块小尺寸单晶固态连接，制备大尺寸高纯半导体单晶。
为实现上述目的，本发明采用的技术方案是，一种高纯半导体单晶的热等静压连接方法，包括以下步骤：
材料选取：选取物理特性整体相近且拼接面晶向精度基本一致的半导体单晶块，
拼接面加工：对半导体单晶块的拼接面进行定向、抛光、酸洗处理，
单晶装配：将加工后的单晶块，拼接面与拼接面对接，装配成一体，
单晶连接：将装配好的单晶块，放置于热等静压炉体中进行加热和加压处理，完成单晶块间的固态连接。
进一步地，拼接面的粗糙度为0.3nm-10nm，平整度为1-10微米，拼接面间的晶向差小于0.05°。
进一步地，通过对单个晶锭或多个晶锭进行切割获取半导体晶块。
本发明的实现原理是：拼装好的单晶块，经热等静压处理，在一定的压力和温度下，按着晶格的一致性，通过较长时间的固态原子相互扩散，单晶块间的拼接面在高温高压下实现原子键合连接，所有的单晶块固态连接，形成一个大的单晶体。
有益效果：1、可以实现将小尺寸的单晶块连接制备成大尺寸的单晶，2、设备简单，3、制备过程中，不必考虑错位、孪晶、多晶化等在传统单晶生长过程中需要注意的问题，4、理论上可以制备任意尺寸的单晶。
附图说明
图1热等静压连接单晶体的装配示意图，
图2晶体拼接装配示意图，
图3多块单晶体精密拼接装配示意图，
图4晶锭及其计划切取晶棒位置示意图，
图5为存在孪晶和多晶的晶棒切割单晶块的示意图，
图6为同一晶锭上切割的单晶块拼接组合，
图7为不同晶锭上单晶块切取及拼接单晶块的示意图，
图8为不同晶锭上单晶块切取单晶块的示意图。
其中：
图1-3中，21：单晶块；22：紧固卡圈；23：包套上盖；23-1：包套上盖封边；23-2：抽气孔；24：卡具；25；石英包裹层；26：半导体粉层；27：包套保护层；28：包套主体；28-1：包套主体封边；29；紧固卡圈保护层；30：拼接面；31：基板，32：填充块。
图4中，1：LEC晶锭；2：VGF晶锭；3：晶棒；4：孪晶界；5：多晶界。
图5中，4：孪晶界；5：多晶界；6：粘合树脂；7：切割线轨迹I；8：切割线轨迹II；9：切割线轨迹III；10：基准面；3-1：单晶块I；3-2：单晶块II。
图6中，3-3：拼接面I。
图7中，11：切割轨迹IV；12：切割轨迹V；13：晶锭/晶棒中心；3-4：单晶块III；3-5：单晶块IV；3-6：拼接面II。
图8中，14：单晶块VI。
具体实施方式
制备大尺寸单晶，本发明通过以下步骤完成。
一、选取物理特性整体相近且拼接面晶向精度基本一致的半导体单晶块。
物理特性整体相近是指其晶体生长热场及生长条件相同，熔体中掺杂剂的浓度及晶体形状相近。
单晶块中没有孪晶和多晶等缺陷。
合适的单晶块可以从已经切割好的单晶中选择。
本发明提供了直接从晶锭中切割获取单晶块的方法。
图4中显示了三个晶锭：两个LEC晶锭1、一个VGF晶锭2，晶锭存在孪晶和多晶宏观缺陷，孪晶界4和多晶界5代表了缺陷的位置。从晶锭中切取的晶棒3中也存在缺陷。
1、通过对单个晶锭切割获取半导体晶块，参看图5。图中，圆柱体为晶棒3(图中未标出)，左右两部分表示在不同位置、具有两种不同的宏观(孪晶或多晶)缺陷的晶棒。
一个晶锭整体物理特性相同；由于切割面即为拼接面，因此能够保证两块单晶块的拼接面晶向相同且拼接精度很高。
切割时，要保证切取的单晶块内部无宏观缺陷，同时要考虑材料的利用率。
切割方法包括：
A1、将晶锭1或2切割成圆柱体晶棒3，将晶棒3粘接在树脂块6上，加工出基准面10，基于基准面10设定坐标系。
A2、设定切割线轨迹I7、切割线轨迹II8和切割线轨迹III9。
通过肉眼或仪器观察晶棒3，在设定切割轨迹时，要保证切取的两个单晶块3-1和3-2避开孪晶界4或多晶界5，同时尽量使两个单晶块的高度一致。
A3、按着切割线轨迹I7和切割线轨迹II8切割晶棒3。
A4、按着切割线轨迹III9切割晶棒3。
加工过程不将树脂块6切透，晶棒3和树脂块处于整体状态，然后通过水煮去掉树脂块6。
通过上述步骤，得到了单晶块I3-1和单晶块II3-2。步骤A3、A4不分先后。
由于按着切割线轨迹III9切割晶棒3，单晶块I3-1和单晶块II3-2可以拼合成一个整圆；为了得到高度一致的单晶块，可以根据较薄的单晶块的高度，加工另一个单晶块。
单晶块I3-1和单晶块II3-2通过拼接面3-3进行拼接，保持两块晶体的[def]晶向相同。
2、通过对多个晶锭切割获取半导体晶块。
本发明提供了两种方法。
方法1，从两个晶锭上切取两个单晶块，单晶块组合成圆柱体，参看图7。
选取晶体生长热场及生长条件相同，熔体中掺杂剂的浓度及晶体形状相近的晶锭。
切割时要保证切取的单晶块内部无宏观缺陷，拼接面晶向精度基本一致，同时要考虑材料的利用率。
切割方法包括：
B1、在两个不同的晶锭1或2上分别切取直径相同的圆柱体晶棒3，分别加工出基准面10，两个晶棒3的晶向指数相同。
B2、在其中一个晶棒3上设定切割线轨迹IV11，沿着切割线轨迹IV11切割晶棒3，得到单晶块III3-4。
B3、测试单晶块III3-4上切割晶面的晶向指数[ghi]，测量基准面10圆心13至切割线轨迹IV11的距离d。
B4、在另一个晶棒上选取[-g-h-i]晶面，圆心13至该晶面的距离为d的位置设计切割线轨迹IV11，沿着切割线轨迹IV11进行切割，获得单晶块IV3-5。
切取体晶棒3时，尽量使两个晶棒3的高度一致。
通过肉眼或仪器观察晶棒3，在设定切割轨迹时，要保证切取的两个单晶块3-5和3-6避开图中曲线表示的缺陷区域。
通过定向(测出晶向[jkh])保持两个晶棒3的晶向指数相同。
由于按着切割线轨迹IV11切割晶棒3，单晶块I3-4和单晶块II3-5可以拼合成一个圆 柱体；为了得到高度一致的单晶块，可以根据高度较低的单晶块的高度，加工另一个单晶块。
方法2，从多个晶锭上切取多个单晶块，单晶块组合成长方体或立方体，参看图8。
选取晶体生长热场及生长条件相同，熔体中掺杂剂的浓度及晶体形状相近的晶锭。
切割时要保证切取的单晶块内部无宏观缺陷，拼接面晶向精度基本一致，同时要考虑材料的利用率。
切割方法包括：
C1、在不同的晶锭1分别切取直径相同的圆柱体晶棒3，分别加工出基准面10，基于基准面10设定坐标系，每个晶棒3的晶向指数相同。
C2、从不同晶棒3中切取单晶块VI14，所有单晶块的[mno]和[pqr]晶向一致，各单晶块VI14各面距离其晶棒3基准面圆心13距离n1、n2、n3、n4数值相同。
步骤C2保证了在晶棒3上切取位置一致。
二、拼接面加工：对半导体单晶块的拼接面进行定向、抛光、酸洗处理。
通过上述方法切取的晶块，无需再做定向。
不是通过上述方法选取的晶块，通过测量晶向，对单晶进行定向。
选择的晶块或切割好的晶块，对其拼接面进行抛光、酸洗处理，使拼接面的粗糙度为0.3nm-10nm，平整度为1-10微米，拼接面间的晶向差小于0.05°。
三、单晶装配：将加工后的单晶块，拼接面与拼接面对接，装配成一体。
如图6所示，单晶块I3-1和单晶块II3-2通过拼接面3-3进行拼接，保持两块晶体的[def]晶向相同。图7最右面的图中，单晶块III3-4和单晶块IV3-5通过拼接面II3-6进行拼接，可以保证整个拼接晶棒连接以后加工出的单晶衬底电学均匀性和对称性高。
图8中切取的单晶块拼接后如2中间图形或图3所示，单晶块之间拼接时保证[mno]晶向与另一个单晶块的[-m-n-o]晶向的拼接面相连接，[pqr]晶向与另一个单晶块的[-p-q-r]晶向的拼接面相连接。可以实现更多数量单晶块的连接，该拼接方法可以保证片间的均匀性分布连续。
为了便于在热等静压炉内处理，本实施例使用装配结构完成单晶装配，装配过程如下：
1：加工出单晶块21及其拼接面30，相互连接的两个单晶块21的拼接面30为两个单晶块21的共用晶面，保持晶面上任取两个不同晶向保持基本一致(晶向差小于0.05°)，实现不同单晶块上总体晶格排列的周期性近似一致。
对拼接面30进行机械化学抛光，拼接面30的表面粗糙度为0.3nm-10nm，平整度为 1-10微米。
如需要夹具4固定，则在单晶块21上加工出卡槽，并加工出卡具24，卡具24的尺寸根据多个单晶块21组合后的大小确定。
卡具24使用与晶块1相同材质的半导体材料切制，与单晶快21配合装配，防止不同材质的热膨胀系数的不同产生应力缺陷。
加工卡槽的位置要保证夹具24的方向与拼接面30的方向垂直，以保证夹具4作用力的方向垂直于拼接面30。
用卡具24将单晶块21连接在一起，如图2所示，在单晶块21组合的上下位置分别设置卡具24，这样保证了连接的精度，又保证了拼接面30不易在热等静压下相对移动。
图2是将两个单晶块21拼接在一起的示意图。
图3是另一个实施例，将多个单晶块21拼接在一起的示意图。图3的实施例中，使用填充块32填充最外侧单晶块21的外围，使整体形状适合包裹。填充块32使用与晶块21相同材质的半导体材料切制。
为了保证组合固定后单晶块21在包裹过程中不发生错位，固定的单晶块21组合下面有基板31，基板31使用与晶块1相同材质的半导体材料，可为单晶或者多晶材料。
石英布或者石英纤维线经过有机溶剂洗涤、高温真空处理，去除表面的油污，同时经过振动及吹扫去除易脱落石英丝。效果是防止污染，防止拼接面进入液体和其他杂质。
用石英包裹层25将组合固定好的单晶块21紧密包裹。
包裹完成后用紧固卡圈22紧固，紧固卡圈22外有紧固卡圈保护层29，紧固卡圈22的表面有厚度为0.5-1mm的氧化硼涂层，氧化硼涂层可以防止金属污染半导体材料。
完成上述装配后得到晶块单元。
将晶块单元放入包套主体28中，四周利用与单晶块21同质的半导体材料粉末填充，形成半导体粉层26，使晶块单元位于包套主体28中央位置(不要求精准，大概在中央即可)，压实半导体粉末，如图1所示。
图1中，包套保护层27为厚度为0.5-1mm的氧化硼涂层，包套上盖封边23-1和包套主体封边28-1处无氧化硼涂层。
包套上盖封边23-1与包套主体封边28-1利用激光或者电子束焊接，完成结构的装配。
四、预处理：单晶装配完成后，通过抽气孔23-2对整个包套进行抽真空至10 -3至10 - 6Pa，并在400℃温度下进行0.5-5小时的预热处理。
热处理的主要作用是去掉晶体表面的氧化层。
预处理完成后，对抽气孔23-2进行挤压，然后激光或者电子束焊接密封抽气孔23-2，检漏。
五、单晶连接：将装配好并经预处理的单晶块，放置于热等静压炉体中进行加热和加压处理，完成单晶块间的固态连接。
设定热等静压的温度为0.8-0.9Tm，达到设定的热等静压温度以后，向热等静压炉体中充入保护气体，缓慢升高压力至20MPa-300MPa，根据半导体材料的不同选择不同的压力。
虽然对拼接面进行了处理，但不排除拼接面上还有微小的凸起。低温下施加压力，拼接面上局部(凸起部分)会承受极大压力，超过低温下的最大强度，晶体局部会发生断裂，处理后会产生缺陷。
另外，低温环境下，氧化硼材料比较脆，如果在低温时施加压力，压力可能会造成热等静压包套变形，导致氧化硼层断裂，脱落或移动，暴露包套主体28或包套上盖23的金属层，造成金属原子扩散，污染半导体材料。
处理完成后，排出保护性气体，缓慢降温至室温，利用线切割去除金属包套，然后利用线锯切割半导体粉层26在高压下形成的半导体多晶区域、石英包裹层25、卡具24、填充块32及同质半导体基板31，得到连接生成的大尺寸晶块。
为了减少局部热应力对半导体晶体的影响，包套上盖封边23-1与包套主体封边28-1的焊接位置尽量远离包套主体28，抽气孔23-2的缝口焊缝位置距离热等静压主体28至少为5mm。
整个热等静压过程中，保持好位置：装配结构始终按着单晶块1位于同质半导体基板11上方的方向放置在热等静压炉中。

Claims (10)

  1. 一种高纯半导体单晶的热等静压连接方法，其特征在于包括以下步骤：
    材料选取：选取物理特性整体相近且拼接面晶向精度基本一致的半导体单晶块，
    拼接面加工：对半导体单晶块的拼接面进行定向、抛光、酸洗处理，
    单晶装配：将加工后的单晶块，拼接面与拼接面对接，装配成一体，
    单晶连接：将装配好的单晶块，放置于热等静压炉体中进行加热和加压处理，完成单晶块间的固态连接。
  2. 根据权利要求1所述的方法，其特征在于：拼接面的粗糙度为0.3nm-10nm，平整度为1-10微米，拼接面间的晶向差小于0.05°。
  3. 根据权利要求1所述的方法，其特征在于：通过对单个晶锭切割获取半导体晶块，切割方法包括：
    A1、将晶锭(1)切割成圆柱体晶棒(3)，加工出基准面(10)，基于基准面(10)设定坐标系，
    A2、设定切割线轨迹I(7)、切割线轨迹II(8)和切割线轨迹III(9)，
    A3、按着切割线轨迹I(7)和切割线轨迹II(8)切割晶棒(3)，
    A4、按着切割线轨迹III(9)切割晶棒(3)，得到单晶块I(3-1)和单晶块II(3-2)。
  4. 根据权利要求1所述的方法，其特征在于：通过对多个晶锭切割获取半导体晶块，切割方法包括：
    B1、在两个不同的晶锭(1)分别切取直径相同的圆柱体晶棒(3)，分别加工出基准面(10)，通过定向保持两个晶棒(3)的晶向指数相同，
    B2、在其中一个晶棒(3)上设定切割线轨迹IV(11)，沿着切割线轨迹IV(11)切割晶棒(3)，得到单晶块III(3-4)，
    B3、测试单晶块III(3-4)上切割晶面的晶向指数[ghi]，测量基准面(10)圆心(13)至切割线轨迹IV(11)的距离d；
    B4、在另一个晶棒上选取[-g-h-i]晶面，圆心(13)至该晶面的距离为d的位置设计切割线轨迹IV(11)，沿着切割线轨迹IV(11)进行切割，获得单晶块IV(3-5)。
  5. 根据权利要求1所述的方法，其特征在于：通过对多个晶锭切割获取半导体晶块，切割方法包括：
    C1、在不同的晶锭(1)分别切取直径相同的圆柱体晶棒(3)，分别加工出基准面(10)，每个晶棒(3)的晶向指数相同，
    C2、从不同晶棒(3)中切取单晶块VI(14)，所有单晶块的[mno]和[pqr]晶向一致，各单晶 块VI(14)各面距离其晶棒(3)基准面圆心(13)距离n1、n2、n3、n4数值相同。
  6. 根据权利要求1所述的方法，其特征在于：使用装配结构完成单晶装配，
    所述装配结构包括包套和置于包套内部的晶块单元，所述包套由包套主体(28)和包套上盖(23)组成，
    所述包套主体(28)或包套上盖(23)上设置抽气孔(23-2)，包套主体(28)和包套上盖(23)的内表面设置包套保护层(27)；
    所述晶块单元包括多个单晶块(21)，单晶块(21)间通过拼接面(30)组合，并使用夹具(24)进行固定，固定的单晶块(21)组合的外表面设置石英包裹层(25)；
    所述夹具(24)使用与晶块(21)相同材质的半导体材料。
  7. 根据权利要求6所述的方法，其特征在于：所述晶块单元置于包套主体(28)中央位置，周围使用与单晶块(21)同质的半导体材料粉末填充。
  8. 根据权利要求7所述的方法，其特征在于：半导体粉末的粒径大于拼接面的平整度。
  9. 根据权利要求7所述的方法，其特征在于，单晶装配完成后，通过抽气孔(23-2)对整个包套进行抽真空至10 -3至10 -6Pa，并在400℃温度下进行0.5-5小时的预热处理；密封抽气孔(23-2)。
  10. 根据权利要求9所述的方法，其特征在于，
    单晶连接：将装配好的单晶块，放置于热等静压炉体中进行加热和加压处理，热等静压的温度为0.8-0.9Tm；当达到设定温度后，向热等静压炉体中充入保护气体，缓慢升高压力至20MPa-300MPa，然后保持30min-10小时；
    Tm为连接的半导体材料的熔点。
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