WO2021203945A1 - 沟槽隔离结构制备方法和半导体器件制备方法 - Google Patents

沟槽隔离结构制备方法和半导体器件制备方法 Download PDF

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WO2021203945A1
WO2021203945A1 PCT/CN2021/081784 CN2021081784W WO2021203945A1 WO 2021203945 A1 WO2021203945 A1 WO 2021203945A1 CN 2021081784 W CN2021081784 W CN 2021081784W WO 2021203945 A1 WO2021203945 A1 WO 2021203945A1
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Prior art keywords
trench
dielectric layer
isolation structure
trench isolation
compensation
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PCT/CN2021/081784
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English (en)
French (fr)
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徐陈明
车范锡
关文婧
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长鑫存储技术有限公司
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Priority to US17/406,970 priority Critical patent/US20210384066A1/en
Publication of WO2021203945A1 publication Critical patent/WO2021203945A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Definitions

  • This application relates to the field of semiconductors, and in particular to a method for preparing a trench isolation structure and a method for preparing a semiconductor device.
  • the semiconductor device needs to form a trench isolation structure to achieve isolation of adjacent active regions.
  • processes such as cleaning, thermal oxidation, and atomic layer deposition (ALD) are generally carried out.
  • ALD atomic layer deposition
  • polysilicon film compensation technology is generally introduced, that is, after the trench is opened, a polysilicon film is formed on the inner wall of the trench. Oxidation, atomic layer deposition (ALD) and other processes are consumed, thereby reducing the loss of active area size.
  • a method for manufacturing a trench isolation structure and a method for manufacturing a semiconductor device are provided.
  • a method for preparing a trench isolation structure includes:
  • a second dielectric layer is filled in the trench to form the trench isolation structure, and the compensation film is completely consumed after the second dielectric layer is filled.
  • the filling of a first dielectric layer with a preset depth at the bottom of the trench includes:
  • the first dielectric material is engraved back, the first dielectric material at the bottom of the trench is retained, and the retained first dielectric material forms the first dielectric layer.
  • the depth of the first dielectric material that is etched back in the trench ranges from 70 nm to 300 nm.
  • the first dielectric layer is spin-coated carbon or photoresist.
  • the forming a compensation film on the sidewall of the trench above the first dielectric layer includes:
  • the compensation material is etched back to remove the compensation material located on the upper surface of the first dielectric layer and the upper surface of the substrate, and the compensation material located at the sidewall of the trench is retained, and the retained compensation material forms the compensation membrane.
  • the forming a compensation film on the sidewall of the trench above the first dielectric layer includes:
  • An epitaxial layer is grown on the sidewall of the trench by epitaxial growth to serve as the compensation film.
  • the compensation film is a polysilicon layer.
  • the thickness range of the polysilicon layer is
  • a compensation film is formed on the sidewall of the trench above the first dielectric layer, and before a second dielectric layer is filled in the trench to form the trench isolation structure, include:
  • the first dielectric layer is removed.
  • the filling a second dielectric layer in the trench to form the trench isolation structure includes:
  • the second dielectric layer is filled in the trench by a chemical vapor deposition process or an atomic layer deposition process to form the trench isolation structure.
  • the second dielectric layer includes one or more of oxide, nitride, and oxynitride.
  • a method for manufacturing a semiconductor device includes:
  • a transistor structure is prepared in the active region to form the semiconductor device.
  • the semiconductor device is a dynamic random access memory
  • the gate of the transistor is prepared in the substrate to form a buried word line.
  • a first dielectric layer of a preset thickness is first filled in the bottom of the trench, and then a compensation film is formed on the sidewall of the trench above the first dielectric layer. Since the bottom of the trench is filled with The first dielectric layer, so no compensation film will be formed at the bottom of the trench.
  • the compensation film will be consumed in the cleaning and deposition processes.
  • the introduction of thin film compensation technology can reduce the loss of the active area during cleaning, thermal oxidation and other processes.
  • no compensation film is formed at the bottom of the trench, which can avoid the compensation of the narrow area at the bottom of the trench. The film is difficult to be consumed and a residual phenomenon occurs. That is, the above-mentioned trench isolation structure preparation method can not only reduce the size loss of the active region, but also ensure the isolation effect of the trench isolation structure.
  • Fig. 1a and Fig. 1b are schematic structural diagrams corresponding to the relevant steps of the preparation method for forming the trench isolation structure in the conventional technology
  • FIG. 2 is a flow chart of the steps of a method for fabricating a trench isolation structure according to an embodiment
  • 3a to 3f are structural schematic diagrams corresponding to relevant steps of a method for fabricating a trench isolation structure according to an embodiment
  • FIG. 4 is a top view of the trench isolation structure of an embodiment after the active region is defined;
  • FIG. 5 is a schematic diagram of the structure of a dynamic random access memory according to an embodiment.
  • a polysilicon film compensation technique is used to form a polysilicon film 130' on the inner wall of the trench and the upper surface of the substrate 110'.
  • a chemical vapor deposition process or an atomic deposition process is used to fill the dielectric layer 150' in the trench to form a trench isolation structure.
  • ALD atomic deposition process
  • the polysilicon film 130' will be consumed in processes such as cleaning, thermal oxidation, and atomic layer deposition (ALD), thereby reducing the loss of the active area.
  • FIG. 1b there is usually a polysilicon film 130' remaining in the narrow area at the bottom of the trench that cannot be consumed, resulting in a shallower trench isolation structure and a weaker isolation effect.
  • This application relates to a method for preparing a trench isolation structure.
  • the method for preparing a trench isolation structure at least includes the following steps:
  • a trench is opened on the substrate, and a first dielectric layer of a preset thickness is filled at the bottom of the trench.
  • a compensation film is formed on the sidewall of the trench above the first dielectric layer.
  • a second dielectric layer is filled in the trench to form the trench isolation structure, and the compensation film is completely consumed in the process of filling the second dielectric layer.
  • the preset thickness of the first dielectric layer can be set according to the thickness of the compensation film. For example, the filling height of the compensation film remaining at the bottom of the trench in the traditional technology can be obtained first, and the preset thickness of the first dielectric layer is greater than Or equal to the filling height of the compensation film remaining in the traditional technology. Without forming a compensation film in the narrow area at the bottom of the trench, the problem of residual compensation film in the narrow area at the bottom of the trench can be avoided.
  • the compensation film is completely consumed after filling the second dielectric layer, which means that the compensation film is consumed during the cleaning process after the compensation film is formed and during the deposition process of the second dielectric layer, which can be physically removed. It is also possible that a chemical reaction occurs to transform into a dielectric structure, and after the filling of the second dielectric layer is completed, the compensation film is also completely consumed. Therefore, the thickness design of the compensation film is related to the specific process, and it is necessary to ensure that the compensation film will be completely consumed in the subsequent cleaning and deposition processes.
  • a first dielectric layer of a preset thickness is first filled in the bottom of the trench, and then a compensation film is formed on the sidewall of the trench above the first dielectric layer. Since the bottom of the trench is filled with The first dielectric layer, so no compensation film will be formed at the bottom of the trench.
  • the compensation film will be consumed in the cleaning and deposition processes.
  • the introduction of thin film compensation technology can reduce the loss of the active area during cleaning, thermal oxidation and other processes.
  • no compensation film is formed at the bottom of the trench, which can avoid the compensation of the narrow area at the bottom of the trench. The film is difficult to be consumed and a residual phenomenon occurs. That is, the above-mentioned trench isolation structure preparation method can not only reduce the size loss of the active region, but also ensure the isolation effect of the trench isolation structure.
  • the method for preparing the trench isolation structure includes the following steps:
  • Step S100 Opening a trench on the substrate, and filling the bottom of the trench with a first dielectric layer of a preset thickness.
  • a trench is formed on the substrate 110, and a first dielectric layer 131 of a predetermined thickness is filled at the bottom of the trench.
  • the substrate 110 may be one of a silicon wafer, a germanium wafer, a silicon-on-insulator (SOI) wafer, a germanium-on-insulator (GOI) wafer, a silicon germanium wafer, and a substrate with an epitaxial layer.
  • SOI silicon-on-insulator
  • GOI germanium-on-insulator
  • a mask layer 120 may be formed on the substrate 110 first, an etching pattern is defined by the mask layer 120, and then the trench is etched on the substrate 110 through an etching process.
  • the mask layer 120 is a hard mask, and specifically, silicon nitride or silicon oxide can be selected.
  • a self-aligned multiple exposure process SAQP
  • the groove is in the shape of an inverted trapezoid with a wide top and a narrow bottom.
  • the opening width of the trench can be set as required, and the opening width of the trench can be the same or different.
  • the greater the opening width of the trench the deeper the etching depth, that is, the etching depth of a trench with a wider opening width is greater than that of a trench with a narrower opening width
  • the etching depth should be deep. At this time, we only need to ensure that the preset thickness of the first dielectric layer 131 filled in the shallowest trench is greater than the filling height of the residual compensation film in the traditional technology.
  • the first dielectric layer 131 with a preset thickness can be filled in the bottom of the trench by the following sub-steps:
  • Step S110 depositing a first dielectric material to fill the trench.
  • Step S120 Engrave the first dielectric material to a preset depth, retain the first dielectric material at the bottom of the trench, and the retained first dielectric material forms the first dielectric layer.
  • the first dielectric material 130 is deposited to fill the trench. Specifically, the first dielectric material 130 fills the trench and overflows the trench to a certain height to ensure that the trench is filled with the first dielectric material. Material 130 is filled. Then, the first dielectric material 130 is engraved back to a preset depth, and the first dielectric material 130 with a preset thickness at the bottom of the groove is retained, and the retained first dielectric material 130 forms a first dielectric layer 131 with a preset thickness.
  • the surface of the first dielectric material 130 may be planarized by a chemical mechanical polishing process, and then the first dielectric material 130 may be etched to The preset depth.
  • the etching process used in the back etching may be dry etching, and specifically may be plasma etching.
  • the depth of the first dielectric material 130 that is etched back in the trench ranges from 70 nm to 300 nm.
  • Step S200 forming a compensation film on the sidewall of the trench above the first dielectric layer.
  • a compensation film 141 is formed on the sidewall of the trench above the first dielectric layer 131.
  • the compensation film 141 has a thinner thickness and is attached to the sidewall of the trench and does not fill the trench.
  • the above-mentioned compensation film 141 can be formed in a variety of ways.
  • the compensation film 141 may be formed on the sidewall of the trench above the first dielectric layer 131 through the following substeps:
  • Step S211 deposit a compensation material to cover the sidewall of the trench, the upper surface of the first dielectric layer, and the upper surface of the substrate.
  • Step S212 Re-etch the compensation material to remove the compensation material located on the upper surface of the first dielectric layer and the upper surface of the substrate, retain the compensation material located at the sidewall of the trench, and the retained compensation material is formed The compensation film.
  • a layer of compensation material 140 is deposited by a deposition process, the compensation material 140 covers the sidewalls of the trench, the upper surface of the first dielectric layer 131 and the upper surface of the substrate 110, when the substrate When the mask layer 120 on the 110 is not removed, the compensation material 140 covers the upper surface of the substrate 110, which actually covers the mask layer 120.
  • the compensation material 140 is etched back, and the compensation material 140 is thinned in a direction perpendicular to the upper surface of the substrate 110 to remove the upper surface of the first dielectric layer 131 and the upper surface of the substrate 110.
  • the compensation material 140 retains the compensation material 140 at the sidewall of the trench, and the remaining compensation material 140 forms the aforementioned compensation film 141.
  • the deposition process may specifically be a chemical vapor deposition process or an atomic layer deposition process.
  • the compensation film 141 can also be formed on the sidewall of the trench above the first dielectric layer 131 by the following method: an epitaxial layer is grown on the sidewall of the trench by epitaxial growth to serve as the Compensation film 141.
  • an epitaxial layer is grown on the sidewall of the trench by epitaxial growth to serve as the Compensation film 141.
  • the aforementioned compensation film 141 may be a thin film that is consumed during a cleaning or deposition process.
  • the compensation film 141 may be made of the same material as the substrate 110.
  • the compensation film 141 may be a semiconductor material such as silicon, germanium, etc., for example, the compensation film 141 is a polysilicon layer, and the thickness of the polysilicon layer is in the range of
  • the method further includes a step of removing the first dielectric layer 131.
  • the first dielectric layer 131 at the bottom of the trench is removed.
  • the compensation film 141 formed on the sidewall of the trench remains in the trench, and the compensation film 141 does not extend to the bottom of the trench.
  • Step S300 Filling the trench with a second dielectric layer to form the trench isolation structure, and the compensation film is completely consumed after being filled with the second dielectric layer.
  • the second dielectric layer 150 is filled in the trench, and trench isolation is formed on the substrate 110. At this time, the compensation film 141 is completely consumed after the second dielectric layer 150 is filled.
  • the second dielectric layer 150 can be filled in the trench by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or spin-on insulating dielectric layer (SOD). Any one of the processes fills the second dielectric layer 150 in the trench. Of course, other suitable processes can also be used.
  • the chemical vapor deposition process may specifically include plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), flame chemical vapor deposition (FCVP), atmospheric pressure chemical vapor deposition (APCVD) or low pressure chemical vapor deposition.
  • PECVD plasma enhanced chemical vapor deposition
  • HDPCVD high density plasma chemical vapor deposition
  • FCVP flame chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • LPACVD low pressure chemical vapor deposition
  • the second dielectric layer 150 includes one or more materials in a low-K dielectric.
  • the second dielectric layer 150 may include oxide, nitride, or oxynitride, or a composite of oxide and nitride. Structure layer such as silicon oxide-silicon nitride-silicon oxide (ONO structure).
  • the compensation film 141 is consumed and may be physically removed and thinned during the cleaning process, or may be thermally oxidized and converted into oxide to be filled in the trench as a dielectric structure.
  • the second dielectric layer 150 is filled in the entire trench.
  • the first dielectric layer 131 selects a material with a high selectivity and easy to remove, such as spin-on carbon (SOC), amorphous carbon layer (ACL), photoresist, etc. Resistance materials, etc.
  • the first dielectric layer 131 may not be removed, the bottom of the trench is filled with the first dielectric layer 131, and the top of the trench is filled with the second dielectric layer 150, that is, the first dielectric layer 131 and the second dielectric layer 150 Both are filled in the trench.
  • the first dielectric layer 131 and the second dielectric layer 150 have the same properties, and one or more materials in the low-K dielectric are selected.
  • the second dielectric layer 150 may be oxide or Nitride may also be a composite structure layer of oxide and nitride.
  • the first dielectric layer 131 of a preset thickness is first filled in the bottom of the trench, and then a compensation film 141 is formed on the sidewall of the trench above the first dielectric layer 131.
  • the first dielectric layer 131 is filled, so the compensation film 141 is not formed at the bottom of the trench.
  • the compensation film 141 will be consumed during cleaning and deposition processes.
  • the introduction of thin film compensation technology can reduce the loss of the active region 111 during cleaning, thermal oxidation and other processes.
  • no compensation film 141 is formed at the bottom of the trench, which can avoid the narrow area at the bottom of the trench.
  • the compensation film 141 is difficult to be consumed and a residual phenomenon occurs. That is, the above-mentioned trench isolation structure preparation method can not only reduce the size loss of the active region 111, but also ensure the isolation effect of the trench isolation structure.
  • the present application also relates to a method for manufacturing a semiconductor device.
  • the method for manufacturing a semiconductor device includes:
  • a transistor structure is prepared in the active region to form the semiconductor device.
  • FIG. 4 is a top view of the active region 111 defined by the trench isolation structure on the substrate 110
  • FIG. 3f is a side cross-sectional view along the AA' section line in FIG.
  • the trench isolation structure is prepared on the substrate 110 by the trench isolation structure preparation method in any of the above embodiments
  • the active region 111 is defined by the trench isolation structure, that is, the area of the substrate 110 where the trench isolation structure is formed is Active area 111.
  • Transistors are formed in the active region 111 through processes such as doping, thereby fabricating semiconductor devices.
  • the trench isolation structure is prepared by introducing an improved trench isolation structure manufacturing method, which can not only reduce the size loss of the active region 111, but also ensure the isolation effect, thereby improving the stability of the semiconductor device.
  • the above-mentioned semiconductor device is a dynamic random access memory (DRAM).
  • the gate of the transistor is prepared in the substrate 110 to form a buried word line 160 of the DRAM.
  • the drain of the transistor is connected to the bit line 170 of the DRAM, the bit line 170 and the word line 160 are criss-crossed, and the source of the transistor is connected to a storage capacitor (not shown in the figure).
  • the DRAM forms a buried word line 160.
  • the depth of the word line 160 is limited by the depth of the trench isolation structure.
  • the trench isolation structure formed in the present application can avoid the compensation film 141 at the bottom of the trench. Residue, that is, the depth of the formed trench isolation structure is not affected by the compensation film 141. Therefore, when the DRAM is prepared by the above method, the influence of the compensation film residue on the depth of the buried word line 160 can be improved.

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Abstract

本申请涉及一种沟槽隔离结构制备方法和半导体器件制备方法，该沟槽隔离结构制备方法包括：在衬底上开设沟槽，并在沟槽的底部填入预设厚度的第一介质层；在第一介质层上方的沟槽侧壁上形成补偿膜；在沟槽内填入第二介质层以形成沟槽隔离结构，补偿膜在填入第二介质层后被全部消耗。

Description

沟槽隔离结构制备方法和半导体器件制备方法
相关申请的交叉引用
本申请要求于2020年4月9日提交中国专利局、申请号为2020102729670、发明名称为“沟槽隔离结构制备方法和半导体器件制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体领域，尤其涉及一种沟槽隔离结构制备方法和半导体器件制备方法。
技术背景
半导体器件通过需要形成沟槽隔离结构以实现相邻有源区的隔离。在具体的工艺制程中，在衬底上开设沟槽后，一般会经过清洗、热氧化、原子层沉积(ALD)等工艺。为了减少有源区尺寸在上述工艺中的损失，一般会引入多晶硅薄膜补偿技术，即在开设沟槽后，在沟槽内壁上形成一层多晶硅薄膜，该引入的多晶硅薄膜会在上述清洗、热氧化、原子层沉积(ALD)等工艺中被消耗掉，从而减小有源区尺寸的损失。
然而，在多晶硅薄膜补偿技术的实际使用中，当沟槽深宽比较高或者沟槽底部比较狭窄时，通常会出现沟槽底部还残留有多晶硅薄膜不能被消耗掉，导致沟槽隔离结构的实际深度减小，隔离效果减弱。
发明内容
根据本申请的各种实施例，提供一种沟槽隔离结构制备方法和半导体器件制备方法。
一种沟槽隔离结构制备方法，包括：
在衬底上开设沟槽，并在所述沟槽的底部填入预设厚度的第一介质层；
在所述第一介质层上方的沟槽侧壁上形成补偿膜；及
在所述沟槽内填入第二介质层以形成所述沟槽隔离结构，所述补偿膜在填入所述第二介质层后被全部消耗。
在其中一个实施例中，所述在所述沟槽的底部填入预设深度的第一介质层，包括：
沉积第一介质材料以填满所述沟槽；
回刻所述第一介质材料，保留沟槽底部的第一介质材料，所保留的所述第一介质材料形成所述第一介质层。
在其中一个实施例中，所述沟槽内被回刻掉的第一介质材料的深度范围为70nm～300nm。
在其中一个实施例中，所述第一介质层为旋涂碳或光刻胶。
在其中一个实施例中，所述在所述第一介质层上方的沟槽侧壁上形成补偿膜，包括：
沉积补偿材料以覆盖所述沟槽的侧壁、所述第一介质层的上表面以及所述衬底的上表面；
回刻所述补偿材料以去除位于所述第一介质层上表面和所述衬底上表面的补偿材料，保留位于所述沟槽侧壁处的补偿材料，所保留的补偿材料形成所述补偿膜。
在其中一个实施例中，所述在所述第一介质层上方的沟槽侧壁上形成补偿膜，包括：
通过外延生长在所述沟槽侧壁生长出外延层以作为所述补偿膜。
在其中一个实施例中，所述补偿膜为多晶硅层。
在其中一个实施例中，所述多晶硅层的厚度范围为
Figure PCTCN2021081784-appb-000001
在其中一个实施例中，在所述第一介质层上方的沟槽侧壁上形成补偿膜之后，以及在所述沟槽内填入第二介质层以形成所述沟槽隔离结构之前，还包括：
去除所述第一介质层。
在其中一个实施例中，所述在所述沟槽内填入第二介质层以形成所述沟槽隔离结构，包括：
通过化学气相沉积工艺或原子层沉积工艺在所述沟槽内填满所述第二介质层以形成所述沟槽隔离结构。
在其中一个实施例中，所述第二介质层包括氧化物、氮化物、氮氧化物中的一种或多种。
一种半导体器件制备方法，包括：
通过上述的沟槽隔离结构制备方法在衬底上制备沟槽隔离结构以定义出有源区；
在所述有源区内制备晶体管结构以形成所述半导体器件。
在其中一个实施例中，所述半导体器件为动态随机存取存储器，所述晶体管的栅极制备于所述衬底内以形成埋入式字线。
上述沟槽隔离结构制备方法，首先在沟槽底部填入预设厚度的第一介质层，然后再在第一介质层上方的沟槽侧壁形成一层补偿膜，由于沟槽底部填入有第一介质层，因此沟槽底部不会形成补偿膜。向沟槽内填入第二介质层形成沟槽隔离结构时，补偿膜会在清洗、沉积工艺中消耗掉。在本申请中，首先，引入薄膜补偿技术，可以减小有源区在清洗、热氧化等工艺中的损耗，同时，在沟槽底部不形成补偿膜，可以避免出现沟槽底部狭窄区域的补偿膜难以被消耗掉而出现残余的现象，即，通过上述沟槽隔离结构制备方法，既能减小有源区的尺寸损耗，又能保证沟槽隔离结构的隔离效果。
附图说明
通过附图中所示的本申请的优选实施例的更具体说明，本申请的上述及其它目的、特征和优势将变得更加清晰。在全部附图中相同的附图标记指示相同的部分，且并未刻意按实际尺寸等比例缩放绘制附图，重点在于示出本申请的主旨。
图1a和图1b为传统技术中形成沟槽隔离结构制备方法相关步骤对应的 结构示意图；
图2为一实施例的沟槽隔离结构制备方法的步骤流程图；
图3a至图3f为一实施例的沟槽隔离结构制备方法相关步骤对应的结构示意图；
图4为一实施例的沟槽隔离结构定义出有源区后的俯视图；
图5为一实施例动态随机存取存储器的结构示意图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的具体实施的限制。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体地实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在传统技术中，如图1a和图1b所示，在衬底110＇上开设沟槽后，使用多晶硅薄膜补偿技术，在沟槽内壁以及衬底110＇上表面形成一层多晶硅薄膜130＇。然后采用化学气相沉积工艺或者原子沉积工艺(ALD)，在沟槽内填满介质层150＇，形成沟槽隔离结构。在填充介质层150＇之前，还可能存在清洗工艺。在此过程中，多晶硅薄膜130＇会在清洗、热氧化、原子层沉积(ALD)等工艺中被消耗掉，从而减少有源区的损失。然而，如图1b所示，沟槽底部的狭窄区域通常还残留有多晶硅薄膜130＇不能被消耗，从而导致沟槽隔离结构深度变浅，使得隔离效果变弱。
本申请涉及一种沟槽隔离结构制备方法，该沟槽隔离结构制备方法至少 包括以下几个步骤：
在衬底上开设沟槽，并在所述沟槽的底部填入预设厚度的第一介质层。
在所述第一介质层上方的沟槽侧壁上形成补偿膜。
在所述沟槽内填入第二介质层以形成所述沟槽隔离结构，所述补偿膜在填入所述第二介质层的过程中被全部消耗。
需要说明的是，第一介质层的预设厚度可以根据补偿膜的厚度设定，例如，可以先获取传统技术中沟槽底部残留的补偿膜的填充高度，第一介质层的预设厚度大于或等于传统技术中所残留的补偿膜的填充高度。在沟槽底部的狭窄区域不形成补偿膜，就可以避免出现在沟槽底部的狭窄区域残留补偿膜的问题。
另外，补偿膜在填入第二介质层后被全部消耗，指的是在形成补偿膜后的清洗过程以及在第二介质层的沉积过程中，补偿膜被消耗，具体可以是被物理去除，也可以是发生化学反应转变成介质结构，且在完成第二介质层的填充后，补偿膜也被完全消耗。因此，补偿膜的厚度设计与具体的工序有关，需保证在补偿膜会在后续的清洗和沉积工艺中被全部消耗完。
上述沟槽隔离结构制备方法，首先在沟槽底部填入预设厚度的第一介质层，然后再在第一介质层上方的沟槽侧壁形成一层补偿膜，由于沟槽底部填入有第一介质层，因此沟槽底部不会形成补偿膜。向沟槽内填入第二介质层形成沟槽隔离结构时，补偿膜会在清洗、沉积工艺中消耗掉。在本申请中，首先，引入薄膜补偿技术，可以减小有源区在清洗、热氧化等工艺中的损耗，同时，在沟槽底部不形成补偿膜，可以避免出现沟槽底部狭窄区域的补偿膜难以被消耗掉而出现残余的现象，即，通过上述沟槽隔离结构制备方法，既能减小有源区的尺寸损耗，又能保证沟槽隔离结构的隔离效果。
以下，以具体的实施例对上述沟槽隔离结构制备方法进行详细介绍。
如图2所示，本申请中，沟槽隔离结构制备方法包括以下几个步骤：
步骤S100：在衬底上开设沟槽，并在所述沟槽的底部填入预设厚度的第一介质层。
结合图3b所示，在衬底110上开设沟槽，在沟槽底部填入预设厚度的第一介质层131。
其中，衬底110可以为硅晶片、锗晶片、绝缘体上硅(SOI)晶片、绝缘体上锗(GOI)晶片、硅锗晶片和形成有外延层的基板中的一种。
具体的，在衬底110上开设沟槽，可以先在衬底110上形成掩膜层120，通过掩膜层120定义出刻蚀图案，然后通过刻蚀工艺在衬底110上刻蚀出沟槽。掩膜层120为硬掩膜，具体可以选用氮化硅或氧化硅。具体的，可利用自对准多重曝光工艺(SAQP)形成上述沟槽，通过多重曝光技术，可以获得小尺寸的结构。通常，沟槽呈上宽下窄的倒梯形形状。其中，沟槽的开口宽度可以根据需要设定，沟槽的开口宽度可以相同，也可以不同。通过，当沟槽的开口宽度不同时，沟槽的开口宽度越大，其刻蚀深度越深，也即，具有较宽开口宽度的沟槽的刻蚀深度比具有较窄开口宽度的沟槽的刻蚀深度要深，此时，我们只需要保证最浅的沟槽中填入的第一介质层131的预设厚度大于传统技术中残留的补偿膜的填充高度即可。
在一具体实施例中，可以通过以下子步骤在沟槽的底部填入预设厚度的第一介质层131：
步骤S110：沉积第一介质材料以填满所述沟槽。
步骤S120：回刻所述第一介质材料至预设深度，保留沟槽底部的第一介质材料，所保留的所述第一介质材料形成所述第一介质层。
结合图3a和图3b所示，首先，沉积第一介质材料130以填满沟槽，具体的，第一介质材料130填满沟槽并溢出沟槽一定高度以保证沟槽内被第一介质材料130填满。然后对第一介质材料130进行回刻至预设深度，保留沟槽底部预设厚度的第一介质材料130，所保留的第一介质材料130即形成具有预设厚度的第一介质层131。在一实施例中，在对第一介质材料130进行回刻之前，还可通过化学机械研磨工艺对第一介质材料130的表面进行平坦化处理，然后再对第一介质材料130进行刻蚀至预设深度。回刻所采用的刻蚀工艺可为干法刻蚀，具体可为等离子体刻蚀。具体的，沟槽内被回刻掉的 第一介质材料130的深度范围为70nm～300nm。
步骤S200：在所述第一介质层上方的沟槽侧壁上形成补偿膜。
如图3d所示，在第一介质层131上方的沟槽侧壁上形成补偿膜141，补偿膜141厚度较薄，其贴附于沟槽侧壁上且并未填满沟槽。
其中，可以通过多种方式形成上述补偿膜141。
例如，在一具体的实施例中，可以通过以下子步骤在第一介质层131上方的沟槽侧壁上形成补偿膜141：
步骤S211：沉积补偿材料以覆盖所述沟槽的侧壁、所述第一介质层的上表面以及所述衬底的上表面。
步骤S212：回刻所述补偿材料以去除位于所述第一介质层上表面和所述衬底上表面的补偿材料，保留位于所述沟槽侧壁处的补偿材料，所保留的补偿材料形成所述补偿膜。
结合图3c和图3d所示，首先，通过沉积工艺沉积一层补偿材料140，补偿材料140覆盖沟槽的侧壁、第一介质层131的上表面以及衬底110的上表面，当衬底110上的掩膜层120未被去除时，补偿材料140覆盖衬底110的上表面，实际是覆盖于掩膜层120上。在沉积补偿材料140后，再对补偿材料140进行回刻，沿垂直于衬底110上表面的方向对补偿材料140减薄，以去除位于第一介质层131上表面和衬底110上表面的补偿材料140，保留位于沟槽侧壁处的补偿材料140，所保留的补偿材料140则形成上述补偿膜141。具体的，该沉积工艺具体可为化学气相沉积工艺或原子层沉积工艺。
例如，在另一实施例中，还可通过以下方式在第一介质层131上方的沟槽侧壁上形成补偿膜141：通过外延生长在所述沟槽侧壁生长出外延层以作为所述补偿膜141。此时，由于沟槽第一具有第一介质层131，沉积上表面具有掩膜层120，第一介质层131和掩膜层120上均不会出现外延生长，因此，仅在沟槽暴露的侧壁上外延层，所生长的外延层直接作为补偿膜141。
其中，上述补偿膜141可以为在清洗或沉积工艺中被消耗掉的薄膜。补偿膜141可与衬底110的材质相同。具体的，该补偿膜141可为硅、锗等半 导体材料，例如，补偿膜141为多晶硅层，该多晶硅层的厚度范围为
Figure PCTCN2021081784-appb-000002
在一实施例中，在所述第一介质层131上方的沟槽侧壁上形成补偿膜141之后，还包括步骤：去除所述第一介质层131。
如图3e所示，去除沟槽底部的第一介质层131，此时，沟槽内仅剩余形成于沟槽侧壁上的补偿膜141，且补偿膜141未延伸至沟槽底部。
步骤S300：在所述沟槽内填入第二介质层以形成所述沟槽隔离结构，所述补偿膜在填入所述第二介质层后被全部消耗。
如图3f所示，在沟槽内填入第二介质层150，在衬底110上形成沟槽隔离，此时，补偿膜141在填入第二介质层150后被完全消耗。具体的，在沟槽内填入第二介质层150，可以通过化学气相沉积工艺(CVD)、物理气相沉积工艺(PVD)、原子层沉积工艺(ALD)或旋涂绝缘介质层工艺(SOD)中的任一种工艺在所述沟槽内填满所述第二介质层150，当然，也可以使用其他合适的工艺。其中，化学气相沉积工艺具体可以包括等离子体增强化学气相沉积(PECVD)、高密度等离子体化学气相沉积(HDPCVD)、火焰化学气相沉积(FCVP)、常压化学气相沉积(APCVD)或低压化学气相沉积(LPACVD)。具体的，第二介质层150包括低K介质中的一种或多种材料，例如，第二介质层150可以包括氧化物或氮化物或氮氧化物，也可以包括氧化物和氮化物的复合结构层如氧化硅-氮化硅-氧化硅(ONO结构)。
需要说明的是，补偿膜141被消耗，可以是在清洗过程中被物理去除而减薄，也可以是被热氧化而转变为氧化物以作为介质结构填充于沟槽内。
在一实施例中，当在填入第二介质层150之前，第一介质层131被去除，则第二介质层150填充于整个沟槽内。在本实施例中，若去除第一介质层131，第一介质层131则选择高选择比易去除的材料，例如旋涂碳(SOC)、无定型碳层(ACL)、光刻胶等光阻材料等。
在其他实施例中，也可以不去除第一介质层131，沟槽底部填入第一介质层131，沟槽顶部填入第二介质层150，即第一介质层131和第二介质层150均填于沟槽内，此时，第一介质层131与第二介质层150性质相同，选 择低K介质中的一种或多种材料构成，例如，第二介质层150可以为氧化物或氮化物，也可以是氧化物和氮化物的复合结构层。
上述沟槽隔离结构制备方法，首先在沟槽底部填入预设厚度的第一介质层131，然后再在第一介质层131上方的沟槽侧壁形成一层补偿膜141，由于沟槽底部填入有第一介质层131，因此沟槽底部不会形成补偿膜141。向沟槽内填入第二介质层150形成沟槽隔离结构时，补偿膜141会在清洗、沉积工艺中消耗掉。在本申请中，首先，引入薄膜补偿技术，可以减小有源区111在清洗、热氧化等工艺中的损耗，同时，在沟槽底部不形成补偿膜141，可以避免出现沟槽底部狭窄区域的补偿膜141难以被消耗掉而出现残余的现象，即，通过上述沟槽隔离结构制备方法，既能减小有源区111的尺寸损耗，又能保证沟槽隔离结构的隔离效果。
本申请还涉及一种半导体器件制备方法，该半导体器件制备方法包括：
通过上述沟槽隔离结构制备方法在衬底上制备沟槽隔离结构以定义出有源区区域；
在所述有源区内制备晶体管结构以形成所述半导体器件。
结合图3f和图4所示，其中，图4为在衬底110上通过沟槽隔离结构定义出有源区111的俯视图，图3f为沿图4中AA＇剖面线的侧剖图。通过上述任一实施例中的沟槽隔离结构制备方法在衬底110上制备出沟槽隔离结构，通过沟槽隔离结构定义出有源区111，即形成沟槽隔离结构的衬底110区域为有源区111。在有源区111内通过掺杂等工艺形成晶体管，从而制备出半导体器件。
上述半导体器件制备方法，通过引入改进的沟槽隔离结构制备方法制备沟槽隔离结构，既能够减少有源区111尺寸的损耗，又能保证隔离效果，从而提高了半导体器件的稳定性。
在一具体的实施例中，上述半导体器件为动态随机存取存储器(DRAM)，结合图4和图5所示，晶体管的栅极制备于衬底110内以形成DRAM的埋入式字线160，晶体管的漏极与DRAM的位线170连接，位线170和字线160 纵横交错，晶体管的源极则与存储电容(图中未示出)连接。在本实施例中，DRAM形成埋入式字线160，该字线160的深度受限于沟槽隔离结构的深度，由于本申请所形成的沟槽隔离结构可以避免沟槽底部补偿膜141的残留，即所形成的沟槽隔离结构深度不受补偿膜141的影响，因此，通过上述方法制备DRAM时，可以改善补偿膜残留对埋入式字线160深度的影响。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (11)

  1. 一种沟槽隔离结构制备方法，包括：
    在衬底上开设沟槽，并在所述沟槽的底部填入预设厚度的第一介质层；
    在所述第一介质层上方的沟槽侧壁上形成补偿膜；
    在所述沟槽内填入第二介质层以形成所述沟槽隔离结构，所述补偿膜在填入所述第二介质层后被全部消耗。
  2. 如权利要求1所述的沟槽隔离结构制备方法，其中所述在所述沟槽的底部填入预设深度的第一介质层，包括：
    沉积第一介质材料以填满所述沟槽；
    回刻所述第一介质材料，保留沟槽底部的第一介质材料，所保留的所述第一介质材料形成所述第一介质层。
  3. 如权利要求2所述的沟槽隔离结构制备方法，其中所述沟槽内被回刻掉的第一介质材料的深度范围为70nm～300nm。
  4. 如权利要求1所述的沟槽隔离结构制备方法，其中所述在所述第一介质层上方的沟槽侧壁上形成补偿膜，包括：
    沉积补偿材料以覆盖所述沟槽的侧壁、所述第一介质层的上表面以及所述衬底的上表面；
    回刻所述补偿材料以去除位于所述第一介质层上表面和所述衬底上表面的补偿材料，保留位于所述沟槽侧壁处的补偿材料，所保留的补偿材料形成所述补偿膜。
  5. 如权利要求1所述的沟槽隔离结构制备方法，其中所述补偿膜为多晶硅层。
  6. 如权利要求5所述的沟槽隔离结构制备方法，其中所述多晶硅层的厚度范围为
    Figure PCTCN2021081784-appb-100001
  7. 如权利要求1所述的沟槽隔离结构制备方法，其中在所述第一介质层上方的沟槽侧壁上形成补偿膜之后，以及在所述沟槽内填入第二介质层以形成所述沟槽隔离结构之前，还包括：
    去除所述第一介质层。
  8. 如权利要求1所述的沟槽隔离结构制备方法，其中在所述沟槽内填入第二介质层所使用的工艺包括化学气相沉积、物理气相沉积、原子层沉积或旋涂绝缘介质层工艺。
  9. 如权利要求1所述的沟槽隔离结构制备方法，其中所述第二介质层包括氧化物、氮化物、氮氧化物中的一种或几种。
  10. 一种半导体器件制备方法，包括：
    通过权利要求1至9任一项所述的沟槽隔离结构制备方法在衬底上制备沟槽隔离结构以定义出有源区；
    在所述有源区内制备晶体管结构以形成所述半导体器件。
  11. 如权利要求10所述的半导体器件制备方法，其中所述半导体器件为动态随机存取存储器，所述晶体管的栅极制备于所述衬底内以形成埋入式字线。
PCT/CN2021/081784 2020-04-09 2021-03-19 沟槽隔离结构制备方法和半导体器件制备方法 WO2021203945A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050090047A1 (en) * 2000-12-20 2005-04-28 Actel Corporation, A California Corporation. Method of making a MOS transistor having improved total radiation-induced leakage current
CN101789389A (zh) * 2009-01-23 2010-07-28 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离结构的制造方法
CN102437083A (zh) * 2011-08-17 2012-05-02 上海华力微电子有限公司 一种减小高深宽比工艺填充浅沟隔离槽关键尺寸损失的方法
CN110880472A (zh) * 2018-09-06 2020-03-13 长鑫存储技术有限公司 具有浅沟槽隔离结构的半导体器件及其制备方法
CN110890313A (zh) * 2018-09-07 2020-03-17 长鑫存储技术有限公司 浅沟槽隔离结构及其制备方法
CN210272358U (zh) * 2019-08-30 2020-04-07 长鑫存储技术有限公司 半导体结构及动态随机存储器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4665007A (en) * 1985-08-19 1987-05-12 International Business Machines Corporation Planarization process for organic filling of deep trenches
US6090661A (en) * 1998-03-19 2000-07-18 Lsi Logic Corporation Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls
US20030054608A1 (en) * 2001-09-17 2003-03-20 Vanguard International Semiconductor Corporation Method for forming shallow trench isolation in semiconductor device
TW200847337A (en) * 2007-05-16 2008-12-01 Promos Technologies Inc Method for preparing a shallow trench isolation
CN104779195A (zh) * 2015-04-15 2015-07-15 上海华力微电子有限公司 一种浅沟槽隔离结构的制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050090047A1 (en) * 2000-12-20 2005-04-28 Actel Corporation, A California Corporation. Method of making a MOS transistor having improved total radiation-induced leakage current
CN101789389A (zh) * 2009-01-23 2010-07-28 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离结构的制造方法
CN102437083A (zh) * 2011-08-17 2012-05-02 上海华力微电子有限公司 一种减小高深宽比工艺填充浅沟隔离槽关键尺寸损失的方法
CN110880472A (zh) * 2018-09-06 2020-03-13 长鑫存储技术有限公司 具有浅沟槽隔离结构的半导体器件及其制备方法
CN110890313A (zh) * 2018-09-07 2020-03-17 长鑫存储技术有限公司 浅沟槽隔离结构及其制备方法
CN210272358U (zh) * 2019-08-30 2020-04-07 长鑫存储技术有限公司 半导体结构及动态随机存储器

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