WO2021199431A1 - 高周波増幅器、無線通信装置及びレーダ装置 - Google Patents

高周波増幅器、無線通信装置及びレーダ装置 Download PDF

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WO2021199431A1
WO2021199431A1 PCT/JP2020/015343 JP2020015343W WO2021199431A1 WO 2021199431 A1 WO2021199431 A1 WO 2021199431A1 JP 2020015343 W JP2020015343 W JP 2020015343W WO 2021199431 A1 WO2021199431 A1 WO 2021199431A1
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gate
fingers
transistor
source
grounded
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English (en)
French (fr)
Japanese (ja)
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純 神岡
新庄　真太郎
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to EP20928877.8A priority Critical patent/EP4113832B1/en
Priority to JP2022511484A priority patent/JP7195480B2/ja
Priority to PCT/JP2020/015343 priority patent/WO2021199431A1/ja
Publication of WO2021199431A1 publication Critical patent/WO2021199431A1/ja
Priority to US17/882,105 priority patent/US12456954B2/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H10D84/813—Combinations of field-effect devices and capacitor only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/483—Interconnections over air gaps, e.g. air bridges
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Definitions

  • the present disclosure relates to a high-frequency amplifier for amplifying a signal, a wireless communication device including a high-frequency amplifier, and a radar device including a high-frequency amplifier.
  • Wireless communication devices and radar devices may be equipped with a high frequency amplifier that amplifies high frequency signals.
  • the high-frequency amplifier includes, for example, a source-grounded multi-finger field effect transistor (FET), and the source-grounded FET amplifies a high-frequency signal.
  • FET source-grounded multi-finger field effect transistor
  • the output power of the high-frequency amplifier increases as the voltage applied to the drain of the FET increases. However, since the FET has a withstand voltage, the drain voltage of the FET is limited.
  • Patent Document 1 discloses a high-frequency amplifier in which a drain of a grounded FET and a source of a grounded gate FET whose gate is grounded via a capacitor are connected.
  • a plurality of gate fingers included in the gate-grounded FET are bundled by a gate bus bar.
  • One end of the capacitor is connected to the gate bus bar, and the other end of the capacitor is grounded.
  • the drain of the source grounded FET is twice as much as that of the high frequency amplifier having only one source grounded FET. There is a possibility that a voltage can be applied.
  • the parasitic component between the respective gate fingers and the grounded gate capacitance is obtained. Are different from each other. Since the parasitic components between each gate finger and the gate ground capacitance are different from each other, an imbalance occurs in the amplification operation of each gate finger. Due to the imbalance in the amplification operation of each gate finger, the combined loss of the high frequency signal after amplification by the plurality of gate fingers increases, so that there is a problem that the output power decreases.
  • the present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to obtain a high-frequency amplifier capable of suppressing an imbalance in amplification operations in a plurality of gate fingers.
  • the high-frequency amplifier has a plurality of gate fingers, a plurality of drain fingers, and a plurality of source fingers, amplifies a signal to be amplified given to each gate finger, and after amplification from each drain finger. It has a source grounded transistor that outputs a signal, a plurality of source fingers connected to a plurality of drain fingers of the source grounded transistor, a plurality of drain fingers, and a plurality of gate fingers, and each drain finger of the source grounded transistor has.
  • a gate grounded transistor that amplifies the amplified signal output from the gate, a gate bus bar that is connected to a plurality of gate fingers of the gate grounded transistor, and a plurality of gate bus bars that are connected at one end and grounded at the other end.
  • a plurality of capacitors are arranged at positions where the impedances in anticipation of the capacitor side are aligned with each other from each gate finger of the grounded gate transistor.
  • the high frequency amplifier is configured so that a plurality of capacitors are arranged at positions where the impedances expected from the capacitor side are aligned with each other from each gate finger of the grounded gate transistor. Therefore, the high frequency amplifier according to the present disclosure can suppress the imbalance of the amplification operation in the plurality of gate fingers.
  • FIG. 1 It is a block diagram which shows the wireless communication apparatus which includes the high frequency amplifier 1 which concerns on Embodiment 1.
  • FIG. It is a block diagram which shows the radar apparatus which includes the high frequency amplifier 1 which concerns on Embodiment 1.
  • FIG. It is a block diagram which shows the high frequency amplifier 1 which concerns on Embodiment 1.
  • FIG. It is an equivalent circuit diagram which shows the high frequency amplifier 1 which concerns on Embodiment 1.
  • It is a block diagram which shows the other high frequency amplifier 1 which concerns on Embodiment 1.
  • FIG. It is a block diagram which shows the other high frequency amplifier 1 which concerns on Embodiment 1.
  • FIG. It is a block diagram which shows the other high frequency amplifier 1 which concerns on Embodiment 1.
  • FIG. 1 It is a block diagram which shows the other high frequency amplifier 1 which concerns on Embodiment 1.
  • FIG. It is sectional drawing of the part from A 1 to A 2 of FIG. It is a block diagram which shows the high frequency amplifier 1 which concerns on Embodiment 2.
  • FIG. It is an equivalent circuit diagram which shows the high frequency amplifier 1 which concerns on Embodiment 2.
  • FIG. It is a block diagram which shows the other high frequency amplifier 1 which concerns on Embodiment 2.
  • FIG. 1 is a configuration diagram showing a wireless communication device including the high frequency amplifier 1 according to the first embodiment.
  • the high-frequency amplifier 1 included in the wireless communication device shown in FIG. 1 amplifies the high-frequency signal as the signal to be amplified, and outputs the amplified high-frequency signal to the transmitting antenna 2.
  • the transmitting antenna 2 radiates radio waves related to high-frequency signals output from the high-frequency amplifier 1 into space.
  • FIG. 2 is a configuration diagram showing a radar device including the high frequency amplifier 1 according to the first embodiment.
  • the high-frequency amplifier 1 included in the radar device shown in FIG. 2 amplifies the radar signal as the signal to be amplified, and outputs the amplified radar signal to the transmitting antenna 3.
  • the transmitting antenna 3 radiates radio waves related to the radar signal output from the high frequency amplifier 1 into space.
  • FIG. 3 is a configuration diagram showing a high frequency amplifier 1 according to the first embodiment.
  • FIG. 4 is an equivalent circuit diagram showing the high frequency amplifier 1 according to the first embodiment.
  • the signal input terminal 11 is a terminal to which a high frequency signal, a radar signal, or a received signal is given as a signal to be amplified from the outside.
  • a high frequency signal is given to the signal input terminal 11.
  • an input side matching circuit is connected to the signal input terminal 11.
  • the grounded source transistor 12 has a gate electrode 12a, a drain electrode 12b, and a source electrode 12c.
  • the gate electrode 12a of the source grounded transistor 12 is connected to the signal input terminal 11.
  • the drain electrode 12b of the source grounded transistor 12 is connected to the source electrode 32a of the gate grounded transistor 32 described later.
  • the source electrode 12c of the source grounded transistor 12 is connected to the ground.
  • the source ground transistor 12 amplifies the high frequency signal given to the gate electrode 12a, and outputs the amplified high frequency signal from the drain electrode 12b to the source electrode 32a of the gate ground transistor 32.
  • the source grounded transistor 12 for example, a GaN multi-finger transistor formed by GaN (Gallium Nitride) on an MMIC (Monolithic Microwave Integrated Circuit) is used.
  • the gate electrode 12a has a gate bus bar 13 and gate fingers 14-1 to 14-8.
  • the gate electrode 12a has eight gate fingers 14-1 to 14-8.
  • the gate electrode 12a may have a plurality of gate fingers 14, and is not limited to those having eight gate fingers 14-1 to 14-8.
  • the gate bus bar 13 is connected to the signal input terminal 11.
  • Each end of each of the gate fingers 14-1 to 14-8 is connected to the gate bus bar 13.
  • the drain electrode 12b has drain fingers 15-1 to 15-4.
  • the drain finger 15-1 is arranged between the gate finger 14-1 and the gate finger 14-2 in parallel with the gate fingers 14-1 and 14-2, respectively.
  • the drain finger 15-2 is arranged between the gate finger 14-3 and the gate finger 14-4 in parallel with the gate finger 14-3 and 14-4, respectively.
  • the drain finger 15-3 is arranged between the gate finger 14-5 and the gate finger 14-6 in parallel with each of the gate finger 14-5 and 14-6.
  • the drain finger 15-4 is arranged between the gate finger 14-7 and the gate finger 14-8 in parallel with the gate finger 14-7 and 14-8, respectively.
  • the source electrode 12c has source fingers 16-1 to 16-5.
  • the source finger 16-1 is arranged on the left side of the gate finger 14-1 in FIG. 3 in parallel with the gate finger 14-1.
  • the source finger 16-2 is arranged between the gate finger 14-2 and the gate finger 14-3 in parallel with the gate finger 14-2 and 14-3, respectively.
  • the source finger 16-3 is arranged between the gate finger 14-4 and the gate finger 14-5 in parallel with the gate finger 14-4 and 14-5, respectively.
  • the source fingers 16-4 are arranged between the gate fingers 14-6 and the gate fingers 14-7 in parallel with the gate fingers 14-6 and 14-7, respectively.
  • the source finger 16-5 is arranged on the right side of the gate finger 14-8 in FIG. 3 in parallel with the gate finger 14-8.
  • One end of the via hole 17-n is connected to the source finger 16-n, and the other end of the via hole 17-n is connected to the ground.
  • the bus bar 18 is connected to the drain fingers 15-1 to 15-4 included in the source grounded transistor 12, and is also connected to the source fingers 33-1 to 33-8 included in the gate grounded transistor 32.
  • the gate terminal 31 has gate terminals 31-1 and 31-2.
  • the gate terminal 31 is a terminal to which a gate bias is applied.
  • Each of the gate terminals 31-1 and 31-2 is connected to a gate bus bar 38, which will be described later.
  • the grounded gate transistor 32 has a source electrode 32a, a drain electrode 32b, and a gate electrode 32c.
  • the source electrode 32a of the gate grounded transistor 32 is connected to the drain electrode 12b of the source grounded transistor 12.
  • the drain electrode 32b of the gate grounded transistor 32 is connected to a signal output terminal 37 described later.
  • the gate electrode 32c of the gate grounded transistor 32 is connected to the gate terminal 31 and the capacitor 39.
  • the capacitor 39 is any of the capacitors 39-1 to 39-8 described later.
  • the gate ground transistor 32 amplifies the high frequency signal output from the drain electrode 12b of the source ground transistor 12, and outputs the amplified high frequency signal from the drain electrode 32b to the signal output terminal 37.
  • the grounded gate transistor 32 for example, a GaN multi-finger transistor formed of GaN on an MMIC is used.
  • the source electrode 32a has source fingers 33-1 to 33-8. Each end of the source fingers 33-1 to 33-8 is connected to the bus bar 18.
  • the drain electrode 32b has drain fingers 34-1 to 34-4. Each end of each of the drain fingers 34-1 to 34-4 is connected to a drain bus bar 36 described later.
  • the drain finger 34-1 is arranged between the gate finger 35-1 described later and the gate finger 35-2 described later in parallel with the gate fingers 35-1 and 35-2, respectively.
  • the drain finger 34-2 is arranged between the gate finger 35-3 described later and the gate finger 35-4 described later in parallel with the gate fingers 35-3 and 35-4, respectively.
  • the drain finger 34-3 is arranged between the gate finger 35-5 described later and the gate finger 35-6 described later in parallel with each of the gate fingers 35-5 and 35-6.
  • the drain finger 34-4 is arranged between the gate finger 35-7 described later and the gate finger 35-8 described later in parallel with the gate fingers 35-7 and 35-8, respectively.
  • the gate electrode 32c has gate fingers 35-1 to 35-8. Each end of each of the gate fingers 35-1 to 35-8 is connected to the gate bus bar 38.
  • the gate finger 35-1 is arranged between the source finger 33-1 and the drain finger 34-1 in parallel with each of the source finger 33-1 and the drain finger 34-1.
  • the gate finger 35-2 is arranged between the drain finger 34-1 and the source finger 33-2 in parallel with the drain finger 34-1 and the source finger 33-2, respectively.
  • the gate finger 35-3 is arranged between the source finger 33-3 and the drain finger 34-2 in parallel with the source finger 33-3 and the drain finger 34-2, respectively.
  • the gate finger 35-4 is arranged between the drain finger 34-2 and the source finger 33-4 in parallel with each of the drain finger 34-2 and the source finger 33-4.
  • the gate finger 35-5 is arranged between the source finger 33-5 and the drain finger 34-3 in parallel with the source finger 33-5 and the drain finger 34-3, respectively.
  • the gate finger 35-6 is arranged between the drain finger 34-3 and the source finger 33-6 in parallel with the drain finger 34-3 and the source finger 33-6, respectively.
  • the gate finger 35-7 is arranged between the source finger 33-7 and the drain finger 34-4 in parallel with the source finger 33-7 and the drain finger 34-4, respectively.
  • the gate finger 35-8 is arranged between the drain finger 34-4 and the source finger 33-8 in parallel with the drain finger 34-4 and the source finger 33-8, respectively.
  • the drain bus bar 36 is connected to each of the drain fingers 34-1 to 34-4 and the signal output terminal 37.
  • the signal output terminal 37 is connected to the drain bus bar 36.
  • the signal output terminal 37 is a terminal for outputting a high frequency signal after amplification by the grounded gate transistor 32 to the outside.
  • an output side matching circuit is connected to the signal output terminal 37.
  • the gate bus bar 38 is connected to the gate terminals 31-1 and 31-2, the gate fingers 35-1 to 35-8, and the capacitors 39-1 to 39-8 described later, respectively.
  • Each end of the capacitors 39-1 to 39-8 is connected to the gate bus bar 38.
  • the other ends of the capacitors 39-1 to 39-8 are connected to the ground.
  • the capacitor 39-1 is provided on the upper layer of the source finger 16-1.
  • the capacitor 39-2 is provided on the upper layer of the source finger 16-2, and the capacitor 39-3 is provided on the upper layer of the source finger 16-2.
  • the capacitor 39-4 is provided on the upper layer of the source finger 16-3, and the capacitor 39-5 is provided on the upper layer of the source finger 16-3.
  • the capacitor 39-6 is provided on the upper layer of the source finger 16-4, and the capacitor 39-6 is provided on the upper layer of the source finger 16-4.
  • the capacitors 39-8 are provided on the upper layer of the source fingers 16-5.
  • the impedance that is expected on the capacitor 39 side is the combined impedance when all of the capacitors 39-1 to 39-8 are expected. That is, from each gate finger 35-m of the gate ground transistor 32, one capacitor 39 related to each gate finger 35-m of the gate ground transistor 32 among the capacitors 39-1 to 39-8.
  • Capacitors 39-1 to 39-8 are arranged at positions where the distances Lm to ⁇ m are aligned with each other.
  • One of the related capacitors 39-m is the capacitor among the capacitors 39-1 to 39-8 that has a corresponding relationship with the gate finger 35-m, that is, the capacitor closest to the gate finger 35-m. That is, among the capacitors 39-1 to 39-8, the capacitor related to the gate finger 35-m is the capacitor 39-m.
  • the impedance expected on the capacitor 39 side includes the impedance of the capacitor 39.
  • a DC drain voltage is applied to the signal output terminal 37 to enable the operation of both the source grounded transistor 12 and the gate grounded transistor 32. Further, a DC gate voltage is applied to the signal input terminal 11 in order to enable the operation of the source grounded transistor 12. Further, in order to enable the operation of the grounded gate transistor 32, a DC gate voltage is applied to the gate terminal 31 of either the gate terminal 31-1 or the gate terminal 31-2.
  • the high-frequency signal When a high-frequency signal is given to the signal input terminal 11 as the signal to be amplified, the high-frequency signal is distributed to the gate fingers 14-1 to 14-8 by the gate bus bar 13.
  • the source grounded transistor 12 amplifies the respective high frequency signals when the respective high frequency signals after distribution by the gate bus bar 13 are given to the gate fingers 14-1 to 14-8. Then, the grounded source transistor 12 outputs the high-frequency signals after each amplification to the drain fingers 15-1 to 15-4.
  • the amplified high-frequency signals output to the drain fingers 15-1 to 15-4 are distributed to the source fingers 33-1 to 33-8 by the bus bar 18.
  • the gate grounded transistor 32 amplifies the respective high frequency signals when the respective high frequency signals after distribution by the bus bar 18 are given to the source fingers 33-1 to 33-8. Then, the grounded gate transistor 32 outputs the high-frequency signals after each amplification to the drain fingers 34-1 to 34-4. The amplified high-frequency signals output to the drain fingers 34-1 to 34-4 are combined by the drain bus bar 36, and the combined high-frequency signals are output to the signal output terminal 37.
  • the source grounded transistor 12 and the gate grounded transistor 32 ideally operate in the same phase and with the same amplitude.
  • the high frequency amplifier 1 When the grounded source transistor 12 and the grounded gate transistor 32 operate in the same phase and with the same amplitude, the high frequency amplifier 1 has twice the drain voltage of the signal output terminal 37 as compared with the high frequency amplifier having only one grounded source transistor. Can be applied to. Therefore, the high-frequency amplifier 1 when operating in phase and with the same amplitude can obtain twice as much output power as a high-frequency amplifier having only one grounded source transistor.
  • the arrows indicate the parts that make up the parasitic impedance between the gate finger 35-m and the capacitor 39-m.
  • the impedances expected from the respective gate fingers 35-m to the capacitor 39-m are substantially equal.
  • the impedances expected from the respective gate fingers 35-m to the capacitor 39-m may be deviated from each other within a range where there is no practical problem. If each impedance has a phase shift of, for example, ⁇ 2 ° or less with respect to the operating frequency, there is no problem in practical use.
  • FIG. 6 is a configuration diagram showing another high frequency amplifier 1 according to the first embodiment.
  • the capacitor 39-11 is a capacitor in which the capacitor 39-2 and the capacitor 39-3 are put together, and is related to each of the gate finger 35-2 and the gate finger 35-3.
  • the capacitor 39-12 is a capacitor in which the capacitor 39-4 and the capacitor 39-5 are put together, and is related to each of the gate finger 35-4 and the gate finger 35-5.
  • the capacitor 39-13 is a capacitor in which the capacitor 39-6 and the capacitor 39-7 are put together, and is related to each of the gate finger 35-6 and the gate finger 35-7. If the capacitance of the capacitor 39-11 is C11, the capacitance of the capacitor 39-12 is C12, and the capacitance of the capacitor 39-13 is C13, the capacitances C1 and C8 of the capacitors 39-1, 39-8 are given by the following equation (1). ), It is half of the capacities C11, C12, and C13.
  • the capacitances C1 and C8 of the capacitors 39-1 and 39-8 are half of the capacitors C11, C12 and C13.
  • the capacitances C1 and C8 of the capacitors 39-1 and 39-8 are not limited to those having half the capacitances C11, C12 and C13.
  • the high frequency signals given from the drain fingers 15-1 to 15-4 of the source ground transistor 12 to the source fingers 33-1 to 33-8 of the gate ground transistor 32 may not be completely in phase. Further, the impedances of the gate fingers 35-1 to 35-8 of the grounded gate transistor 32 in anticipation of the signal output terminals 37 may not be equal.
  • the imbalance of the respective amplification operations in the gate fingers 35-1 to 35-8 is eliminated.
  • the capacitances of the capacitors 39-1, 39-8 are large. If C1 and C8 are made smaller than half of the capacitances C11, C12 and C13, the imbalance is eliminated.
  • the high frequency amplifier 1 has gate fingers 14-1 to 14-8, drain fingers 15-1 to 15-4, and source fingers 16-1 to 16-5, and the respective gate fingers.
  • the source grounding transistor 12 that outputs a signal, the source fingers 33-1 to 33-8 connected to the drain fingers 15-1 to 15-4 of the source grounding transistor 12, the drain fingers 34-1 to 34-4, and the drain fingers 34-1 to 34-4. It has gate fingers 35-1 to 35-8, and includes a gate ground transistor 32 that amplifies the amplified signal output from each drain finger 15-j of the source ground transistor 12.
  • the high frequency amplifier 1 has a gate bus bar 38 connected to the gate fingers 35-1 to 35-8 included in the gate ground transistor 32, and a capacitor 39 having one end connected to the gate bus bar 38 and the other end grounded. It has -1 to 39-8. Then, in the high frequency amplifier 1, the capacitors 39-1 to 39-8 are arranged at positions where the impedances in anticipation of the capacitor 39 side are aligned with each other from each gate finger 35-m of the grounded gate transistor 32. Configured. Therefore, the high frequency amplifier 1 can suppress the imbalance of the amplification operation in the gate fingers 35-1 to 35-8.
  • FIG. 7 is a configuration diagram showing another high frequency amplifier 1 according to the first embodiment.
  • the high frequency amplifier 1 shown in FIG. 7 has drain source fingers 20-1 to 20-8.
  • the drain source fingers 20-1 to 20-8 are fingers in which the drain fingers 15-1 to 15-4 of the source grounded transistor 12 and the source fingers 33-1 to 33-8 of the gate grounded transistor 32 are integrated. Is. Then, in the high frequency amplifier 1 shown in FIG.
  • the high-frequency amplifier 1 shown in FIG. 7 includes capacitors 39-1, 39-8, 39-11, 39-12, 39-13, similarly to the high-frequency amplifier 1 shown in FIG. 6, but is shown in FIG. Similar to the high frequency amplifier 1, capacitors 39-1 to 39-8 may be provided. If the grounded source transistor 12 and the grounded gate transistor 32 are dual gate transistors, it is possible to realize a high frequency amplifier having a higher frequency or a wider band than the high frequency amplifier 1 shown in FIGS. 3 and 6. If the gate of the grounded source transistor 12 and the gate of the grounded gate transistor 32 are on the same channel, the drain source fingers 20-1 to 20-8 may be omitted.
  • FIG. 8 is a configuration diagram showing another high frequency amplifier 1 according to the first embodiment.
  • FIG. 9 is a cross-sectional view of a portion of FIG . 8 from A 1 to A 2.
  • the configuration in which one end of the condenser 39-m is connected to the gate finger 35-m via the air bridge 40-m is higher than the configuration in which one end of the condenser 39-m is connected to the gate bus bar 38.
  • the parasitic component between 35-m and the capacitor 39-m becomes smaller.
  • Embodiment 2 In the second embodiment, the high frequency amplifier 1 including the shunt feedback capacitors 51-1 to 51-4 will be described.
  • FIG. 10 is a configuration diagram showing a high frequency amplifier 1 according to the second embodiment.
  • the same reference numerals as those in FIGS. 3 and 6 indicate the same or corresponding parts, and thus the description thereof will be omitted.
  • shunt feedback capacitors 51-1 to 51-4 are applied to the high frequency amplifier 1 shown in FIG.
  • FIG. 11 is an equivalent circuit diagram showing the high frequency amplifier 1 according to the second embodiment.
  • the same reference numerals as those in FIG. 4 indicate the same or corresponding parts, and thus the description thereof will be omitted.
  • the shunt feedback capacitor 51 is any one of the shunt feedback capacitors 51-1 to 51-4.
  • the other end of the shunt feedback capacitor 51-j is connected to the drain finger 15-j.
  • One end of the air bridge 52-j is connected to the drain finger 34-j, and the other end of the air bridge 52-j is connected to one end of the shunt feedback capacitor 51-j.
  • the high frequency amplifier 1 includes the shunt feedback capacitors 51-1 to 51-4, impedance matching between the source grounded transistor 12 and the gate grounded transistor 32 can be achieved. Since the shunt feedback capacitors 51-1 to 51-4 are dispersedly arranged for each drain finger 15-j, the unbalanced operation of the drain fingers 15-1 to 15-4 is suppressed.
  • FIG. 12 is a configuration diagram showing another high frequency amplifier 1 according to the second embodiment.
  • gate fingers 14-1 to 14-8, source fingers 16-1 to 16-5, drain source fingers 20-1 to 20-8, and drain fingers 34-1 to 34 -4 and gate fingers 35-1 to 35-8 are arranged in parallel with each other.
  • the high-frequency amplifier 1 shown in FIG. 12 includes capacitors 39-1, 39-8, 39-11, 39-12, 39-13, similarly to the high-frequency amplifier 1 shown in FIG.
  • capacitors 39-1 to 39-8 may be provided. If the grounded source transistor 12 and the grounded gate transistor 32 are dual gate transistors, it is possible to realize a high frequency amplifier having a higher frequency or a wider band than the high frequency amplifier 1 shown in FIG.
  • the capacitors 39-1 to 39-8, or the capacitors 39-1, 39-8, 39-11, 39-12, 39-13 are used as MIMs (Metal Instruments). It is realized by a Metal) capacitor.
  • the capacitors 39-1 to 39-8 and 39-11 to 39-13 are not limited to MIM capacitors, and may be realized by, for example, an interdigital capacitor.
  • the capacitors 39-1 to 39-8 and the like are formed in any of the source fingers 16-1 to 16-5.
  • each of the source grounded transistor 12 and the gate grounded transistor 32 is realized by a GaN multi-finger transistor.
  • each of the source grounded transistor 12 and the gate grounded transistor 32 may be a transistor formed on a substrate whose substrate material is GaAs (gallium arsenide) or the like.
  • each of the grounded source transistor 12 and the grounded gate transistor 32 may be realized by a bipolar transistor instead of the field effect transistor.
  • each capacitor 39 is arranged at a position sandwiched between the two gate fingers 14 or at a position next to the one gate finger 14.
  • a plurality of capacitors 39-1 to 39-8 and the like may be arranged at positions where the impedances expected from the capacitor 39 side are aligned with each other from each gate finger 35-m, as shown in FIGS. 3 or 5 and the like. It is not limited to those that are arranged.
  • the capacitors 39 may be dispersedly arranged every other gate finger 14, and the effect of reducing imbalance can be obtained.
  • the source grounded transistor 12 and the gate grounded transistor 32 are connected in series as two transistors. However, this is only an example, and three or more transistors may be connected in cascade.
  • the present disclosure is suitable for high frequency amplifiers that amplify high frequency signals.
  • the present disclosure is suitable for wireless communication devices including high frequency amplifiers.
  • the present disclosure is suitable for radar devices including high frequency amplifiers.
  • 1 High frequency amplifier 2 Transmitting antenna, 3 Transmitting antenna, 11 Signal input terminal, 12 Source grounded transistor, 12a Gate electrode, 12b Drain electrode, 12c Source electrode, 13 Gate bus bar, 14, 14-1 to 14-8 Gate finger, 15-1 to 15-4 drain finger, 16-1 to 16-5 source finger, 17-1 to 17-5 via hole, 18 bus bar, 20-1 to 20-8 drain source finger, 31,31-1,31 -2 Gate terminal, 32 gate grounded transistor, 32a source electrode, 32b drain electrode, 32c gate electrode, 33-1 to 33-8 source finger, 34-1 to 34-4 drain finger, 35-1 to 35-8 gate Finger, 36 drain bus bar, 37 signal output terminal, 38 gate bus bar, 39, 39-1 to 39-8 capacitors, 40-1 to 40-8 air bridge, 51, 51-1 to 51-4 shunt feedback capacitors, 52 -1 to 52-4 Air bridge.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
PCT/JP2020/015343 2020-04-03 2020-04-03 高周波増幅器、無線通信装置及びレーダ装置 Ceased WO2021199431A1 (ja)

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EP20928877.8A EP4113832B1 (en) 2020-04-03 2020-04-03 High-frequency amplifier, radio communication device, and radar device
JP2022511484A JP7195480B2 (ja) 2020-04-03 2020-04-03 高周波増幅器、無線通信装置及びレーダ装置
PCT/JP2020/015343 WO2021199431A1 (ja) 2020-04-03 2020-04-03 高周波増幅器、無線通信装置及びレーダ装置
US17/882,105 US12456954B2 (en) 2020-04-03 2022-08-05 High-frequency amplifier, radio communication device, and radar device

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EP4343831A1 (en) * 2022-09-25 2024-03-27 Wolfspeed, Inc. Field effect transistor with integrated series capacitance

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JP2023049404A (ja) * 2021-09-29 2023-04-10 住友電工デバイス・イノベーション株式会社 半導体装置
US12599008B2 (en) * 2023-04-06 2026-04-07 Nxp Usa, Inc. Transistor with source manifold in non-active die region

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JP2015192205A (ja) * 2014-03-27 2015-11-02 三菱電機株式会社 カスコード増幅器

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JP3925417B2 (ja) 2003-01-29 2007-06-06 富士通株式会社 分布型増幅器実装装置
JP4821214B2 (ja) * 2005-08-26 2011-11-24 三菱電機株式会社 カスコード接続回路
JP7302925B2 (ja) * 2018-08-29 2023-07-04 住友電工デバイス・イノベーション株式会社 高周波増幅器

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JP2015192205A (ja) * 2014-03-27 2015-11-02 三菱電機株式会社 カスコード増幅器

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EP4343831A1 (en) * 2022-09-25 2024-03-27 Wolfspeed, Inc. Field effect transistor with integrated series capacitance

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EP4113832A4 (en) 2023-08-02
US20220385246A1 (en) 2022-12-01
EP4113832A1 (en) 2023-01-04
EP4113832B1 (en) 2025-04-23
US12456954B2 (en) 2025-10-28
JP7195480B2 (ja) 2022-12-23

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