WO2021196330A1 - 用于 goa 电路的保护系统及液晶显示面板 - Google Patents

用于 goa 电路的保护系统及液晶显示面板 Download PDF

Info

Publication number
WO2021196330A1
WO2021196330A1 PCT/CN2020/087748 CN2020087748W WO2021196330A1 WO 2021196330 A1 WO2021196330 A1 WO 2021196330A1 CN 2020087748 W CN2020087748 W CN 2020087748W WO 2021196330 A1 WO2021196330 A1 WO 2021196330A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
signal
comparator
goa
Prior art date
Application number
PCT/CN2020/087748
Other languages
English (en)
French (fr)
Inventor
陈书志
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/254,902 priority Critical patent/US11443665B2/en
Publication of WO2021196330A1 publication Critical patent/WO2021196330A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • This application relates to the field of display technology, and in particular to a protection system for GOA circuits and a liquid crystal display panel.
  • a conventional liquid crystal display device includes a source driver, a gate driver, and a liquid crystal display panel, and the gate driver is arranged outside the liquid crystal display panel.
  • the liquid crystal display panel has made the gate driver on the liquid crystal display panel, that is, the gate driving technology (Gate driver on array, GOA).
  • the GOA technology utilizes the existing thin film transistor liquid crystal display panel array manufacturing process to fabricate the gate row scan driving signal circuit on the array substrate to realize the progressive scan of the gate.
  • the GOA unit When the clock signal generated by the control board and the start-stop signal STV are transmitted to the GOA unit, the GOA unit will generate a scan signal to the pixel unit in the pixel array area, and at the same time, the source driver will output the gray-scale voltage to the pixel unit in the pixel array area , In order to realize the normal display of the liquid crystal display panel.
  • the GOA circuit is a plurality of cascaded GOA units.
  • the first-stage GOA unit 101 receives the start-stop signal STV, the first-stage GOA unit outputs the first row scan signal G001, and the first row scan signal G001 passes
  • the signal line 1012 is used as the cascade signal of the second-level GOA unit 102, and the second-line scan signal G001 output by the second-level GOA unit 102 is used as a pull-up signal.
  • the pull-up signal is transmitted to the first-level GOA unit 101 through the signal line 1011.
  • GOA unit Used to modify the waveform of the first line of scan signal G001, and the cascaded signal transmission mode of other GOA units is the same as the above, so that the GOA unit can output the scan signal of the entire liquid crystal display panel. Since the GOA unit in the entire GOA circuit is in a state of mutual influence between the upper and lower levels, as long as any GOA unit fails, it will affect the scan signal output by the next GOA unit.
  • the embodiments of the present application provide a protection system and a liquid crystal display panel for a GOA circuit, which can solve multiple cascaded GOA units in the GOA circuit in the liquid crystal display panel in the prior art, and the low voltage signal VSSQ/ in any GOA unit
  • the VSSG is short-circuited with the high-potential signal line to form a large current, which may affect the normal operation of the entire GOA circuit, cause display abnormalities, and even cause technical problems of LCD panel burn-in.
  • An embodiment of the present application provides a protection system for a GOA circuit, including: a detection circuit connected to the GOA circuit and configured to generate a corresponding drive signal according to a low-potential signal of the GOA circuit; The initial trigger signal, the detection circuit, and the GOA circuit are connected, and the switch circuit is used to control the GOA circuit to access the initial trigger signal according to the drive signal.
  • the switch circuit when the low potential signal is at a low level, the switch circuit is turned on, and the GOA circuit is connected to the initial trigger signal; when the low potential signal is at a high level, the switch circuit is turned off , The GOA circuit does not access the start trigger signal.
  • the detection circuit includes a first comparator and an inverter
  • the low-level signal includes a first low-level signal
  • the input terminal of the first comparator is connected to the first low-level signal Signal connection
  • the output terminal of the first comparator is connected with the input terminal of the inverter
  • the output terminal of the inverter is connected with the control terminal of the switch circuit.
  • the low-level signal further includes a second low-level signal
  • the detection circuit further includes a second comparator
  • the input terminal of the second comparator is connected to the second low-level signal
  • the output terminal of the second comparator and the output terminal of the first comparator are both connected to the input terminal of the inverter.
  • the switch circuit includes a switch thin film transistor; the drain of the switch thin film transistor is connected to the initial trigger signal; the source of the switch thin film transistor is connected to the GOA circuit; The gate of the switching thin film transistor is connected to the driving signal.
  • the first comparator includes first, second, third, fourth, fifth, sixth, seventh, and eighth thin film transistors, wherein the first to fourth thin film transistors Set in the first row, the sources of the first row of thin film transistors are electrically connected with 28V voltage to form a high-potential loop; the fifth, sixth, seventh, and eighth thin film transistors are set in the second row, and the second row of thin film transistors The drains are all electrically connected with a voltage of 0V, forming a low-potential loop.
  • the inverter includes a ninth, tenth, eleventh, and twelfth thin film transistor, wherein the gate of the ninth thin film transistor and the gate of the twelfth thin film transistor are at the same time as
  • the output terminals of the first comparator and the second comparator are electrically connected, the drain of the ninth thin film transistor is electrically connected to the drain of the twelfth thin film transistor, and is electrically connected to the -10V voltage, forming Low potential loop;
  • the source of the ninth thin film transistor is electrically connected to the source of the eleventh thin film transistor, and the source of the ninth thin film transistor is electrically connected to the drain of the tenth thin film transistor.
  • the source of the tenth thin film transistor and the source of the eleventh thin film transistor are electrically connected, and are electrically connected to a voltage of 28V, forming a high-potential loop.
  • the first comparator and the second comparator have the same structure and function, and are used to input different low-voltage signals in the GOA unit. Any output of the second comparator outputs a high-level voltage, and the inverter outputs a low-level voltage.
  • the switching thin film transistor is an N-type thin film transistor.
  • the first thin film transistor to the eighth thin film transistor are all N-type thin film transistors.
  • the eighth thin film transistor to the twelfth thin film transistor are all N-type thin film transistors.
  • the present application also provides a liquid crystal display panel, including the protection system of the GOA circuit in the above embodiment.
  • the protection system of the GOA circuit includes: a detection circuit connected to the GOA circuit for A corresponding drive signal is generated according to the low-potential signal of the GOA circuit; and a switch circuit is connected to the initial trigger signal, the detection circuit and the GOA circuit, and the switch circuit is used to control the drive signal according to the drive signal.
  • the GOA circuit is connected to the initial trigger signal; wherein, when the low potential signal is low, the switch circuit is turned on, and the GOA circuit is connected to the initial trigger signal; when the low potential signal When the level is high, the switch circuit is disconnected, the GOA circuit does not access the initial trigger signal, the GOA circuit includes multi-level GOA units; except for the last level of GOA units, each level of GOA unit
  • the output scan signal is used as the cascade signal of the next GOA unit of the GOA unit of this level; except for the first level GOA unit, the output scan signal of each level of GOA unit and the pull-down signal of the previous GOA unit of this level of GOA unit
  • the pull-down signal is used to modify the waveform of the scanning signal in the GOA unit of the upper level.
  • the detection circuit includes a first comparator and an inverter
  • the low-level signal includes a first low-level signal
  • the input terminal of the first comparator is connected to the first low-level signal Signal connection
  • the output terminal of the first comparator is connected with the input terminal of the inverter
  • the output terminal of the inverter is connected with the control terminal of the switch circuit.
  • the low-level signal further includes a second low-level signal
  • the detection circuit further includes a second comparator
  • the input terminal of the second comparator is connected to the second low-level signal
  • the output terminal of the second comparator and the output terminal of the first comparator are both connected to the input terminal of the inverter.
  • the switch circuit includes a switch thin film transistor; the drain of the switch thin film transistor is connected to the initial trigger signal; the source of the switch thin film transistor is connected to the GOA circuit; The gate of the switching thin film transistor is connected to the driving signal.
  • the first comparator includes first, second, third, fourth, fifth, sixth, seventh, and eighth thin film transistors, wherein the first to fourth thin film transistors Set in the first row, the sources of the first row of thin film transistors are electrically connected with 28V voltage to form a high-potential loop; the fifth, sixth, seventh, and eighth thin film transistors are set in the second row, and the second row of thin film transistors The drains are all electrically connected with a voltage of 0V, forming a low-potential loop.
  • the inverter includes a ninth, tenth, eleventh, and twelfth thin film transistor, wherein the gate of the ninth thin film transistor and the gate of the twelfth thin film transistor are at the same time as
  • the output terminals of the first comparator and the second comparator are electrically connected, the drain of the ninth thin film transistor is electrically connected to the drain of the twelfth thin film transistor, and is electrically connected to the -10V voltage, forming Low potential loop;
  • the source of the ninth thin film transistor is electrically connected to the source of the eleventh thin film transistor, and the source of the ninth thin film transistor is electrically connected to the drain of the tenth thin film transistor.
  • the source of the tenth thin film transistor and the source of the eleventh thin film transistor are electrically connected, and are electrically connected to a voltage of 28V, forming a high-potential loop.
  • the first comparator and the second comparator have the same structure and function, and are used to input different low-voltage signals in the GOA unit. Any output of the second comparator outputs a high-level voltage, and the inverter outputs a low-level voltage.
  • the switching thin film transistor is an N-type thin film transistor.
  • the first thin film transistor to the eighth thin film transistor are all N-type thin film transistors.
  • the eighth thin film transistor to the twelfth thin film transistor are all N-type thin film transistors.
  • the present application provides a protection system and a liquid crystal display panel for a GOA circuit.
  • the protection system of the GOA circuit in the present application includes a detection circuit connected to the GOA circuit for generating a corresponding drive signal according to the low potential signal of the GOA circuit; and a switch;
  • the circuit is connected with the initial trigger signal, the detection circuit and the GOA circuit.
  • the switch circuit is used to control the GOA circuit to access the initial trigger signal according to the drive signal; among them, when the low potential signal is low, the switch circuit is turned on and the GOA circuit Connect the initial trigger signal; when the low potential signal is high, the switch circuit is disconnected, the GOA circuit does not connect to the initial trigger signal, and the GOA circuit stops working to avoid high-voltage scanning signals causing the display panel to burn.
  • Fig. 1 is a schematic diagram of a GOA circuit structure in the prior art.
  • FIG. 2 is a schematic diagram of a protection system for GOA circuits according to an embodiment of the application.
  • FIG. 3 is a schematic diagram of a GOA unit in a GOA circuit according to an embodiment of the application.
  • FIG. 4 is a schematic diagram of a detection circuit in a protection system for a GOA circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of a short-circuit voltage in a protection system for a GOA circuit provided by an embodiment of the application.
  • This application is directed to multiple cascaded GOA units in the GOA circuit in the liquid crystal display panel in the prior art.
  • the low-voltage signal VSSQ/VSSG in any GOA unit is short-circuited with the high-potential signal line, forming a large current, which may affect the entire GOA circuit Normal operation may cause display abnormalities and even cause technical problems of LCD panel burn-in.
  • This embodiment can solve this defect.
  • an embodiment of the present application provides a protection system for a GOA circuit, including: a detection circuit 30, connected to the GOA circuit, for generating a corresponding drive according to the low-potential signal (VSSQ/VSSG) of the GOA circuit Signal; and a switch circuit 10, which is connected to the start trigger signal STV, the detection circuit 30, and the GOA circuit.
  • a detection circuit 30 connected to the GOA circuit, for generating a corresponding drive according to the low-potential signal (VSSQ/VSSG) of the GOA circuit Signal
  • a switch circuit 10 which is connected to the start trigger signal STV, the detection circuit 30, and the GOA circuit.
  • the switch circuit 10 is used to control the GOA circuit to access the start trigger signal STV according to the drive signal; wherein, when the low potential signal is a low voltage Normally, the switch circuit 10 is turned on, and the GOA circuit is connected to the start trigger signal STV; when the low potential signal is at a high level, the switch circuit 10 is disconnected, and the GOA circuit does not connect to the start trigger signal STV.
  • the switching circuit 10 is preferably an N-type switching thin film transistor, the drain of the switching thin film transistor is connected to the initial trigger signal; the source of the switching thin film transistor is connected to the GOA circuit; the gate of the switching thin film transistor is connected to the driving signal, If the drive signal is a high potential voltage signal, the switch is turned on, and the GOA unit is electrically connected to the initial trigger signal line. If the drive signal is a low potential voltage signal, the switch is turned off, and the GOA unit and the initial trigger signal STV The line is broken.
  • the GOA circuit in this embodiment includes multi-level GOA units. Except for the last level of GOA unit, the output scan signal of each level of GOA unit is used as the cascaded signal of the next level of GOA unit of the level of GOA unit; except for the last level of GOA unit In addition to the unit, the output scan signal of each level of GOA unit is used as the pull-down signal of the previous GOA unit of the GOA unit of that level, and the pull-down signal is used to modify the waveform of the scan signal in the previous GOA unit. For example, the scan signal G001 output by the first-level GOA unit 101 is used as the second-level GOA unit 102 cascade signal, and is transmitted to the control module of the second-level GOA unit 102 through the signal line 1012.
  • the scan output by the second-level GOA unit 102 The signal G002 is used as the pull-up signal of the first-level GOA unit 101.
  • the pull-up signal is transmitted through the signal line 1011 to the pull-up module of the first-level GOA unit 101.
  • the cascaded signal transmission mode of other GOA units is the same as the above. To repeat it again, in order to realize the normal operation of the entire GOA circuit.
  • each level of GOA unit includes a control module 201, a pull-up module 202, a download module 203, a pull-down module 204, a pull-down maintenance module 205, and a bootstrap module 206.
  • the control module is connected to the level transmission signal (ST(N-1)) of the N-1 level GOA unit and the scanning signal (G(N-1)) of the N-1 level GOA unit, which is used to follow the N-1 level
  • the level transmission signal (ST(N-1)) of the level GOA unit and the scan signal (G(N-1)) of the N-1 level GOA unit raise the potential of the first node (Q(N)); pull up the module 202 is electrically connected to the first node (Q(N)) and connected to the clock signal (CK) or the reverse clock signal (XCK) for using the clock signal under the control of the first node (Q(N)) (CK) or reverse clock signal (XCK) to output the scan signal (G(N+1)); the download module 203 is electrically connected to the first node (Q(N)) and connected to the clock signal (CK) or reverse To the clock signal (XCK), used to use the clock signal (CK) or the reverse clock signal (XCK) under the control of the first node (Q
  • the pull-down module 204 is electrically connected to the first node (Q(N)) and accesses the scanning signal (G(N)), the stage transmission signal of the N+1th GOA unit (ST(N+1)), and the pull-down stage
  • the transmission signal (STA) and the DC low potential (VSS) are used to utilize the DC low under the control of the stage transmission signal (ST(N+1)) and the pull-down stage transmission signal (STA) of the N+1th GOA unit
  • the potential (VSS) pulls down the potential of the first node (Q(N)) and the scan signal (G(N)).
  • the pull-down maintenance module 205 is electrically connected to the first node (Q(N)) and accesses the scan signal (G(N)) and the direct current low potential (VSS), and is used to connect the first node (Q(N)) and scan The potential of the signal (G(N)) is maintained at a low level signal (VSSQ/VSSG), and a pull-up signal LC is output.
  • the pull-down maintenance module 205 includes a first pull-down maintenance module 2051 and a second pull-down maintenance module 2052. The first pull-down maintaining module 2051 outputs the first pull-up LC1, and the second pull-down maintaining module 2052 outputs the second pull-up signal LC2.
  • the bootstrap module 206 is electrically connected to the first node (Q(N)) and accesses the scan signal (G(N)) for enabling the first node (Q(N)) to be output during the output period of the scan signal (G(N)). )) is raised and maintained at the raised potential.
  • the detection circuit 30 in this embodiment includes a first comparator 31 and an inverter 33.
  • the low-potential signal includes a first low-potential signal VSSQ and a second low-potential signal VSSG.
  • the first comparator The input terminal of 31 is electrically connected to the first low potential signal VSSQ in the corresponding GOA unit; the output terminal of the first comparator 31 is connected to the input terminal of the inverter 33, namely node M; the output terminal of the inverter 33 is connected to the switch The control terminal of the circuit 10 is connected.
  • the detection circuit 30 also includes a second comparator 32.
  • the first comparator 31 and the second comparator 32 have the same structure and function, and are used to input different low-voltage signals in the GOA unit.
  • the second low-level signal VSSG is connected; the output terminal of the second comparator 32 is connected to the output terminal of the first comparator 31 and the input terminal of the inverter 33. If either of the first comparator 31 and the second comparator 32 is The output outputs a high-potential voltage, and the inverter 33 outputs a low-potential voltage.
  • the start signal STV cannot enter the first-stage GOA unit in the GOA circuit, so that the liquid crystal display panel is protected to avoid burn-in.
  • the first comparator includes a first thin film transistor 301, a second thin film transistor 302, a third thin film transistor 303, a fourth thin film transistor 304, a fifth thin film transistor 305, a sixth thin film transistor 306, a seventh thin film transistor 307, and an eighth thin film transistor.
  • the first low-potential signal VSSQ is always -8V
  • the second low-potential signal VSSG is -6V. After a period of time, the second low-potential signal VSSG changes from -6V to a high voltage. Between 0V and 28V, refer to Figure 5.
  • the inverter 33 includes a ninth thin film transistor 309, a tenth thin film transistor 3010, an eleventh thin film transistor 3011, and a twelfth thin film transistor 3012, wherein the gate of the ninth thin film transistor 309 and the gate of the twelfth thin film transistor 3012
  • the electrode is electrically connected to the output terminals of the first comparator 31 and the second comparator 32 at the same time.
  • the drain of the ninth thin film transistor 309 is electrically connected to the drain of the twelfth thin film transistor 3012, and is electrically connected to the -10V voltage.
  • the source of the ninth thin film transistor 309 is electrically connected to the source of the eleventh thin film transistor 3011, and the source of the ninth thin film transistor 309 is electrically connected to the drain of the tenth thin film transistor 3010.
  • the gate of the tenth thin film transistor 3010, the source of the tenth thin film transistor 3010, and the source of the eleventh thin film transistor 3011 are electrically connected, and are electrically connected to the 28V voltage to form a high-potential loop.
  • the first to the twelfth The thin film transistors are all N-type thin film transistors.
  • the first low-potential signal VSSQ is always -8V
  • the second low-potential signal VSSG is -6V
  • the inverter 33 outputs a voltage of 28V
  • the switch circuit 10 is turned on, and the GOA circuit works normally.
  • a low-level signal VSSQ is always -8V.
  • the GOA circuit is short-circuited, the voltage of the second low-level signal VSSG will be pulled up, greater than 0V, the inverter 33 will output a -10V voltage, the switch circuit 10 will be turned off, and the GOA circuit will stop working.
  • the start signal STV cannot enter the first-stage GOA unit 101 in the GOA circuit to avoid the high-voltage scan signal from causing the display panel to burn-in. Refer to FIG. 5.
  • the present application also provides a liquid crystal display panel including the above-mentioned GOA circuit.
  • the present application provides a protection system and a liquid crystal display panel for a GOA circuit.
  • the protection system of the GOA circuit in the present application includes a detection circuit connected to the GOA circuit for generating a corresponding drive signal according to the low potential signal of the GOA circuit; and a switch;
  • the circuit is connected with the initial trigger signal, the detection circuit and the GOA circuit.
  • the switch circuit is used to control the GOA circuit to access the initial trigger signal according to the drive signal; among them, when the low potential signal is low, the switch circuit is turned on and the GOA circuit Connect the initial trigger signal; when the low potential signal is high, the switch circuit is disconnected, the GOA circuit does not connect to the initial trigger signal, and the GOA circuit stops working to avoid high-voltage scanning signals causing the display panel to burn.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种用于GOA电路的保护系统及液晶显示面板，开关电路（10）与起始触发信号（STV）、其中检测电路（30）以及其中GOA电路连接，当低电位信号为低电平时，开关电路（10）导通，GOA电路接入起始触发信号，液晶显示面板正常工作；当低电位信号为高电平时，开关电路（10）断开，GOA电路不接入其中起始触发信号，避免高电压扫描信号导致显示面板烧屏。

Description

用于GOA电路的保护系统及液晶显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种用于GOA电路的保护系统及液晶显示面板。
 背景技术
传统的液晶显示装置包含源极驱动器、栅极驱动器(gate driver)以及液晶显示面板，栅极驱动器设置在液晶显示面板外面的。现有技术中液晶显示面板已经将栅极驱动器制作在液晶显示面板上，也就是栅极驱动技术(Gate driver on array，GOA)。GOA技术利用现有薄膜晶体管液晶显示面板阵列制程来将栅极行扫描驱动信号电路制作在阵列基板上，实现对栅极逐行扫描。当控制板产生的时钟信号以及起止信号STV传送至GOA单元时，GOA单元会产生扫描信号至像素阵列区的像素单元，与此同时，源极驱动器会输出灰阶电压至像素阵列区的像素单元，以此实现液晶显示面板正常显示。
如图1所示，GOA电路为多个级联的GOA单元，当第一级GOA单元101接收到起止信号STV，第一级GOA单元输出第一行扫描信号G001，第一行扫描信号G001通过信号线1012作为第二级GOA单元102的级联信号，第二级GOA单元102输出的第二行扫描信号G001作为上拉信号，该上拉信号通过信号线1011传递第一级GOA单元101中，用于修正第一行扫描信号G001的波形，其他的GOA单元的级联信号传递方式跟上述相同，以此实现GOA单元输出整个液晶显示面板的扫描信号。由于整个GOA电路中GOA单元处于上下级相互影响的状态，只要任何一级GOA单元出现了故障都会影响下一级GOA单元输出的扫描信号。
因此，现有技术中液晶显示面板内GOA电路中多个级联的GOA单元，任意一个GOA单元中低电压信号VSSQ/VSSG与高电位信号线短路，形成大电流，将可能影响整个GOA电路正常工作，引起显示异常，甚至造成液晶显示面板烧屏的技术问题，需要改进。
 技术问题
本申请实施例提供一种用于GOA电路的保护系统及液晶显示面板，能够解决现有技术中液晶显示面板内GOA电路中多个级联的GOA单元，任意一个GOA单元中低电压信号VSSQ/VSSG与高电位信号线短路，形成大电流，将可能影响整个GOA电路正常工作，引起显示异常，甚至造成液晶显示面板烧屏的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种用于GOA电路的保护系统，包括：检测电路，与所述GOA电路连接，用于根据所述GOA电路的低电位信号生成对应的驱动信号；以及开关电路，与起始触发信号、所述检测电路以及所述GOA电路连接，所述开关电路用于根据所述驱动信号控制所述GOA电路接入所述起始触发信号。
其中，当所述低电位信号为低电平时，所述开关电路导通，所述GOA电路接入所述起始触发信号；当所述低电位信号为高电平时，所述开关电路断开，所述GOA电路不接入所述起始触发信号。
根据本申请一优选实施例，所述检测电路包括第一比较器和反相器，所述低电位信号包括第一低电位信号；所述第一比较器的输入端与所述第一低电位信号连接；所述第一比较器的输出端与所述反相器的输入端连接；所述反相器的输出端与所述开关电路的控制端连接。
根据本申请一优选实施例，所述低电位信号还包括第二低电位信号；所述检测电路还包括第二比较器；所述第二比较器的输入端与所述第二低电位信号连接；所述第二比较器的输出端与所述第一比较器的输出端均和所述反相器的输入端连接。
根据本申请一优选实施例，所述开关电路包括开关薄膜晶体管；所述开关薄膜晶体管的漏极与所述起始触发信号连接；所述开关薄膜晶体管的源极与所述GOA电路连接；所述开关薄膜晶体管的栅极与所述驱动信号连接。
根据本申请一优选实施例，所述第一比较器包括第一、第二、第三、第四、第五、第六、第七、第八薄膜晶体管，其中，第一至第四薄膜晶体管设置在第一排，第一排薄膜晶体管的源极均28V电压电性连接，构成高电位回路；第五、第六、第七、第八薄膜晶体管设置在第二排，第二排薄膜晶体管的漏极均0V电压电性连接，构成低电位回路。
根据本申请一优选实施例，所述反相器包括第九、第十、第十一、第十二薄膜晶体管，其中，第九薄膜晶体管的栅极、第十二薄膜晶体管的栅极同时与所述第一比较器和所述第二比较器的输出端电性连接，第九薄膜晶体管的漏极与第十二薄膜晶体管的漏极电性连接，且与-10V电压电性连接，构成低电位回路；第九薄膜晶体管的源极与第十一薄膜晶体管源极电性连接，且第九薄膜晶体管的源极与第十薄膜晶体管漏极电性连接，第十薄膜晶体管栅极、第十薄膜晶体管源极及第十一薄膜晶体管源极电性连接，且与28V电压电性连接，构成高电位回路。
根据本申请一优选实施例，，所述第一比较器和所述第二比较器的结构和功能相同，用于输入所述GOA单元中不同的低压信号，若所述第一比较器和所述第二比较器的任一输出输出高电位电压，所述反相器输出低电位电压。
根据本申请一优选实施例，所述开关薄膜晶体管为N型薄膜晶体管。
根据本申请一优选实施例，所述第一薄膜晶体管至所述第八薄膜晶体管均为N型薄膜晶体管。
根据本申请一优选实施例，所述第八薄膜晶体管至所述第十二薄膜晶体管均为N型薄膜晶体管。
依据上述GOA电路的保护系统，本申请还提供一种液晶显示面板，包括上述实施例中GOA电路的保护系统，所述GOA电路的保护系统包括：检测电路，与所述GOA电路连接，用于根据所述GOA电路的低电位信号生成对应的驱动信号；以及开关电路，与起始触发信号、所述检测电路以及所述GOA电路连接，所述开关电路用于根据所述驱动信号控制所述GOA电路接入所述起始触发信号；其中，当所述低电位信号为低电平时，所述开关电路导通，所述GOA电路接入所述起始触发信号；当所述低电位信号为高电平时，所述开关电路断开，所述GOA电路不接入所述起始触发信号，所述GOA电路包括多级GOA单元；除了最后一级GOA单元以外，每一级GOA单元的输出扫描信号作为该级GOA单元的下一级GOA单元的级联信号；除了第一级GOA单元以外，每一级GOA单元的输出扫描信号与该级GOA单元的上一级GOA单元的下拉信号，所述下拉信号用于修正上一级GOA单元中扫描信号的波形。
根据本申请一优选实施例，所述检测电路包括第一比较器和反相器，所述低电位信号包括第一低电位信号；所述第一比较器的输入端与所述第一低电位信号连接；所述第一比较器的输出端与所述反相器的输入端连接；所述反相器的输出端与所述开关电路的控制端连接。
根据本申请一优选实施例，所述低电位信号还包括第二低电位信号；所述检测电路还包括第二比较器；所述第二比较器的输入端与所述第二低电位信号连接；所述第二比较器的输出端与所述第一比较器的输出端均和所述反相器的输入端连接。
根据本申请一优选实施例，所述开关电路包括开关薄膜晶体管；所述开关薄膜晶体管的漏极与所述起始触发信号连接；所述开关薄膜晶体管的源极与所述GOA电路连接；所述开关薄膜晶体管的栅极与所述驱动信号连接。
根据本申请一优选实施例，所述第一比较器包括第一、第二、第三、第四、第五、第六、第七、第八薄膜晶体管，其中，第一至第四薄膜晶体管设置在第一排，第一排薄膜晶体管的源极均28V电压电性连接，构成高电位回路；第五、第六、第七、第八薄膜晶体管设置在第二排，第二排薄膜晶体管的漏极均0V电压电性连接，构成低电位回路。
根据本申请一优选实施例，所述反相器包括第九、第十、第十一、第十二薄膜晶体管，其中，第九薄膜晶体管的栅极、第十二薄膜晶体管的栅极同时与所述第一比较器和所述第二比较器的输出端电性连接，第九薄膜晶体管的漏极与第十二薄膜晶体管的漏极电性连接，且与-10V电压电性连接，构成低电位回路；第九薄膜晶体管的源极与第十一薄膜晶体管源极电性连接，且第九薄膜晶体管的源极与第十薄膜晶体管漏极电性连接，第十薄膜晶体管栅极、第十薄膜晶体管源极及第十一薄膜晶体管源极电性连接，且与28V电压电性连接，构成高电位回路。
根据本申请一优选实施例，所述第一比较器和所述第二比较器的结构和功能相同，用于输入所述GOA单元中不同的低压信号，若所述第一比较器和所述第二比较器的任一输出输出高电位电压，所述反相器输出低电位电压。
根据本申请一优选实施例，所述开关薄膜晶体管为N型薄膜晶体管。
根据本申请一优选实施例，所述第一薄膜晶体管至所述第八薄膜晶体管均为N型薄膜晶体管。
根据本申请一优选实施例，所述第八薄膜晶体管至所述第十二薄膜晶体管均为N型薄膜晶体管。
 有益效果
本申请提供一种用于GOA电路的保护系统及液晶显示面板，本申请中GOA电路的保护系统包括检测电路与GOA电路连接，用于根据GOA电路的低电位信号生成对应的驱动信号；以及开关电路，与起始触发信号、检测电路以及GOA电路连接，开关电路用于根据驱动信号控制GOA电路接入起始触发信号；其中，当低电位信号为低电平时，开关电路导通，GOA电路接入起始触发信号；当低电位信号为高电平时，开关电路断开，GOA电路不接入起始触发信号，GOA电路停止工作，避免高电压扫描信号导致显示面板烧屏。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中一种GOA电路结构示意图。
图2为本申请实施例提供一种用于GOA电路的保护系统示意图。
图3为本申请实施例提供一种GOA电路中GOA单元示意图。
图4为本申请实施例提供一种用于GOA电路的保护系统中检测电路示意图。
图5为本申请实施例提供一种用于GOA电路的保护系统中短路电压示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围，在图中，结构相似的单元是用以相同标号表示，图中虚线表示在结构中并不存在的，仅仅说明结构的形状和位置。
本申请针对现有技术中液晶显示面板内GOA电路中多个级联的GOA单元，任意一个GOA单元中低电压信号VSSQ/VSSG与高电位信号线短路，形成大电流，将可能影响整个GOA电路正常工作，引起显示异常，甚至造成液晶显示面板烧屏的技术问题，本实施例能够解决该缺陷。
如图2所示，本申请实施例提供一种用于GOA电路的保护系统，包括：检测电路30，与GOA电路连接，用于根据GOA电路的低电位信号（VSSQ/VSSG）生成对应的驱动信号；以及开关电路10，与起始触发信号STV、检测电路30以及GOA电路连接，开关电路10用于根据驱动信号控制GOA电路接入起始触发信号STV；其中，当低电位信号为低电平时，开关电路10导通，GOA电路接入起始触发信号STV；当低电位信号为高电平时，开关电路10断开，GOA电路不接入起始触发信号STV。本实施例中开关电路10优选为N型开关薄膜晶体管，开关薄膜晶体管的漏极与起始触发信号连接；开关薄膜晶体管的源极与GOA电路连接；开关薄膜晶体管的栅极与驱动信号连接，若驱动信号为高电位电压信号时，切换开关导通，GOA单元与起始触发信号线的电性连接，若驱动信号为低电位电压信号时，切换开关截止，GOA单元与起始触发信号STV线断开。
本实施例中GOA电路包括多级GOA单元，除了最后一级GOA单元以外，每一级GOA单元的输出扫描信号作为该级GOA单元的下一级GOA单元的级联信号；除了最后一级GOA单元以外，每一级GOA单元的输出扫描信号作为该级GOA单元的上一级GOA单元的下拉信号，下拉信号用于修正上一级GOA单元中扫描信号的波形。例如第一级GOA单元101输出的扫描信号G001作为第二级GOA单元102级联信号，通过通过信号线1012传输到第二级GOA单元102中控制模块中，第二级GOA单元102输出的扫描信号G002作为第一级GOA单元101的上拉信号，该上拉信号通过信号线1011传递第一级GOA单元101的上拉模块中，其他的GOA单元的级联信号传递方式跟上述相同，不再赘述，以此实现整个GOA电路的正常工作。
如图3所示，每级GOA单元均包括控制模块201、上拉模块202、下传模块203、下拉模块204、下拉维持模块205和自举模块206。控制模块接入第N-1级GOA单元的级传信号(ST(N-1))及第N-1级GOA单元的扫描信号(G(N-1))，用于根据第N-1级GOA单元的级传信号(ST(N-1))及第N-1级GOA单元的扫描信号(G(N-1))抬升第一节点(Q(N))的电位；上拉模块202与第一节点(Q(N))电性连接并接入时钟信号(CK)或反向时钟信号(XCK)，用于在第一节点(Q(N))的控制下，利用时钟信号(CK)或反向时钟信号(XCK)输出扫描信号(G(N+1))；下传模块203与第一节点(Q(N))电性连接并接入时钟信号(CK)或反向时钟信号(XCK)，用于在第一节点(Q(N))的控制下，利用时钟信号(CK)或反向时钟信号(XCK)输出级传信号(ST(N))，ST(N)即为每一级GOA单元的起始触发信号STV。下拉模块204与第一节点(Q(N))电性连接并接入扫描信号(G(N))、第N+1级GOA单元的级传信号(ST(N+1))、下拉级传信号(STA)以及直流低电位(VSS)，用于在第N+1级GOA单元的级传信号(ST(N+1))以及下拉级传信号(STA)的控制下，利用直流低电位(VSS)下拉第一节点(Q(N))和扫描信号(G(N))的电位。下拉维持模块205与第一节点(Q(N))电性连接并接入扫描信号(G(N))以及直流低电位(VSS)，用于将第一节点(Q(N))及扫描信号(G(N))的电位维持在低电位信号(VSSQ/VSSG)，输出上拉信号LC，本实施例中下拉维持模块205包括第一下拉维持模块2051和第二下拉维持模块2052，第一下拉维持模块2051输出第一上拉LC1，第二下拉维持模块2052输出第二上拉信号LC2。自举模块206与第一节点(Q(N))电性连接并接入扫描信号(G(N))，用于在扫描信号(G(N))输出期间使第一节点(Q(N))的电位抬升并保持抬升后的电位。
如图4和图5所示，本实施例中检测电路30包括第一比较器31和反相器33，低电位信号包括第一低电位信号VSSQ和第二低电位信号VSSG，第一比较器31的输入端与相应GOA单元中第一低电位信号VSSQ电性连接；第一比较器31的输出端与反相器33的输入端连接，即节点M；反相器33的输出端与开关电路10的控制端连接。检测电路30还包括第二比较器32，其中，第一比较器31和第二比较器32的结构和功能相同，用于输入GOA单元中不同的低压信号，第二比较器32的输入端与第二低电位信号VSSG连接；第二比较器32的输出端与第一比较器31的输出端和反相器33的输入端连接，若第一比较器31和第二比较器32的任一输出输出高电位电压，反相器33输出低电位电压，起始信号STV无法进入GOA电路中第一级GOA单元，从而液晶显示面板得到保护，避免烧屏。
第一比较器包括第一薄膜晶体管301、第二薄膜晶体管302、第三薄膜晶体管303、第四薄膜晶体管304、第五薄膜晶体管305、第六薄膜晶体管306、第七薄膜晶体管307、第八薄膜晶体管308，其中，第一薄膜晶体管301、第二薄膜晶体管302、第三薄膜晶体管303、第四薄膜晶体管304设置在第一排，第一排薄膜晶体管的源极均28V电压电性连接，构成高电位回路；第五薄膜晶体管305、第六薄膜晶体管306、第七薄膜晶体管307、第八薄膜晶体管308设置在第二排，第二排薄膜晶体管的漏极均0V电压电性连接，构成低电位回路，本实施例中第一低电位信号VSSQ始终为-8V，第二低电位信号VSSG为-6V，经过一段时间后第二低电位信号VSSG由-6V变为高电压，该高电压位于0V至28V之间，参考图5。
反相器33包括第九薄膜晶体管309、第十薄膜晶体管3010、第十一薄膜晶体管3011及第十二薄膜晶体管3012，其中，第九薄膜晶体管309的栅极、第十二薄膜晶体管3012的栅极同时与第一比较器31和第二比较器32的输出端电性连接，第九薄膜晶体管309的漏极与第十二薄膜晶体管3012的漏极电性连接，且与-10V电压电性连接，构成低电位回路；第九薄膜晶体管309的源极与第十一薄膜晶体管3011源极电性连接，且第九薄膜晶体管309的源极与第十薄膜晶体管3010漏极电性连接，第十薄膜晶体管3010栅极、第十薄膜晶体管3010源极及第十一薄膜晶体管3011源极电性连接，且与28V电压电性连接，构成高电位回路，本实施例中第一至第十二薄膜晶体管均为N型薄膜晶体管，第一低电位信号VSSQ始终为-8V，第二低电位信号VSSG为-6V，反相器33输出28V电压，开关电路10导通，GOA电路正常工作，第一低电位信号VSSQ始终为-8V，GOA电路发生短路时候，第二低电位信号VSSG的电压会拉高，大于0V，反相器33输出-10V电压，开关电路10截止，GOA电路停止工作，起始信号STV无法进入GOA电路中第一级GOA单元101，避免高电压扫描信号导致显示面板烧屏，参考图5。
依据上述GOA电路，本申请还提供一种液晶显示面板，包括上述GOA电路。
本申请提供一种用于GOA电路的保护系统及液晶显示面板，本申请中GOA电路的保护系统包括检测电路与GOA电路连接，用于根据GOA电路的低电位信号生成对应的驱动信号；以及开关电路，与起始触发信号、检测电路以及GOA电路连接，开关电路用于根据驱动信号控制GOA电路接入起始触发信号；其中，当低电位信号为低电平时，开关电路导通，GOA电路接入起始触发信号；当低电位信号为高电平时，开关电路断开，GOA电路不接入起始触发信号，GOA电路停止工作，避免高电压扫描信号导致显示面板烧屏。
综上，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种用于GOA电路的保护系统，其包括：
    检测电路，与所述GOA电路连接，用于根据所述GOA电路的低电位信号生成对应的驱动信号；
    开关电路，与起始触发信号、所述检测电路以及所述GOA电路连接，所述开关电路用于根据所述驱动信号控制所述GOA电路接入所述起始触发信号；
    其中，当所述低电位信号为低电平时，所述开关电路导通，所述GOA电路接入所述起始触发信号；当所述低电位信号为高电平时，所述开关电路断开，所述GOA电路不接入所述起始触发信号。
  2. 根据权利要求1所述的GOA电路的保护系统，其中，所述检测电路包括第一比较器和反相器，所述低电位信号包括第一低电位信号；
    所述第一比较器的输入端与所述第一低电位信号连接；所述第一比较器的输出端与所述反相器的输入端连接；所述反相器的输出端与所述开关电路的控制端连接。
  3. 根据权利要求2所述的GOA电路的保护系统，其中，所述低电位信号还包括第二低电位信号，所述检测电路还包括第二比较器；
    所述第二比较器的输入端与所述第二低电位信号连接；所述第二比较器的输出端与所述第一比较器的输出端均和所述反相器的输入端连接。
  4. 根据权利要求1所述的GOA电路的保护系统，其中，所述开关电路包括开关薄膜晶体管；
    所述开关薄膜晶体管的漏极与所述起始触发信号连接；所述开关薄膜晶体管的源极与所述GOA电路连接；所述开关薄膜晶体管的栅极与所述驱动信号连接。
  5. 根据权利要求3所述的GOA电路的保护系统，其中，所述第一比较器包括第一、第二、第三、第四、第五、第六、第七、第八薄膜晶体管，其中，第一至第四薄膜晶体管设置在第一排，第一排薄膜晶体管的源极均28V电压电性连接，构成高电位回路；第五、第六、第七、第八薄膜晶体管设置在第二排，第二排薄膜晶体管的漏极均0V电压电性连接，构成低电位回路。
  6. 根据权利要求5所述的GOA电路的保护系统，其中，所述反相器包括第九、第十、第十一、第十二薄膜晶体管，其中，第九薄膜晶体管的栅极、第十二薄膜晶体管的栅极同时与所述第一比较器和所述第二比较器的输出端电性连接，第九薄膜晶体管的漏极与第十二薄膜晶体管的漏极电性连接，且与-10V电压电性连接，构成低电位回路；第九薄膜晶体管的源极与第十一薄膜晶体管源极电性连接，且第九薄膜晶体管的源极与第十薄膜晶体管漏极电性连接，第十薄膜晶体管栅极、第十薄膜晶体管源极及第十一薄膜晶体管源极电性连接，且与28V电压电性连接，构成高电位回路。
  7. 根据权利要求3所述的GOA电路的保护系统，其中，所述第一比较器和所述第二比较器的结构和功能相同，用于输入所述GOA单元中不同的低压信号，若所述第一比较器和所述第二比较器的任一输出输出高电位电压，所述反相器输出低电位电压。
  8. 根据权利要求4所述的GOA电路的保护系统，其中，所述开关薄膜晶体管为N型薄膜晶体管。
  9. 根据权利要求5所述的GOA电路的保护系统，其中，所述第一薄膜晶体管至所述第八薄膜晶体管均为N型薄膜晶体管。
  10. 根据权利要求6所述的GOA电路的保护系统，其中，所述第八薄膜晶体管至所述第十二薄膜晶体管均为N型薄膜晶体管。
  11. 一种液晶显示面板，其包括GOA电路的保护系统，所述GOA电路的保护系统包括：检测电路，与所述GOA电路连接，用于根据所述GOA电路的低电位信号生成对应的驱动信号；以及开关电路，与起始触发信号、所述检测电路以及所述GOA电路连接，所述开关电路用于根据所述驱动信号控制所述GOA电路接入所述起始触发信号；其中，当所述低电位信号为低电平时，所述开关电路导通，所述GOA电路接入所述起始触发信号；当所述低电位信号为高电平时，所述开关电路断开，所述GOA电路不接入所述起始触发信号，所述GOA电路包括多级GOA单元，除了最后一级GOA单元以外，每一级GOA单元的输出扫描信号作为该级GOA单元的下一级GOA单元的级联信号；除了第一级GOA单元以外，每一级GOA单元的输出扫描信号与该级GOA单元的上一级GOA单元的下拉信号，所述下拉信号用于修正上一级GOA单元中扫描信号的波形。
  12. 根据权利要求11所述的液晶显示面板，其中，所述检测电路包括第一比较器和反相器，所述低电位信号包括第一低电位信号；
    所述第一比较器的输入端与所述第一低电位信号连接；所述第一比较器的输出端与所述反相器的输入端连接；所述反相器的输出端与所述开关电路的控制端连接。
  13. 根据权利要求12所述的液晶显示面板，其中，所述低电位信号还包括第二低电位信号，所述检测电路还包括第二比较器；
    所述第二比较器的输入端与所述第二低电位信号连接；所述第二比较器的输出端与所述第一比较器的输出端均和所述反相器的输入端连接。
  14. 根据权利要求11所述的液晶显示面板，其中，所述开关电路包括开关薄膜晶体管；
    所述开关薄膜晶体管的漏极与所述起始触发信号连接；所述开关薄膜晶体管的源极与所述GOA电路连接；所述开关薄膜晶体管的栅极与所述驱动信号连接。
  15. 根据权利要求13所述的液晶显示面板，其中，所述第一比较器包括第一、第二、第三、第四、第五、第六、第七、第八薄膜晶体管，其中，第一至第四薄膜晶体管设置在第一排，第一排薄膜晶体管的源极均28V电压电性连接，构成高电位回路；第五、第六、第七、第八薄膜晶体管设置在第二排，第二排薄膜晶体管的漏极均0V电压电性连接，构成低电位回路。
  16. 根据权利要求15所述的液晶显示面板，其中，所述反相器包括第九、第十、第十一、第十二薄膜晶体管，其中，第九薄膜晶体管的栅极、第十二薄膜晶体管的栅极同时与所述第一比较器和所述第二比较器的输出端电性连接，第九薄膜晶体管的漏极与第十二薄膜晶体管的漏极电性连接，且与-10V电压电性连接，构成低电位回路；第九薄膜晶体管的源极与第十一薄膜晶体管源极电性连接，且第九薄膜晶体管的源极与第十薄膜晶体管漏极电性连接，第十薄膜晶体管栅极、第十薄膜晶体管源极及第十一薄膜晶体管源极电性连接，且与28V电压电性连接，构成高电位回路。
  17. 根据权利要求13所述的液晶显示面板，其中，所述第一比较器和所述第二比较器的结构和功能相同，用于输入所述GOA单元中不同的低压信号，若所述第一比较器和所述第二比较器的任一输出输出高电位电压，所述反相器输出低电位电压。
  18. 根据权利要求14所述的液晶显示面板，其中，所述开关薄膜晶体管为N型薄膜晶体管。
  19. 根据权利要求15所述的液晶显示面板，其中，所述第一薄膜晶体管至所述第八薄膜晶体管均为N型薄膜晶体管。
  20. 根据权利要求16所述的液晶显示面板，其中，所述第八薄膜晶体管至所述第十二薄膜晶体管均为N型薄膜晶体管。
PCT/CN2020/087748 2020-04-03 2020-04-29 用于 goa 电路的保护系统及液晶显示面板 WO2021196330A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/254,902 US11443665B2 (en) 2020-04-03 2020-04-29 Protection system for goa circuit and liquid crystal display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010257397.8 2020-04-03
CN202010257397.8A CN111312194B (zh) 2020-04-03 2020-04-03 用于goa电路的保护系统及液晶显示面板

Publications (1)

Publication Number Publication Date
WO2021196330A1 true WO2021196330A1 (zh) 2021-10-07

Family

ID=71147412

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/087748 WO2021196330A1 (zh) 2020-04-03 2020-04-29 用于 goa 电路的保护系统及液晶显示面板

Country Status (3)

Country Link
US (1) US11443665B2 (zh)
CN (1) CN111312194B (zh)
WO (1) WO2021196330A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11763718B1 (en) * 2022-05-20 2023-09-19 Tcl China Star Optoelectronics Technology Co., Ltd GOA circuit and array substrate

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104092448A (zh) * 2014-06-18 2014-10-08 京东方科技集团股份有限公司 比较器、显示基板和显示装置
CN104700811A (zh) * 2015-03-27 2015-06-10 友达光电股份有限公司 一种驱动控制电路及其 goa 电路的过流保护方法
CN105096876A (zh) * 2015-08-19 2015-11-25 深圳市华星光电技术有限公司 Goa驱动系统及液晶面板
US20160247430A1 (en) * 2015-02-24 2016-08-25 Samsung Display Co., Ltd Display device and method of inspecting the same
CN108303581A (zh) * 2018-02-01 2018-07-20 深圳市华星光电技术有限公司 Goa电路及goa电路过流保护侦测方法
CN109036241A (zh) * 2017-06-09 2018-12-18 三星电子株式会社 显示驱动设备和显示驱动设备的操作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI413050B (zh) * 2009-03-17 2013-10-21 Au Optronics Corp 高可靠度閘極驅動電路
US10488961B2 (en) * 2015-07-17 2019-11-26 Innolux Corporation Gate driving circuit for driving a pixel array having a trigger circuit for receiving a touch sensing signal
CN105304050B (zh) * 2015-11-20 2017-07-25 深圳市华星光电技术有限公司 一种过流保护电路和过流保护方法
CN105448260B (zh) * 2015-12-29 2017-11-03 深圳市华星光电技术有限公司 一种过流保护电路及液晶显示器
CN106297702B (zh) * 2016-08-31 2018-11-23 深圳市华星光电技术有限公司 液晶显示装置及其过流保护电路
CN106128401A (zh) * 2016-08-31 2016-11-16 深圳市华星光电技术有限公司 一种双边阵列基板行驱动电路、液晶显示面板、驱动方法
CN106169289B (zh) * 2016-09-27 2019-01-04 深圳市华星光电技术有限公司 一种阵列基板行驱动电路及其过流保护方法、液晶显示器
CN106409263B (zh) * 2016-11-29 2020-05-22 海信视像科技股份有限公司 液晶面板及其线路短路保护方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104092448A (zh) * 2014-06-18 2014-10-08 京东方科技集团股份有限公司 比较器、显示基板和显示装置
US20160247430A1 (en) * 2015-02-24 2016-08-25 Samsung Display Co., Ltd Display device and method of inspecting the same
CN104700811A (zh) * 2015-03-27 2015-06-10 友达光电股份有限公司 一种驱动控制电路及其 goa 电路的过流保护方法
CN105096876A (zh) * 2015-08-19 2015-11-25 深圳市华星光电技术有限公司 Goa驱动系统及液晶面板
CN109036241A (zh) * 2017-06-09 2018-12-18 三星电子株式会社 显示驱动设备和显示驱动设备的操作方法
CN108303581A (zh) * 2018-02-01 2018-07-20 深圳市华星光电技术有限公司 Goa电路及goa电路过流保护侦测方法

Also Published As

Publication number Publication date
CN111312194A (zh) 2020-06-19
US11443665B2 (en) 2022-09-13
US20220051595A1 (en) 2022-02-17
CN111312194B (zh) 2021-06-22

Similar Documents

Publication Publication Date Title
US10460671B2 (en) Scanning driving circuit and display apparatus
TWI625710B (zh) 閘極驅動電路與採用其之顯示裝置
WO2019104823A1 (zh) 一种goa电路及液晶面板、显示装置
US11037515B2 (en) Shift register unit and method for controlling the same, gate driving circuit, display device
US11749154B2 (en) Gate driver on array circuit and display panel
WO2018126656A1 (zh) 阵列基板行驱动单元、装置、驱动方法及显示装置
US11626050B2 (en) GOA circuit and display panel
WO2020133823A1 (zh) Goa电路
WO2020124822A1 (zh) Goa 电路及显示面板
WO2021223303A1 (zh) Goa 电路和显示面板
JP2008140522A (ja) シフトレジスタ回路およびそれを備える画像表示装置、並びに電圧信号生成回路
US11151959B2 (en) GOA circuit and display device
US7430268B2 (en) Dynamic shift register with built-in disable circuit
WO2021103164A1 (zh) 一种 goa 电路及液晶显示面板
WO2021196330A1 (zh) 用于 goa 电路的保护系统及液晶显示面板
WO2022095159A1 (zh) Goa 电路及其驱动方法、显示面板
WO2021027091A1 (zh) Goa电路及显示面板
US11682330B2 (en) GOA circuit and display panel
WO2023000357A1 (zh) Goa电路
WO2021258539A1 (zh) Mog 电路及显示面板
US20200027383A1 (en) Goa circuit and display panel and display device including the same
CN219534035U (zh) 一种提升gip电路可靠性的新型闸级电路
US11996025B2 (en) Gate driver on array circuit and display panel
CN219105739U (zh) 一种gip驱动前后抗噪电路
CN111161689B (zh) 一种goa电路及其显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20929317

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20929317

Country of ref document: EP

Kind code of ref document: A1