WO2021258539A1 - Mog 电路及显示面板 - Google Patents

Mog 电路及显示面板 Download PDF

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Publication number
WO2021258539A1
WO2021258539A1 PCT/CN2020/111996 CN2020111996W WO2021258539A1 WO 2021258539 A1 WO2021258539 A1 WO 2021258539A1 CN 2020111996 W CN2020111996 W CN 2020111996W WO 2021258539 A1 WO2021258539 A1 WO 2021258539A1
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WIPO (PCT)
Prior art keywords
signal
thin film
film transistor
unit
node
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Application number
PCT/CN2020/111996
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English (en)
French (fr)
Inventor
张典
戴荣磊
Original Assignee
武汉华星光电技术有限公司
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Priority to US17/051,443 priority Critical patent/US11967266B2/en
Publication of WO2021258539A1 publication Critical patent/WO2021258539A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • This application relates to the field of display technology, in particular to the field of MOG driving technology, and in particular to a MOG circuit and a display panel.
  • the scanning signals output by the MOG (Mux On Gate, GOA circuit and MUX circuit combination) circuit in the traditional technical solution are all related to the MUX signal connected to the MUX circuit.
  • the off-state scanning signal that is, the all gate off function
  • the potential state of the scanning signal is adjusted to the off state through the MUX signal, and the size of the thin film transistor in the MUX circuit is limited, and the load that it can bear is therefore limited.
  • the MUX signal needs to jump from a high potential state to a low potential state, which is limited by the load capacity of the MUX circuit, and the output scan signal cannot really reach the off state, which seriously affects all The realization of gate off function.
  • the present application provides a MOG circuit, which solves the problem that the off state of the scan signal is not easily realized due to its load capacity.
  • this application provides a MOG circuit.
  • the MOG circuit is provided with a plurality of cascaded MOG sub-circuits; one of the MOG sub-circuits includes the current-level GOA circuit and the current-level MUX circuit; the current-level GOA circuit is used to generate Corresponding first node signal and second node signal; and the current level MUX circuit, connected with the current level GOA circuit, the first low potential signal and the MUX signal, and used to control the MUX according to the first node signal and/or the second node signal Signal to output the corresponding scan signal; among them, when the MOG circuit outputs the scan signal in the off state, the first node signal controls the MUX circuit at this level to block the input of the MUX signal; and the second node signal controls the MUX circuit at this level , To pull down the potential of the scan signal to the potential of the first low potential signal.
  • the MUX circuit of this level includes at least two MUX units connected in parallel; the first input terminal of the MUX unit is connected with the MUX signal; the second input terminal of the MUX unit is connected with The first low-potential signal is connected; the first control terminal of the MUX unit is connected with the first node signal; the second control terminal of the MUX unit is connected with the second node signal; the output terminal of the MUX unit is used to output the corresponding scanning signal.
  • the GOA circuit of the current stage is connected to the second low potential signal; the first low potential signal and the second low potential signal are the same or different.
  • the GOA circuit at this stage includes a first global control unit; the first end of the first global control unit is signally connected to the first node; The second end of the first global control unit is connected to the second low-level signal; the control end of the first global control unit is connected to the first global control signal; the first global control unit is used to pull down the first global control signal according to the first global control signal. The potential of the one-node signal to the potential of the second low-level signal.
  • the GOA circuit of this stage further includes a second global control unit; the second global control signal and the input end of the second global control unit and The control terminal of the second global control unit is connected; the output terminal of the second global control unit is connected to the first node signal; the second global control unit is used to raise the potential of the first node signal to the second node according to the second global control signal The potential of the global control signal.
  • the GOA circuit of this stage further includes a cascade unit; the input terminal of the cascade unit is connected with a high-potential signal; the control of the cascade unit The terminal is connected to the first node signal of the corresponding stage; the cascade unit is used for controlling the output of the high-potential signal according to the first node signal of the corresponding stage.
  • the GOA circuit of the current stage further includes a first generating unit; the input terminal of the first generating unit is connected with the clock signal of the current stage; The output terminal of a generating unit is connected with the first node signal; the control terminal of the first generating unit is connected with the output terminal of the cascade unit; the first generating unit is used for generating the first node signal.
  • the GOA circuit at this stage further includes a second generating unit; the input of the second generating unit is connected to the third global control signal; The control terminal of the second generating unit is connected with the clock signal of the corresponding stage; the output terminal of the second generating unit is connected with the second node signal; the second generating unit is used for generating the second node signal.
  • the GOA circuit at this level further includes a first pull-down unit; the first terminal of the first pull-down unit and the second low-potential signal Connection; the second end of the first pull-down unit is connected to the output end of the cascade unit; the control end of the first pull-down unit is connected to the second node signal; the first pull-down unit is used to pull down the level according to the second node signal
  • the potential of the output terminal of the connection unit is to the potential of the second low potential signal.
  • the GOA circuit at this stage further includes a second pull-down unit; the first end of the second pull-down unit is connected to the second low-potential signal; The second end of the second pull-down unit is connected to the first node signal; the control end of the second pull-down unit is connected to the second low-level signal; the second pull-down unit is used to pull down the first node signal according to the second low-level signal Potential to the potential of the second low potential signal.
  • the present application provides a display panel, which includes the MOG circuit in any of the above embodiments.
  • the MOG circuit provided in this application controls the MUX circuit of the current level through the first node signal, blocking the input of the MUX signal; at the same time, controls the MUX circuit of the current level through the second node signal to pull down the potential of the scan signal to the first low
  • the potential of the potential signal, and in the case of reducing the load of the MUX circuit, all the scanning signals are placed in the off state.
  • FIG. 1 is a schematic structural diagram of a MOG circuit provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of the first circuit of the MOG circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of the second circuit of the MOG circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of waveforms of related signals in the MOG circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • this embodiment provides a MOG circuit.
  • the MOG circuit is provided with a plurality of cascaded MOG sub-circuits; one of the MOG sub-circuits includes the current-level GOA circuit 100 and the current-level MUX circuit 200; the current-level GOA
  • the circuit 100 is used to generate the corresponding first node signal JS1 (N) and the second node signal JS2 (N); and the current level MUX circuit 200, which is connected to the current level GOA circuit 100, the first low potential signal VGL1 and the MUX signal , Used to control the MUX signal according to the first node signal JS1(N) and/or the second node signal JS2(N) to output the corresponding scan signal; wherein, when the MOG circuit outputs the scan signal in the off state, the first node The signal JS1(N) controls the MUX circuit 200 of the current level to block the input of the MUX signal; and the second node signal JS2(N) controls the MUX
  • the MOG circuit provided by the present application controls the MUX circuit 200 of the current stage through the first node signal JS1(N), blocking the input of the MUX signal; at the same time, controls the current stage through the second node signal JS2(N)
  • the MUX circuit 200 pulls down the potential of the scan signal to the potential of the first low potential signal VGL1, and then places all the scan signals in the off state when the load of the MUX circuit is reduced. This situation can effectively prevent the MUX circuit from being overloaded and affecting the normal drive inside the display panel.
  • the MUX circuit 200 of this stage includes at least two MUX units 10 connected in parallel; the first input terminal of the MUX unit 10 is connected with the MUX signal; the second input terminal of the MUX unit 10 is connected with The first low potential signal VGL1 is connected; the first control terminal of the MUX unit 10 is connected to the first node signal JS1(N); the second control terminal of the MUX unit 10 is connected to the second node signal JS2(N); The output terminal is used to output the corresponding scan signal.
  • each MUX unit 10 may include a first thin film transistor T1 and a second thin film transistor T2; the input terminal of the first thin film transistor T1 is connected to the corresponding MUX signal; the output terminal of the first thin film transistor T1 is connected to the first thin film transistor T1.
  • the input terminals of the two thin film transistors T2 are connected and serve as the output node of one of the scanning signals; the output terminal of the second thin film transistor T2 is connected to the first low potential signal VGL1; the first node signal JS1(N) is connected to the first thin film transistor T1
  • the gate of the second node signal JS2 (N) is connected to the gate of the second thin film transistor T2.
  • the number of MUX units 10 included in the MUX circuit 200 at this level can be but not limited to two, or three, or six, or nine, or twelve, etc., depending on the application of the product.
  • the number of MUX units 10 needs to be flexibly configured.
  • the first MUX unit 10 is connected to the Nth level MUX signal MUX(N), and correspondingly outputs the Nth level scanning signal G(N); the second MUX unit 10 The unit 10 is connected to the N+1 level MUX signal MUX(N+1), and correspondingly outputs the N+1 level scanning signal G(N+1); the third MUX unit 10 is connected to the N+2 level MUX signal MUX (N+2), corresponding to the output of the N+2 level scanning signal G (N+2).
  • the GOA circuit 100 of the current stage is connected to the second low potential signal VGL2; the first low potential signal VGL1 and the second low potential signal VGL2 are the same or different.
  • the first low-level signal VGL1 and the second low-level signal VGL2 are the same, that is, the GOA circuit 100 and the MUX circuit 200 of the current level use the same low level signal, which can save the number of signals required by the MOG circuit.
  • the first low-potential signal VGL1 is different from the second low-potential signal VGL2, that is, the current-level MUX circuit 200 and the current-level GOA circuit 100 respectively use the first low-potential signal VGL1 and the second low-potential signal VGL2.
  • the two circuits Using low-potential signals separately can reduce or eliminate crosstalk between low-potential signals between two circuits, avoid affecting the normal operation of the MOG circuit, and improve the reliability of the MOG circuit.
  • the GOA circuit 100 at this stage includes a first global control unit 20; the first end of the first global control unit 20 is connected to the first node signal JS1(N); The second end of the control unit 20 is connected to the second low-potential signal VGL2; the control end of the first global control unit 20 is connected to the first global control signal GAS1; the first global control unit 20 is used to, according to the first global control signal GAS1, Pull down the potential of the first node signal JS1 (N) to the potential of the second low potential signal VGL2.
  • the first global control unit 20 includes a third thin film transistor T3; the input terminal of the third thin film transistor T3 is connected to the second low potential signal VGL2; the output terminal of the third thin film transistor T3 is connected to the first node signal JS1 (N) Connection: The control terminal of the third thin film transistor T3 is connected to the first global control signal GAS1.
  • the GOA circuit 100 at this stage further includes a second global control unit 30; the second global control signal GAS2 and the input terminal of the second global control unit 30 and the second global control unit 30
  • the output terminal of the second global control unit 30 is connected to the first node signal JS1(N); the second global control unit 30 is used to raise the first node signal JS1(N) according to the second global control signal GAS2 ) To the potential of the second global control signal GAS2.
  • the second global control unit 30 includes a fourth thin film transistor T4; the output terminal of the fourth thin film transistor T4 is connected to the first node signal JS1(N); the second global control signal GAS2 and the fourth thin film transistor T4 The input terminal of is connected to the gate of the fourth thin film transistor T4.
  • the GOA circuit 100 of this stage further includes a cascade unit 40; the input terminal of the cascade unit 40 is connected to the high-potential signal VGH; the control terminal of the cascade unit 40 is connected to the corresponding stage
  • the first node signal JS1(N) is connected; the cascade unit 40 is used to control the output of the high potential signal VGH according to the first node signal JS1(N) of the corresponding stage.
  • the cascade unit 40 may include a fifth thin film transistor T5; the input terminal of the fifth thin film transistor T5 is connected to the high potential signal VGH; the gate of the fifth thin film transistor T5 may be, but is not limited to, the same as that of the upper stage.
  • the first node signal JS(N-1) connection may also be the first node signal JS1(N) connection of other levels.
  • the GOA circuit 100 of the current stage further includes a first generating unit 50; the input terminal of the first generating unit 50 is connected to the clock signal CK(N) of the current stage; the first generating unit 50 The output terminal of is connected with the first node signal JS1(N); the control terminal of the first generating unit 50 is connected with the output terminal of the cascade unit 40; the first generating unit 50 is used to generate the first node signal JS1(N).
  • the first generating unit 50 may include a sixth thin film transistor T6; the gate of the sixth thin film transistor T6 is connected to the output terminal of the fifth thin film transistor T5; the input terminal of the sixth thin film transistor T6 is connected to the current stage Clock signal CK (N); the output terminal of the sixth thin film transistor T6 is used to output the corresponding first node signal JS1 (N).
  • the GOA circuit 100 of this stage further includes a second generating unit 60; the input of the second generating unit 60 is connected to the third global control signal GAS3; the control of the second generating unit 60 The terminal is connected with the clock signal of the corresponding stage; the output terminal of the second generating unit 60 is connected with the second node signal JS2(N); the second generating unit 60 is used to generate the second node signal JS2(N).
  • the second generating unit 60 may include a seventh thin film transistor T7; the input end of the seventh thin film transistor T7 is connected to the third global control signal GAS3; the gate of the seventh thin film transistor T7 may but is not limited to be connected to The clock signal CK(N+1) of the upper stage may also be a clock signal of other stages; the output terminal of the seventh thin film transistor T7 is used to output the corresponding second node signal JS2(N).
  • the GOA circuit 100 of this stage further includes a first pull-down unit 70; the first end of the first pull-down unit 70 is connected to the second low-level signal VGL2; The second end of the unit 70 is connected to the output end of the cascade unit 40; the control end of the first pull-down unit 70 is connected to the second node signal JS2(N); the first pull-down unit 70 is used to respond to the second node signal JS2 (N), pull down the potential of the output terminal of the cascade unit 40 to the potential of the second low potential signal VGL2.
  • the first pull-down unit 70 may include an eighth thin film transistor T8; the input terminal of the eighth thin film transistor T8 is connected to the second low potential signal VGL2; the output terminal of the eighth thin film transistor T8 is connected to the fifth thin film transistor The output terminal of T5 is connected to the gate of the sixth thin film transistor T6; the gate of the eighth thin film transistor T8 is connected to the output terminal of the seventh thin film transistor T7 and the gate of the second thin film transistor T2.
  • the GOA circuit 100 of this stage further includes a second pull-down unit 80; the first end of the second pull-down unit 80 is connected to the second low-potential signal VGL2; The second end is connected to the first node signal JS1(N); the control end of the second pull-down unit 80 is connected to the second low-level signal VGL2; the second pull-down unit 80 is used to pull down the first low-level signal VGL2.
  • the potential of the node signal JS1 (N) is to the potential of the second low potential signal VGL2.
  • the second pull-down unit 80 may include a ninth thin film transistor T9; the input terminal of the ninth thin film transistor T9 is connected to the second low potential signal VGL2; the output terminal of the ninth thin film transistor T9 is connected to the sixth thin film transistor T6 The output terminal of the first thin film transistor T1, the output terminal of the third thin film transistor T3, and the output terminal of the fourth thin film transistor T4 are connected; the gate of the ninth thin film transistor T9 is connected to the output terminal of the seventh thin film transistor T7 .
  • the first thin film transistor T1 to the ninth thin film transistor T9 in the above-mentioned embodiment can be, but not limited to, N-type thin film transistors; they can also be P-type thin film transistors or other types that can achieve corresponding functions. Thin film transistors.
  • the work of the MOG circuit provided by the present disclosure may include the following stages:
  • the level states of the first global control signal GAS1, the second global control signal GAS2, and the third global control signal GAS3 are all in an invalid state, and the corresponding unit cannot be controlled to work.
  • the MOG circuit is connected to the MUX Signal, and output the corresponding scan signal.
  • Black screen wake-up stage In this stage, the Low Power Wake-up Gesture (LPWG) function will be performed. As shown in Fig. 4, the implementation of this function includes two stages.
  • the potential of a node signal JS1 (N) is pulled high, and the MUX signal output is the corresponding scanning signal.
  • the scanning signals are all high (all gate on), to turn on all pixel circuits to erase the screen; the second stage T2: In order to further save power consumption, the scanning signal can be set to low level (all gate off), at this time, the first global control signal GAS1 is In the effective state, the first global control unit 20 can pull down the potential of the first node signal JS1(N) to prevent the input of the MUX signal.
  • the third global control signal GAS3 is in the effective state, and the clock signal of the corresponding level is controlled
  • the second node signal JS2(N) controls the MUX circuit 200 at this stage to pull all the scanning signals down to the first low level signal VGL1/second low The potential of the potential signal VGL2 to achieve the all gate off function.
  • the MUX signal is not used to pull down the potential of the scan signal, and then all gate lines are turned off; instead, the all gate off function is implemented through the above-mentioned working process.
  • the MUX circuit 200 of the current level bears the transition process of the scanning signal, and therefore, the load condition of the MUX circuit 200 of the current level can be reduced, and the subsequent work can be avoided or affected, thereby adversely affecting the gate driving and causing abnormal display of the screen.
  • the present application provides a display panel, which includes the MOG circuit in any of the above embodiments.
  • the display panel further includes a signal generator; the signal generator 300 is connected to the MUX circuit 200 of the current stage for providing corresponding MUX signals. It can be understood that the signal generator 300 can generate the required MUX signal.
  • the MOG circuit provided by the present disclosure can be, but is not limited to, a row scan (Gate) drive circuit integrated on an array substrate, and can also be a gate drive circuit applied to the fields of mobile phones, displays, televisions, etc.
  • the MOG circuit provided in the present disclosure can be applied to the field of liquid crystal display or self-luminous display technology, and can also be applied to OLED display technology.

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Abstract

本申请公开了一种MOG电路及显示面板，通过第一节点信号控制本级MUX电路，阻断了MUX信号的输入；同时，通过第二节点信号控制本级MUX电路，将扫描信号的电位拉低至第一低电位信号的电位，进而在降低MUX电路带载的情况下，将所有的扫描信号置于关断状态。

Description

MOG电路及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及MOG驱动技术领域，具体涉及一种MOG电路及显示面板。
 背景技术
传统技术方案中的MOG（Mux On Gate，GOA电路与MUX电路的结合）电路输出的扫描信号均与MUX电路接入的MUX信号相关，在需要输出关断状态的扫描信号即all gate off功能时，通常是通过MUX信号将扫描信号的电位状态调节至关断状态的，而MUX电路中薄膜晶体管的尺寸受到限制，其可以承受的负荷也因此受到限制。
于是，在实现all gate off功能时，MUX信号需要从高电位状态跳变至低电位状态，受限于MUX电路的带载能力，其输出的扫描信号不能够真正达到关断状态，严重影响了all gate off功能的实现。
 技术问题
本申请提供一种MOG电路，解决了受限于其带载能力，扫描信号的关断状态不易实现的问题。
 技术解决方案
第一方面，本申请提供了一种MOG电路，MOG电路设置有多个级联的MOG子电路；其中一个MOG子电路包括本级GOA电路和本级MUX电路；本级GOA电路，用于生成对应的第一节点信号和第二节点信号；和本级MUX电路，与本级GOA电路、第一低电位信号以及MUX信号连接，用于根据第一节点信号和/或第二节点信号控制MUX信号，以输出对应的扫描信号；其中，MOG电路输出关断状态的扫描信号时，第一节点信号控制本级MUX电路，以阻断MUX信号的输入；且第二节点信号控制本级MUX电路，以拉低扫描信号的电位至第一低电位信号的电位。
基于第一方面，在第一方面的第一种实施方式中，本级MUX电路包括至少两个并联的MUX单元；MUX单元的第一输入端与MUX信号连接；MUX单元的第二输入端与第一低电位信号连接；MUX单元的第一控制端与第一节点信号连接；MUX单元的第二控制端与第二节点信号连接；MUX单元的输出端用于输出对应的扫描信号。
基于第一方面，在第一方面的第二种实施方式中，本级GOA电路与第二低电位信号连接；第一低电位信号与第二低电位信号相同或者相异。
基于第一方面的第二种实施方式，在第一方面的第三种实施方式中，本级GOA电路包括第一全局控制单元；第一全局控制单元的第一端与第一节点信号连接；第一全局控制单元的第二端与第二低电位信号连接；第一全局控制单元的控制端与第一全局控制信号连接；第一全局控制单元用于根据第一全局控制信号，拉低第一节点信号的电位至第二低电位信号的电位。
基于第一方面的第三种实施方式，在第一方面的第四种实施方式中，本级GOA电路还包括第二全局控制单元；第二全局控制信号与第二全局控制单元的输入端和第二全局控制单元的控制端连接；第二全局控制单元的输出端与第一节点信号连接；第二全局控制单元用于根据第二全局控制信号，拉高第一节点信号的电位至第二全局控制信号的电位。
基于第一方面的第四种实施方式，在第一方面的第五种实施方式中，本级GOA电路还包括级联单元；级联单元的输入端与高电位信号连接；级联单元的控制端与对应级的第一节点信号连接；级联单元用于根据对应级的第一节点信号控制高电位信号的输出。
基于第一方面的第五种实施方式，在第一方面的第六种实施方式中，本级GOA电路还包括第一生成单元；第一生成单元的输入端与本级的时钟信号连接；第一生成单元的输出端与第一节点信号连接；第一生成单元的控制端与级联单元的输出端连接；第一生成单元用于生成第一节点信号。
基于第一方面的第六种实施方式，在第一方面的第七种实施方式中，本级GOA电路还包括第二生成单元；第二生成单元的输入端与第三全局控制信号连接；第二生成单元的控制端与对应级的时钟信号连接；第二生成单元的输出端与第二节点信号连接；第二生成单元用于生成第二节点信号。
基于第一方面的第七种实施方式，在第一方面的第八种实施方式中，本级GOA电路还包括第一下拉单元；第一下拉单元的第一端与第二低电位信号连接；第一下拉单元的第二端与级联单元的输出端连接；第一下拉单元的控制端与第二节点信号连接；第一下拉单元用于根据第二节点信号，拉低级联单元的输出端电位至第二低电位信号的电位。
基于第一方面的第八种实施方式，在第一方面的第九种实施方式中，本级GOA电路还包括第二下拉单元；第二下拉单元的第一端与第二低电位信号连接；第二下拉单元的第二端与第一节点信号连接；第二下拉单元的控制端与第二低电位信号连接；第二下拉单元用于根据第二低电位信号，拉低第一节点信号的电位至第二低电位信号的电位。
第二方面，本申请提供了一种显示面板，其包括上述任一实施方式中的MOG电路。
 有益效果
本申请提供的MOG电路，通过第一节点信号控制本级MUX电路，阻断了MUX信号的输入；同时，通过第二节点信号控制本级MUX电路，将扫描信号的电位拉低至第一低电位信号的电位，进而在降低MUX电路带载的情况下，将所有的扫描信号置于关断状态。
 附图说明
图1为本申请实施例提供的MOG电路的结构示意图。
图2为本申请实施例提供的MOG电路的第一种电路原理图。
图3为本申请实施例提供的MOG电路的第二种电路原理图。
图4为本申请实施例提供的MOG电路中相关信号的波形示意图。
图5为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
如图1所示，本实施例提供了一种MOG电路，MOG电路设置有多个级联的MOG子电路；其中一个MOG子电路包括本级GOA电路100和本级MUX电路200；本级GOA电路100，用于生成对应的第一节点信号JS1（N）和第二节点信号JS2(N)；和本级MUX电路200，与本级GOA电路100、第一低电位信号VGL1以及MUX信号连接，用于根据第一节点信号JS1（N）和/或第二节点信号JS2(N)控制MUX信号，以输出对应的扫描信号；其中，MOG电路输出关断状态的扫描信号时，第一节点信号JS1（N）控制本级MUX电路200，以阻断MUX信号的输入；且第二节点信号JS2（N）控制本级MUX电路200，以拉低扫描信号的电位至第一低电位信号VGL1的电位。
可以理解的是，本申请提供的MOG电路，通过第一节点信号JS1（N）控制本级MUX电路200，阻断了MUX信号的输入；同时，通过第二节点信号JS2（N）控制本级MUX电路200，将扫描信号的电位拉低至第一低电位信号VGL1的电位，进而在降低MUX电路带载的情况下，将所有的扫描信号置于关断状态。这种情况可以有效避免MUX电路带载过重而影响显示面板内部的正常驱动。
如图2所示，在其中一个实施例中，本级MUX电路200包括至少两个并联的MUX单元10；MUX单元10的第一输入端与MUX信号连接；MUX单元10的第二输入端与第一低电位信号VGL1连接；MUX单元10的第一控制端与第一节点信号JS1（N）连接；MUX单元10的第二控制端与第二节点信号JS2（N）连接；MUX单元10的输出端用于输出对应的扫描信号。
需要进行说明的是，每个MUX单元10可以包括第一薄膜晶体管T1和第二薄膜晶体管T2；第一薄膜晶体管T1的输入端与对应的MUX信号连接；第一薄膜晶体管T1的输出端与第二薄膜晶体管T2的输入端连接，并作为其中一个扫描信号的输出节点；第二薄膜晶体管T2的输出端与第一低电位信号VGL1连接；第一节点信号JS1（N）与第一薄膜晶体管T1的栅极连接；第二节点信号JS2（N）与第二薄膜晶体管T2的栅极连接。
需要进行说明的是，本级MUX电路200包括的MUX单元10数量可以但不限于为两个，也可以是三个，或者六个，或者九个，或者十二个等，可以根据产品应用的需求灵活配置MUX单元10的数量。
例如，当本级MUX电路200包括三个MUX单元10时，第一个MUX单元10接入第N级MUX信号MUX（N），对应输出第N级扫描信号G（N）；第二个MUX单元10接入第N+1级MUX信号MUX（N+1），对应输出第N+1级扫描信号G（N+1）；第三个MUX单元10接入第N+2级MUX信号MUX（N+2），对应输出第N+2级扫描信号G（N+2）。
如图2和/或图3所示，在其中一个实施例中，本级GOA电路100与第二低电位信号VGL2连接；第一低电位信号VGL1与第二低电位信号VGL2相同或者相异。
可以理解的是，第一低电位信号VGL1与第二低电位信号VGL2相同，即为本级GOA电路100、本级MUX电路200共同使用同一低电位信号，可以节省MOG电路所需要的信号数量。第一低电位信号VGL1与第二低电位信号VGL2相异，即为本级MUX电路200、本级GOA电路100分别对应使用第一低电位信号VGL1、第二低电位信号VGL2，该两个电路分开单独使用低电位信号，可以减少或者消除两个电路之间低电位信号发生相互串扰，避免影响MOG电路的正常工作，进而提升MOG电路的工作可靠性。
如图3所示，在其中一个实施例中，本级GOA电路100包括第一全局控制单元20；第一全局控制单元20的第一端与第一节点信号JS1（N）连接；第一全局控制单元20的第二端与第二低电位信号VGL2连接；第一全局控制单元20的控制端与第一全局控制信号GAS1连接；第一全局控制单元20用于根据第一全局控制信号GAS1，拉低第一节点信号JS1（N）的电位至第二低电位信号VGL2的电位。
需要进行说明的是，第一全局控制单元20包括第三薄膜晶体管T3；第三薄膜晶体管T3的输入端与第二低电位信号VGL2连接；第三薄膜晶体管T3的输出端与第一节点信号JS1（N）连接；第三薄膜晶体管T3的控制端与第一全局控制信号GAS1连接。
如图3所示，在其中一个实施例中，本级GOA电路100还包括第二全局控制单元30；第二全局控制信号GAS2与第二全局控制单元30的输入端和第二全局控制单元30的控制端连接；第二全局控制单元30的输出端与第一节点信号JS1（N）连接；第二全局控制单元30用于根据第二全局控制信号GAS2，拉高第一节点信号JS1（N）的电位至第二全局控制信号GAS2的电位。
需要进行说明的是，第二全局控制单元30包括第四薄膜晶体管T4；第四薄膜晶体管T4的输出端与第一节点信号JS1（N）连接；第二全局控制信号GAS2与第四薄膜晶体管T4的输入端和第四薄膜晶体管T4的栅极连接。
如图3所示，在其中一个实施例中，本级GOA电路100还包括级联单元40；级联单元40的输入端与高电位信号VGH连接；级联单元40的控制端与对应级的第一节点信号JS1（N）连接；级联单元40用于根据对应级的第一节点信号JS1（N）控制高电位信号VGH的输出。
需要进行说明的是，级联单元40可以包括第五薄膜晶体管T5；第五薄膜晶体管T5的输入端接入高电位信号VGH；第五薄膜晶体管T5的栅极可以但不限于与上一级的第一节点信号JS（N-1）连接，也可以是其他级的第一节点信号JS1（N）连接。
如图3所示，在其中一个实施例中，本级GOA电路100还包括第一生成单元50；第一生成单元50的输入端与本级时钟信号CK（N）连接；第一生成单元50的输出端与第一节点信号JS1（N）连接；第一生成单元50的控制端与级联单元40的输出端连接；第一生成单元50用于生成第一节点信号JS1（N）。
需要进行说明的是，第一生成单元50可以包括第六薄膜晶体管T6；第六薄膜晶体管T6的栅极与第五薄膜晶体管T5的输出端连接；第六薄膜晶体管T6的输入端接入本级时钟信号CK（N）；第六薄膜晶体管T6的输出端用于输出对应的第一节点信号JS1（N）。
如图3所示，在其中一个实施例中，本级GOA电路100还包括第二生成单元60；第二生成单元60的输入端与第三全局控制信号GAS3连接；第二生成单元60的控制端与对应级的时钟信号连接；第二生成单元60的输出端与第二节点信号JS2（N）连接；第二生成单元60用于生成第二节点信号JS2（N）。
需要进行说明的是，第二生成单元60可以包括第七薄膜晶体管T7；第七薄膜晶体管T7的输入端接入第三全局控制信号GAS3；第七薄膜晶体管T7的栅极可以但不限于接入上一级时钟信号CK（N+1），也可以是其他级的时钟信号；第七薄膜晶体管T7的输出端用于输出对应的第二节点信号JS2（N）。
如图3所示，在其中一个实施例中，本级GOA电路100还包括第一下拉单元70；第一下拉单元70的第一端与第二低电位信号VGL2连接；第一下拉单元70的第二端与级联单元40的输出端连接；第一下拉单元70的控制端与第二节点信号JS2（N）连接；第一下拉单元70用于根据第二节点信号JS2（N），拉低级联单元40的输出端电位至第二低电位信号VGL2的电位。
需要进行说明的是，第一下拉单元70可以包括第八薄膜晶体管T8；第八薄膜晶体管T8的输入端与第二低电位信号VGL2连接；第八薄膜晶体管T8的输出端与第五薄膜晶体管T5的输出端和第六薄膜晶体管T6的栅极连接；第八薄膜晶体管T8的栅极与第七薄膜晶体管T7的输出端和第二薄膜晶体管T2的栅极连接。
如图3所示，在其中一个实施例中，本级GOA电路100还包括第二下拉单元80；第二下拉单元80的第一端与第二低电位信号VGL2连接；第二下拉单元80的第二端与第一节点信号JS1（N）连接；第二下拉单元80的控制端与第二低电位信号VGL2连接；第二下拉单元80用于根据第二低电位信号VGL2，拉低第一节点信号JS1（N）的电位至第二低电位信号VGL2的电位。
需要进行说明的是，第二下拉单元80可以包括第九薄膜晶体管T9；第九薄膜晶体管T9的输入端与第二低电位信号VGL2连接；第九薄膜晶体管T9的输出端与第六薄膜晶体管T6的输出端、第一薄膜晶体管T1的栅极、第三薄膜晶体管T3的输出端以及第四薄膜晶体管T4的输出端连接；第九薄膜晶体管T9的栅极与第七薄膜晶体管T7的输出端连接。
需要进行说明的是，对于上述实施例中的第一薄膜晶体管T1至第九薄膜晶体管T9均可以但不限于为N型薄膜晶体管；也可以为能够实现对应作用的P型薄膜晶体管或者其他类型的薄膜晶体管。
可以理解的是，上述实施例中的各种信号可以根据MOG电路的需求，给出对应的高电位状态和/或低电位状态，以便实现在本公开中的对应作用。
综上所述，本公开提供的MOG电路的工作可以包括以下几个阶段：
正常工作阶段：第一全局控制信号GAS1、第二全局控制信号GAS2以及第三全局控制信号GAS3的电平状态均为无效状态，不能够控制对应的单元进行工作，此时，MOG电路接入MUX信号，并输出对应的扫描信号。
黑屏唤醒阶段：在该阶段中，会进行黑屏手势唤醒(Low Power Wake-up Gesture,LPWG)功能。如图4所示，该功能的实施包括两个阶段，第一阶段T1：第二全局控制信号GAS2的电平状态为有效状态，例如，可以为高电平，第二全局控制单元30将第一节点信号JS1（N）的电位拉高，MUX信号输出为对应的扫描信号，此时的扫描信号均为高电位（all gate on），以打开全部的像素电路进行画面擦黑；第二阶段T2：为了进一步节约功耗，可以把扫描信号均置为低电位（all gate off），此时，第一全局控制信号GAS1为有效状态，可以通过第一全局控制单元20拉低第一节点信号JS1（N）的电位，进而阻止MUX信号的输入，同时第三全局控制信号GAS3为有效状态，在对应级的时钟信号的控制下，第二节点信号JS2（N）也为有效状态，此时，第二节点信号JS2（N）控制本级MUX电路200，将扫描信号全部拉低至第一低电位信号VGL1/第二低电位信号VGL2的电位，从而实现的all gate off功能。
基于上述可知，本公开在实现all gate off功能时，并没有通过MUX信号来拉低扫描信号的电位，进而关闭所有栅线；而是通过上述的工作过程来实现all gate off功能的，不需要本级MUX电路200承受扫描信号的跳变过程，因此，可以减轻本级MUX电路200的负载情况，避免影响或者波及到后续的工作，进而给栅极驱动造成不良影响，导致画面显示异常。
在其中一个实施例中，本申请提供了一种显示面板，其包括上述任一实施方式中的MOG电路。
如图5所示，在其中一个实施例中，显示面板还包括信号发生器；信号发生器300与本级MUX电路200连接，用于提供对应的MUX信号。可以理解的是，信号发生器300可以生成需要的MUX信号。
综上所述，本公开提供的MOG电路可以但不限于为集成在阵列基板上的行扫描（Gate）驱动电路，也可以为应用于手机、显示器、电视等领域的栅极驱动电路。本公开提供的MOG电路可以应用于液晶显示或者自发光显示技术领域，也可以应用于OLED显示技术中。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种MOG电路，其中，所述MOG电路设置有多个级联的MOG子电路；其中一个所述MOG子电路包括：
    本级GOA电路，用于生成对应的第一节点信号和第二节点信号；和
    本级MUX电路，与所述本级GOA电路、第一低电位信号以及MUX信号连接，用于根据所述第一节点信号和/或所述第二节点信号控制所述MUX信号，以输出对应的扫描信号；
    其中，所述MOG电路输出关断状态的所述扫描信号时，所述第一节点信号控制所述本级MUX电路，以阻断所述MUX信号的输入；且所述第二节点信号控制所述本级MUX电路，以拉低所述扫描信号的电位至所述第一低电位信号的电位。
  2. 根据权利要求1所述的MOG电路，其中，所述本级MUX电路包括至少两个并联的MUX单元；
    所述MUX单元的第一输入端与所述MUX信号连接；所述MUX单元的第二输入端与所述第一低电位信号连接；所述MUX单元的第一控制端与所述第一节点信号连接；所述MUX单元的第二控制端与所述第二节点信号连接；
    所述MUX单元的输出端用于输出对应的所述扫描信号。
  3. 根据权利要求1所述的MOG电路，其中，所述本级GOA电路与第二低电位信号连接；所述第一低电位信号与所述第二低电位信号相同或者相异。
  4. 根据权利要求3所述的MOG电路，其中，所述本级GOA电路包括第一全局控制单元；
    所述第一全局控制单元的第一端与所述第一节点信号连接；所述第一全局控制单元的第二端与所述第二低电位信号连接；所述第一全局控制单元的控制端与第一全局控制信号连接；
    所述第一全局控制单元用于根据所述第一全局控制信号，拉低所述第一节点信号的电位至所述第二低电位信号的电位。
  5. 根据权利要求4所述的MOG电路，其中，所述本级GOA电路还包括第二全局控制单元；
    第二全局控制信号与所述第二全局控制单元的输入端和所述第二全局控制单元的控制端连接；所述第二全局控制单元的输出端与所述第一节点信号连接；
    所述第二全局控制单元用于根据所述第二全局控制信号，拉高所述第一节点信号的电位至所述第二全局控制信号的电位。
  6. 根据权利要求5所述的MOG电路，其中，所述本级GOA电路还包括级联单元；
    所述级联单元的输入端与高电位信号连接；所述级联单元的控制端与对应级的所述第一节点信号连接；
    所述级联单元用于根据对应级的所述第一节点信号控制所述高电位信号的输出。
  7. 根据权利要求6所述的MOG电路，其中，所述本级GOA电路还包括第一生成单元；
    所述第一生成单元的输入端与本级的时钟信号连接；所述第一生成单元的输出端与所述第一节点信号连接；所述第一生成单元的控制端与所述级联单元的输出端连接；
    所述第一生成单元用于生成所述第一节点信号。
  8. 根据权利要求7所述的MOG电路，其中，所述本级GOA电路还包括第二生成单元；
    所述第二生成单元的输入端与第三全局控制信号连接；所述第二生成单元的控制端与对应级的时钟信号连接；所述第二生成单元的输出端与所述第二节点信号连接；
    所述第二生成单元用于生成所述第二节点信号。
  9. 根据权利要求8所述的MOG电路，其中，所述本级GOA电路还包括第一下拉单元；
    所述第一下拉单元的第一端与所述第二低电位信号连接；所述第一下拉单元的第二端与所述级联单元的输出端连接；所述第一下拉单元的控制端与所述第二节点信号连接；
    所述第一下拉单元用于根据所述第二节点信号，拉低所述级联单元的输出端电位至所述第二低电位信号的电位。
  10. 根据权利要求9所述的MOG电路，其中，MUX单元包括第一薄膜晶体管和第二薄膜晶体管；
    所述第一薄膜晶体管的输入端与对应的所述MUX信号连接；所述第一薄膜晶体管的输出端与所述第二薄膜晶体管的输入端连接，并作为其中一个扫描信号的输出节点；所述第二薄膜晶体管的输出端与第一低电位信号连接；第一节点信号与所述第一薄膜晶体管的栅极连接；第二节点信号与所述第二薄膜晶体管的栅极连接。
  11. 根据权利要求10所述的MOG电路，其中，所述第一全局控制单元包括第三薄膜晶体管；
    所述第三薄膜晶体管的输入端与所述第二低电位信号连接；所述第三薄膜晶体管的输出端与所述第一节点信号连接；所述第三薄膜晶体管的控制端与所述第一全局控制信号连接。
  12. 根据权利要求11所述的MOG电路，其中，所述第二全局控制单元包括第四薄膜晶体管；
    所述第四薄膜晶体管的输出端与所述第一节点信号连接；所述第二全局控制信号与所述第四薄膜晶体管的输入端和所述第四薄膜晶体管的栅极连接。
  13. 根据权利要求12所述的MOG电路，其中，所述级联单元包括第五薄膜晶体管；
    所述第五薄膜晶体管的输入端接入所述高电位信号；所述第五薄膜晶体管的栅极与所述第一节点信号连接。
  14. 根据权利要求13所述的MOG电路，其中，所述第一生成单元包括第六薄膜晶体管；
    所述第六薄膜晶体管的栅极与所述第五薄膜晶体管的输出端连接；所述第六薄膜晶体管的输入端接入所述本级的时钟信号；所述第六薄膜晶体管的输出端用于输出对应的所述第一节点信号。
  15. 根据权利要求14所述的MOG电路，其中，所述第二生成单元包括第七薄膜晶体管；
    所述第七薄膜晶体管的输入端接入所述第三全局控制信号；所述第七薄膜晶体管的栅极接入所述对应级的时钟信号；所述第七薄膜晶体管的输出端用于输出对应的所述第二节点信号。
  16. 根据权利要求15所述的MOG电路，其中，所述第一下拉单元包括第八薄膜晶体管；
    所述第八薄膜晶体管的输入端与所述第二低电位信号连接；所述第八薄膜晶体管的输出端与所述第五薄膜晶体管的输出端和所述第六薄膜晶体管的栅极连接；所述第八薄膜晶体管的栅极与所述第七薄膜晶体管的输出端和所述第二薄膜晶体管的栅极连接。
  17. 根据权利要求16所述的MOG电路，其中，所述第二下拉单元包括第九薄膜晶体管；
    所述第九薄膜晶体管的输入端与所述第二低电位信号连接；所述第九薄膜晶体管的输出端与所述第六薄膜晶体管的输出端、所述第一薄膜晶体管的栅极、所述第三薄膜晶体管的输出端以及所述第四薄膜晶体管的输出端连接；所述第九薄膜晶体管的栅极与所述第七薄膜晶体管的输出端连接。
  18. 根据权利要求17所述的MOG电路，其中，所述第九薄膜晶体管为N型薄膜晶体管。
  19. 一种显示面板，其中，包括如权利要求1所述的MOG电路。
  20. 根据权利要求19所述的显示面板，其中，所述显示面板还包括信号发生器；
    所述信号发生器与所述本级MUX电路连接，用于提供对应的所述MUX信号至所述本级MUX电路。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111754951A (zh) * 2020-07-15 2020-10-09 武汉华星光电技术有限公司 一种mog电路及显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104103321A (zh) * 2013-04-04 2014-10-15 株式会社半导体能源研究所 脉冲发生电路及半导体装置
CN106486043A (zh) * 2015-08-25 2017-03-08 中华映管股份有限公司 栅极驱动电路
CN108010480A (zh) * 2017-12-12 2018-05-08 中华映管股份有限公司 栅极驱动电路
WO2018173281A1 (ja) * 2017-03-24 2018-09-27 シャープ株式会社 表示装置およびその駆動方法
CN111223433A (zh) * 2020-01-19 2020-06-02 深圳市华星光电半导体显示技术有限公司 一种goa电路和显示装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006119581A (ja) 2004-09-24 2006-05-11 Koninkl Philips Electronics Nv アクティブマトリクス型液晶表示装置およびその駆動方法
KR101108165B1 (ko) * 2010-02-04 2012-01-31 삼성모바일디스플레이주식회사 스캔 드라이버 및 이를 포함하는 평판 디스플레이 장치
TWI476742B (zh) 2010-12-06 2015-03-11 Au Optronics Corp 多工式驅動電路
EP2610846A3 (en) * 2011-12-28 2014-07-09 Samsung Electronics Co., Ltd. Device and method for displaying image, device and method for supplying power, and method for adjusting brightness of contents
EP2610862B1 (en) 2011-12-30 2015-07-08 Samsung Electronics Co., Ltd. Electronic apparatus and method of controlling electronic apparatus
US20150295575A1 (en) * 2014-04-15 2015-10-15 Shenzhen China Star Optoelectronics Technology Co. Ltd. Gate driving circuit and gate driving method
CN104599621A (zh) * 2015-02-04 2015-05-06 京东方科技集团股份有限公司 多路复用转换器及显示装置
CN105118430B (zh) * 2015-08-31 2018-05-25 上海和辉光电有限公司 像素驱动电路及其驱动方法和显示装置
CN105047122A (zh) * 2015-09-08 2015-11-11 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN105206237B (zh) * 2015-10-10 2018-04-27 武汉华星光电技术有限公司 应用于In Cell型触控显示面板的GOA电路
KR102352607B1 (ko) * 2016-09-02 2022-01-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 표시 모듈, 및 전자 기기
US10355673B2 (en) * 2016-09-29 2019-07-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
EP3724917A4 (en) * 2017-12-15 2021-07-28 Boe Technology Group Co., Ltd. DISPLAY DEVICE AND GATE DRIVER ON ARRAY CIRCUIT
CN111048051A (zh) * 2019-12-23 2020-04-21 武汉华星光电技术有限公司 显示面板
CN114170891B (zh) * 2020-09-11 2023-03-10 京东方科技集团股份有限公司 显示基板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104103321A (zh) * 2013-04-04 2014-10-15 株式会社半导体能源研究所 脉冲发生电路及半导体装置
CN106486043A (zh) * 2015-08-25 2017-03-08 中华映管股份有限公司 栅极驱动电路
WO2018173281A1 (ja) * 2017-03-24 2018-09-27 シャープ株式会社 表示装置およびその駆動方法
CN108010480A (zh) * 2017-12-12 2018-05-08 中华映管股份有限公司 栅极驱动电路
CN111223433A (zh) * 2020-01-19 2020-06-02 深圳市华星光电半导体显示技术有限公司 一种goa电路和显示装置

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