WO2021191734A1 - 記憶装置、及び電子機器 - Google Patents

記憶装置、及び電子機器 Download PDF

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Publication number
WO2021191734A1
WO2021191734A1 PCT/IB2021/052197 IB2021052197W WO2021191734A1 WO 2021191734 A1 WO2021191734 A1 WO 2021191734A1 IB 2021052197 W IB2021052197 W IB 2021052197W WO 2021191734 A1 WO2021191734 A1 WO 2021191734A1
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WIPO (PCT)
Prior art keywords
transistor
insulator
conductor
oxide
layer
Prior art date
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Ceased
Application number
PCT/IB2021/052197
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English (en)
French (fr)
Japanese (ja)
Inventor
大貫達也
池田隆之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to CN202180024777.XA priority Critical patent/CN115349169A/zh
Priority to US17/911,196 priority patent/US12477952B2/en
Priority to KR1020227034253A priority patent/KR20220158241A/ko
Priority to JP2022509749A priority patent/JP7706440B2/ja
Publication of WO2021191734A1 publication Critical patent/WO2021191734A1/ja
Anticipated expiration legal-status Critical
Priority to JP2025111750A priority patent/JP2025133834A/ja
Priority to US19/369,677 priority patent/US20260052909A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1657—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/40—Devices controlled by magnetic fields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H10N52/80—Constructional details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • One aspect of the present invention relates to a storage device and an electronic device.
  • one aspect of the present invention is not limited to the above technical fields.
  • the technical field of the invention disclosed in the present specification and the like relates to a product, an operation method, or a manufacturing method.
  • one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, power storage devices, image pickup devices, storage devices, signal processing devices, and sensors. , Processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods.
  • the time required for access is short, in other words, the writing speed and the reading speed are high.
  • the access time (sometimes called delay time, latency, etc.) of SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) is about several ns to several tens of ns, so that the cache memory of the computer. , Used as main memory, etc.
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • the storage device used for the cache memory and the main memory of a computer is required to have a large storage capacity and low power consumption.
  • One aspect of the present invention is to provide a storage device having low power consumption.
  • one aspect of the present invention is to provide a storage device having a large storage capacity.
  • one aspect of the present invention is to provide a new storage device or the like.
  • one aspect of the present invention is to provide an electronic device having the above storage device.
  • the problem of one aspect of the present invention is not limited to the problems listed above.
  • the issues listed above do not preclude the existence of other issues.
  • Other issues are issues not mentioned in this item, which are described below. Issues not mentioned in this item can be derived from descriptions in the description, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one aspect of the present invention solves at least one of the above-listed problems and other problems. It should be noted that one aspect of the present invention does not need to solve all of the above-listed problems and other problems.
  • One aspect of the present invention is a storage device having a first layer and a second layer overlapping the first layer.
  • the first layer has a circuit
  • the second layer has a first memory cell.
  • the circuit includes a bit line driver circuit for transmitting a signal to the first memory cell and / or a word line driver circuit.
  • the first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element, and the MTJ element has a free layer.
  • the free layer is electrically connected to the conductor, and the first terminal of the first transistor is electrically connected to the first terminal of the second transistor via the conductor.
  • the circuit has a transistor in which silicon is contained in the channel forming region, and each of the first transistor and the second transistor contains a metal oxide in the channel forming region.
  • one aspect of the present invention is a storage device having a first layer and a second layer overlapping the first layer, and having a different configuration from the above (1).
  • the first layer has a circuit
  • the second layer has a first memory cell.
  • the circuit includes a bit line driver circuit for transmitting a signal to the first memory cell and / or a word line driver circuit.
  • the first memory cell has a first transistor, a second transistor, a conductor, and an MTJ element, and the MTJ element has a free layer and a fixed layer.
  • the free layer is electrically connected to the conductor, the first terminal of the first transistor is electrically connected to the first terminal of the second transistor, and the second terminal of the second transistor is electrically connected to the conductor.
  • the second terminal of the first transistor is electrically connected to the fixed layer.
  • the fixed layer is located above the free layer.
  • the circuit has a transistor in which silicon is contained in the channel forming region, and each of the first transistor and the second transistor contains a metal oxide in the channel forming region.
  • the conductor has a metal material in which a spin Hall effect occurs when an electric current flows.
  • one aspect of the present invention may be a configuration having a third layer in any one of the above (1) to (3). It is preferable that the third layer has a second memory cell, and the third layer is laminated on the second layer.
  • one aspect of the present invention is an electronic device having a storage device according to any one of (1) to (4) above and a housing.
  • the semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics.
  • a semiconductor element transistor, diode, photodiode, etc.
  • the storage device, the display device, the light emitting device, the lighting device, the electronic device, and the like are themselves semiconductor devices, and may have the semiconductor device.
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display
  • One or more devices, light emitting devices, loads, etc. can be connected between X and Y.
  • the switch has a function of controlling on / off. That is, the switch is in a conducting state (on state) or a non-conducting state (off state), and has a function of controlling whether or not a current flows.
  • a circuit that enables functional connection between X and Y for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion, etc.) Circuits (digital-to-analog conversion circuit, analog-digital conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes the signal potential level, etc.), voltage source, current source , Switching circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, storage circuit, control circuit, etc.) It is possible to connect one or more to and from. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. do.
  • X and Y are electrically connected, it means that X and Y are electrically connected (that is, another element between X and Y). Or when they are connected with another circuit in between) and when X and Y are directly connected (that is, they are connected without sandwiching another element or another circuit between X and Y). If there is) and.
  • X and Y, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and the X, the source (or the second terminal, etc.) of the transistor are connected to each other. (1 terminal, etc.), the drain of the transistor (or the 2nd terminal, etc.), and Y are electrically connected in this order.
  • the source of the transistor (or the first terminal, etc.) is electrically connected to X
  • the drain of the transistor (or the second terminal, etc.) is electrically connected to Y
  • the X, the source of the transistor (such as the second terminal).
  • the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.
  • X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor. (Terminals, etc.), transistor drains (or second terminals, etc.), and Y are provided in this connection order.
  • the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be separated. Separately, the technical scope can be determined. Note that these expression methods are examples, and are not limited to these expression methods.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • circuit diagram shows that independent components are electrically connected to each other, one component has the functions of a plurality of components.
  • one component has the functions of a plurality of components.
  • the term "electrically connected” as used herein includes the case where one conductive film has the functions of a plurality of components in combination.
  • the “resistance element” can be, for example, a circuit element having a resistance value higher than 0 ⁇ , wiring, or the like. Therefore, in the present specification and the like, the “resistive element” includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, a coil, and the like. Therefore, the term “resistor element” can be paraphrased into terms such as “resistance”, “load”, and “region having a resistance value”, and conversely, “resistance", “load”, and “region having a resistance value”. Can be rephrased as a term such as “resistive element”.
  • the resistance value can be, for example, preferably 1 m ⁇ or more and 10 ⁇ or less, more preferably 5 m ⁇ or more and 5 ⁇ or less, and further preferably 10 m ⁇ or more and 1 ⁇ or less. Further, for example, it may be 1 ⁇ or more and 1 ⁇ 10 9 ⁇ or less.
  • the “capacitance element” means, for example, a circuit element having a capacitance value higher than 0F, a wiring region having a capacitance value, a parasitic capacitance, a transistor gate capacitance, and the like. Can be. Therefore, in the present specification and the like, the terms “capacitive element”, “parasitic capacitance”, “gate capacitance” and the like can be paraphrased into terms such as “capacity”, and conversely, the term “capacity” is “capacity”. It can be paraphrased into terms such as “capacitive element”, “parasitic capacitance”, and “gate capacitance”.
  • the term “pair of electrodes” in “capacity” can be rephrased as “pair of conductors", “pair of conductive regions", “pair of regions” and the like.
  • the value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. Further, for example, it may be 1 pF or more and 10 ⁇ F or less.
  • the transistor has three terminals called a gate, a source, and a drain.
  • the gate is a control terminal that controls the conduction state of the transistor.
  • the two terminals that function as sources or drains are the input and output terminals of the transistor.
  • One of the two input / output terminals becomes a source and the other becomes a drain depending on the high and low potentials given to the conductive type (n-channel type, p-channel type) of the transistor and the three terminals of the transistor. Therefore, in the present specification and the like, the terms source and drain can be paraphrased with each other.
  • the transistor when explaining the connection relationship of transistors, "one of the source or drain” (or the first electrode or the first terminal), “the other of the source or drain” (or the second electrode, or The notation (second terminal) is used.
  • it may have a back gate in addition to the above-mentioned three terminals.
  • one of the gate or the back gate of the transistor may be referred to as a first gate
  • the other of the gate or the back gate of the transistor may be referred to as a second gate.
  • the terms “gate” and “backgate” may be interchangeable.
  • the respective gates When the transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, and the like in the present specification and the like.
  • the circuit element may have a plurality of circuit elements.
  • one resistor when one resistor is described on the circuit diagram, it includes the case where two or more resistors are electrically connected in series.
  • one capacity when one capacity is described on the circuit diagram, it includes the case where two or more capacities are electrically connected in parallel.
  • one transistor when one transistor is described on the circuit diagram, two or more transistors are electrically connected in series, and the gates of the respective transistors are electrically connected to each other. Shall include.
  • the switch has two or more transistors, and two or more transistors are electrically connected in series, respectively. It is assumed that the case where the gates of the transistors of the above are electrically connected to each other is included.
  • a node can be paraphrased as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on a circuit configuration, a device structure, and the like.
  • terminals, wiring, etc. can be paraphrased as nodes.
  • ground potential ground potential
  • the potentials are relative, and when the reference potential changes, the potential given to the wiring, the potential applied to the circuit or the like, the potential output from the circuit or the like also changes.
  • the terms “high level potential” and “low level potential” do not mean a specific potential.
  • both of the two wires “function as a wire that supplies a high level potential”
  • the high level potentials provided by both wires do not have to be equal to each other.
  • both of the two wires are described as “functioning as a wire that supplies a low level potential”
  • the low level potentials given by both wires do not have to be equal to each other. ..
  • the "current” is a charge transfer phenomenon (electrical conduction).
  • the description “electrical conduction of a positively charged body is occurring” means “electrical conduction of a negatively charged body in the opposite direction”. Is happening. " Therefore, in the present specification and the like, “current” refers to a charge transfer phenomenon (electrical conduction) accompanying the movement of carriers, unless otherwise specified.
  • the carrier here include electrons, holes, anions, cations, complex ions, and the like, and the carriers differ depending on the system in which the current flows (for example, semiconductor, metal, electrolytic solution, vacuum, etc.).
  • the "current direction” in the wiring or the like shall be the direction in which the carriers having a positive charge move, and shall be described as a positive current amount.
  • the direction in which the carriers that become negative charges move is opposite to the direction of the current, and is expressed by the amount of negative current. Therefore, in the present specification and the like, if there is no notice about the positive or negative of the current (or the direction of the current), the description such as “current flows from element A to element B” means “current flows from element B to element A” or the like. It can be paraphrased as. Further, the description such as “a current is input to the element A” can be rephrased as "a current is output from the element A” or the like.
  • the ordinal numbers “first”, “second”, and “third” are added to avoid confusion of the components. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. For example, the component referred to in “first” in one of the embodiments of the present specification and the like may be the component referred to in “second” in another embodiment or in the claims. There can also be. Further, for example, the component mentioned in “first” in one of the embodiments of the present specification and the like may be omitted in another embodiment or in the claims.
  • electrode B on the insulating layer A it is not necessary that the electrode B is formed in direct contact with the insulating layer A, and another configuration is formed between the insulating layer A and the electrode B. Do not exclude those that contain elements.
  • words such as “membrane” and “layer” can be interchanged with each other depending on the situation.
  • the terms “insulating layer” and “insulating film” may be changed to the term "insulator”.
  • Electrode may be used as part of a “wiring” and vice versa.
  • the terms “electrode” and / or “wiring” also include the case where a plurality of “electrodes” and / or “wiring” are integrally formed.
  • a “terminal” may be used as part of a “wiring” and / or an “electrode” and vice versa.
  • the term “terminal” includes a case where a plurality of "electrodes”, “wiring”, “terminals” and the like are integrally formed.
  • the "electrode” can be a part of the “wiring” or the “terminal”, and for example, the “terminal” can be a part of the “wiring” or the “electrode”.
  • terms such as “electrode”, “wiring”, and “terminal” may be replaced with terms such as "area” in some cases.
  • terms such as “wiring”, “signal line”, and “power supply line” can be interchanged with each other in some cases or depending on the situation.
  • the reverse is also true, and it may be possible to change terms such as “signal line” and “power supply line” to the term “wiring”.
  • a term such as “power line” may be changed to a term such as "signal line”.
  • terms such as “signal line” may be changed to terms such as "power line”.
  • the term “potential” applied to the wiring may be changed to a term such as “signal” in some cases or depending on the situation.
  • the reverse is also true, and terms such as “signal” may be changed to the term “potential”.
  • semiconductor impurities refer to, for example, components other than the main components constituting the semiconductor layer.
  • an element having a concentration of less than 0.1 atomic% is an impurity.
  • the inclusion of impurities may result in, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, a decrease in crystallinity, and the like.
  • the impurities that change the characteristics of the semiconductor include, for example, group 1 element, group 2 element, group 13 element, group 14 element, group 15 element, and other than the main component.
  • transition metals and the like and in particular, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like.
  • the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, oxygen, and the like. There is.
  • the switch means a switch that is in a conductive state (on state) or a non-conducting state (off state) and has a function of controlling whether or not a current flows.
  • the switch means a switch having a function of selecting and switching a path through which a current flows.
  • an electric switch, a mechanical switch, or the like can be used. That is, the switch is not limited to a specific switch as long as it can control the current.
  • Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, and MIS (Metal Insulator Semiconductor) diodes. , A diode-connected transistor, etc.), or a logic circuit that combines these.
  • transistors for example, bipolar transistors, MOS transistors, etc.
  • diodes for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, and MIS (Metal Insulator Semiconductor) diodes. , A diode-connected transistor, etc.
  • the "conducting state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited.
  • the "non-conducting state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically cut off.
  • the polarity (conductive type) of the transistor is not particularly limited.
  • An example of a mechanical switch is a switch that uses MEMS (Micro Electro Mechanical System) technology.
  • the switch has an electrode that can be moved mechanically, and the movement of the electrode controls conduction and non-conduction.
  • parallel means a state in which two straight lines are arranged at an angle of -10 ° or more and 10 ° or less. Therefore, the case of ⁇ 5 ° or more and 5 ° or less is also included.
  • substantially parallel or approximately parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 ° or more and 30 ° or less.
  • vertical means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included.
  • substantially vertical or “approximately vertical” means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.
  • a storage device having low power consumption it is possible to provide a storage device having low power consumption.
  • a storage device having a large storage capacity can be provided.
  • a new storage device or the like can be provided by one aspect of the present invention.
  • an electronic device having the above storage device can be provided.
  • the effect of one aspect of the present invention is not limited to the effects listed above.
  • the effects listed above do not preclude the existence of other effects.
  • the other effects are the effects not mentioned in this item, which are described below. Effects not mentioned in this item can be derived from those described in the description, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one aspect of the present invention has at least one of the above-listed effects and other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.
  • FIG. 1A and 1B are block diagrams showing a configuration example of a storage device.
  • FIG. 2 is a block diagram showing a configuration example of the storage device.
  • 3A to 3D are circuit diagrams showing a configuration example of a memory cell.
  • FIG. 4 is a schematic diagram illustrating a configuration example of a memory element included in the memory cell.
  • 5A and 5B are block diagrams showing a configuration example of a storage device.
  • 6A to 6C are circuit diagrams showing a configuration example of a memory cell.
  • FIG. 7 is a schematic cross-sectional view showing a configuration example of the storage device.
  • 8A to 8C are schematic cross-sectional views showing a configuration example of a transistor.
  • FIG. 9 is a schematic cross-sectional view showing a configuration example of the storage device.
  • FIG. 1A and 1B are block diagrams showing a configuration example of a storage device.
  • FIG. 2 is a block diagram showing a configuration example of the storage device.
  • FIG. 10 is a schematic cross-sectional view showing a configuration example of the storage device.
  • FIG. 11A is a diagram for explaining the classification of the crystal structure of IGZO
  • FIG. 11B is a diagram for explaining the XRD spectrum of crystalline IGZO
  • FIG. 11C is a diagram for explaining the microelectron diffraction pattern of crystalline IGZO.
  • .. 12A is a perspective view showing an example of a semiconductor wafer
  • FIG. 12B is a perspective view showing an example of a chip
  • FIGS. 12C and 12D are perspective views showing an example of an electronic component.
  • FIG. 13 is a block diagram illustrating a CPU.
  • 14A to 14J are perspective views or schematic views illustrating an example of the product.
  • 15A to 15E are perspective views or schematic views illustrating an example of the product.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel forming region of a transistor having at least one of an amplification action, a rectifying action, and a switching action, the metal oxide is referred to as a metal oxide semiconductor. be able to. Further, when describing as an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.
  • a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.
  • the configuration shown in each embodiment can be appropriately combined with the configuration shown in other embodiments to form one aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.
  • the content (may be a part of the content) described in one embodiment is the other content (may be a part of the content) described in the embodiment and one or more other implementations. It is possible to apply, combine, or replace at least one content with the content described in the form of (may be a part of the content).
  • figure (which may be a part) described in one embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more other figures.
  • the figure (which may be a part) described in the embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more other figures.
  • more figures can be formed.
  • FIG. 2 shows the configuration of a storage device according to an aspect of the present invention.
  • the storage device MDV has a peripheral circuit PHL and a memory cell array MCA.
  • the peripheral circuit PHL includes a low decoder 2621, a word line driver circuit 2622, a bit line driver circuit 2630, an output circuit 2640, and a control logic circuit 2660.
  • the bit line driver circuit 2630 includes a column decoder 2631, a precharge circuit 2632, a sense amplifier 2633, and a write circuit 2634.
  • the precharge circuit 2632 has a function of precharging a wiring (not shown in FIG. 2) electrically connected to the memory cell MC described later to a predetermined potential.
  • the sense amplifier 2633 has a function of acquiring the potential (or current) read from the memory cell MC as a data signal and amplifying the data signal. The amplified data signal is output to the outside of the storage device MDV as a digital data signal RDATA via the output circuit 2640.
  • the storage device MDV is supplied with a low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (VDD) for the peripheral circuit PHL, and a power supply voltage (VIL) for the memory cell array MCA from the outside.
  • VSS low power supply voltage
  • VDD high power supply voltage
  • VIL power supply voltage
  • control signal (CE, WE, RE), the address signal ADDR, and the data signal WDATA are input to the storage device MDV from the outside.
  • the address signal ADDR is input to the low decoder 2621 and the column decoder 2631, and the data signal WDATA is input to the write circuit 2634.
  • the control logic circuit 2660 processes input signals (CE, WE, RE) from the outside to generate control signals for the low decoder 2621 and the column decoder 2631.
  • CE is a chip enable signal
  • WE is a write enable signal
  • RE is a read enable signal.
  • the signal processed by the control logic circuit 2660 is not limited to this, and other control signals may be input as needed.
  • the configuration example of this embodiment is not limited to the configuration shown in FIG.
  • the configuration may be appropriately changed such that all or a part of the peripheral circuit PHL is provided in the lower layer of the memory cell array MCA.
  • the storage device MDV may have a configuration in which the peripheral circuit PHL is provided in the lower layer and the memory cell array MCA is provided above the peripheral circuit PHL.
  • the memory cell array MCA has m ⁇ n memory cells MC as an example. Further, in the memory cell array MCA, the memory cells MC are arranged in a matrix of m rows and n columns. In FIG. 1A, among the plurality of memory cell MCs, the memory cell MC [1,1], the memory cell MC [m, 1], the memory cell MC [1, n], and the memory cell MC [m, n] are shown. Excerpted and shown.
  • the peripheral circuit PHL has a circuit WD, a circuit BD, a circuit SD, a circuit CLC, and a circuit OPC.
  • the peripheral circuit PHL does not have a configuration including all of the circuit WD, the circuit BD, the circuit SD, the circuit CLC, and the circuit OPC, but the circuit WD, the circuit BD, the circuit SD, and the circuit CLC.
  • Circuit OPC and may be configured to have one or more circuits selected from.
  • the circuit WD can be a circuit corresponding to the word line driver circuit 2622 in FIG. Further, as an example, the circuit WD is electrically connected to the wiring WL [1] to the wiring WL [m]. The circuit WD functions to transmit a selection signal to a plurality of memory cell MCs included in the memory cell array MCA via the wiring WL [1] to the wiring WL [m].
  • FIG. 1A shows an example in which one wiring WL [1] to one wiring WL [m] is provided for each row of the memory cell array MCA, a plurality of wirings WL [1] to one wiring WL [m] are provided for each row of the memory cell array MCA. Wiring may be provided.
  • the circuit BD can be a circuit corresponding to the bit line driver circuit 2630 in FIG. Further, as an example, the circuit BD is electrically connected to the wiring BL [1] to the wiring BL [n].
  • the circuit BD functions as a circuit for transmitting a write signal to the memory cell MC included in the memory cell array MCA via the wiring BL [1] to the wiring BL [n]. Further, the circuit BD functions as a circuit that applies a predetermined voltage or current to the memory cell MC included in the memory cell array MCA via the wiring BL [1] to the wiring BL [n] at the time of reading. ..
  • FIG. 1A shows an example in which one wiring BL [1] to one wiring BL [n] is provided in each row of the memory cell array MCA, a plurality of wiring BL [1] to one wiring BL [n] are provided for each row of the memory cell array MCA. Wiring may be provided. For example, wiring for transmitting a write signal and wiring for transmitting a read signal may be provided for one row of the memory cell array MCA.
  • the circuit SD can be a voltage generation circuit for applying a predetermined voltage to a plurality of memory cell MCs of the memory cell array MCA. Further, as an example, the circuit SD is electrically connected to the wiring SL [1] to the wiring SL [m].
  • the storage device MDV may be configured to directly input the power supply voltage (VIL) for the memory cell array MCA shown in FIG. 2 without providing the circuit SD in FIG. 1A.
  • FIG. 1A shows an example in which one wiring SL [1] to one wiring SL [m] is provided in each row of the memory cell array MCA, a plurality of wiring SL [1] to one wiring SL [m] is provided for each row of the memory cell array MCA. Wiring may be provided.
  • the circuit CLC can be a circuit corresponding to the control logic circuit 2660 in FIG.
  • the circuit OPC can be a circuit corresponding to the output circuit 2640 in FIG.
  • the peripheral circuit PHL can be formed on, for example, a semiconductor substrate. That is, the circuit WD, the circuit BD, the circuit SD, the circuit OPC, and the circuit CLC can be formed on the semiconductor substrate. Further, as the semiconductor substrate, for example, by using a substrate made of silicon as a material, a transistor containing silicon in a channel forming region (hereinafter, referred to as a Si transistor) can be formed on the substrate. Therefore, a Si transistor can be applied as a transistor included in the peripheral circuit PHL.
  • a Si transistor containing silicon in a channel forming region
  • the peripheral circuit PHL may be formed on a compound semiconductor substrate, and the compound semiconductor substrate is a substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like. Can be mentioned. Further, the peripheral circuit PHL may be formed on a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate.
  • SOI Silicon On Insulator
  • the peripheral circuit PHL can be formed on, for example, an insulator substrate.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria-stabilized zirconia substrate, etc.), a resin substrate, and the like.
  • the peripheral circuit PHL can be formed on, for example, a conductor substrate.
  • the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate and the like.
  • the insulator substrate and the conductor substrate cannot form a channel forming region on the substrate itself, so that the transistor cannot be directly formed on the insulator substrate and the conductor substrate. Therefore, in order to form a transistor on an insulator substrate or a conductor substrate, it is necessary to separately provide a semiconductor film above the insulator substrate or the conductor substrate.
  • the memory cell array MCA is provided above the semiconductor substrate and the peripheral circuit PHL by applying the OS transistor as the transistor included in the memory cell array MCA. Can be done.
  • FIG. 1A shows a configuration in which one memory cell array MCA is provided above the peripheral circuit PHL, but the storage device of one aspect of the present invention is not limited to this.
  • a plurality of stacked memory cell array MCA may be provided above the peripheral circuit PHL.
  • FIG. 1B shows the configuration of a storage device in which a memory cell array MCA [1] to a memory cell array MCA [p] (p is an integer of 2 or more) are stacked above the peripheral circuit PHL.
  • FIG. 3A shows an example of a memory cell that can be provided in the storage device MDV.
  • the memory cell MC shown in FIG. 3A can be said to be an example of SOT-MRAM (Spin Orbit Magnetoresistive Ramdom Access Memory), which is a three-terminal memory element.
  • SOT-MRAM Spin Orbit Magnetoresistive Ramdom Access Memory
  • the memory cell MC has, for example, a transistor M1, a transistor M2, and a resistance change device MD.
  • an OS transistor can be applied.
  • the channel forming region of the OS transistor is preferably an oxide containing at least one of indium, gallium, and zinc.
  • indium and element M element M includes, for example, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, etc.
  • cerium, neodymium, hafnium, tantalum, tungsten, gallium and the like can be mentioned), and oxides containing at least one of zinc may be used.
  • the OS transistor has a transistor structure described in the second embodiment.
  • the transistor M1 and the transistor M2 shown in FIG. 3A have a back gate, but the storage device of one aspect of the present invention is not limited to this.
  • the transistor M1 and the transistor M2 shown in FIG. 3A may have a configuration without a back gate, that is, a transistor having a single gate structure. Further, some transistors may have a back gate, and some other transistors may not have a back gate.
  • the respective sizes of the transistor M1 and the transistor M2 are equal to each other.
  • the electrical characteristics of each transistor can be made substantially equal. Therefore, by making the sizes of the transistor M1 and the transistor M2 equal to each other, each of the transistor M1 and the transistor M2 can perform substantially the same operation under the same conditions.
  • the same condition here refers to, for example, the input potentials of the transistors M1 and M2 to their respective sources, drains, gates, and the like.
  • each of the transistor M1 and the transistor M2 includes a case where it operates as a switching element. That is, it is assumed that the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are in the voltage range in which they operate as switching elements. Further, each of the transistor M1 and the transistor M2 may operate in a linear region or a saturated region when it is in the ON state.
  • the resistance change device MD has an MTJ (magnetic tunnel junction) element ME. Further, the resistance change device MD has a terminal IT1, a terminal IT2, and a terminal OT. The details of the resistance change device MD will be described later.
  • MTJ magnetic tunnel junction
  • the first terminal of the transistor M1 is electrically connected to the terminal IT1 of the resistance change device MD, the second terminal of the transistor M1 is electrically connected to the wiring BL1, and the gate of the transistor M1 is electrically connected to the wiring WL. It is connected to the.
  • the first terminal of the transistor M2 is electrically connected to the terminal IT2 of the resistance change device MD, the second terminal of the transistor M2 is electrically connected to the wiring BL2, and the gate of the transistor M2 is electrically connected to the wiring WL. It is connected to the.
  • the terminal OT of the resistance change device MD is electrically connected to the wiring RBL.
  • Wiring BL1 and wiring BL2 function as, for example, a write bit line for the memory cell MC or a wiring that gives a constant voltage.
  • the wiring WL functions as a word line for the memory cell MC as an example.
  • the wiring RBL functions as a read bit line for the memory cell MC as an example.
  • a back gate is shown for the transistor M1 and / or the transistor M2, and the connection configuration of the back gate is not shown, but the electrical connection destination of the back gate is at the design stage.
  • the gate and the back gate may be electrically connected in order to increase the on-current of the transistor. That is, for example, the gate of the transistor M1 and the back gate may be electrically connected, or the gate of the transistor M2 and the back gate may be electrically connected.
  • the back gate of the transistor and an external circuit are electrically connected in order to fluctuate the threshold voltage of the transistor or to reduce the off current of the transistor.
  • a wiring for connection may be provided, and a potential may be applied to the back gate of the transistor by the external circuit or the like.
  • the memory cell MC can have the configuration shown in FIG. 3B.
  • the memory cell MC of FIG. 3B has a configuration in which a wiring BGE is electrically connected to the back gates of the transistors M1 and the transistors M2 included in the memory cell MC of FIG. 3A. By applying a predetermined potential to the wiring BGE, the threshold voltage of each of the transistor M1 and the transistor M2 can be changed.
  • FIG. 4 is a block diagram showing an example of the resistance change device MD.
  • the resistance change device MD of FIG. 4 has a layer RL, a layer TIS, a layer FL, and a layer CA.
  • the layer RL, the layer TIS, and the layer FL are included in the MTJ element ME.
  • the layer CA has, for example, a conductive film. Further, the terminal IT1 and the terminal IT2 are electrically connected via the film. Therefore, by applying a voltage between the terminal IT1 and the terminal IT2, a current flows between the terminal IT1-terminal IT2. Further, the layer CA may be referred to as a channel layer.
  • the film is used as a material in which a spin Hall effect is generated by passing a current between terminals IT1-terminal IT2.
  • the spin Hall effect is a phenomenon in which a spin current is generated in a direction substantially perpendicular to the direction in which a current flows.
  • a current flows in a two-dimensional plane such as a thin film
  • electrons having different spin directions are polarized on the upper surface and the lower surface of the thin film, thereby causing a spin flow in a direction substantially perpendicular to the thin film. appear. Therefore, the layer CA can generate a spin current in a substantially vertical direction of the layer CA by allowing a current to flow between the terminals IT1-terminal IT2.
  • the layer CA has a metal material that causes a spin Hall effect.
  • the metal material it is preferable to use a transition metal having a strong spin-orbit interaction. Examples of the transition metal include tungsten, platinum, tantalum and the like.
  • the layer CA may have a topological insulator that causes a spin Hall effect instead of a metal material. In this case, an alloy of bismuth and antimony, an alloy of bismuth and selenium, or the like may be used.
  • the layer FL functions as a free layer in the MTJ element ME.
  • the layer FL has a ferromagnet, and the ferromagnet can take a state of a magnetic moment that is parallel to or antiparallel to the magnetization direction of the layer RL, which will be described later.
  • the ferromagnet contained in the layer FL for example, it is preferable to use a material in which the magnetization of the ferromagnet is inverted by a small spin current. Further, the ferromagnetic material contained in the layer FL is preferably a material in which magnetization reversal is unlikely to occur due to thermal energy.
  • the ferromagnet for example, one kind or two or more kinds of alloys selected from iron, cobalt, and nickel can be used.
  • an alloy of cobalt, iron and boron can be used.
  • examples thereof include an alloy of manganese and gallium, and an alloy of manganese and germanium.
  • the magnetic moment of the layer FL receives spin torque due to the spin current generated in the layer CA.
  • the direction of the magnetic moment of the layer FL is reversed, for example, when the spin torque exceeds the threshold value. That is, the magnetization direction of the layer FL can be changed by passing a current through the layer CA (between the terminal IT1 and the terminal IT2). By this operation, information can be recorded in the MTJ element ME.
  • the layer TIS functions as a layer having a tunnel insulator in the MTJ element ME.
  • a tunnel current can flow through the layer TIS due to the tunnel magnetoresistive effect by applying a voltage between the layer FL and the layer RL (terminal OT).
  • the electric resistance value of the layer TIS changes depending on the direction of the magnetic moment of the layer FL.
  • the electrical resistance value of the layer TIS changes depending on whether the magnetization directions of the layer FL and the layer RL are parallel or antiparallel.
  • the tunnel insulator for example, magnesium oxide, aluminum oxide and the like can be used. In particular, it is preferable to use crystalline magnesium oxide as the tunnel insulator.
  • the layer RL functions as a fixed layer in the MTJ element ME.
  • Layer RL has a ferromagnet. It is assumed that the ferromagnet of the layer RL has a fixed magnetization direction unlike the ferromagnet of the layer FL.
  • the ferromagnet contained in the layer RL for example, a material applicable to the ferromagnet contained in the layer FL can be used.
  • MR ratio magnetic resistance ratio
  • a high level potential is applied to the wiring WL to turn on each of the transistor M1 and the transistor M2.
  • the first potential is applied from the wiring BL1 to the terminal IT1 via the transistor M1
  • the second potential is applied from the wiring BL2 to the terminal IT2 via the transistor M2.
  • a current flows through the layer CA of the MTJ element ME
  • a spin current is generated in the layer CA
  • the spin current determines the magnetization direction of the ferromagnet in the layer FL.
  • the first potential may be higher or lower than the second potential.
  • the potential given by the wiring RBL is preferably a potential in a range in which no current flows between the terminals IT1-terminal OTs and / or between the terminals IT2-terminal OTs.
  • a high level potential is applied to the wiring WL to turn on each of the transistor M1 and the transistor M2.
  • a predetermined voltage is applied to each of the terminal IT1, the terminal IT2, and the terminal OT so that a current flows between the terminals IT1-terminal OT and / or between the terminal IT2-terminal OT.
  • the electric resistance value of the MTJ element ME changes depending on whether the magnetization directions of the layer RL and the layer FL are parallel or antiparallel, the amount of tunnel current flowing through the layer TIS of the MTJ element ME. Also changes.
  • the information recorded in the MTJ element ME can be read out.
  • Information recorded on the MTJ element ME can also be measured by applying a predetermined potential to each of the terminal IT1 and the terminal IT2, passing a constant current between the MTJ element ME and the terminal OT, and measuring the potential of the terminal OT. Can be read.
  • FIG. 5A a configuration example in which the memory cell MC of FIG. 3A is applied to the storage device MDV of FIG. 1A is shown in FIG. 5A. Although each component is shown on a plane in FIG. 5A for easy viewing, it is assumed that the memory cell array MCA is provided above the peripheral circuit PHL as shown in the storage device MDV of FIG. 1A. ..
  • the peripheral circuit PHL includes a circuit WD, a circuit BD, and a circuit RBD.
  • the description of the storage device MDV of FIG. 1A will be referred to.
  • the circuit RBD is electrically connected to the wiring RBL [1] to the wiring RBL [m]. Further, the circuit RBD functions as a circuit for receiving read information from the memory cell MC included in the memory cell array MCA via the wiring RBL [1] to the wiring RBL [m]. That is, the circuit RBD can be, for example, a circuit corresponding to the sense amplifier 2633 in the storage device MDV of FIG. Therefore, the circuit RBD may be included in the circuit BD corresponding to the bit line driver circuit 2630.
  • the wiring BL1 [1] to the wiring BL [n] in the storage device MDV of FIG. 1A the wiring BL1 [1] to the wiring BL1 [n] and the wiring BL2 [1] to the wiring BL2 [n] Is electrically connected to. That is, wiring BL1 and wiring BL2 are provided for each row of the memory cell array MCA.
  • the circuit BD has a configuration in which different voltages (or currents) are input to the wiring BL1 and the wiring BL2 when the information is written to the memory cell MC and when the information is read from the memory cell MC. It is preferable to do so.
  • the configuration example in which the memory cell MC of FIG. 3A is applied to the storage device MDV of FIG. 1A is not limited to the configuration of the storage device MDV of FIG. 5A.
  • the circuit configuration of the storage device MDV of FIG. 5A may be changed depending on the situation.
  • FIG. 3C shows an example of a memory cell that can be provided in the storage device MDV, which is different from FIG. 3A.
  • the memory cell MC shown in FIG. 3C can also be said to be an example of SOT-MRAM.
  • the memory cell MC has, for example, a transistor M3, a transistor M4, and a resistance change device MD.
  • the resistance change device MD has the MTJ element ME of FIG. 4 like the resistance change device MD of FIG. 3A.
  • the first terminal of the transistor M3 is electrically connected to the terminal IT2 of the resistance change device MD, the second terminal of the transistor M3 is electrically connected to the wiring SL, and the gate of the transistor M3 is electrically connected to the wiring WLa. It is connected to the.
  • the first terminal of the transistor M4 is electrically connected to the terminal OT of the resistance change device MD, the second terminal of the transistor M4 is electrically connected to the wiring SL, and the gate of the transistor M4 is electrically connected to the wiring WLb. It is connected to the.
  • the terminal IT1 of the resistance change device MD is electrically connected to the wiring BL.
  • the wiring BL functions as, for example, a bit wire to the memory cell MC or a wiring that gives a constant voltage.
  • the wiring SL functions as a wiring that gives a constant voltage as an example.
  • the wiring WLa functions as a write word line and a read word line for the memory cell MC as an example.
  • the wiring WLb functions as a read word line for the memory cell MC as an example.
  • a high level potential is applied to the wiring WLa to turn on the transistor M3, and a low level potential is applied to the wiring WLb to turn off the transistor M4.
  • the wiring BL gives the terminal IT1 a third potential higher than the low level potential.
  • a current flows through the layer CA of the MTJ element ME, a spin current is generated in the layer CA, and the spin current determines the magnetization direction of the ferromagnet in the layer FL.
  • a high level potential is applied to the wiring WLa to turn on the transistor M3, and a high level potential is applied to the wiring WLb to turn on the transistor M4.
  • a fourth potential higher than the low level potential and lower than the third potential from the wiring BL is applied to the terminal IT1
  • a current flows between the terminal IT1-terminal IT2 and / or between the terminal IT1-terminal OT. ..
  • the electric resistance value of the MTJ element ME changes depending on whether the magnetization directions of the layer RL and the layer FL are parallel or antiparallel, the amount of tunnel current flowing through the layer TIS of the MTJ element ME. Also changes.
  • the information recorded in the MTJ element ME can be read out by measuring the amount of current flowing through the MTJ element ME and the terminal IT1. Further, the information recorded in the MTJ element ME can also be read out by applying a predetermined potential to the wiring SL, passing a constant current from the wiring BL to the terminal IT1 of the MTJ element ME, and measuring the potential of the terminal IT1.
  • the memory cell MC of FIG. 3C may have a configuration in which the back gates of the transistor M3 and the transistor M4 are electrically connected to the wiring BGE, as in the case of FIG. 3B.
  • the memory cell MC can have the configuration shown in FIG. 3D.
  • FIG. 5B a configuration example in which the memory cell MC of FIG. 3C is applied to the storage device MDV of FIG. 1A is shown in FIG. 5B. Although each component is shown on a plane in FIG. 5B for easy viewing, the memory cell array MCA is provided above the peripheral circuit PHL as in the storage device MDV of FIG. 1A, as in FIG. 5A. It is assumed that it has been done.
  • the peripheral circuit PHL includes a circuit WD, a circuit BD, and a circuit SD. Further, with respect to the circuit WD, the circuit BD, and the circuit SD, the description of the storage device MDV of FIG. 1A will be taken into consideration.
  • the wiring SL [1] to the wiring SL [n] are different from the storage device MDV of FIG. 1A in that they are provided in the column direction instead of the row direction.
  • the direction in which the wiring is extended is not particularly limited.
  • the wiring WLa [1] to the wiring WLa [m] and the wiring WLb [1] to the wiring WLb [m] Is electrically connected to. That is, a wiring WLa and a wiring WLb are provided for each row of the memory cell array MCA.
  • the circuit WD is configured to input different voltages to the wiring WLa and the wiring WLb depending on whether the information is written to the memory cell MC or the information is read from the memory cell MC. ..
  • the configuration example in which the memory cell MC of FIG. 3C is applied to the storage device MDV of FIG. 1A is not limited to the configuration of the storage device MDV of FIG. 5B.
  • the circuit configuration of the storage device MDV of FIG. 5B may be changed depending on the situation.
  • FIG. 6A shows an example of a memory cell that can be provided in the storage device MDV.
  • the memory cell shown in FIG. 6A can be said to be an example of STT-MRAM (Spin Transfer Magnetoresistive Ramdom Access Memory).
  • the memory cell MC has a transistor M10 and the MTJ element ME described above.
  • an OS transistor can be applied in the same manner as the transistor M1 and the transistor M2.
  • the MTJ element ME has a layer FL having a free layer, a layer TIS having a tunnel insulator, and a layer RL having a fixed layer, via the layer TIS.
  • the layer FL and the layer RL are superimposed.
  • the first terminal of the transistor M10 is electrically connected to the layer RL of the MTJ element ME, the second terminal of the transistor M10 is electrically connected to the wiring SL, and the gate of the transistor M10 is electrically connected to the wiring WL. Has been done.
  • the layer FL of the MTJ element ME is electrically connected to the wiring BL.
  • the wiring BL functions as a write bit line or a read bit line for the memory cell MC as an example.
  • the wiring WL functions as a word line for the memory cell MC as an example.
  • the wiring SL functions as a wiring that gives a constant voltage as an example.
  • the constant voltage can be, for example, a low level potential.
  • a high level potential is applied to the wiring WL to turn on the transistor M10.
  • the layer RL and the wiring SL are in a conductive state.
  • a tunnel current is generated in the layer TIS, so that a current flows between the wiring BL and the wiring SL.
  • the magnetization direction of the layer FL can be changed by flowing a large amount of electrons having spins aligned in a certain direction through the layer FL. As a result, information can be recorded in the MTJ element ME.
  • the layer RL and the wiring SL are in a conductive state.
  • the amount of current flowing through the MTJ element ME is determined by whether the magnetization directions of the layer RL and the layer FL are parallel or antiparallel. Specifically, for example, the amount of current when the magnetization directions of the layer RL and the layer FL are parallel is larger than the amount of the current when the magnetization directions of the layer RL and the layer FL are antiparallel. growing. That is, the information recorded in the MTJ element ME can be read out by measuring the amount of current flowing through the MTJ element ME.
  • the memory cell MC of FIG. 6A can record information by flowing electrons whose spins are aligned in a certain direction through the MTJ element ME to change the magnetization direction of the layer FL.
  • the configuration of the memory cell MC provided in the storage device is not limited to this.
  • a wiring having a function of generating a magnetic field may be provided near the MTJ element ME.
  • information can be written to the MTJ element ME by generating a magnetic field from the wiring and changing the magnetization direction of the layer FL of the MTJ element ME.
  • FIG. 6B shows an example of a memory cell that can be provided in the storage device MDV.
  • the memory cell shown in FIG. 6B can be said to be an example of ReRAM (Resistive Random Access Memory).
  • the memory cell MC has a transistor M10 and a resistance changing element RM.
  • an OS transistor can be applied in the same manner as the transistor M1 and the transistor M2.
  • the memory cell MC of FIG. 6B has a configuration in which the MTJ element ME of the memory cell MC of FIG. 6A is replaced with the resistance changing element RM.
  • the first terminal of the resistance changing element RM is electrically connected to the first terminal of the transistor M10, and the second terminal of the resistance changing element RM is electrically connected to the wiring BL. It is assumed that it has been done.
  • the wiring BL functions as a write bit line or a read bit line for the memory cell MC as an example.
  • the wiring WL functions as a word line for the memory cell MC as an example.
  • the wiring SL functions as a wiring that gives a constant voltage as an example.
  • the constant voltage can be, for example, a reference potential.
  • the wiring BL and the wiring SL are in a conductive state.
  • the amount of current flowing through the resistance changing element RM is determined by the value of the electrical resistance of the resistance changing element RM. That is, by measuring the amount of current flowing through the resistance changing element RM, the information recorded in the resistance changing element RM can be read out.
  • FIG. 6C shows an example of a memory cell that can be provided in the storage device MDV.
  • the memory cell shown in FIG. 6C can be said to be an example of a phase change memory (sometimes referred to as PCM, PRAM, or the like).
  • the memory cell MC has a transistor M10 and a phase change memory PCM1.
  • an OS transistor can be applied in the same manner as the transistor M1 and the transistor M2.
  • the phase change memory PCM1 has an electrode TE, a phase change layer CHL, and an electrode BE as an example, and is electrically connected in the order of the electrode TE, the phase change layer CHL, and the electrode BE.
  • phase change layer CHL for example, chalcogenide glass can be applied.
  • the phase change layer CHL will be described as applying chalcogenide glass.
  • the electrode TE and the electrode BE have different areas of contact with the phase change layer CHL.
  • the contact area between the electrode TE and the phase change layer CHL is shown to be larger than the contact area between the electrode BE and the phase change layer CHL.
  • the memory cell MC of FIG. 6C has a configuration in which the MTJ element ME of the memory cell MC of FIG. 6A is replaced with the phase change memory PCM1.
  • the electrode BE of the phase change memory PCM1 is electrically connected to the first terminal of the transistor M10, and the electrode TE of the phase change memory PCM1 is electrically connected to the wiring BL. It is assumed that there is.
  • the wiring BL functions as a write bit line or a read bit line for the memory cell MC as an example.
  • the wiring WL functions as a word line for the memory cell MC as an example.
  • the wiring SL functions as a wiring that gives a constant voltage as an example.
  • the constant voltage can be, for example, a low level potential.
  • a high level potential is applied to the wiring WL to turn on the transistor M10.
  • the wiring BL and the wiring SL are in a conductive state.
  • a high level potential is applied from the wiring BL (specifically, a high voltage is applied between the electrode TE and the electrode BE).
  • the chalcogenide glass can transition to the polycrystalline state. Even if the voltage supply from the wiring BL and the wiring SL is stopped after the chalcogenide glass is made into a polycrystalline state, the chalcogenide glass can maintain the polycrystalline state.
  • the temperature of the chalcogenide glass is raised by Joule heat to melt the chalcogenide glass, and then the voltage supply from the wiring BL and the wiring SL is stopped to rapidly cool the chalcogenide glass, whereby the chalcogenide glass is brought into an amorphous state. Can be transitioned to.
  • the memory cell MC can record information in the phase change memory PCM1 by changing the phase of the chalcogenide glass contained in the phase change layer CHL.
  • the amount of current flowing between the electrode TE and the electrode BE of the phase change memory PCM1 is such that the chalcogenide glass of the phase change layer CHL is in an amorphous state or a polycrystalline state. It depends on whether or not. Specifically, for example, when the chalcogenide glass is in an amorphous state, the amount of current is small, and when the chalcogenide glass is in a polycrystalline state, the amount of current is large. That is, by measuring the amount of current flowing through the phase change memory PCM1, the information recorded in the phase change memory PCM1 can be read out.
  • a memory cell having a memory element such as the MTJ element ME, the resistance change element RM, and the phase change memory PCM1 functions as a non-volatile memory, the power for holding the data can be reduced. Therefore, by applying the above-described configuration as a storage device, it is possible to provide a storage device with low power consumption. Further, by applying an OS transistor or the like as the transistor of the memory cell, the memory cell array can be manufactured in the semiconductor process, so that the memory cell array can be stacked above the peripheral circuit. By stacking a plurality of memory cell arrays, it is possible to provide a storage device having a large storage capacity.
  • FIG. 7 is a cross-sectional view schematically showing a configuration example of the storage device MDV of FIG. 1B.
  • the storage device MDV shown in FIG. 7 has a layer SIL and a layer OSL [1] to a layer OSL [p] provided above the layer SIL (where p is an integer of 1 or more).
  • the layer SIL has, for example, the peripheral circuit PHL described in the first embodiment.
  • each of the layer OSL [1] to the layer OSL [p] has, for example, the memory cell array MCA described in the first embodiment.
  • the layer SIL has a transistor 300, and each of the layers OSL [1] to OSL [p] has a transistor 500A, a transistor 500B, and a memory element 400.
  • the transistor 500A and the transistor 500B may be referred to as the transistor 500.
  • FIG. 8A shows a cross-sectional view of the transistor 500 in the channel length direction
  • FIG. 8B shows a cross-sectional view of the transistor 500 in the channel width direction
  • FIG. 8C shows a cross-sectional view of the transistor 300 in the channel width direction.
  • a cross-sectional view of the direction is shown.
  • the transistors shown in FIGS. 8A to 8C may have a partially different shape from the transistors shown in FIG. 7 for the sake of explanation.
  • each of the layer OSL [1] to the layer OSL [p] has a memory cell 600, and the memory cell 600 includes a transistor 500A, a transistor 500B, and a memory element 400.
  • the memory cell MC of FIG. 3A is used.
  • the transistor 500A corresponds to one of the transistors M1 or M2
  • the transistor 500B corresponds to the other of the transistors M1 or M2
  • the memory element 400 corresponds to the resistance change device MD. Therefore, in the storage device MDV of FIG. 7, the first terminal of the transistor 500A is electrically connected to the first terminal of the transistor 500B and the first terminal of the memory element 400.
  • one of the wiring BL1 or the wiring BL2 in FIG. 3A can be, for example, a conductor 450 that is electrically connected to the second terminal of one of the transistor 500A or the transistor 500B.
  • the other of the wiring BL1 or the wiring BL2 in FIG. 3A can be, for example, a conductor 450 that is electrically connected to the second terminal of the other of the transistor 500A or the transistor 500B.
  • the conductor 450 will be described later.
  • the wiring WL in FIG. 3A can be, for example, a conductor 560 corresponding to each gate of the transistor 500A and the transistor 500B.
  • the wiring RBL of FIG. 3A can be, for example, a conductor 460 that is electrically connected to the second terminal of the memory element 400. The conductor 460 will be described later.
  • the transistor 500 is a transistor (OS transistor) having a metal oxide in the channel forming region.
  • the transistor 500 has a characteristic that the off-current is small and the field effect mobility does not easily change even at a high temperature.
  • the peripheral circuit PHL included in the layer SIL has a circuit WD, a circuit BD, a circuit SD, a circuit CLC, a circuit OPC, and the like as shown in the configuration of the storage device MDV in FIG. 1B. Therefore, the transistor 300 can be a transistor included in a circuit WD, a circuit BD, a circuit RBD, a circuit SD, a circuit CLC, a circuit OPC, or the like.
  • the transistor 300 has a semiconductor region 313 composed of a conductor 316, an element separation layer 312, an insulator 315, and a part of a substrate 310, a low resistance region 314a functioning as a source region or a drain region, and a low resistance region 314b.
  • a semiconductor substrate can be applied.
  • examples of the semiconductor substrate include a substrate made of silicon and a substrate made of germanium.
  • a compound semiconductor substrate can be applied.
  • examples of the compound semiconductor substrate include substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and the like, as described above.
  • the transistor 300 is covered with the conductor 316 on the upper surface of the semiconductor region 313 and the side surface in the channel width direction via the insulator 315.
  • the on-characteristics of the transistor 300 can be improved by increasing the effective channel width. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristic of the transistor 300 can be improved.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like.
  • It preferably contains crystalline silicon.
  • it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like.
  • a configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used.
  • the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs or the like.
  • an element that imparts n-type conductivity such as arsenic and phosphorus, or a p-type conductivity such as boron is imparted.
  • the conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy that contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.
  • a material or a conductive material such as a metal oxide material can be used.
  • the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.
  • the element separation layer 312 is provided to separate a plurality of transistors formed on the substrate 310.
  • the element separation layer 312 can be formed by using, for example, a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a mesa separation method, or the like.
  • LOCOS Local Oxidation of Silicon
  • STI Shallow Trench Isolation
  • the transistor 300 shown in FIGS. 7 and 8C is an example, and is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration, the driving method, and the like.
  • the transistor 300 shown in FIGS. 7 and 8C may be a planar type transistor.
  • the transistor 300 shown in FIG. 7 is provided with an insulator 320, an insulator 322, an insulator 324, and an insulator 326 stacked in this order from the substrate 310 side.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride, aluminum nitride and the like can be used. Just do it.
  • silicon oxide refers to a material having a higher oxygen content than nitrogen as its composition
  • silicon nitride as its composition means a material having a higher nitrogen content than oxygen as its composition. Is shown.
  • aluminum nitride refers to a material whose composition has a higher oxygen content than nitrogen
  • aluminum nitride refers to a material whose composition has a higher nitrogen content than oxygen. Is shown.
  • the insulator 322 may have a function as a flattening film for flattening a step caused by the insulator 320 and the transistor 300 covered with the insulator 322.
  • the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • the insulator 324 it is preferable to use a film having a barrier property such that impurities such as water and hydrogen do not diffuse in the region where the transistor 500 is provided from the substrate 310 or the transistor 300.
  • a film having a barrier property against hydrogen for example, silicon nitride formed by the CVD method can be used.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, so that the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300.
  • the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.
  • the amount of hydrogen desorbed can be analyzed using, for example, a heated desorption gas analysis method (TDS).
  • TDS heated desorption gas analysis method
  • the amount of hydrogen desorbed from the insulator 324 is the amount desorbed in terms of hydrogen atoms in the range of 50 ° C. to 500 ° C. in the surface temperature of the film, which is converted per area of the insulator 324. It may be 10 ⁇ 10 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • the insulator 326 has a lower dielectric constant than the insulator 324.
  • the relative permittivity of the insulator 326 is preferably less than 4, more preferably less than 3.
  • the relative permittivity of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative permittivity of the insulator 324.
  • the conductor 328, the conductor 330, and the like are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326.
  • the conductor 328 and the conductor 330 have a function as a plug or wiring.
  • a conductor having a function as a plug or wiring may collectively give a plurality of structures the same reference numerals.
  • the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • each plug and wiring As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or laminated. be able to. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are laminated on the insulator 326 and the conductor 330 in this order.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 has a function as a plug or wiring for connecting to the transistor 300.
  • the conductor 356 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 350 it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similarly to the insulator 324.
  • the insulator 352 and the insulator 354 it is preferable to use an insulator having a relatively low relative permittivity in order to reduce the parasitic capacitance generated between the wirings, similarly to the insulator 326.
  • the conductor 356 preferably contains a conductor having a barrier property against water, hydrogen and the like.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen.
  • the conductor having a barrier property against hydrogen for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen has a structure in contact with the insulator 350 having a barrier property against hydrogen.
  • the insulator 360, the insulator 362, and the insulator 364 are laminated in this order on the insulator 354 and the conductor 356.
  • the insulator 360 it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similarly to the insulator 324 and the like. Therefore, as the insulator 360, for example, a material applicable to the insulator 324 and the like can be used.
  • the insulator 362 and the insulator 364 have a function as an interlayer insulating film and a flattening film. Further, as the insulator 362 and the insulator 364, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similarly to the insulator 324. Therefore, as the insulator 362 and / or the insulator 364, a material applicable to the insulator 324 can be used.
  • an opening is formed in a region of each of the insulator 360, the insulator 362, and the insulator 364 that overlaps with a part of the conductor 356, and the conductor 366 is provided so as to fill the opening.
  • the conductor 366 is also formed on the insulator 362.
  • the conductor 366 has a function as a plug or wiring for connecting to the transistor 300.
  • the conductor 366 can be provided by using the same material as the conductor 328 and the conductor 330.
  • Insulator 510, insulator 512, insulator 513, insulator 514, and insulator 516 are laminated in this order on the insulator 364 and the conductor 366.
  • any of the insulator 510, the insulator 512, the insulator 513, the insulator 514, and the insulator 516 it is preferable to use a substance having a barrier property against oxygen and / or hydrogen.
  • the insulator 510 and the insulator 514 it is preferable to use a film having a barrier property such that impurities such as water and hydrogen do not diffuse in the region where the transistor 500 is provided from the substrate 310 or the like. Therefore, the same material as the insulator 324 and the like can be used.
  • Silicon nitride formed by the CVD method can be used as an example of a film having a barrier property against hydrogen.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, so that the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the substrate 310.
  • the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.
  • metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.
  • aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • the insulator 513 it is preferable to use a film having a barrier property so that impurities such as water and hydrogen do not diffuse, like the insulator 510 and the insulator 514.
  • the insulator 513 functions as a film for sealing the transistor 500 together with the insulator 576 described later. Therefore, it is preferable to use a material applicable to the insulator 576 as the insulator 513. Further, as the insulator 513, a material applicable to the insulator 510 or the insulator 514 may be used.
  • the same material as the insulator 320 or the insulator 326 can be used. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings. For example, silicon oxide, silicon oxide and the like can be used as the insulator 512 and the insulator 516.
  • the insulator 510, the insulator 512, the insulator 513, the insulator 514, and the insulator 516 include the conductor 518 and the conductors constituting the transistor 500 (for example, the conductors shown in FIGS. 8A and 8B). 503) etc. are embedded.
  • the conductor 518 has a function as a plug or wiring for connecting the conductor 450, the conductor 460, the transistor 300, etc., which will be described later.
  • the conductor 518 can be provided, for example, by using the same material as the conductor 328 and the conductor 330.
  • the conductor 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having a barrier property against oxygen, hydrogen, and water.
  • the transistor 300 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.
  • a transistor 500 is provided above the insulator 516.
  • the transistor 500 includes a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, and an insulator arranged on the insulator 516 and the insulator 503.
  • 520 insulator 522 placed on insulator 520
  • insulator 524 placed on insulator 522
  • oxide 530a placed on insulator 524
  • oxide 530a placed on oxide 530a
  • the oxide 530b arranged on the oxide 530b, the conductor 542a and the conductor 542b arranged apart from each other on the oxide 530b, and the conductor 542a and the conductor 542b arranged on the conductor 542a and the conductor 542b.
  • the oxide 530c arranged on the bottom surface and the side surface of the opening, the insulator 550 arranged on the forming surface of the oxide 530c, and the forming surface of the insulator 550. It has an arranged conductor 560 and. In this specification and the like, the conductor 542a and the conductor 542b are collectively referred to as the conductor 542.
  • the insulator 544 is arranged between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b, and the insulator 580.
  • the conductor 560 includes a conductor 560a provided inside the insulator 550, a conductor 560b provided so as to be embedded inside the conductor 560a, and the conductor 560b. It is preferable to have.
  • the insulator 574 is arranged on the insulator 580, the conductor 560, and the insulator 550.
  • oxide 530a, oxide 530b, and oxide 530c may be collectively referred to as oxide 530.
  • the transistor 500 shows a configuration in which three layers of oxide 530a, oxide 530b, and oxide 530c are laminated in a region where a channel is formed and in the vicinity thereof.
  • One aspect of the present invention is this. It is not limited to.
  • a single layer of oxide 530b, a two-layer structure of oxide 530b and oxide 530a, a two-layer structure of oxide 530b and oxide 530c, or a laminated structure of four or more layers may be provided.
  • the conductor 560 is shown as a two-layer laminated structure, but one aspect of the present invention is not limited to this.
  • the conductor 560 may have a single-layer structure or a laminated structure of three or more layers.
  • the transistor 500 shown in FIGS. 7, 8A, and 8B is an example, and the transistor 500 is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration, driving method, and the like.
  • the conductor 560 functions as a gate electrode of the transistor, and the conductor 542a and the conductor 542b function as a source electrode or a drain electrode, respectively.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
  • the arrangement of the conductor 560, the conductor 542a and the conductor 542b is self-aligned with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing the alignment margin, the occupied area of the transistor 500 can be reduced. As a result, the storage device can be miniaturized and highly integrated.
  • the conductor 560 is formed in a region between the conductor 542a and the conductor 542b in a self-aligned manner, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Therefore, the switching speed of the transistor 500 can be improved and a high frequency characteristic can be provided.
  • the conductor 560 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode.
  • the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560 without interlocking with the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, it is possible to increase the threshold voltage of the transistor 500 and reduce the off-current. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when it is not applied.
  • the conductor 503 is arranged so as to overlap the oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected to cover the channel forming region formed in the oxide 530. Can be done.
  • the structure of the transistor that electrically surrounds the channel formation region by the electric fields of the first gate electrode and the second gate electrode is referred to as a surroundd channel (S-channel) structure.
  • the conductor 503 has the same configuration as the conductor 518, and the conductor 503a is formed in contact with the inner wall of the opening of the insulator 514 and the insulator 516, and the conductor 503b is further formed inside.
  • the transistor 500 shows a configuration in which the conductor 503a and the conductor 503b are laminated, one aspect of the present invention is not limited to this.
  • the conductor 503 may be provided as a single layer or a laminated structure having three or more layers.
  • a conductive material for the conductor 503a which has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate).
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one oxygen atom, oxygen molecule, etc.
  • the function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.
  • the conductor 503a since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 503b from being oxidized and the conductivity from being lowered.
  • the conductor 503 also functions as a wiring
  • the conductor 503a does not necessarily have to be provided.
  • the conductor 503b is shown as a single layer, it may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.
  • the insulator 520, the insulator 522, and the insulator 524 have a function as a second gate insulating film.
  • the insulator 524 in contact with the oxide 530 it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition. That is, it is preferable that the insulator 524 is formed with an excess oxygen region.
  • oxygen deficiency in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.
  • the oxygen deficiency in the metal oxide and V O (oxygen vacancy) sometimes called the oxygen deficiency in the metal oxide and V O (oxygen vacancy).
  • Transistors using metal oxides are likely to fluctuate in electrical characteristics and may be unreliable if impurities or oxygen deficiencies (VO ) are present in the region where channels are formed in the metal oxide.
  • the oxygen-deficient (V O) in the vicinity of hydrogen, oxygen vacancy (V O) containing hydrogen defects (hereinafter sometimes referred to as V O H.) Is formed, to generate electrons serving as carriers In some cases. Therefore, if oxygen deficiency is contained in the region where the channel is formed in the oxide semiconductor, the transistor has normal-on characteristics (the channel exists even if no voltage is applied to the gate electrode, and the current is applied to the transistor. Flowing characteristics).
  • the region in which the channel is formed in the oxide semiconductor is preferably i-type (intrinsicized) or substantially i-type with a reduced carrier concentration.
  • an oxide material in which a part of oxygen is desorbed by heating is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis.
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
  • the insulator having the excess oxygen region and the oxide 530 may be brought into contact with each other to perform one or more of heat treatment, microwave treatment, or RF treatment.
  • heat treatment microwave treatment, or RF treatment.
  • water or hydrogen in the oxide 530 can be removed.
  • reactions occur which bonds VoH is disconnected, when other words happening reaction of "V O H ⁇ V O + H", can be dehydrogenated.
  • the hydrogen generated as oxygen combines with H 2 O, it may be removed from the oxide 530 or oxide 530 near the insulator.
  • a part of hydrogen may be diffused or captured (also referred to as gettering) in the conductor 542a and the conductor 542b.
  • the microwave processing for example, it is preferable to use an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side.
  • an apparatus having a power source for generating high-density plasma for example, by using a gas containing oxygen and using a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be generated.
  • the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more.
  • oxygen and argon are used as the gas to be introduced into the apparatus for performing microwave treatment, and the oxygen flow rate ratio (O 2 / (O 2 + Ar)) is 50% or less, preferably 10% or more and 30. It is better to do it at% or less.
  • the heat treatment may be performed, for example, at 100 ° C. or higher and 450 ° C. or lower, more preferably 350 ° C. or higher and 400 ° C. or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment is preferably performed in an oxygen atmosphere.
  • oxygen can be supplied to the oxide 530 to reduce oxygen deficiency (VO ).
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas. good.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of the oxidizing gas, and then the heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.
  • the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate).
  • oxygen for example, oxygen atom, oxygen molecule, etc.
  • the oxygen contained in the oxide 530 does not diffuse to the insulator 520 side, which is preferable. Further, it is possible to suppress the conductor 503 from reacting with the oxygen contained in the insulator 524 and the oxide 530.
  • the insulator 522 may be, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTIO 3 ), or It is preferable to use an insulator containing a so-called high-k material such as (Ba, Sr) TiO 3 (BST) in a single layer or in a laminated state. As transistors become finer and more integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as a gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • a so-called high-k material such as (Ba, Sr) TiO 3 (BST)
  • an insulator containing oxides of one or both of aluminum and hafnium which are insulating materials having a function of suppressing diffusion of impurities and oxygen (the above oxygen is difficult to permeate).
  • the insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.
  • the insulator 522 is formed by using such a material, the insulator 522 suppresses the release of oxygen from the oxide 530 and the mixing of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530. Functions as a layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated on the above insulator.
  • the insulator 520 is thermally stable.
  • silicon oxide and silicon nitride nitride are suitable because they are thermally stable.
  • an insulator made of high-k material and silicon oxide or silicon oxide nitride an insulator 520 having a laminated structure that is thermally stable and has a high relative permittivity can be obtained.
  • the insulator 520, the insulator 522, and the insulator 524 are shown as the second gate insulating film having a three-layer laminated structure.
  • the gate insulating film may have a single layer, two layers, or a laminated structure of four or more layers.
  • the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • oxide 530 a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel forming region.
  • oxide 530 In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium).
  • Hafnium, tantalum, tungsten, magnesium, etc. (one or more) and the like may be used.
  • the In-M-Zn oxide that can be applied as the oxide 530 is preferably CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) and CAC-OS (Cloud-Aligned Compound Semiconductor).
  • CAAC-OS C-Axis Aligned Crystalline Oxide Semiconductor
  • CAC-OS Cloud-Aligned Compound Semiconductor
  • In—Ga oxide, In—Zn oxide, In oxide and the like may be used as the oxide 530.
  • a metal oxide having a low carrier concentration for the transistor 500 it is preferable to use a metal oxide having a low carrier concentration for the transistor 500.
  • the impurity concentration in the metal oxide may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • impurities in the metal oxide include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon and the like.
  • hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency in the metal oxide.
  • oxygen vacancies and hydrogen combine to form a V O H.
  • V O H acts as a donor, sometimes electrons serving as carriers are generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using a metal oxide containing a large amount of hydrogen tends to have a normally-on characteristic.
  • the metal oxide since hydrogen in the metal oxide is easily moved by stress such as heat and electric field, if the metal oxide contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.
  • the highly purified intrinsic or substantially highly purified intrinsic it is preferable that the highly purified intrinsic or substantially highly purified intrinsic.
  • the impurities such as hydrogen (dehydration, may be described as dehydrogenation.) It is important to supply oxygen to the metal oxide to compensate for the oxygen deficiency (sometimes referred to as dehydrogenation treatment).
  • the metal oxide impurities is sufficiently reduced such V O H By using the channel formation region of the transistor, it is possible to have stable electrical characteristics.
  • a defect containing hydrogen in an oxygen deficiency can function as a donor of a metal oxide.
  • the carrier concentration may be evaluated instead of the donor concentration. Therefore, in the present specification and the like, as the parameter of the metal oxide, the carrier concentration assuming a state in which an electric field is not applied may be used instead of the donor concentration. That is, the "carrier concentration" described in the present specification and the like may be paraphrased as the "donor concentration".
  • the hydrogen concentration obtained by secondary ion mass spectrometry is less than 1 ⁇ 10 20 atoms / cm 3 , preferably 1 ⁇ 10 19 atoms / cm. It is less than 3, more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the metal oxide is a semiconductor having a large band gap and is intrinsic (also referred to as type I) or substantially intrinsic, and has a channel forming region.
  • the carrier concentration of the metal oxide is preferably less than 1 ⁇ 10 18 cm -3 , more preferably less than 1 ⁇ 10 17 cm -3 , and further preferably less than 1 ⁇ 10 16 cm -3. It is preferably less than 1 ⁇ 10 13 cm -3 , even more preferably less than 1 ⁇ 10 12 cm -3.
  • the lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but may be, for example, 1 ⁇ 10 -9 cm -3 .
  • the oxygen in the oxide 530 diffuses to the conductor 542a and the conductor 542b due to the contact between the conductor 542a and the conductor 542b and the oxide 530, and the conductor The 542a and the conductor 542b may be oxidized. It is highly probable that the conductivity of the conductor 542a and the conductor 542b will decrease due to the oxidation of the conductor 542a and the conductor 542b.
  • the diffusion of oxygen in the oxide 530 to the conductor 542a and the conductor 542b can be rephrased as the conductor 542a and the conductor 542b absorbing the oxygen in the oxide 530.
  • the oxide 530 diffuses into the conductor 542a and the conductor 542b, so that different layers are formed between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. May be done. Since the different layer contains more oxygen than the conductor 542a and the conductor 542b, it is presumed that the different layer has an insulating property.
  • the three-layer structure of the conductor 542a or the conductor 542b, the different layer, and the oxide 530b can be regarded as a three-layer structure composed of a metal-insulator-semiconductor, and MIS (Metal-Insulator-). It may be referred to as a Semiconductor) structure, or it may be referred to as a diode junction structure mainly composed of a MIS structure.
  • the different layer is not limited to being formed between the conductor 542a and the conductor 542b and the oxide 530b.
  • the different layer is formed between the conductor 542a and the conductor 542b and the oxide 530c. May be formed in.
  • the metal oxide that functions as a channel forming region in the oxide 530 it is preferable to use a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using a metal oxide having a large bandgap, the off-current of the transistor can be reduced.
  • the oxide 530 can suppress the diffusion of impurities into the oxide 530b from the structure formed below the oxide 530a. Further, by having the oxide 530c on the oxide 530b, it is possible to suppress the diffusion of impurities into the oxide 530b from the structure formed above the oxide 530c.
  • the oxide 530 preferably has a laminated structure due to a plurality of oxide layers having different atomic number ratios of each metal atom.
  • the atomic number ratio of the element M in the constituent elements is larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used in the oxide 530b. Is preferable.
  • the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 530b.
  • the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a.
  • the oxide 530c a metal oxide that can be used for the oxide 530a or the oxide 530b can be used.
  • the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a is smaller than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530b
  • In-Ga-Zn oxide having a composition of 3 or its vicinity can be used.
  • a metal oxide having a composition in the vicinity of any one can be used.
  • oxides 530a, oxides 530b, and oxides 530c so as to satisfy the above-mentioned atomic number ratio relationship.
  • the above composition indicates the atomic number ratio in the oxide formed on the substrate or the atomic number ratio in the sputter target.
  • the composition of the oxide 530b by increasing the ratio of In, the on-current of the transistor, the mobility of the field effect, and the like can be increased, which is preferable.
  • the energy at the lower end of the conduction band of the oxide 530a and the oxide 530c is higher than the energy at the lower end of the conduction band of the oxide 530b.
  • the electron affinity of the oxide 530a and the oxide 530c is smaller than the electron affinity of the oxide 530b.
  • the energy level at the lower end of the conduction band changes gently.
  • the energy level at the lower end of the conduction band at the junction of the oxide 530a, the oxide 530b, and the oxide 530c is continuously changed or continuously bonded.
  • the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) other than oxygen, so that a mixed layer having a low defect level density is formed.
  • a common element (main component) other than oxygen so that a mixed layer having a low defect level density is formed.
  • the oxide 530b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide or the like may be used as the oxide 530a and the oxide 530c.
  • the main path of the carrier is oxide 530b.
  • the defect level density at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.
  • a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided on the oxide 530b.
  • the conductors 542a and 542b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium.
  • Iridium, strontium, lanthanum, or an alloy containing the above-mentioned metal element as a component, or an alloy in which the above-mentioned metal element is combined is preferably used.
  • tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are used. Is preferable.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.
  • the conductor 542a and the conductor 542b are shown as a single-layer structure, but a laminated structure of two or more layers may be used.
  • a tantalum nitride film and a tungsten film may be laminated.
  • the titanium film and the aluminum film may be laminated.
  • a two-layer structure in which an aluminum film is laminated on a tungsten film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a tungsten film. It may have a two-layer structure in which copper films are laminated.
  • a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed on the aluminum film or the copper film.
  • a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.
  • a region 543a and a region 543b may be formed as low resistance regions at the interface between the conductor 542a and the conductor 542b and the vicinity thereof of the oxide 530, respectively. ..
  • the region 543a functions as one of the source region or the drain region
  • the region 543b functions as the other of the source region or the drain region.
  • a channel forming region is formed in a region sandwiched between the region 543a and the region 543b.
  • the oxygen concentration in the region 543a (region 543b) may be reduced. Further, in the region 543a (region 543b), a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the component of the oxide 530 may be formed. In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.
  • the insulator 544 is provided so as to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided so as to cover each side surface of the oxide 530 and the insulator 524 so as to be in contact with the insulator 522.
  • insulator 544 a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Can be used. Further, as the insulator 544, silicon nitride oxide, silicon nitride or the like can also be used.
  • the insulator 544 it is preferable to use aluminum or an oxide containing one or both oxides of hafnium, such as aluminum oxide, hafnium oxide, aluminum, and an oxide containing hafnium (hafnium aluminate). ..
  • hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in the subsequent step.
  • the conductors 542a and 542b are made of a material having oxidation resistance, or if the conductivity does not significantly decrease even if oxygen is absorbed, the insulator 544 is not an indispensable configuration. It may be appropriately designed according to the desired transistor characteristics.
  • the insulator 544 By having the insulator 544, it is possible to prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. Further, it is possible to suppress the oxidation of the conductor 560 due to the excess oxygen contained in the insulator 580.
  • the insulator 550 functions as a first gate insulating film.
  • the insulator 550 is preferably arranged in contact with the inside (upper surface and side surface) of the oxide 530c.
  • the insulator 550 is preferably formed by using an insulator that contains excess oxygen and releases oxygen by heating.
  • silicon oxide having excess oxygen silicon oxide, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, carbon, silicon oxide to which nitrogen is added, and vacancies are used.
  • Silicon oxide having can be used.
  • silicon oxide and silicon nitride nitride are preferable because they are stable against heat.
  • oxygen is effectively applied from the insulator 550 through the oxide 530c to the channel forming region of the oxide 530b. Can be supplied. Further, similarly to the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced.
  • the film thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.
  • a metal oxide may be provided between the insulator 550 and the conductor 560.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560.
  • the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to the oxide 530.
  • oxidation of the conductor 560 due to excess oxygen can be suppressed.
  • a material that can be used for the insulator 544 may be used.
  • the insulator 550 may have a laminated structure as in the case of the second gate insulating film.
  • an insulator that functions as a gate insulating film is made of a high-k material and heat.
  • the conductor 560 functioning as the first gate electrode is shown as a two-layer structure in FIGS. 8A and 8B, it may have a single-layer structure or a laminated structure of three or more layers.
  • Conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), conductive having a function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 560b from being oxidized by the oxygen contained in the insulator 550 and the conductivity from being lowered.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b into a film by a sputtering method, the electric resistance value of the conductor 560a can be lowered to form a conductor. This can be referred to as an OC (Oxide Conductor) electrode.
  • the conductor 560b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductor 560b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 560b may have a laminated structure, for example, titanium or a laminated structure of titanium nitride and the conductive material.
  • the insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544.
  • the insulator 580 preferably has an excess oxygen region.
  • silicon, resin, or the like silicon oxide and silicon oxide nitride are preferable because they are thermally stable.
  • silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later step.
  • the insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating in contact with the oxide 530c, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. It is preferable that the concentration of impurities such as water and hydrogen in the insulator 580 is reduced.
  • the opening of the insulator 580 is formed so as to overlap the region between the conductor 542a and the conductor 542b.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
  • the conductor 560 may have a shape having a high aspect ratio.
  • the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a shape having a high aspect ratio, the conductor 560 is formed without collapsing during the process. Can be done.
  • the insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550.
  • an excess oxygen region can be provided in the insulator 550 and the insulator 580. Thereby, oxygen can be supplied into the oxide 530 from the excess oxygen region.
  • the insulator 574 use one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like. Can be done.
  • aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, the aluminum oxide formed by the sputtering method can have a function as a barrier film for impurities such as hydrogen as well as an oxygen supply source.
  • the insulator 513 and the insulator 576 preferably have a high function of suppressing the diffusion of hydrogen (for example, at least one hydrogen atom, hydrogen molecule, etc.) or water molecule.
  • hydrogen for example, at least one hydrogen atom, hydrogen molecule, etc.
  • the insulator 513 and the insulator 576 it is preferable to use silicon nitride or silicon nitride oxide, which is a material having a high hydrogen barrier property.
  • silicon nitride or silicon nitride oxide which is a material having a high hydrogen barrier property.
  • the insulator 581 that functions as an interlayer film and a flattening film on the insulator 576.
  • the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.
  • the insulator 552 is provided on the side surface of the insulator 581, the insulator 576, the insulator 574, the insulator 580, and the opening formed in the insulator 544. Then, the conductor 540a and the conductor 540b are provided so as to be in contact with the side surface of the insulator 552 and the bottom surface of the opening. In FIG. 8A, the conductor 540a and the conductor 540b are provided so as to face each other with the conductor 560 interposed therebetween.
  • the insulator 552 is provided in contact with, for example, the insulator 581, the insulator 576, the insulator 574, the insulator 580, and the insulator 544.
  • the insulator 552 preferably has a function of suppressing the diffusion of hydrogen or water molecules.
  • an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide, which is a material having a high hydrogen barrier property.
  • silicon nitride is a material having a high hydrogen barrier property, it is suitable to be used as an insulator 552.
  • the insulator 552 By using a material having a high hydrogen barrier property as the insulator 552, it is possible to suppress the diffusion of impurities such as water or hydrogen from the insulator 580 or the like to the oxide 530 through the conductor 540a and the conductor 540b. Further, it is possible to prevent the oxygen contained in the insulator 580 from being absorbed by the conductor 540a and the conductor 540b. As described above, the reliability of the storage device of one aspect of the present invention can be enhanced.
  • each of the conductor 540a and the conductor 540b has a laminated structure of two or more layers, and impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms are diffused in the first layer in contact with the insulator 552.
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms are diffused in the first layer in contact with the insulator 552.
  • an insulator 582 is provided on the insulator 581.
  • the insulator 582 it is preferable to use a substance having a barrier property against oxygen and / or hydrogen. Therefore, the same material as the insulator 514 can be used for the insulator 582.
  • a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.
  • aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • an insulator 586 is provided on the insulator 582.
  • the same material as the insulator 320 can be used. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 586.
  • a conductor 540a, a conductor 540b, a conductor 546, and the like are embedded in the body 586.
  • the conductor 546 for example, a material applicable to the conductor 540a and the conductor 540b can be used.
  • the conductor 540a, the conductor 540b, and the conductor 546 function as a plug or wiring for connecting the transistor 500, the transistor 300, the conductor 450 described later, the conductor 460, and the like. Further, the conductor 540a and the conductor 540b can be provided by using the same materials as the conductor 328 and the conductor 330. In particular, in FIG. 7, the conductor 546 is formed so as to come into contact with the conductor 518.
  • the conductor 450 may be provided on the conductor 540a, the conductor 540b, the conductor 546, and the insulator 586.
  • the conductor 450 functions as wiring for connecting the conductor 460, the transistor 300, the transistor 500, etc., which will be described later.
  • the conductor 450 is formed so as to come into contact with the conductor 540a, the conductor 540b, the conductor 546, and the like.
  • the conductor 450 includes, for example, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned elements (tantallum nitride).
  • a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium or a metal nitride film containing the above-mentioned elements (tantallum nitride).
  • a film, a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) or the like can be used.
  • indium tin oxide indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply a conductive material such as indium tin oxide.
  • the conductor 450 has a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used.
  • a conductor having a barrier property and a conductor having a high adhesion to a conductor having a high conductivity may be formed between a conductor having a barrier property and a conductor having a high conductivity.
  • the memory element 400 is an MTJ element ME included in the resistance change device MD of the memory cell MC shown in FIGS. 3A and 3B.
  • the memory element 400 is provided in a part of the area on the conductor 450.
  • the memory element 400 has a conductor 401, an insulator 402, a conductor 403, and a conductor 404, and the conductor 401, the insulator 402, the conductor 403, and the conductor 404 are in this order. It is laminated in the area.
  • the conductor 401 is a free layer in the memory element 400 and corresponds to the layer FL of the MTJ element ME in FIG.
  • the insulator 402 is a tunnel insulator in the memory element 400, and corresponds to the layer TIS of the MTJ element ME in FIG.
  • the conductor 403 is a fixed layer in the MTJ element ME, and corresponds to the layer RL of the MTJ element ME in FIG. Therefore, for the materials applicable to each of the conductor 401, the insulator 402, and the conductor 403, the description of the MTJ element ME in FIG. 4 is taken into consideration.
  • the conductor 404 is provided as a hard mask for forming the conductor 401, the insulator 402, and the conductor 403. Therefore, as the conductor 404, for example, a material applicable to the conductor 328, the conductor 330, and the like can be used.
  • the insulator 452 is provided so as to cover the insulator 586, the conductor 450, the conductor 401, the insulator 402, the conductor 403, and the conductor 404.
  • the insulator 452 for example, like the insulator 324, it is preferable to use a film having a barrier property so that impurities such as water and hydrogen do not diffuse in the region where the transistor 500 is provided. That is, as the insulator 452, it is preferable to use a material applicable to the insulator 324 and the like.
  • An insulator 454 is provided on the insulator 452.
  • the insulator 454 functions as a flattening film that flattens the steps generated by the conductor 450, the memory element 400, the insulator 452, and the like. Further, the insulator 454 is flattened until the conductor 404 is exposed by using, for example, a chemical mechanical polishing (CMP) method or the like after the insulator to be the insulator 454 is formed on the insulator 452. Can be formed by performing.
  • CMP chemical mechanical polishing
  • Insulator 456 is provided on the insulator 454, the insulator 452, and the conductor 404.
  • the insulator 454 and the insulator 456, for example, like the insulator 326, it is preferable to use an insulator having a relatively low relative permittivity. That is, as the insulator 454 and the insulator 456, it is preferable to use a material applicable to the insulator 326.
  • a conductor 457 is embedded in the insulator 456. Further, a conductor 458 is embedded in the insulator 452, the insulator 454, and the insulator 456.
  • the conductor 457 and the conductor 458 have a function as a plug or wiring.
  • a conductor having a function as a plug or wiring may collectively give a plurality of structures the same reference numerals. Further, in the present specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • a conductor 460 is provided on the insulator 456, the conductor 457, and the conductor 458.
  • the conductor 460 can be, for example, a wiring that is electrically connected to the memory element 400. Specifically, it can be the wiring RBL shown in the memory cell MC of FIG.
  • the conductor 460 for example, a material applicable to the conductor 450 can be used.
  • An insulator 459 is provided on the insulator 456. Further, in some cases, an insulator 459 may be provided on the conductor 457 and / or the conductor 458. The insulator 459 functions as, for example, an insulator for separating wirings. In the storage device MDV of FIG. 7, the insulator 459 has the same height as the conductor 460 by a flattening treatment such as a chemical mechanical polishing (CMP) method.
  • CMP chemical mechanical polishing
  • the insulator 459 for example, it is preferable to use an insulator having a relatively low relative permittivity, like the insulator 326. That is, as the insulator 459, it is preferable to use a material applicable to the insulator 326.
  • an insulator 462 is provided on the conductor 460 and the insulator 459.
  • the insulator 462 for example, it is preferable to use a film having a barrier property so that impurities such as water and hydrogen do not diffuse between the OSLs of the upper layer and the lower layer. Therefore, as the insulator 462, for example, like the insulator 324, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen.
  • a layer OSL [2] (not shown) to a layer OSL [p] is provided above the insulator 462, and the layer OSL [2] to the layer OSL [p] is the layer OSL [1]. It can be produced in the same process as above. Therefore, the insulator 462 may be formed as the same material as the insulator 510. Further, by producing the layer OSL [2] to the layer OSL [p] in the same process as the layer OSL [1], the layer OSL [1] is placed above the memory cell array MCA contained in the layer OSL [1], for example, a layer. The respective memory cell array MCA of OSL [2] to layer OSL [p] can be stacked.
  • each memory cell 600 of the layer OSL [2] to the layer OSL [p] can be laminated on the memory cell 600 included in the layer OSL [1].
  • the configuration example of the storage device MDV shown in FIG. 7 can be applied to the storage device MDV shown in FIG. 1B.
  • FIG. 7 shows a configuration example of a storage device MDV in which the memory cell 600 is the memory cell MC of FIG. 3A, but one aspect of the present invention is not limited to this.
  • the storage device MDV may be configured by using the memory cell 600 as the memory cell MC of FIG. 3C.
  • FIG. 9 shows the configuration of the storage device MDV in which the memory cell 600 is the memory cell MC of FIG. 3C.
  • the transistor 500A corresponds to the transistor M4 of FIG. 3C
  • the transistor 500B corresponds to the transistor M3
  • the memory element 400 corresponds to the resistance change device MD.
  • the transistor 500A and the transistor 500B are formed so as to share the insulator 524, the oxide 530a, the oxide 530b, and one of the conductor 542a or the conductor 542b with each other.
  • the insulator 580 and the conductor 542 are provided with two openings reaching the oxide 530, and the oxide 530c, the insulator 550, and the conductor 560 are provided in the respective openings. It is provided.
  • the first terminal of the transistor 500A and the first terminal of the transistor 500B can be provided so as to share either the conductor 542a or the conductor 542b with each other.
  • the area formed by the transistor 500A and the transistor 500B can be made smaller than the area formed by the transistor 500A and the transistor 500B separately. As a result, the area for forming the memory cell 600 can be reduced, so that the area per bit can be reduced as the bit density.
  • the first terminal of the transistor 500A is electrically connected to the first terminal of the transistor 500B, and the second terminal of the transistor 500B is electrically connected to the first terminal of the memory element 400.
  • the second terminal of the memory element 400 is electrically connected to the second terminal of the transistor 500A.
  • the wiring SL in FIG. 3C can be, for example, a conductor 450 electrically connected to the first terminal of the transistor 500A and the first terminal of the transistor 500B.
  • the wiring BL in FIG. 3C can be, for example, a conductor 450 that is electrically connected between the second terminal of the transistor 500B and the memory element 400.
  • the wiring WLa in FIG. 3C can be, for example, a conductor 560 corresponding to the gate of the transistor 500B.
  • the wiring WLb in FIG. 3C can be, for example, a conductor 560 corresponding to the gate of the transistor 500A.
  • the storage device MDV may be configured by using the memory cell 600 as the memory cell MC of FIGS. 6A to 6C.
  • FIG. 10 shows the configuration of a storage device MDV in which the memory cell 600 is the memory cell MC of FIGS. 6A to 6C.
  • the transistor 500A corresponds to the transistor M10 of FIGS. 6A to 6C
  • the memory element 400 is the MTJ element of FIG. 6A, the resistance changing element RM of FIG. 6B, and FIG. 6C.
  • the first terminal of the transistor 500A is electrically connected to the first terminal of the memory element 400.
  • the wiring SL of FIGS. 6A to 6C can be, for example, a conductor 450 electrically connected to the second terminal of the transistor 500A.
  • the wiring BL of FIGS. 6A to 6C can be, for example, a conductor 460 electrically connected to the second terminal of the memory element 400.
  • the wiring WL of FIGS. 6A to 6C can be, for example, a conductor 560 electrically connected to the gate of the transistor 500A.
  • the configuration of the memory element 400 is different for each memory cell MC of FIGS. 6A to 6C. Therefore, in the storage device MDV of FIG. 10, the portion where the memory element 400 is formed is indicated by vertical stripe hatching. Further, in FIG. 10, an insulator 452 is provided on the side surface of the memory element 400, but depending on the configuration of the memory element 400, the insulator 452 may not be provided on the side surface of the memory element 400.
  • a storage device By applying the above configuration as a storage device, it is possible to provide a storage device with low power consumption. Alternatively, a storage device having a large storage capacity can be provided. Alternatively, a new storage device can be provided.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium, tin and the like are contained. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like. ..
  • FIG. 11A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (metal oxides containing In, Ga, and Zn).
  • IGZO metal oxides containing In, Ga, and Zn
  • oxide semiconductors are roughly classified into “Amorphous”, “Crystalline”, and “Crystal”.
  • Amorphous includes complete amorphous.
  • the “Crystalline” includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite) (exclusion single crystal crystal).
  • CAAC c-axis-aligned crystalline
  • nc nanocrystalline
  • CAC Cloud-Aligned Composite
  • single crystal, poly crystal, and single crystal amorphous are excluded from the classification of "Crystalline”.
  • “Crystal” includes single crystal and poly crystal.
  • the structure in the thick frame shown in FIG. 11A is an intermediate state between "Amorphous” and “Crystal", and belongs to a new boundary region (New crystal phase). .. That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous” and "Crystal".
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum.
  • XRD X-ray diffraction
  • FIG. 11B the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in FIG. 11B (the vertical axis represents the intensity in any unit (a.u.)). (Represented by).
  • the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum obtained by the GIXD measurement shown in FIG. 11B may be simply referred to as an XRD spectrum.
  • the thickness of the CAAC-IGZO film shown in FIG. 11B is
  • a peak showing clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film.
  • the crystal structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a microelectron diffraction pattern) observed by a micro electron diffraction method (NBED: Nano Beam Electron Diffraction).
  • the diffraction pattern of the CAAC-IGZO film is shown in FIG. 11C.
  • FIG. 11C is a diffraction pattern observed by the NBED in which the electron beam is incident parallel to the substrate.
  • electron beam diffraction is performed with the probe diameter set to 1 nm.
  • oxide semiconductors may be classified differently from FIG. 11A.
  • oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS.
  • the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.
  • CAAC-OS CAAC-OS
  • nc-OS nc-OS
  • a-like OS the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.
  • CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions are oriented in a specific direction on the c-axis.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
  • the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region in which the lattice arrangement is aligned. Further, the CAAC-OS has a region in which a plurality of crystal regions are connected in the ab plane direction, and the region may have distortion.
  • the strain refers to a region in which a plurality of crystal regions are connected in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another grid arrangement is aligned. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and not clearly oriented in the ab plane direction.
  • Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the size of the crystal region may be about several tens of nm.
  • CAAC-OS has indium (In) and oxygen. It tends to have a layered crystal structure (also referred to as a layered structure) in which a layer (hereinafter, In layer) and a layer having elements M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are laminated. There is. Indium and element M can be replaced with each other. Therefore, the (M, Zn) layer may contain indium. In addition, the In layer may contain the element M. The In layer may contain Zn.
  • the layered structure is observed as a lattice image in, for example, a high-resolution TEM image.
  • the position of the peak indicating the c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.
  • a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film.
  • a certain spot and another spot are observed at point-symmetrical positions with the spot of the incident electron beam passing through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit lattice is not limited to a regular hexagon and may be a non-regular hexagon. Further, in the above strain, it may have a lattice arrangement such as a pentagon or a heptagon.
  • a clear grain boundary cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and that the bond distance between atoms changes due to the replacement of metal atoms. it is conceivable that.
  • CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
  • a configuration having Zn is preferable.
  • In-Zn oxide and In-Ga-Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries. Further, since the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities and the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures (so-called thermal budgets) in the manufacturing process. Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • nc-OS has tiny crystals. Since the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also referred to as a nanocrystal.
  • nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
  • nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductor depending on the analysis method. For example, when a structural analysis is performed on an nc-OS film using an XRD apparatus, a peak indicating crystallinity is not detected in the Out-of-plane XRD measurement using a ⁇ / 2 ⁇ scan. Further, when electron beam diffraction (also referred to as selected area electron diffraction) using an electron beam having a probe diameter (for example, 50 nm or more) larger than that of nanocrystals is performed on the nc-OS film, a diffraction pattern such as a halo pattern is performed. Is observed.
  • electron beam diffraction also referred to as selected area electron diffraction
  • a probe diameter for example, 50 nm or more
  • electron diffraction also referred to as nanobeam electron diffraction
  • an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
  • An electron diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be acquired.
  • the a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. In addition, a-like OS has a higher hydrogen concentration in the membrane than nc-OS and CAAC-OS.
  • CAC-OS relates to the material composition.
  • CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the mixed state is also called a mosaic shape or a patch shape.
  • CAC-OS has a structure in which the material is separated into a first region and a second region to form a mosaic shape, and the first region is distributed in the film (hereinafter, also referred to as a cloud shape). It says.). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
  • the atomic number ratios of In, Ga, and Zn with respect to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
  • the first region is a region in which [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region in which [Ga] is larger than [Ga] in the composition of the CAC-OS film.
  • the first region is a region in which [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
  • the first region is a region in which indium oxide, indium zinc oxide, or the like is the main component.
  • the second region is a region in which gallium oxide, gallium zinc oxide, or the like is the main component. That is, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
  • a region containing In as a main component (No. 1) by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region (1 region) and the region containing Ga as a main component (second region) have a structure in which they are unevenly distributed and mixed.
  • EDX Energy Dispersive X-ray spectroscopy
  • CAC-OS When CAC-OS is used for a transistor, the conductivity caused by the first region and the insulating property caused by the second region act in a complementary manner to switch the switching function (On / Off function). Can be added to the CAC-OS. That is, the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS for the transistor, high on-current ( Ion ), high field effect mobility ( ⁇ ), and good switching operation can be realized.
  • Ion on-current
  • ⁇ high field effect mobility
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one aspect of the present invention has two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. You may.
  • the oxide semiconductor as a transistor, a transistor with high field effect mobility can be realized. Moreover, a highly reliable transistor can be realized.
  • the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm -3 or less, preferably 1 ⁇ 10 15 cm -3 or less, more preferably 1 ⁇ 10 13 cm -3 or less, more preferably 1 ⁇ 10 11 cm ⁇ . It is 3 or less, more preferably less than 1 ⁇ 10 10 cm -3 , and more than 1 ⁇ 10 -9 cm -3.
  • the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor are determined. , 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less. , More preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency.
  • oxygen deficiency When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , and more preferably 5 ⁇ 10 18 atoms / cm. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the present embodiment shows an example of a semiconductor wafer on which the storage device and the like shown in the above embodiment are formed, and an electronic component in which the storage device is incorporated.
  • the semiconductor wafer 4800 shown in FIG. 12A has a wafer 4801 and a plurality of circuit units 4802 provided on the upper surface of the wafer 4801.
  • the portion without the circuit portion 4802 is the spacing 4803, which is a dicing region.
  • the semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 by the previous process. Further, after that, the surface of the wafer 4801 on the opposite side on which the plurality of circuit portions 4802 are formed may be ground to reduce the thickness of the wafer 4801. By this step, the warp of the wafer 4801 can be reduced and the size of the wafer can be reduced.
  • a dicing process is performed. Dicing is performed along the scribing line SCL1 and the scribing line SCL2 (sometimes referred to as a dicing line or a cutting line) indicated by an alternate long and short dash line.
  • the spacing 4803 is provided so that a plurality of scribe lines SCL1 are parallel to each other and a plurality of scribe lines SCL2 are parallel to each other in order to facilitate the dicing process. It is preferable to provide it so that it is vertical.
  • the chip 4800a as shown in FIG. 12B can be cut out from the semiconductor wafer 4800.
  • the chip 4800a has a wafer 4801a, a circuit unit 4802, and a spacing 4803a.
  • the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between the adjacent circuit units 4802 may be substantially the same as the cutting margin of the scribe line SCL1 or the cutting margin of the scribe line SCL2.
  • the shape of the element substrate of one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in FIG. 12A.
  • the shape of the element substrate can be appropriately changed depending on the process of manufacturing the device and the device for manufacturing the device.
  • FIG. 12C shows a perspective view of a substrate (mounting substrate 4704) on which the electronic component 4700 and the electronic component 4700 are mounted.
  • the electronic component 4700 shown in FIG. 12C has a chip 4800a in the mold 4711.
  • the chip 4800a shown in FIG. 12C shows a configuration in which circuit units 4802 are laminated. That is, the storage device described in the above embodiment can be applied as the circuit unit 4802. In FIG. 12C, a part is omitted in order to show the inside of the electronic component 4700.
  • the electronic component 4700 has a land 4712 on the outside of the mold 4711.
  • the land 4712 is electrically connected to the electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a by a wire 4714.
  • the electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected to each other on the printed circuit board 4702 to complete the mounting board 4704.
  • FIG. 12D shows a perspective view of the electronic component 4730.
  • the electronic component 4730 is an example of SiP (System in package) or MCM (Multi Chip Module).
  • an interposer 4731 is provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.
  • the electronic component 4730 has a semiconductor device 4710.
  • the semiconductor device 4710 can be, for example, the storage device described in the above embodiment, a wideband memory (HBM: High Bandwidth Memory), or the like.
  • HBM High Bandwidth Memory
  • an integrated circuit semiconductor device such as a CPU, GPU, FPGA, or storage device can be used.
  • the package substrate 4732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 4731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or multiple layers.
  • the interposer 4731 has a function of electrically connecting the integrated circuit provided on the interposer 4731 to the electrode provided on the package substrate 4732.
  • the interposer may be referred to as a "rewiring board” or an "intermediate board”.
  • a through electrode may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode.
  • a TSV Through Silicon Via
  • interposer 4731 It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide an active element in the silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with a resin interposer.
  • the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer on which the HBM is mounted.
  • the reliability is unlikely to decrease due to the difference in the expansion coefficient between the integrated circuit and the interposer. Further, since the surface of the silicon interposer is high, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
  • a heat sink may be provided so as to be overlapped with the electronic component 4730.
  • the heat sink it is preferable that the heights of the integrated circuits provided on the interposer 4731 are the same.
  • the heights of the semiconductor device 4710 and the semiconductor device 4735 are the same.
  • an electrode 4733 may be provided on the bottom of the package substrate 4732.
  • FIG. 12D shows an example in which the electrode 4733 is formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Further, the electrode 4733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 4730 can be mounted on another substrate by using various mounting methods, not limited to BGA and PGA.
  • BGA Band-GPU
  • PGA Stimble Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN QuadFNeged
  • FIG. 13 is a block diagram showing a configuration of an example of a CPU using the storage device described in the above embodiment as a part.
  • the CPU shown in FIG. 13 has an ALU 1191 (ALU: Arithmetic logic unit, arithmetic unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198 on a substrate 1190. It has (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F).
  • the substrate 1190 a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used.
  • the ROM 1199 and the ROM interface 1189 may be provided on separate chips.
  • the configuration including the CPU or the arithmetic circuit shown in FIG. 13 may be one core, and a plurality of the cores may be included and each core may operate in parallel, that is, a configuration such as a GPU.
  • the number of bits that the CPU can handle in the internal arithmetic circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.
  • Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.
  • the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. Further, the interrupt controller 1194 determines and processes an interrupt request from an external input / output device, peripheral circuits, etc. from its priority, mask state, etc. during the execution of the CPU program. The register controller 1197 generates the address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.
  • the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197.
  • the timing controller 1195 includes an internal clock generator that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the above-mentioned various circuits.
  • Register 1196 may include, for example, the storage device shown in the previous embodiment.
  • the register controller 1197 selects the holding operation in the register 1196 according to the instruction from the ALU 1191. That is, in the memory cell of the register 1196, it is selected whether to hold the data by the flip-flop or the data by the capacitive element. When the holding of data by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When the retention of data in the capacitive element is selected, the data is rewritten to the capacitive element, and the supply of the power supply voltage to the memory cell in the register 1196 can be stopped.
  • FIGS. 14A to 14J and FIGS. 15A to 15E show how the electronic component 4700 having the storage device is included in each electronic device.
  • the information terminal 5500 shown in FIG. 14A is a mobile phone (smartphone) which is a kind of information terminal.
  • the information terminal 5500 has a housing 5510 and a display unit 5511, and as an input interface, a touch panel is provided in the display unit 5511 and buttons are provided in the housing 5510.
  • the information terminal 5500 can hold a temporary file (for example, a cache when using a web browser) generated when the application is executed.
  • a temporary file for example, a cache when using a web browser
  • FIG. 14B shows an information terminal 5900 which is an example of a wearable terminal.
  • the information terminal 5900 includes a housing 5901, a display unit 5902, an operation button 5903, an operator 5904, a band 5905, and the like.
  • the wearable terminal can hold a temporary file generated when the application is executed by applying the storage device described in the above embodiment.
  • FIG. 14C shows a desktop information terminal 5300.
  • the desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can hold a temporary file generated when the application is executed by applying the storage device described in the above embodiment.
  • smartphones, wearable terminals, and desktop information terminals are taken as examples of electronic devices and are shown in FIGS. 14A to 14C, respectively.
  • information terminals other than smartphones, wearable terminals, and desktop information terminals can be applied.
  • Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook-type information terminals, and workstations.
  • FIG. 14D shows an electric freezer / refrigerator 5800 as an example of an electric appliance.
  • the electric freezer / refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric freezer / refrigerator 5800 can be used as, for example, IoT (Internet of Things).
  • IoT Internet of Things
  • the electric freezer / refrigerator 5800 can send / receive information such as the foodstuffs stored in the electric freezer / refrigerator 5800 and the expiration date of the foodstuffs to the above-mentioned information terminal or the like via the Internet or the like. can.
  • the electric refrigerator / freezer 5800 transmits the information, the information can be stored in the storage device as a temporary file.
  • an electric refrigerator / freezer has been described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Equipment, washing machines, dryers, audiovisual equipment, etc. can be mentioned.
  • FIG. 14E shows a portable game machine 5200, which is an example of a game machine.
  • the portable game machine 5200 has a housing 5201, a display unit 5202, a button 5203, and the like.
  • FIG. 14F shows a stationary game machine 7500, which is an example of a game machine.
  • the stationary game machine 7500 has a main body 7520 and a controller 7522.
  • the controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 can be provided with a display unit for displaying a game image, a touch panel serving as an input interface other than buttons, a stick, a rotary knob, a slide type knob, and the like.
  • the controller 7522 is not limited to the shape shown in FIG. 14F, and the shape of the controller 7522 may be variously changed according to the genre of the game.
  • a controller shaped like a gun can be used by using a trigger as a button.
  • a controller having a shape imitating a musical instrument, a music device, or the like can be used.
  • the stationary game machine may be in a form in which a controller is not used, and instead, a camera, a depth sensor, a microphone, and the like are provided and operated by the gesture and / or voice of the game player.
  • the above-mentioned video of the game machine can be output by a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • the portable game machine 5200 with low power consumption can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • Examples of the electronic device of one aspect of the present invention include an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, and the like.
  • the storage device described in the above embodiment can be applied to a moving vehicle and the vicinity of the driver's seat of the automobile.
  • FIG. 14G shows an automobile 5700 as an example of a moving body.
  • an instrument panel that provides various information by displaying speedometer, tachometer, mileage, fuel gauge, gear status, air conditioner setting, etc. is provided. Further, a display device for displaying such information may be provided around the driver's seat.
  • the storage device described in the above embodiment can temporarily hold information
  • the storage device is an automatic driving system for an automobile 5700
  • the storage device is a system for road guidance, danger prediction, and the like. It can be used to retain necessary temporary information in.
  • the display device may be configured to display temporary information such as road guidance and danger prediction.
  • the image of the driving recorder installed in the automobile 5700 may be held.
  • moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the like.
  • FIG. 14H shows a digital camera 6240, which is an example of an imaging device.
  • the digital camera 6240 has a housing 6241, a display unit 6242, an operation button 6243, a shutter button 6244, and the like, and a removable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 has a configuration in which the lens 6246 can be removed from the housing 6241 and replaced here, the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured so that a strobe device, a viewfinder, and the like can be separately attached.
  • a low power consumption digital camera 6240 can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • Video camera The storage device described in the above embodiment can be applied to a video camera.
  • FIG. 14I shows a video camera 6300, which is an example of an imaging device.
  • the video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation key 6304, a lens 6305, a connection unit 6306, and the like.
  • the operation key 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302.
  • the first housing 6301 and the second housing 6302 are connected by a connecting portion 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connecting portion 6306. be.
  • the image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 on the connecting unit 6306.
  • the video camera 6300 When recording the video captured by the video camera 6300, it is necessary to encode according to the data recording format. By utilizing the storage device described above, the video camera 6300 can hold a temporary file generated during encoding.
  • ICD implantable cardioverter defibrillator
  • FIG. 14 (J) is a schematic cross-sectional view showing an example of ICD.
  • the ICD body 5400 has at least a battery 5401, an electronic component 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.
  • the ICD body 5400 is surgically placed in the body, and two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body, and one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium. To be done.
  • the ICD main body 5400 has a function as a pacemaker and performs pacing to the heart when the heart rate deviates from the specified range. Also, if pacing does not improve heart rate (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with electric shock is given.
  • the ICD body 5400 needs to constantly monitor the heart rate in order to properly perform pacing and electric shock. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. Further, the ICD main body 5400 can store the heart rate data acquired by the sensor or the like, the number of times of treatment by pacing, the time, etc. in the electronic component 4700.
  • the ICD main body 5400 has a plurality of batteries, so that the safety can be enhanced. Specifically, even if a part of the battery of the ICD main body 5400 becomes unusable, the remaining battery can function, so that it also functions as an auxiliary power source.
  • the antenna 5404 that can receive power it may have an antenna that can transmit physiological signals.
  • physiological signals such as pulse, respiratory rate, heart rate, and body temperature can be confirmed by an external monitoring device.
  • a system for monitoring various cardiac activities may be configured.
  • the storage device described in the above embodiment can be applied to a computer such as a PC (Personal Computer) and an expansion device for an information terminal.
  • a computer such as a PC (Personal Computer) and an expansion device for an information terminal.
  • FIG. 15A shows an expansion device 6100 externally attached to a PC, which is equipped with a portable chip capable of storing information, as an example of the expansion device.
  • the expansion device 6100 can store information by the chip by connecting to a PC by, for example, USB (Universal Serial Bus) or the like.
  • USB Universal Serial Bus
  • FIG. 15A illustrates a portable expansion device 6100, but the expansion device according to one aspect of the present invention is not limited to this, and is relatively equipped with, for example, a cooling fan. It may be a large form of expansion device.
  • the expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104.
  • the substrate 6104 is housed in the housing 6101.
  • the substrate 6104 is provided with a circuit for driving the storage device and the like described in the above embodiment.
  • an electronic component 4700 and a controller chip 6106 are attached to the substrate 6104.
  • the USB connector 6103 functions as an interface for connecting to an external device.
  • SD card The storage device described in the above embodiment can be applied to an SD card that can be attached to an electronic device such as an information terminal or a digital camera.
  • FIG. 15B is a schematic view of the appearance of the SD card
  • FIG. 15C is a schematic view of the internal structure of the SD card.
  • the SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113.
  • the connector 5112 functions as an interface for connecting to an external device.
  • the substrate 5113 is housed in the housing 5111.
  • the substrate 5113 is provided with a storage device and a circuit for driving the storage device.
  • an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113.
  • the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and the circuit configurations may be appropriately changed depending on the situation.
  • the writing circuit, the low driver, the reading circuit, and the like provided in the electronic component may be incorporated in the controller chip 5115 instead of the electronic component 4700.
  • the capacity of the SD card 5110 can be increased.
  • a wireless chip having a wireless communication function may be provided on the substrate 5113. As a result, wireless communication can be performed between the external device and the SD card 5110, and the data of the electronic component 4700 can be read and written.
  • SSD Solid State Drive
  • electronic device such as an information terminal.
  • FIG. 15D is a schematic view of the appearance of the SSD
  • FIG. 15E is a schematic view of the internal structure of the SSD.
  • the SSD 5150 has a housing 5151, a connector 5152, and a substrate 5153.
  • the connector 5152 functions as an interface for connecting to an external device.
  • the board 5153 is housed in the housing 5151.
  • the substrate 5153 is provided with a storage device and a circuit for driving the storage device.
  • an electronic component 4700, a memory chip 5155, and a controller chip 5156 are attached to the substrate 5153.
  • a work memory is incorporated in the memory chip 5155.
  • a DRAM chip may be used as the memory chip 5155.
  • a processor, an ECC circuit, and the like are incorporated in the controller chip 5156.
  • the circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to the above description, and the circuit configurations may be appropriately changed depending on the situation.
  • the controller chip 5156 may also be provided with a memory that functions as a work memory.
  • a new electronic device can be provided by applying the storage device of the first embodiment or the second embodiment to the storage device included in the electronic device described above.
  • MDV Storage device
  • MCA Memory transistor
  • MCA [1] Memory cell
  • MCA [p-1] Memory transistor
  • MCA [p] Memory transistor
  • PHL Peripheral circuit
  • MC Memory cell
  • MC [1, 1] Memory cell
  • MC [m, 1] Memory cell
  • MC [1, n] Memory cell
  • MC [m, n] Memory cell
  • BD Circuit
  • WD Circuit
  • SD Circuit
  • RBD Circuit
  • CLC Circuit
  • OPC Circuit
  • M2 Transistor
  • M3 Transistor
  • M4 Transistor
  • M10 Transistor
  • MD Resistance change device
  • ME MTJ element
  • RM Resistance change element
  • PCM1 Phase Change memory
  • IT1 terminal
  • IT2 terminal
  • OT terminal
  • BL1 Phase Change memory
  • IT1 terminal
  • IT2 terminal
  • OT terminal
  • BL1 Phase Change memory
  • IT1 terminal
  • IT2 terminal
  • OT terminal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Hall/Mr Elements (AREA)
PCT/IB2021/052197 2020-03-27 2021-03-17 記憶装置、及び電子機器 Ceased WO2021191734A1 (ja)

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CN202180024777.XA CN115349169A (zh) 2020-03-27 2021-03-17 存储装置及电子设备
US17/911,196 US12477952B2 (en) 2020-03-27 2021-03-17 Memory device and electronic device
KR1020227034253A KR20220158241A (ko) 2020-03-27 2021-03-17 기억 장치 및 전자 기기
JP2022509749A JP7706440B2 (ja) 2020-03-27 2021-03-17 記憶装置、及び電子機器
JP2025111750A JP2025133834A (ja) 2020-03-27 2025-07-01 記憶装置
US19/369,677 US20260052909A1 (en) 2020-03-27 2025-10-27 Memory device and electronic device

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JP2020-058397 2020-03-27

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US19/369,677 Continuation US20260052909A1 (en) 2020-03-27 2025-10-27 Memory device and electronic device

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CN118588129B (zh) * 2024-08-06 2024-11-19 青岛海存微电子有限公司 磁存储结构及磁存储模块

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US20260052909A1 (en) 2026-02-19
JP2025133834A (ja) 2025-09-11
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US12477952B2 (en) 2025-11-18

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