WO2021189838A1 - 用于过压击穿功能的缓冲区变掺杂结构及半导体器件 - Google Patents

用于过压击穿功能的缓冲区变掺杂结构及半导体器件 Download PDF

Info

Publication number
WO2021189838A1
WO2021189838A1 PCT/CN2020/123817 CN2020123817W WO2021189838A1 WO 2021189838 A1 WO2021189838 A1 WO 2021189838A1 CN 2020123817 W CN2020123817 W CN 2020123817W WO 2021189838 A1 WO2021189838 A1 WO 2021189838A1
Authority
WO
WIPO (PCT)
Prior art keywords
dopant region
dopant
region
electric field
semiconductor device
Prior art date
Application number
PCT/CN2020/123817
Other languages
English (en)
French (fr)
Inventor
曾嵘
刘佳鹏
赵彪
陈政宇
余占清
周文鹏
张翔宇
Original Assignee
清华大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 清华大学 filed Critical 清华大学
Priority to EP20927940.5A priority Critical patent/EP4131418A4/en
Publication of WO2021189838A1 publication Critical patent/WO2021189838A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7424—Thyristor-type devices, e.g. having four-zone regenerative action having a built-in localised breakdown/breakover region, e.g. self-protected against destructive spontaneous, e.g. voltage breakover, firing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1012—Base regions of thyristors
    • H01L29/1016—Anode base regions of thyristors

Definitions

  • the invention belongs to the field of power semiconductor devices, and in particular, relates to a buffer variable doping structure for overvoltage breakdown function and a semiconductor device.
  • IGCT devices are a new generation of flow control devices developed on the basis of GTO. From the chip level, GCT chips adopt transparent anode technology and buffer layer design, which reduces the trigger current level and conduction voltage drop of the device. From the perspective of gate drive circuit and turn-on and turn-off mechanism, IGCT uses an integrated drive circuit to reduce the stray parameters of the commutation loop to the nanohenry level by optimizing the circuit layout and the package structure of the tube and case, so that the device is turned off. During the off process, the current can be fully converted from the cathode to the gate in a short time, and then the PNP transistor is turned off naturally.
  • FIG. 1 is a schematic diagram of the structure of a conventional GCT chip.
  • the J2 junction shown in Figure 1 bears the voltage of kV or more between the cathode and anode.
  • the n-type drift region is usually made of the original silicon single crystal into a low doping concentration region.
  • the voltage mainly falls in the n-type drift region in the figure.
  • the rate of change of the electric field is proportional to the doping concentration, that is, the lower the doping concentration means that a reasonably designed structure can withstand a higher blocking voltage.
  • Semiconductor devices show unique advantages in the fields of large-capacity flexible power transmission due to their high blocking voltage capability, high controllable current level, low conduction loss, high reliability, and low cost.
  • Existing semiconductor devices include IGBT, IEGT, IGCT, ETO and MCT.
  • FIG. 1 is a schematic cross-sectional view of a conventional silicon-based GCT unit.
  • the forward withstand voltage is mainly borne by the J2 junction identified in the figure.
  • Figure 2 is a schematic diagram of traditional GCT edge grinding.
  • the direct use of traditional structures for overvoltage breakdown mainly faces two problems: limited by factors such as process stability and contamination, the breakdown voltage and leakage current level of the device after the corner grinding passivation treatment usually has a certain level It is difficult to test and screen; when the structural withstand voltage weak point is at the edge, if overvoltage breakdown occurs, when the system energy is large, the inrush current will easily lead to the rupture of the device shell structure, threatening Safe operation of the entire valve group.
  • the weak points of the breakdown voltage are all at the edge, but IGCT uses corner grinding to process the edge, and IGBT and other devices use junction terminal expansion and other technologies to process the edge, but they are all unstable and Problems that are difficult to control.
  • FIG. 3 is a schematic diagram of the BOD structure of the thyristor.
  • the BOD (Break Over Diode) structure shown in Figure 3 is usually used to achieve overvoltage protection.
  • the BOD structure first generates a relatively strong leakage current, and the lateral voltage drop generated by the leakage current flowing to the gate triggers the electron emission at the amplifying gate, thereby turning on the thyristor device to avoid failure.
  • the essence of the BOD structure is to create a weak point of avalanche breakdown in the device body (usually at the center) to ensure that the device first stably breaks down at the BOD structure under a certain voltage.
  • the avalanche coefficient is greatly affected by temperature, the same doped structure may have a protection threshold change of about 10% or higher at different temperatures.
  • this technology is applied to semiconductor devices, it is difficult to use the BOD structure to achieve reliable overvoltage protection of the device due to the limitations of device structure and process realization.
  • the present invention provides a buffer variable doping structure for overvoltage breakdown function in order to solve the above-mentioned technical problems.
  • the buffer variable doping structure bears the electric field generated by the semiconductor device, so that the electric field breaks down the buffer variable doping structure.
  • the aforementioned buffer variable doping structure includes a first dopant region A and a second dopant region B, and the first dopant region A and the second dopant region B are attached up and down When the semiconductor device is subjected to a breakdown voltage, the first dopant region A and the second dopant region B generate the electric field.
  • the above-mentioned buffer variable doping structure further includes a second dopant region C and a second dopant region D, and the second dopant region C is connected to the second dopant region D,
  • the second dopant region C and the second dopant region D are located in the same layer and are attached to the second dopant region B up and down at the same time.
  • the total dopant dose of the second dopant region D Less than the total dopant dose of the second dopant region C, when the second dopant region C and the second dopant region D are subjected to the electric field, the second dopant region D Pierced by the electric field.
  • the aforementioned buffer variable doping structure further includes a second dopant region C, a second dopant region D, and a first dopant region E.
  • the second dopant region C and the first dopant region A dopant region E is connected to the second dopant region D, and the second dopant region C and the second dopant region D are attached to the second dopant region B up and down ,
  • the first dopant region E and the second dopant region C are attached up and down, and the total dopant dose of the second dopant region D is less than the total dopant dose of the second dopant region C,
  • the second dopant region D is penetrated by the electric field.
  • the aforementioned variable doping structure of the buffer zone further includes a second dopant region C, a second dopant region D, a first dopant region E, and a first dopant region F.
  • the second dopant region The dopant region C is connected to the second dopant region D, the first dopant region E is connected to the first dopant region F, the second dopant region C and the first dopant region
  • the two dopant regions D and the second dopant region B are attached up and down, the first dopant region E and the second dopant region C are attached up and down, the first dopant region
  • the region F and the second dopant region D are attached up and down, and the total dopant dose of the second dopant region D is less than the total dopant dose of the second dopant region C.
  • the total dopant dose of the second dopant region D is obtained according to the following formula:
  • Q 1 is the total net dopant doping per unit area of the second dopant region D
  • ⁇ Si is the dielectric constant of the base material
  • E 1 is the second dopant under the design breakdown voltage.
  • the electric field intensity at the junction of the dopant region D and the second dopant region B, and q is the unit charge.
  • the total net doping amount of dopants per unit area of the first dopant region F is respectively smaller than the net doping total amount of dopants per unit area of other dopant regions.
  • the total net doping amount of the dopant per unit area of the first dopant region F makes the buffer variable doping structure more effective in static blocking conditions. Same or lower hole emission efficiency in the dopant region.
  • the present invention provides a semiconductor device, which includes the buffer variable doping structure described in any one of the above, and when the semiconductor device is subjected to a breakdown voltage, the buffer variable doping structure bears the semiconductor The electric field generated by the device causes the electric field to break down the variable-doped structure of the buffer zone.
  • the semiconductor device is one of IGCT, GTO, SGTO, IGBT, IEGT, MCT, and ETO.
  • the present invention is aimed at the prior art, and its effects are: the buffer variable doping structure of the present invention and the semiconductor device with the same adopt the principle of partial punch-through to realize overvoltage self-destruction, and have good temperature stability, easy process realization, and voltage consistency. Good advantage, and because the punch-through point is located in the body, after self-destruction, the device can usually maintain a long-term reliable short-circuit state.
  • Figure 1 is a schematic cross-sectional view of a traditional silicon-based GCT unit
  • Figure 2 is a schematic diagram of traditional GCT edge grinding
  • Figure 3 is a schematic diagram of the BOD structure of the thyristor
  • FIG. 4 is a schematic diagram of the first embodiment of the variable doping structure of the buffer zone according to the present invention.
  • FIG. 5 is a schematic diagram of the electric field distribution in various places of the variable-doped buffer structure of FIG. 4 under a design breakdown voltage state;
  • FIG. 6 is a schematic diagram of a second embodiment of the variable doping structure of the buffer zone of the present invention.
  • FIG. 7 is a schematic diagram of a third embodiment of the variable doping structure of the buffer zone according to the present invention.
  • Figure 8 is a schematic diagram of the structure of the IGCT of the present invention.
  • Fig. 9 is a schematic diagram of the electric field distribution of the IGCT in Fig. 8 under the design breakdown voltage state;
  • Figure 10 shows the buffer variable doping structure arranged in the center of the GCT chip
  • Figure 11 shows the buffer variable doping structure arranged at the junction of the GCT part and the diode part
  • FIG. 12 is a schematic diagram of the structure of the n-type planar IGBT of the present invention.
  • FIG. 13 is a schematic diagram of electric field distribution in various places of the IGBT of FIG. 12 under the state of withstanding the designed breakdown voltage;
  • FIG. 14 is a schematic diagram of the structure of the n-type MCT of the present invention.
  • Fig. 15 is a schematic diagram of the electric field distribution in various places of the MCT of Fig. 14 under the state of being subjected to the design breakdown voltage.
  • the buffer variable doping structure of the present invention is used to be arranged in a semiconductor device.
  • the buffer variable doping structure bears the electric field generated by the semiconductor device, so that the The electric field breaks down the variable doping structure of the buffer zone.
  • FIG. 4 is a schematic diagram of a first embodiment of a variable-doped buffer structure of the present invention.
  • the buffer variable doping structure for overvoltage breakdown function of the present invention includes a first dopant region A and a second dopant region B.
  • the first dopant region A and The second dopant region B is attached up and down, and when the semiconductor device is subjected to a breakdown voltage, the first dopant region A and the second dopant region B generate the electric field.
  • the first dopant region A and the second dopant region B are each one of a p-type dopant or an n-type dopant. Specifically, when The first dopant region A is a p-type dopant, and the second dopant region B is an n-type dopant. Conversely, when the first dopant region A is an n-type dopant, then the second dopant region A is an n-type dopant.
  • the dopant region B is a P-type dopant.
  • the buffer variable doping structure further includes a second dopant region C and a second dopant region D.
  • the second dopant region C is connected to the second dopant region D, and the The second dopant region C and the second dopant region D are located in the same layer and are attached to the second dopant region B up and down at the same time.
  • the total dopant dose of the second dopant region D is less than that of the first dopant region.
  • the total dopant dose of the two dopant region C, when the second dopant region C and the second dopant region D are subjected to the electric field, the second dopant region D is The electric field punches through.
  • the buffer variable doping structure of the present invention includes a second dopant region C and a second dopant region D.
  • the total dopant dose of the second dopant region D is less than that of the second dopant region C
  • the total dopant dose of the second dopant region D is obtained according to the following formula:
  • Q 1 is the total net dopant doping per unit area of the second dopant region D
  • ⁇ Si is the dielectric constant of the base material
  • E 1 is the second dopant under the design breakdown voltage.
  • the electric field intensity at the junction of the dopant region D and the second dopant region B, and q is the unit charge.
  • FIG. 5 is a schematic diagram of the electric field distribution in various places of the buffer variable doping structure of FIG. 4 under the state of withstanding the designed breakdown voltage.
  • the doping of the second dopant region D needs to be ensured.
  • the semiconductor device is statically subjected to the designed breakdown voltage value, it is applied to the first dopant region A and the second dopant region A.
  • the electric field between the regions B just penetrates the second dopant region D, and the electric field distribution in this critical state is shown in FIG. 5.
  • the design of the total dopant dose of the second dopant region D can be performed with reference to the above formula. Therefore, the design of the second dopant region D can reduce the doping concentration while ensuring the junction depth, and can also reduce the junction depth and the doping concentration at the same time.
  • FIG. 6 is a schematic diagram of a second embodiment of the variable-doped buffer structure of the present invention.
  • the variable doping structure of the buffer zone shown in FIG. 6 is substantially the same as the variable doping structure of the buffer zone shown in FIG.
  • the buffer variable doping structure further includes a second dopant region C, a second dopant region D, a first dopant region E, and a first dopant region F.
  • the dopant region C is connected to the second dopant region D
  • the first dopant region E is connected to the first dopant region F
  • the second dopant region C and the The second dopant region D and the second dopant region B are attached up and down
  • the first dopant region E and the second dopant region C are attached up and down
  • the dopant region F is attached to the second dopant region D up and down
  • the total dopant dose of the second dopant region D is less than the total dopant dose of the second dopant region C, when the second dopant region D
  • the second dopant region D is penetrated by the electric field.
  • the total net dopant doping amount per unit area of the first dopant region F makes the buffer variable doping structure more effective than other dopants under static blocking conditions. Hole emission efficiency in the same area or lower.
  • the first dopant region F doped with a low dose will usually be matched with the first dopant region F with a low dose directly below the second dopant region D, which is To reduce the leakage current level, the first dopant region F can be lower than other regions. More specifically, the first dopant region F may not be doped with the first dopant.
  • the total net dopant doping amount per unit area of the first dopant region F is smaller than the net dopant total doping amount per unit area of the other dopant regions.
  • FIG. 7 is a schematic diagram of a third embodiment of the variable-doped buffer structure of the present invention.
  • the variable doping structure of the buffer zone shown in FIG. 7 is substantially the same as the variable doping structure of the buffer zone shown in FIG.
  • the buffer variable doping structure further includes a second dopant region C, a second dopant region D, and a first dopant region E.
  • the second dopant region C and the The first dopant region E is connected to the second dopant region D, and the second dopant region C and the second dopant region D are attached to the second dopant region B up and down Together, the first dopant region E and the second dopant region C are attached up and down, and the total dopant dose of the second dopant region D is less than the total dopant dose of the second dopant region C
  • the second dopant region C and the second dopant region D are subjected to the electric field, the second dopant region D is penetrated by the electric field.
  • the present invention also provides a semiconductor device, including the buffer variable doping structure HSQ described above.
  • the buffer variable doping structure HCQ is used to withstand the production of the semiconductor device.
  • the electric field causes the electric field to break down the buffer variable-doped structure HCQ.
  • the semiconductor device is one of IGCT, GTO, SGTO, IGBT, IEGT, MCT, and ETO.
  • Example 1 IGCT (GTO, SGTO, ETO) type
  • Figure 8 is a schematic diagram of the structure of the IGCT of the present invention; Schematic diagram of electric field distribution everywhere in the state.
  • the silicon-based GCT chip integrated with a variable-doped buffer structure with over-voltage breakdown function has the following typical characteristics:
  • the doping of the second dopant region D needs to be ensured.
  • the electric field of the J2 junction just penetrates into the second dopant region D.
  • the electric field distribution in this critical state is shown in Figure 9 Shown.
  • the design of the total dopant dose of the second dopant region D can be performed according to the foregoing formula. Specifically, the design of the second dopant region D can not only reduce the doping concentration while ensuring the junction depth, but also reduce the junction depth and the doping concentration at the same time.
  • the concentration of the first dopant region F can be lower than that of other regions.
  • the concentration of the first dopant region F should be selected so that this region has the same or lower hole emission efficiency than other regions in the case of static blocking.
  • the second dopant region D can be arranged at any position other than the boundary.
  • the structure is usually arranged in the center of the GCT chip, as shown in Figure 10, which shows the buffer variable doping structure arranged in the center of the GCT chip.
  • Figure 10 shows the buffer variable doping structure arranged in the center of the GCT chip.
  • Figure 11 shows the buffer variable doping structure arranged at the junction of the GCT part and the diode part. Place.
  • At least one point in the second dopant region D should be at least a distance from the boundary of the region in the lateral direction greater than the thickness of the C region and the D region. Taking the circle arranged in the center as an example, the radius of the low-dose buffer circular area should be greater than the thickness of the C and D areas.
  • the gate metal contact of the second dopant region D corresponding to the cathode side is not necessary. However, in order to ensure the consistency of the breakdown point, it is recommended to configure the corresponding gate metal contact and connect it to the rest of the gate contact.
  • the buffer variable doping structure of the present invention is not only suitable for ETO, GTO and SGTO devices with the same material and different structures, but also for ETO, GCT, GTO and SGTO devices with different materials. For devices with different materials, the types of dopants There may be differences.
  • IGBT the plasma enhanced performance is only achieved through a special structure or design method in the IGBT, so it is collectively referred to as IGBT in this part.
  • IGBT-type devices thousands of small cells are usually connected in parallel on a chip.
  • IGBT-type structures can be divided into planar type and trench type according to the channel type; the type of dopant in the drift region can be divided
  • n-type IGBT and p-type IGBT the following is an example of n-type planar IGBT.
  • FIG. 12 is a schematic diagram of the structure of the n-type planar IGBT of the present invention
  • FIG. 13 is a schematic diagram of the electric field distribution of the IGBT in FIG. 12 under the design breakdown voltage state.
  • the n-type planar IGBT chip integrated with the variable doping structure of the buffer with over-voltage breakdown function has the following typical characteristics:
  • the doping of the second dopant region D needs to be ensured.
  • the electric field of the J2 junction just penetrates the second dopant region D.
  • the electric field distribution in this critical state is shown in Figure 13 .
  • the design of the total dopant dose of the second dopant region D can be performed according to the foregoing formula. Specifically, the design of the second dopant region D can not only reduce the doping concentration while ensuring the junction depth, but also reduce the junction depth and the doping concentration at the same time.
  • the concentration of the first dopant region F corresponding to the second dopant region D may be lower than that of other regions.
  • the concentration of the first dopant region F should be selected so that this region has the same or lower hole emission efficiency than other regions in the case of static blocking.
  • Figure 14 is a schematic diagram of the structure of the n-type MCT of the present invention; Schematic diagram of the electric field distribution in various places under the voltage state.
  • the MCT chip integrated with variable doping structure of the buffer with over-voltage breakdown function has the following typical characteristics:
  • the doping of the second dopant region D needs to be ensured.
  • the electric field of the J2 junction just penetrates the second dopant region D.
  • the electric field distribution in this critical state is shown in Figure 13 .
  • the design of the total dopant dose of the second dopant region D can be performed according to the foregoing formula. Specifically, the design of the second dopant region D can not only reduce the doping concentration while ensuring the junction depth, but also reduce the junction depth and the doping concentration at the same time.
  • the concentration of the first dopant region F corresponding to the second dopant region D may be lower than that of other regions.
  • the concentration of the first dopant region F should be selected so that this region has the same or lower hole emission efficiency than other regions in the case of static blocking.
  • the present invention adopts the principle of partial punch-through to achieve overvoltage breakdown, and has the advantages of good temperature stability, easy process realization, good breakdown voltage consistency, and controllable position of the punch-through point.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thyristors (AREA)

Abstract

本发明属于电力半导体器件领域，公开了一种用于过压击穿功能的缓冲区变掺杂结构及半导体器件，缓冲区变掺杂结构设置于半导体器件内，当半导体器件承受击穿电压时，通过缓冲区变掺杂结构承受半导体器件产生的电场，使得电场击穿所述缓冲区变掺杂结构。本发明采用局部穿通原理实现过压可控击穿，具有温度稳定性好、工艺易实现、击穿电压一致性好、穿通点位置可控的优势。

Description

用于过压击穿功能的缓冲区变掺杂结构及半导体器件
本申请要求在2020年03月24日在中国专利局递交的、申请号为“202010215412.2”、名称为“用于过压击穿功能的缓冲区变掺杂结构及半导体器件”的优先权，以及在2020年03月24日在中国专利局递交的、申请号为“202020388279.6”、名称为“用于过压击穿功能的缓冲区变掺杂结构及半导体器件”的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于电力半导体器件领域，具体地说，尤其涉及一种用于过压击穿功能的缓冲区变掺杂结构及半导体器件。
背景技术
IGCT器件是在GTO的基础上发展出的新一代流控型器件，从芯片层面来看，GCT芯片采用了透明阳极技术与缓冲层设计，降低了器件的触发电流水平及导通压降。从门极驱动电路及开通关断机理来看，IGCT采用集成式驱动电路的方式，通过优化线路布局及管壳封装结构等方式，降低换流回路杂散参数到纳亨量级，使得器件关断过程中电流能在很短时间内由阴极全部转换至门极，而后使PNP三极管自然关断。
参照图1，图1为现有GCT芯片结构的示意图。如图1所示，现有的GCT芯片在静态阻断与动态关断过程中，图1中所示的J2结承担阴阳极间kV级以上电压，特别需要说明的是，为保证高压耐受能力，n型漂移区通常利用原始硅单晶制作成低掺杂浓度区域，此时电压主要降落在图中的n型漂移区内。且根据泊松方程，电场的变化率与掺杂浓度成正比，即越低的掺杂浓度意味着合理设计的结构能承受更高的阻断电压。
半导体器件以其高阻断电压能力、高可控电流水平、低导通损耗、高可靠性、低成本的特点在大容量柔性输电等领域展现出特有的优势。现有的半导体器件包括IGBT、IEGT、IGCT、ETO以及MCT等。
近年来，在模块化多电平等应用中，希望半导体器件在达到特定电压值后稳定击穿或保护，进而保护模块中电容、二极管等其余器件不会因过电压被击穿，或将模块可靠旁路保证系统仍能正常运行，提升系统运行的可靠性。由于利用外部电路进行击穿或保护时，可能存在电磁干扰、保护系统失电等因素。故通过芯片结构级的优化实现过压击穿或保护具有更好的应用意义。
以GCT举例来说，请参照图1，图1为传统硅基GCT单元截面示意图。如图1所示，在传统的GCT或晶闸管类器件中，其正向耐压主要以图中标识的J2结承担。为了保证 器件在高压下具有稳定的击穿电压性能，通常需要在边缘进行磨角和钝化处理，请参照图2，图2为传统GCT边缘磨角示意图。在实际应用中直接运用传统结构进行过压击穿主要面临两个问题：受到工艺稳定性与沾污等因素的限制，磨角钝化处理后的器件的击穿电压与漏电流水平通常具有一定的分散性，且难以进行测试筛选；结构耐压薄弱点在边缘处时，若出现过压击穿，在系统能量较大时，冲击电流的涌入容易导致器件管壳结构的破裂，威胁到整个阀组的安全运行。因此不只是IGCT还是IGBT，或者SGTO等，其击穿电压的薄弱点均在边缘，只不过IGCT通过磨角来处理边缘，IGBT等器件通过结终端拓展等技术处理边缘，但都存在不稳定且难以控制的问题。
另外，请参照图3，图3为晶闸管BOD结构示意图。如图3所示，在传统的晶闸管结构中，为解决这一问题，通常使用图3所示的BOD(Break Over Diode)结构实现过压保护。在出现过电压工况时，BOD结构首先产生较强烈的漏电流，漏电流流至门极产生的横向电压降触发放大门极处的电子发射，进而使晶闸管器件导通，避免失效。
BOD结构的本质是在器件体内(通常是中心处)制造一个雪崩击穿的薄弱点，保证器件在特定电压下首先稳定击穿在BOD结构处。然而由于雪崩系数受温度影响较大，同样的掺杂结构在不同的温度下可能存在约10％或更高的保护阈值变化。但这一技术在半导体器件上应用时，由于受到器件结构与工艺实现的限制，难以使用BOD结构实现器件可靠的过压保护。
因此亟需开发一种克服上述缺陷的一种缓冲区变掺杂结构及具有其的半导体器件。
发明内容
针对上述问题，本发明为解决上述技术问题提供一种用于过压击穿功能的缓冲区变掺杂结构，其中，设置于半导体器件内，当所述半导体器件承受击穿电压时，通过所述缓冲区变掺杂结构承受所述半导体器件产生的电场，使得所述电场击穿所述缓冲区变掺杂结构。
上述的缓冲区变掺杂结构，其中，包括第一掺杂剂区域A及第二掺杂剂区域B，所述第一掺杂剂区域A与所述第二掺杂剂区域B上下贴合，当所述半导体器件承受击穿电压时，所述第一掺杂剂区域A与所述第二掺杂剂区域B产生所述电场。
上述的缓冲区变掺杂结构，其中，还包括第二掺杂剂区域C及第二掺杂剂区域D，所述第二掺杂剂区域C连接于所述第二掺杂剂区域D，所述第二掺杂剂区域C及所述第二掺杂剂区域D位于同一层且同时与所述第二掺杂剂区域B上下贴合，第二掺杂剂区域D的总掺杂剂量小于第二掺杂剂区域C的总掺杂剂量，当所述第二掺杂剂区域C及所述 第二掺杂剂区域D承受所述电场时，使得所述第二掺杂剂区域D被所述电场穿通。
上述的缓冲区变掺杂结构，其中，还包括第二掺杂剂区域C、第二掺杂剂区域D及第一掺杂剂区域E，所述第二掺杂剂区域C及所述第一掺杂剂区域E连接于所述第二掺杂剂区域D，所述第二掺杂剂区域C及所述第二掺杂剂区域D与所述第二掺杂剂区域B上下贴合，所述第一掺杂剂区域E与所述第二掺杂剂区域C上下贴合，第二掺杂剂区域D的总掺杂剂量小于第二掺杂剂区域C的总掺杂剂量，当所述第二掺杂剂区域C及所述第二掺杂剂区域D承受所述电场时，使得所述第二掺杂剂区域D被所述电场穿通。
上述的缓冲区变掺杂结构，其中，还包括第二掺杂剂区域C、第二掺杂剂区域D、第一掺杂剂区域E及第一掺杂剂区域F，所述第二掺杂剂区域C连接于所述第二掺杂剂区域D，所述第一掺杂剂区域E连接于所述第一掺杂剂区域F，所述第二掺杂剂区域C及所述第二掺杂剂区域D与所述第二掺杂剂区域B上下贴合，所述第一掺杂剂区域E与所述第二掺杂剂区域C上下贴合，所述第一掺杂剂区域F与所述第二掺杂剂区域D上下贴合，第二掺杂剂区域D的总掺杂剂量小于第二掺杂剂区域C的总掺杂剂量，当所述第二掺杂剂区域C及所述第二掺杂剂区域D承受所述电场时，使得所述第二掺杂剂区域D被所述电场穿通。
上述的缓冲区变掺杂结构，其中，根据以下公式获得所述第二掺杂剂区域D的总掺杂剂量：
Figure PCTCN2020123817-appb-000001
其中，式中Q 1为第二掺杂剂区域D单位面积的掺杂剂净掺杂总量，ε Si为基底材料的介电常数，E 1为设计击穿电压情况下所述第二掺杂剂区域D与所述第二掺杂剂区域B交界处电场强度，q为单位电荷量。
上述的缓冲区变掺杂结构，其中，所述第一掺杂剂区域F单位面积的掺杂剂净掺杂总量分别小于其他掺杂剂区域单位面积的掺杂剂净掺杂总量。
上述的缓冲区变掺杂结构，其中，所述第一掺杂剂区域F单位面积的掺杂剂净掺杂总量使得所述缓冲区变掺杂结构在静态阻断情况下具有相比其他掺杂剂区域相同或更低的空穴发射效率。
本发明提供一种半导体器件，其中，包括上述中任一项所述的缓冲区变掺杂结构，当所述半导体器件承受击穿电压时，通过所述缓冲区变掺杂结构承受所述半导体器件产生的电场，使得所述电场击穿所述缓冲区变掺杂结构。
上述的半导体器件，其中，所述半导体器件为IGCT、GTO、SGTO、IGBT、IEGT、MCT 及ETO中的一者。
本发明针对于现有技术其功效在于：本发明的缓冲区变掺杂结构及具有其的半导体器件，采用局部穿通原理实现过压自毁，具有温度稳定性好、工艺易实现、电压一致性好的优势，且由于穿通点位于体内，在自毁后，器件通常可以维持长时可靠短路状态。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为传统硅基GCT单元截面示意图；
图2为传统GCT边缘磨角示意图；
图3为晶闸管BOD结构示意图；
图4为本发明缓冲区变掺杂结构第一实施例的示意图；
图5为图4的缓冲区变掺杂结构在承受设计击穿电压状态下各处电场分布示意图；
图6为本发明缓冲区变掺杂结构第二实施例的示意图；
图7为本发明缓冲区变掺杂结构第三实施例的示意图；
图8为本发明IGCT的结构示意图；
图9为图8的IGCT在承受设计击穿电压状态下各处电场分布示意图；
图10为缓冲区变掺杂结构布置在GCT芯片的正中心；
图11为缓冲区变掺杂结构布置在GCT部分与二极管部分交界处；
图12为本发明n型平面型IGBT的结构示意图；
图13为图12的IGBT在承受设计击穿电压状态下各处电场分布示意图；
图14为本发明n型MCT的结构示意图；
图15为图14的MCT在承受设计击穿电压状态下各处电场分布示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地说明，显然，所描述的实施例 是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
关于本文中所使用的方向用语，例如：上、下、左、右、前或后等，仅是参考附图的方向。因此，使用的方向用语是用来说明并非用来限制本创作。
关于本文中所使用的“包含”、“包括”、“具有”、“含有”等等，均为开放性的用语，即意指包含但不限于。
本发明的示意性实施例及其说明用于解释本发明，但并不作为对本发明的限定。另外，在附图及实施方式中所使用相同或类似标号的元件/构件是用来代表相同或类似部分。
本发明的缓冲区变掺杂结构，用以设置于半导体器件内，当所述半导体器件承受击穿电压时，通过所述缓冲区变掺杂结构承受所述半导体器件产生的电场，使得所述电场击穿所述缓冲区变掺杂结构。
请参照图4，图4为本发明缓冲区变掺杂结构第一实施例的示意图。如图4所示，本发明的用于过压击穿功能的缓冲区变掺杂结构包括第一掺杂剂区域A及第二掺杂剂区域B，所述第一掺杂剂区域A与所述第二掺杂剂区域B上下贴合，当所述半导体器件承受击穿电压时，所述第一掺杂剂区域A与所述第二掺杂剂区域B产生所述电场。
其中，在本实施例中，所述第一掺杂剂区域A与所述第二掺杂剂区域B各是p型掺杂剂或n型掺杂剂中的一种，具体地说，当第一掺杂剂区域A为p型掺杂剂，那么第二掺杂剂区域B则为n型掺杂剂；反之当第一掺杂剂区域A为n型掺杂剂，那么第二掺杂剂区域B则为P型掺杂剂。
进一步地，缓冲区变掺杂结构还包括第二掺杂剂区域C及第二掺杂剂区域D，所述第二掺杂剂区域C连接于所述第二掺杂剂区域D，所述第二掺杂剂区域C及所述第二掺杂剂区域D位于同一层且同时与所述第二掺杂剂区域B上下贴合，第二掺杂剂区域D的总掺杂剂量小于第二掺杂剂区域C的总掺杂剂量，当所述第二掺杂剂区域C及所述第二掺杂剂区域D承受所述电场时，使得所述第二掺杂剂区域D被所述电场穿通。
具体地说，为了改善器件整体性能，本发明的缓冲区变掺杂结构包括第二掺杂剂区域C及第二掺杂剂区域D，根据半导体物理原理，当所述半导体器件承受击穿电压时，通过第二掺杂剂区域C及第二掺杂剂区域D均承受所述半导体器件产生的电场，而第二掺杂剂区域D的总掺杂剂量小于第二掺杂剂区域C的总掺杂剂量，因此使得所述第二掺 杂剂区域D被所述电场穿通而第二掺杂剂区域C未被穿通。
更进一步地，根据以下公式获得所述第二掺杂剂区域D的总掺杂剂量：
Figure PCTCN2020123817-appb-000002
其中，式中Q 1为第二掺杂剂区域D单位面积的掺杂剂净掺杂总量，ε Si为基底材料的介电常数，E 1为设计击穿电压情况下所述第二掺杂剂区域D与所述第二掺杂剂区域B交界处电场强度，q为单位电荷量。
具体地说，请参照图5，图5为图4的缓冲区变掺杂结构在承受设计击穿电压状态下各处电场分布示意图。如图5所示，第二掺杂剂区域D的掺杂需保证，在半导体器件静态承受设计击穿电压值时，施加在所述第一掺杂剂区域A与所述第二掺杂剂区域B间的电场恰好穿通第二掺杂剂区域D，该临界状态下的电场分布如图5所示。可参考上述公式进行第二掺杂剂区域D总掺杂剂量的设计。由此，第二掺杂剂区域D的设计既可在保证结深的情况下将掺杂浓度降低，也可以同时将结深与掺杂浓度变低。
请参照图6，图6为本发明缓冲区变掺杂结构第二实施例的示意图。图6所示出的缓冲区变掺杂结构与图4所示出的缓冲区变掺杂结构大致相同，因此相同部分在此就不再赘述了，现将不同部分说明如下。在本实施例中，缓冲区变掺杂结构还包括第二掺杂剂区域C、第二掺杂剂区域D、第一掺杂剂区域E及第一掺杂剂区域F，所述第二掺杂剂区域C连接于所述第二掺杂剂区域D，所述第一掺杂剂区域E连接于所述第一掺杂剂区域F，所述第二掺杂剂区域C及所述第二掺杂剂区域D与所述第二掺杂剂区域B上下贴合，所述第一掺杂剂区域E与所述第二掺杂剂区域C上下贴合，所述第一掺杂剂区域F与所述第二掺杂剂区域D上下贴合，第二掺杂剂区域D的总掺杂剂量小于第二掺杂剂区域C的总掺杂剂量，当所述第二掺杂剂区域C及所述第二掺杂剂区域D承受所述电场时，使得所述第二掺杂剂区域D被所述电场穿通。
其中，在本实施例中，所述第一掺杂剂区域F单位面积的掺杂剂净掺杂总量使得所述缓冲区变掺杂结构在静态阻断情况下具有相比其他掺杂剂区域相同或更低的空穴发射效率。
具体地说，一般的，在大部分半导体器件中，通常会在C区域下侧还存在具有较高浓度的第一掺杂剂，用于载流子发射的第一掺杂剂区域E。在这样的结构中施加本发明所述的缓冲区变掺杂结构时，通常也会在与第二掺杂剂区域D的正下侧配合低剂量掺杂的第一掺杂剂区域F，为降低漏电流水平，第一掺杂剂区域F可以较其余区域较低。更特别的，第一掺杂剂区域F可以不利用第一掺杂剂进行掺杂。
其中，在本发明的一实施例中，所述第一掺杂剂区域F单位面积的掺杂剂净掺杂总量分别小于其他掺杂剂区域单位面积的掺杂剂净掺杂总量。
请参照图7，图7为本发明缓冲区变掺杂结构第三实施例的示意图。图7所示出的缓冲区变掺杂结构与图6所示出的缓冲区变掺杂结构大致相同，因此相同部分在此就不再赘述了，现将不同部分说明如下。在本实施例中，缓冲区变掺杂结构还包括第二掺杂剂区域C、第二掺杂剂区域D及第一掺杂剂区域E，所述第二掺杂剂区域C及所述第一掺杂剂区域E连接于所述第二掺杂剂区域D，所述第二掺杂剂区域C及所述第二掺杂剂区域D与所述第二掺杂剂区域B上下贴合，所述第一掺杂剂区域E与所述第二掺杂剂区域C上下贴合，第二掺杂剂区域D的总掺杂剂量小于第二掺杂剂区域C的总掺杂剂量，当所述第二掺杂剂区域C及所述第二掺杂剂区域D承受所述电场时，使得所述第二掺杂剂区域D被所述电场穿通。
本发明还提供一种半导体器件，包括上述中所述的缓冲区变掺杂结构HSQ，当所述半导体器件承受击穿电压时，通过所述缓冲区变掺杂结构HCQ承受所述半导体器件产生的电场，使得所述电场击穿所述缓冲区变掺杂结构HCQ。
其中，所述半导体器件为IGCT、GTO、SGTO、IGBT、IEGT、MCT及ETO中的一者。
实施例1：IGCT(GTO、SGTO、ETO)类
对IGCT类器件而言，通常在一个芯片上进行数千个小元胞的并联，请参照图8，图8为本发明IGCT的结构示意图；图9为图8的IGCT在承受设计击穿电压状态下各处电场分布示意图。如图8及图9所示集成具有过电压击穿功能的缓冲区变掺杂结构的硅基GCT类芯片来说，具有如下典型特征：
a、第二掺杂剂区域D掺杂需保证，在芯片静态承受设计击穿电压值时，J2结电场恰好穿通至第二掺杂剂区域D内，该临界状态下的电场分布如图9所示。可根据前述公式进行第二掺杂剂区域D的总掺杂剂量的设计。具体地说，第二掺杂剂区域D设计既可在保证结深的情况下将掺杂浓度降低，也可以同时将结深与掺杂浓度变低。
b、为降低漏电流水平，第一掺杂剂区域F的浓度可以较其余区域较低。优选的，第一掺杂剂区域F的浓度选取应使得该区域在静态阻断情况下具有相比其他区域相同或更低的空穴发射效率。
c、第二掺杂剂区域D原则上可以布置在非边界的任意位置。但为使器件面积得到合理利用，对非对称型IGCT，通常将该结构布置在GCT芯片的正中心，如图10所示，图10为缓冲区变掺杂结构布置在GCT芯片的正中心。对二极管与GCT部分分离的逆导 型GCT芯片，通常将该结构布置在GCT部分与二极管部分交界处，如图11所示，图11为缓冲区变掺杂结构布置在GCT部分与二极管部分交界处。
d、第二掺杂剂区域D中应至少有一点在横向上距离该区域边界的距离大于C区域与D区域厚度。以布置在中心的圆形为例，低剂量缓冲圆形区域的半径应大于C区域与D区域厚度。
e、需要特殊说明的是，第二掺杂剂区域D对应阴极侧的门极金属接触不是必须的。但为保证击穿点的一致性，建议配置对应的门极金属接触且与其余部分的门极接触相连。
本发明的缓冲区变掺杂结构既适用于同样材料不同结构的ETO、GTO和SGTO器件，也适用于不同材料的ETO、GCT、GTO、SGTO器件，对于不同材料的器件，掺杂剂的种类可能存在差别。
实施例2：IGBT(IEGT)类
由于IEGT与IGBT的基本结构相同，只是在IGBT中通过特殊的结构或设计方式实现了等离子体增强的性能，故在该部分统称为IGBT。对IGBT类器件而言，通常在一个芯片上进行数千个小元胞的并联，IGBT类结构根据沟道类型可以分为：平面型与沟槽型等；从漂移区掺杂剂种类可以分为n型IGBT和p型IGBT，以下以n型平面型IGBT举例说明。
请参照图12，图12为本发明n型平面型IGBT的结构示意图；图13为图12的IGBT在承受设计击穿电压状态下各处电场分布示意图。如图12及图13所示集成具有过电压击穿功能的缓冲区变掺杂结构的n型平面型IGBT类芯片来说，具有如下典型特征：
a、第二掺杂剂区域D掺杂需保证，在芯片静态承受设计击穿电压值时，J2结电场恰好穿通第二掺杂剂区域D，该临界状态下的电场分布如图13所示。可根据前述公式进行第二掺杂剂区域D总掺杂剂量的设计。具体地说，第二掺杂剂区域D的设计既可在保证结深的情况下将掺杂浓度降低，也可以同时将结深与掺杂浓度变低。
b、为降低漏电流水平，第二掺杂剂区域D对应的第一掺杂剂区域F的浓度可以较其余区域较低。优选的，该第一掺杂剂区域F的浓度选取应使得该区域在静态阻断情况下具有相比其他区域相同或更低的空穴发射效率。
对p型IGBT类器件由于其设计原理与n型完全相同，只在掺杂剂的种类选择上有所差别，在此不做更多赘述。
对集成具有过电压击穿功能的缓冲区变掺杂结构的IEGT类芯片而言，由于其设计 原理与IGBT相同，在此不做更多赘述。
实施例3：MCT类
对MCT类器件而言，通常在一个芯片上进行数千个小元胞的并联，请参照图14，图14为本发明n型MCT的结构示意图；图15为图14的MCT在承受设计击穿电压状态下各处电场分布示意图。如图14及图15所示集成具有过电压击穿功能的缓冲区变掺杂结构的MCT类芯片来说，具有如下典型特征：
a、第二掺杂剂区域D掺杂需保证，在芯片静态承受设计击穿电压值时，J2结电场恰好穿通第二掺杂剂区域D，该临界状态下的电场分布如图13所示。可根据前述公式进行第二掺杂剂区域D总掺杂剂量的设计。具体地说，第二掺杂剂区域D的设计既可在保证结深的情况下将掺杂浓度降低，也可以同时将结深与掺杂浓度变低。
b、为降低漏电流水平，第二掺杂剂区域D对应的第一掺杂剂区域F的浓度可以较其余区域较低。优选的，该第一掺杂剂区域F的浓度选取应使得该区域在静态阻断情况下具有相比其他区域相同或更低的空穴发射效率。
对p型MCT类器件由于其设计原理与n型完全相同，只在掺杂剂的种类选择上有所差别，在此不做更多赘述。
综上所述，本发明采用局部穿通原理实现过压击穿，具有温度稳定性好、工艺易实现、击穿电压一致性好、穿通点位置可控的优势。
尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (10)

  1. 一种用于过压击穿功能的缓冲区变掺杂结构，其特征在于，设置于半导体器件内，当所述半导体器件承受击穿电压时，通过所述缓冲区变掺杂结构承受所述半导体器件产生的电场，使得所述电场击穿所述缓冲区变掺杂结构。
  2. 如权利要求1所述的缓冲区变掺杂结构，其特征在于，包括第一掺杂剂区域A及第二掺杂剂区域B，所述第一掺杂剂区域A与所述第二掺杂剂区域B上下贴合，当所述半导体器件承受击穿电压时，所述第一掺杂剂区域A与所述第二掺杂剂区域B产生所述电场。
  3. 如权利要求2所述的缓冲区变掺杂结构，其特征在于，还包括第二掺杂剂区域C及第二掺杂剂区域D，所述第二掺杂剂区域C连接于所述第二掺杂剂区域D，所述第二掺杂剂区域C及所述第二掺杂剂区域D位于同一层且同时与所述第二掺杂剂区域B上下贴合，第二掺杂剂区域D的总掺杂剂量小于第二掺杂剂区域C的总掺杂剂量，当所述第二掺杂剂区域C及所述第二掺杂剂区域D承受所述电场时，使得所述第二掺杂剂区域D被所述电场穿通。
  4. 如权利要求2所述的缓冲区变掺杂结构，其特征在于，还包括第二掺杂剂区域C、第二掺杂剂区域D及第一掺杂剂区域E，所述第二掺杂剂区域C及所述第一掺杂剂区域E连接于所述第二掺杂剂区域D，所述第二掺杂剂区域C及所述第二掺杂剂区域D与所述第二掺杂剂区域B上下贴合，所述第一掺杂剂区域E与所述第二掺杂剂区域C上下贴合，第二掺杂剂区域D的总掺杂剂量小于第二掺杂剂区域C的总掺杂剂量，当所述第二掺杂剂区域C及所述第二掺杂剂区域D承受所述电场时，使得所述第二掺杂剂区域D被所述电场穿通。
  5. 如权利要求2所述的缓冲区变掺杂结构，其特征在于，还包括第二掺杂剂区域C、第二掺杂剂区域D、第一掺杂剂区域E及第一掺杂剂区域F，所述第二掺杂剂区域C连接于所述第二掺杂剂区域D，所述第一掺杂剂区域E连接于所述第一掺杂剂区域F，所述第二掺杂剂区域C及所述第二掺杂剂区域D与所述第二掺杂剂区域B上下贴合，所述第一掺杂剂区域E与所述第二掺杂剂区域C上下贴合，所述第一掺杂剂区域F与所述第二掺杂剂区域D上下贴合，第二掺杂剂区域D的总掺杂剂量小于第二掺杂剂区域C的总掺杂剂量，当所述第二掺杂剂区域C及所述第二掺杂剂区域D承受所述电场时，使得所述第二掺杂剂区域D被所述电场穿通。
  6. 如权利要求3-5中任一项所述的缓冲区变掺杂结构，其特征在于，根据以下公式获得所述第二掺杂剂区域D的总掺杂剂量：
    Figure PCTCN2020123817-appb-100001
    其中，式中Q 1为第二掺杂剂区域D单位面积的掺杂剂净掺杂总量，ε Si为基底材料的介电常数，E 1为设计击穿电压情况下所述第二掺杂剂区域D与所述第二掺杂剂区域B交界处电场强度，q为单位电荷量。
  7. 如权利要求5所述的缓冲区变掺杂结构，其特征在于，所述第一掺杂剂区域F单位面积的掺杂剂净掺杂总量分别小于其他掺杂剂区域单位面积的掺杂剂净掺杂总量。
  8. 如权利要求5所述的缓冲区变掺杂结构，其特征在于，所述第一掺杂剂区域F单位面积的掺杂剂净掺杂总量使得所述缓冲区变掺杂结构在静态阻断情况下具有相比其他掺杂剂区域相同或更低的空穴发射效率。
  9. 一种半导体器件，其特征在于，包括上述权利要求1-8中任一项所述的缓冲区变掺杂结构，当所述半导体器件承受击穿电压时，通过所述缓冲区变掺杂结构承受所述半导体器件产生的电场，使得所述电场击穿所述缓冲区变掺杂结构。
  10. 如权利要求9所述的半导体器件，其特征在于，所述半导体器件为IGCT、GTO、SGTO、IGBT、IEGT、MCT及ETO中的一者。
PCT/CN2020/123817 2020-03-24 2020-10-27 用于过压击穿功能的缓冲区变掺杂结构及半导体器件 WO2021189838A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP20927940.5A EP4131418A4 (en) 2020-03-24 2020-10-27 VARIABLE BUFFER REGION DOPED STRUCTURE USED FOR OVERVOLTAGE BREAKING FUNCTION, AND SEMICONDUCTOR DEVICE

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010215412.2A CN113451387B (zh) 2020-03-24 2020-03-24 用于过压击穿功能的缓冲区变掺杂结构及半导体器件
CN202010215412.2 2020-03-24

Publications (1)

Publication Number Publication Date
WO2021189838A1 true WO2021189838A1 (zh) 2021-09-30

Family

ID=77806589

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/123817 WO2021189838A1 (zh) 2020-03-24 2020-10-27 用于过压击穿功能的缓冲区变掺杂结构及半导体器件

Country Status (3)

Country Link
EP (1) EP4131418A4 (zh)
CN (1) CN113451387B (zh)
WO (1) WO2021189838A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117153737A (zh) * 2023-10-27 2023-12-01 深圳安森德半导体有限公司 一种抗雪崩击穿的超级结mos终端制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574169A (en) * 1980-06-10 1982-01-09 Toshiba Corp Gaas field-effect transistor
CN101916730A (zh) * 2010-07-22 2010-12-15 中国科学院上海微系统与信息技术研究所 一种具有线性缓冲层的soi超结ldmos制作方法
CN103594504A (zh) * 2013-11-19 2014-02-19 西安永电电气有限责任公司 具有半超结结构的igbt
CN106298898A (zh) * 2015-06-12 2017-01-04 中芯国际集成电路制造(上海)有限公司 垂直导电功率器件及其制作方法
CN106920844A (zh) * 2017-03-09 2017-07-04 电子科技大学 一种具有n型浮空埋层的resurf hemt器件

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5352910A (en) * 1992-04-07 1994-10-04 Tokyo Denki Seizo Kabushiki Kaisha Semiconductor device with a buffer structure
JP3277125B2 (ja) * 1996-07-26 2002-04-22 日本碍子株式会社 半導体装置
DE10325721B4 (de) * 2003-06-06 2009-02-05 Infineon Technologies Ag Halbleiterbauelement
JP5971414B2 (ja) * 2013-06-12 2016-08-17 三菱電機株式会社 半導体装置
JP6392133B2 (ja) * 2015-01-28 2018-09-19 株式会社東芝 半導体装置
CN212161818U (zh) * 2020-03-24 2020-12-15 清华大学 用于过压击穿功能的缓冲区变掺杂结构及半导体器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574169A (en) * 1980-06-10 1982-01-09 Toshiba Corp Gaas field-effect transistor
CN101916730A (zh) * 2010-07-22 2010-12-15 中国科学院上海微系统与信息技术研究所 一种具有线性缓冲层的soi超结ldmos制作方法
CN103594504A (zh) * 2013-11-19 2014-02-19 西安永电电气有限责任公司 具有半超结结构的igbt
CN106298898A (zh) * 2015-06-12 2017-01-04 中芯国际集成电路制造(上海)有限公司 垂直导电功率器件及其制作方法
CN106920844A (zh) * 2017-03-09 2017-07-04 电子科技大学 一种具有n型浮空埋层的resurf hemt器件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117153737A (zh) * 2023-10-27 2023-12-01 深圳安森德半导体有限公司 一种抗雪崩击穿的超级结mos终端制备方法
CN117153737B (zh) * 2023-10-27 2024-02-13 深圳安森德半导体有限公司 一种抗雪崩击穿的超级结mos终端制备方法

Also Published As

Publication number Publication date
EP4131418A1 (en) 2023-02-08
CN113451387A (zh) 2021-09-28
CN113451387B (zh) 2022-12-23
EP4131418A4 (en) 2023-08-23

Similar Documents

Publication Publication Date Title
US20070272978A1 (en) Semiconductor device including a vertical gate zone, and method for producing the same
JP2020532143A (ja) 半導体デバイス
JP2014063980A (ja) 半導体装置
JP6441192B2 (ja) 半導体装置
JP6088586B2 (ja) 逆導通パワー半導体デバイス
US20220157809A1 (en) Semiconductor device
JPH1074959A (ja) 電力用半導体素子
JP2018085449A (ja) 半導体装置
WO2022042481A1 (zh) 逆导型igbt芯片
US5936267A (en) Insulated gate thyristor
CN212161818U (zh) 用于过压击穿功能的缓冲区变掺杂结构及半导体器件
WO2021189838A1 (zh) 用于过压击穿功能的缓冲区变掺杂结构及半导体器件
JP7118033B2 (ja) 半導体装置
US6410950B1 (en) Geometrically coupled field-controlled-injection diode, voltage limiter and freewheeling diode having the geometrically coupled field-controlled-injection diode
JP6799515B2 (ja) 半導体装置
TWI776173B (zh) 碳化矽半導體元件
US8222671B2 (en) Power semiconductor devices
JPH03225960A (ja) 半導体デバイス
CN114497190B (zh) 一种空间寿命非均匀分布的半导体器件及制作方法
CN111092114A (zh) 半导体装置及半导体装置的制造方法
CN116093152A (zh) 半导体器件
US20200373382A1 (en) Semiconductor device
CN112216746B (zh) 碳化硅半导体器件
US8969959B2 (en) Semiconductor device and method of manufacturing the same
CN107591401B (zh) 一种用于高压esd保护的ldmos-scr器件

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20927940

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2020927940

Country of ref document: EP

Effective date: 20221024