WO2021189658A1 - 半导体器件电极的制作方法及半导体欧姆接触结构 - Google Patents

半导体器件电极的制作方法及半导体欧姆接触结构 Download PDF

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WO2021189658A1
WO2021189658A1 PCT/CN2020/093855 CN2020093855W WO2021189658A1 WO 2021189658 A1 WO2021189658 A1 WO 2021189658A1 CN 2020093855 W CN2020093855 W CN 2020093855W WO 2021189658 A1 WO2021189658 A1 WO 2021189658A1
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metal layer
epitaxial wafer
inaln
algan
photoresist
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PCT/CN2020/093855
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English (en)
French (fr)
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于洪宇
蒋玉龙
范梦雅
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南方科技大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

Definitions

  • the embodiments of the present application relate to the technical field of semiconductor devices, for example, to a method for fabricating an electrode of a semiconductor device and a semiconductor ohmic contact structure.
  • AlGaN (InAlN)/GaN High Electron Mobility Transistor (HEMT) is named after the use of a two-dimensional electron gas with high electron mobility to form a conductive channel. Therefore, AlGaN (InAlN)/GaNHEMTs High Electron Mobility Transistor devices are in high power Devices and high-frequency device applications have great prospects.
  • Ohmic contact is an important indicator that affects the final output parameters of AlGaN (InAlN)/GaN HEMTs devices. It directly affects the output current, on-resistance, breakdown voltage, and thermal reliability of the ohmic electrode of the device.
  • High-quality ohmic contacts mainly Including the low ohmic contact resistance, the smooth surface morphology of the ohmic contact layer, and the edge acuity of the ohmic electrode.
  • the surface roughness of the ohmic electrode is too large and the edge of the ohmic electrode spreads laterally, which is not conducive to the thermal stability of the device and affects the yield of the device. , It is impossible to achieve low ohmic contact resistance while taking into account the surface morphology and edge sharpness of the ohmic electrode, and it is also not conducive to the short-channel device process.
  • the embodiments of the present application provide a method for manufacturing a semiconductor device electrode and a semiconductor ohmic contact structure, so as to reduce the size of the ohmic contact resistance while simultaneously improving the surface roughness and edge sensitivity of the ohmic electrode, thereby improving the performance of the GaN semiconductor device. Output characteristics, thermal stability and device yield.
  • the embodiments of the present application provide a method for fabricating a semiconductor device electrode.
  • the fabrication method of the semiconductor device electrode includes: forming a photoresist pattern on an AlGaN (InAlN)/GaN epitaxial wafer, and the photoresist pattern is used to define Source and drain ohmic electrode patterns; on the side of the AlGaN (InAlN)/GaN epitaxial wafer with the photoresist pattern, a Ta x Al y alloy metal layer and an Au metal layer are sequentially formed; where x>0 and y ⁇ 0; remove The photoresist and the alloy and metal on the photoresist form source and drain ohmic electrode patterns; thermal annealing process is performed on the AlGaN (InAlN)/GaN epitaxial wafer that forms the active drain ohmic electrode pattern.
  • the embodiments of the present application also provide a semiconductor ohmic contact structure
  • the semiconductor ohmic contact structure is manufactured by the method for manufacturing a semiconductor device electrode described in the first aspect
  • the semiconductor ohmic contact structure includes: AlGaN (InAlN)/GaN epitaxial wafer, Ta x Al y alloy metal layer on the side of AlGaN(InAlN)/GaN epitaxial wafer, and Au on the side of Ta x Al y alloy metal layer away from AlGaN(InAlN)/GaN epitaxial wafer The metal layer, where x>0 and y ⁇ 0.
  • FIG. 1 is a schematic diagram of a method for fabricating electrodes of a semiconductor device according to Embodiment 1 of the present application;
  • FIG. 2 is a schematic diagram of a photoresist pattern structure in which a photoresist pattern is formed on an epitaxial wafer and the pattern defines a source and drain ohmic electrode pattern according to an embodiment of the application;
  • FIG. 3 is a schematic diagram of the structure of forming a Ta x Al y alloy metal layer and an Au metal layer in sequence on the side of the epitaxial wafer with the photoresist pattern in a real-time example of this application;
  • FIG. 4 is a schematic diagram of the structure of the source and drain ohmic electrodes formed according to an embodiment of the application;
  • FIG. 5 is a schematic diagram of a method for manufacturing a semiconductor device electrode provided in the second embodiment of the application.
  • FIG. 6 is a schematic structural diagram of a semiconductor ohmic contact structure provided by an embodiment of the application.
  • FIG. 1 is a schematic diagram of a manufacturing method of a semiconductor device electrode provided in Embodiment 1 of the application. As shown in FIG. 1, the manufacturing method of the semiconductor device electrode includes:
  • a photoresist pattern is formed on the AlGaN (InAlN)/GaN epitaxial wafer, and the pattern defines a source and drain ohmic electrode pattern.
  • FIG. 2 is a schematic diagram of the photoresist pattern structure in which a photoresist pattern is formed on an epitaxial wafer and the pattern defines a source and drain ohmic electrode pattern provided by an embodiment of the application.
  • the epitaxial wafer is from From bottom to top, it includes the bottom layer 1, the middle layer 2 on the side of the bottom layer 1, the middle layer 3 on the side of the middle layer 2, and the top layer 4.
  • the bottom layer 1 is a Si substrate layer
  • the middle layer 2 is a GaN buffer layer
  • the middle layer 3 is a GaN layer
  • the top layer 4 is an AlGaN layer or an InAlN layer
  • the upper surface of the top layer 4 is the side of the AlGaN (InAlN) layer away from the GaN layer.
  • the process steps of homogenization, pre-baking, photolithography, development, and post-baking are sequentially performed on the upper surface of the top layer 4 to obtain the photoresist pattern layer 5 on the upper surface of the top layer 4 as shown in FIG. 2, and the photoresist
  • the pattern layer 5 defines the source and drain ohmic electrode patterns.
  • the pattern of the source and drain ohmic electrode patterns can be designed according to actual needs.
  • the definition of the source and drain ohmic electrode patterns means that the pattern on the photoresist pattern layer 5 can be fully reflected After the pattern of the source and drain ohmic electrodes is removed, after the photoresist pattern layer 5 is removed, the pattern left on the upper surface of the top layer 4 is the source and drain ohmic electrode pattern.
  • the photoresist pattern is a pattern formed with photoresist.
  • step S200 a Ta x Al y alloy metal layer and an Au metal layer are sequentially formed on the side of the epitaxial wafer with the photoresist pattern; wherein, x>0 and y ⁇ 0.
  • the upper surface of the photoresist pattern layer 5 is a side away from the top layer 4.
  • the side of the epitaxial wafer with the photoresist pattern layer 5 refers to the part of the upper surface of the top layer 4 that is not covered by the photoresist pattern layer 5 and the upper surface of the photoresist pattern layer 5.
  • FIG. 3 is a schematic diagram of the structure of the Ta x Al y alloy metal layer and the Au metal layer sequentially formed on the side of the epitaxial wafer with the photoresist pattern in the embodiment of the application , and the Ta x Al y alloy metal as shown in FIG.
  • Layer 6 and Au metal layer 7 are sequentially formed Layer 6 and Au metal layer 7; where x>0 and y ⁇ 0, for example , the atomic ratio of Ta:Al in the Ta x Al y alloy metal layer can be between 1:10-10:1, and between Any ratio of the ratio interval can achieve the technical effects of the embodiments of the present application.
  • the thickness of the Ta x Al y alloy metal layer and the Au metal layer is 20 nm-200 nm.
  • the thickness of the formed Ta x Al y alloy metal layer may be between 20 nm and 200 nm, including 20 nm and 200 nm, and the thickness of the formed Au metal layer may also be between 20 nm and 200 nm, including 20 nm. And 200nm.
  • the thickness of the metal layer is less than 20nm, the parasitic resistance of the metal itself will be relatively large, and a thicker metal layer is more conducive to the reduction of the parasitic resistance of the metal itself; and when the thickness of the metal layer is greater than 200nm, it will be subjected to subsequent high temperature During the annealing process, the metal layer with too large thickness will roughen its edge due to the effect of high temperature, which affects the stability and reliability of the final device.
  • sequentially forming a Ta x Al y alloy metal layer and an Au metal layer on the side of the epitaxial wafer with the photoresist pattern layer 5 includes: using magnetic The controlled sputtering process sequentially forms the Ta x Al y alloy metal layer 6 and the Au metal layer 7.
  • the epitaxial wafer with the patterned photoresist layer 5 is placed in the vacuum transmission chamber of the magnetron sputtering equipment, and the side of the epitaxial wafer with the patterned photoresist layer 5 is subjected to a coating process, followed by Ta x Al
  • the Ta x Al y alloy metal layer 6 is sputtered and deposited by the y alloy target
  • the Au metal layer 7 is sputtered and deposited by the Au metal target.
  • the sputtering gas used in the magnetron sputtering process can be Ar gas, and the sputtering power can be between 100W and 300W, including 100W and 300W.
  • step S300 the photoresist and the alloy and metal on the photoresist are removed to form source and drain ohmic electrode patterns.
  • the photoresist on the epitaxial wafer and the alloy and metal on the photoresist are all removed.
  • the alloy and metal include the Ta x Al y alloy metal layer 6, the Au metal layer 7, and the metal layer on the photoresist.
  • the impurities such as other alloys and metals newly generated in the process of sequentially forming the Ta x Al y alloy metal layer and the Au metal layer are removed to form the source and drain ohmic electrode patterns.
  • the photoresist pattern layer 5 and the Ta x Al y alloy metal layer 6 and the Au metal layer 7 on the side of the photoresist pattern layer 5 in FIG. 3 are all removed, and the remaining pattern layer is Source and drain ohmic electrode film layer.
  • step S400 a thermal annealing process is performed on the epitaxial wafer on which the active drain ohmic electrode pattern is formed.
  • FIG. 4 is a schematic diagram of the structure of the source and drain ohmic electrodes formed according to the embodiments of the application.
  • the epitaxial wafer forming the active drain ohmic electrode pattern is subjected to rapid thermal annealing. After the rapid thermal annealing, the final Obtain the source and drain ohmic electrodes as shown in FIG. 4 on the upper surface of the top layer 4 of the epitaxial wafer.
  • the gas atmosphere for thermal annealing includes nitrogen, ammonia, a mixed gas of nitrogen and hydrogen, or a mixed gas of hydrogen and argon.
  • the gas atmosphere of the thermal annealing in the rapid thermal annealing process can be selected from one of nitrogen, ammonia, a mixed gas of nitrogen and hydrogen, or a mixed gas of hydrogen and argon.
  • the temperature of thermal annealing is 700°C-1000°C; the time of thermal annealing is 10s-100s.
  • the temperature of the thermal annealing in the rapid thermal annealing process may be 700° C.-1000° C., correspondingly, the time of the thermal annealing may be 10 s-100 s.
  • a semiconductor device manufacturing method of an electrode according to an embodiment of the present application the side of the wafer near the AlGaN (InAlN) sequentially forming Ta x Al y metal alloy layer and an Au layer of two-layer metal film structure of Ta x Al y / Au,
  • the four-layer film structure Ti/Al/X/Au in the related art it also replaces even the five-layer multi-layer film structure, so that in the production process of the source and drain ohmic electrodes, only the introduction of Ta x Al y alloy and For Au metal, if the Ta x Al y alloy metal layer and the Au metal layer are sequentially formed by the magnetron sputtering process, only the Ta x Al y alloy target and the Au metal target need to be introduced.
  • the manufacturing process of the ohmic electrode improves the stability of the formation process of the source and drain ohmic electrodes, avoids cross-infection, and is more conducive to industrialization.
  • the four-layer film structure Ti/Al/X/Au in the related art during the thermal annealing process, the Al layer and the Au layer will undergo mutual diffusion to form an Al-Au alloy, thereby increasing the surface roughness of the source and drain ohmic electrodes
  • the two metals Ta and Al are fully and uniformly mixed in the initial state of deposition, which can avoid excessive alloying between the metals during the thermal annealing process
  • the resulting roughness problem, and compared to Al-Au alloy, Ta-Al has a more stable combination, so it can inhibit Al out-diffusion during the annealing process, thereby reducing the surface roughness of the source and drain ohmic electrodes
  • Ta x Al y alloy can make the two metals Ta and Al fully play their respective roles in the initial stage of thermal annealing, and at the same time, they have a solid phase reaction with the epitaxial wafer, which is more conducive to the reduction of ohmic contact resistance. Accordingly, the embodiments of the present application realize that when reducing the size of the ohmic contact resistance, the surface roughness and edge sharpness of the ohmic electrode are improved, thereby improving the output characteristics, thermal stability, and device yield of the GaN semiconductor device, and further It is more suitable for short-channel radio frequency devices.
  • FIG. 5 is a schematic diagram of a method for manufacturing a semiconductor device electrode provided in the second embodiment of the application. As shown in FIG. 5, the method for manufacturing a semiconductor device electrode includes:
  • step S10 before step S100 acetone and isopropanol are used in order to perform surface cleaning treatment on the epitaxial wafer.
  • the surface of the epitaxial wafer is cleaned by ultrasonic cleaning with acetone for 5-15 mins, isopropanol for 5-15 mins, deionized water for 5-15 mins, and drying with nitrogen.
  • a photoresist pattern is formed on the AlGaN (InAlN)/GaN epitaxial wafer, and the pattern defines a source and drain ohmic electrode pattern.
  • step S20 before step S200 the surface oxide on the side of the epitaxial wafer with the photoresist pattern is removed.
  • the side of the epitaxial wafer with the photoresist pattern layer 5 is immersed in a diluted hydrochloric acid solution for 1 mins-5mins, then rinsed with deionized water for 5-15 mins, and dried with nitrogen to remove the epitaxial wafer.
  • step S200 a Ta x Al y alloy metal layer and an Au metal layer are sequentially formed on the side of the epitaxial wafer with the photoresist pattern; wherein, x>0 and y ⁇ 0.
  • the step S300 includes step S30, the method of immersing the epitaxial wafer with the Ta x Al y alloy metal layer and the Au metal layer on the side with the photoresist pattern in a water bath at 70°C-90°C in an organic solvent The photoresist and the alloy and metal on the photoresist are removed to form source and drain ohmic electrode patterns.
  • the method of immersing in an organic solvent at 70°C-90°C in a water bath means that an epitaxial layer of a Ta x Al y alloy metal layer and an Au metal layer are sequentially formed on the side with the photoresist pattern.
  • the sheet is immersed in an organic solvent, and the organic solvent is maintained at between 70°C and 90°C through a water bath.
  • an epitaxial wafer with a Ta x Al y alloy metal layer and an Au metal layer may be sequentially formed on the side with the photoresist pattern layer 5 as shown in FIG. °C water bath immersion method removes the photoresist and the alloy and metal on the photoresist.
  • step S300 the photoresist and the alloy and metal on the photoresist are removed to form source and drain ohmic electrode patterns.
  • step S400 a thermal annealing process is performed on the epitaxial wafer on which the active drain ohmic electrode pattern is formed.
  • An embodiment of the present application provides a method for fabricating semiconductor device electrodes, which successively pass: the surface of the AlGaN(InAlN)/GaN epitaxial wafer is washed with acetone ultrasonically for 5-15mins, isopropanol for 5-15mins, and deionized water. 5-15mins, the surface is cleaned and dried with nitrogen.
  • the process steps of homogenization, pre-baking, photolithography, development, and post-baking are sequentially performed on the upper surface of the top layer 4 of the epitaxial wafer to obtain the photoresist pattern layer 5 on the upper surface of the top layer 4 as shown in FIG. 2, and
  • the photoresist pattern layer 5 defines source and drain ohmic electrode patterns.
  • the side of the epitaxial wafer with the photoresist pattern layer 5 is immersed in the diluted hydrochloric acid solution for 1 mins-5mins, then rinsed with deionized water for 5-15 mins, and dried with nitrogen to remove one side of the epitaxial wafer with the photoresist pattern layer 5 Side surface oxide.
  • a Ta x Al y alloy metal layer and an Au metal layer are sequentially formed by a magnetron sputtering process.
  • An epitaxial wafer with a Ta x Al y alloy metal layer and an Au metal layer is sequentially formed on the side with the photoresist pattern layer 5, and the photoresist and the top of the photoresist are removed by the method of immersing in an organic solvent 70°C-90°C water bath Alloys and metals.
  • the epitaxial wafer on which the active drain ohmic electrode pattern is formed is subjected to rapid thermal annealing. After the rapid thermal annealing, the source and drain ohmic electrodes on the upper surface of the top layer 4 of the epitaxial wafer are finally obtained.
  • the technical solution of the embodiment of the present application directly uses Ta x Al y /Au film layer to replace the traditional Ti/Al/X/Au multilayer film structure, which reduces the complexity of the process and improves the magnetron sputtering.
  • the stability of the jet deposition chamber avoids cross-contamination.
  • the two metals Ta and Al are fully and uniformly mixed, which is beneficial to reduce the surface roughness of the source and drain ohmic electrodes caused by the alloying caused by thermal annealing.
  • Au and Ta-Al have better thermal stability and can inhibit the out-diffusion of the Al layer.
  • the surface of the source and drain ohmic electrodes can still maintain a good surface morphology and its edges The region is difficult to diffuse laterally, which improves the output characteristics, thermal stability and device yield of the device.
  • the process steps are simple and reliable, which is more conducive to improving the industrialization efficiency.
  • the use of the Ta x Al y alloy ohmic contact layer can make the two metals Ta and Al fully play their respective roles in the initial stage of annealing, and at the same time have a solid phase reaction with the substrate, which is more conducive to the reduction of ohmic contact resistance.
  • the method for fabricating semiconductor device electrodes provided by the embodiments of the present application can reduce the size of the ohmic contact value while simultaneously improving the surface morphology of the source and drain ohmic electrodes and the sharpness of the edge regions, thereby improving the output characteristics of the device.
  • Thermal stability and device yield are more conducive to the industrialization of AlGaN (InAlN)/GaN power and radio frequency devices.
  • the thermal annealing atmosphere can be N 2
  • the thermal annealing time can be 60 s.
  • the temperature can be 900°C; when the thickness of the Ta 10 Al 1 alloy metal layer is 60 nm and the thickness of the Au metal layer is 60 nm, during the thermal annealing process, the thermal annealing atmosphere can be 3% H 2 /Ar, and the thermal annealing time can be 45s, the thermal annealing temperature can be 920°C; when the thickness of the Ta 1 Al 1 alloy metal layer is 60 nm and the thickness of the Au metal layer is 60 nm, the thermal annealing atmosphere can be 3% H 2 /Ar during the thermal annealing process.
  • the annealing time can be 80s, and the thermal annealing temperature can be 870°C; when the thickness of the Ta 1 Al 5 alloy metal layer is 60 nm and the thickness of the Au metal layer is 60 nm, during the thermal annealing process, the thermal annealing atmosphere can be N 2 , thermal The annealing time can be 30s, and the thermal annealing temperature can be 950°C; when the thickness of the Ta 1 Al 10 alloy metal layer is 60 nm and the thickness of the Au metal layer is 60 nm, the thermal annealing atmosphere can be NH 3 during the thermal annealing process.
  • the annealing time can be 40s, and the thermal annealing temperature can be 750°C.
  • the semiconductor ohmic contact structure can be used in high-power devices or high-frequency devices involving high electron mobility transistors.
  • the semiconductor ohmic contact structure can be Manufactured by the method for manufacturing any semiconductor device electrode described in the foregoing embodiment, the semiconductor ohmic contact structure includes: an AlGaN (InAlN)/GaN epitaxial wafer 10, a Ta x Al y alloy metal layer 20 on one side of the epitaxial wafer, And the Au metal layer 30 on the side of the Ta x Al y alloy metal layer away from the epitaxial wafer, where x>0 and y ⁇ 0.
  • the thickness of the Ta x Al y alloy metal layer 20 and the Au metal layer 30 is 20 nm-200 nm.
  • the semiconductor ohmic contact structure provided by the embodiments of the present application, that is, the Ta x Al y /Au double-layer metal film structure, can reduce the ohmic contact value while improving the surface morphology of the source and drain ohmic electrodes and sharp edge regions. It further improves the output characteristics, thermal stability and device yield of the device, which is very conducive to the industrialization of AlGaN (InAlN)/GaN power and radio frequency devices.
  • the manufacturing method of the semiconductor device electrode provided by the embodiment of the application; forming a photoresist pattern on the AlGaN (InAlN)/GaN epitaxial wafer, and the pattern defines the source and drain ohmic electrode pattern; by forming a photoresist pattern on the side of the epitaxial wafer
  • the Ta x Al y alloy metal layer and the Au metal layer are sequentially formed; the photoresist and the alloy and metal on the photoresist are removed to form the source-drain ohmic electrode pattern; the epitaxial wafer forming the active-drain ohmic electrode pattern is heated Annealing process treatment; solves the problem that the surface morphology and edge sharpness of the ohmic electrode cannot be taken into account at the same time when the ohmic contact resistance value is reached, and realizes that the ohmic contact resistance is reduced while taking into account the improvement of the ohmic electrode.
  • the surface roughness and edge acuity can improve the output characteristics, thermal stability and device

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Abstract

一种半导体器件电极的制作方法及半导体欧姆接触结构。该半导体器件电极的制作方法包括：在AlGaN(InAlN)/GaN外延片（10）上形成光刻胶图案；通过在AlGaN(InAlN)/GaN外延片（10）具有光刻胶图案的一侧依次形成Ta xAl y合金金属层（20）和Au金属层（30）；其中，x＞0且y≥0；去除光刻胶以及光刻胶上的合金与金属，形成源漏极欧姆电极图案；对形成有源漏极欧姆电极图案的AlGaN(InAlN)/GaN外延片（10）进行热退火工艺处理。

Description

半导体器件电极的制作方法及半导体欧姆接触结构
本公开要求在2020年03月23日提交中国专利局、申请号为202010207017.X的中国专利申请的优先权，以上申请的全部内容通过引用结合在本公开中。
技术领域
本申请实施例涉及半导体器件技术领域，例如涉及一种半导体器件电极的制作方法及半导体欧姆接触结构。
背景技术
AlGaN(InAlN)/GaN高电子迁移率晶体管(HEMT)因采用具有高电子迁移率的二维电子气形成导电沟道而得名，因此AlGaN(InAlN)/GaNHEMTs高电子迁移率晶体管器件在大功率器件以及高频器件应用中具有很大的前景。
欧姆接触是影响AlGaN(InAlN)/GaN HEMTs器件最终输出参数的重要指标，直接影响到器件的欧姆电极的输出电流、导通电阻、击穿电压、热可靠性等，而高质量的欧姆接触主要包括低欧姆接触电阻值、欧姆接触层平滑的表面形貌以及欧姆电极的边缘敏锐度。相关技术中的欧姆接触膜层Ti/Al/X/Au中，会存在欧姆电极的表面粗糙程度偏大以及欧姆电极的边缘横向扩散的问题，不利于器件的热稳定性且会影响器件良率，无法在达到低欧姆接触电阻值的情况下，同时兼顾欧姆电极的表面形貌以及边缘敏锐度的问题，也不利于短沟道器件工艺。
发明内容
本申请实施例提供一种半导体器件电极的制作方法及半导体欧姆接触结构，以实现在降低欧姆接触阻值的大小时，兼顾改善欧姆电极的表面粗糙程度及边缘敏锐度，从而提高GaN半导体器件的输出特性、热稳定性和器件良率。
第一方面，本申请实施例提供了一种半导体器件电极的制作方法，该半导体器件电极的制作方法包括：在AlGaN(InAlN)/GaN外延片上形成光刻胶图案，光刻胶图案用于定义出源漏极欧姆电极图案；在AlGaN(InAlN)/GaN外延片具有光刻胶图案的一侧依次形成Ta xAl y合金金属层和Au金属层；其中，x＞0且y≥0；去除光刻胶以及光刻胶上的合金与金属，形成源漏极欧姆电极图案；对形成有源漏极欧姆电极图案的AlGaN(InAlN)/GaN外延片进行热退火工艺处理。
第二方面，本申请实施例还提供了一种半导体欧姆接触结构，该半导体欧姆接触结构为由上述第一方面所述的半导体器件电极的制作方法制作而成，该半导体欧姆接触结构包括：AlGaN(InAlN)/GaN外延片、位于AlGaN(InAlN)/GaN外延片一侧的Ta xAl y合金金属层，以及位于Ta xAl y合金金属层远离AlGaN(InAlN)/GaN外延片一侧的Au金属层，其中，x＞0且y≥0。
附图说明
图1为本申请实施例一提供的一种半导体器件电极的制作方法的示意图；
图2为本申请实施例提供的在外延片上形成光刻胶图案且图案定义出源漏极欧姆电极图案的光刻胶图案结构示意图；
图3为本申请实时例在外延片具有光刻胶图案的一侧依次形成Ta xAl y合金金属层和Au金属层的结构示意图；
图4为本申请实施例提供的形成的源漏极欧姆电极的结构示意图；
图5为本申请实施例二提供的一种半导体器件电极的制作方法的示意图；
图6为本申请实施例提供的一种半导体欧姆接触结构的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
实施例一
图1为本申请实施例一提供的一种半导体器件电极的制作方法的示意图，如图1所示，该半导体器件电极的制作方法包括：
S100步骤，在AlGaN(InAlN)/GaN外延片上形成光刻胶图案，图案定义出源漏极欧姆电极图案。
在一些实施例中，图2为本申请实施例提供的在外延片上形成光刻胶图案且图案定义出源漏极欧姆电极图案的光刻胶图案结构示意图，如图2所示，外延片从下至上依次包括底层1、位于底层1一侧的中间层2、位于中间层2一侧的中间层3以及顶层4，其中，底层1为Si衬底层、中间层2为GaN缓冲层、中间层3为GaN层、顶层4为AlGaN层或InAlN层，顶层4的上表面为 AlGaN(InAlN)层远离GaN层的一面。在顶层4的上表面依次进行匀胶、前烘、光刻、显影、后烘的工艺步骤，得到如图2所示的位于顶层4的上表面的光刻胶图案层5，且光刻胶图案层5定义出源漏极欧姆电极图案，源漏极欧姆电极图案的花样可根据实际需要进行设计，定义出源漏极欧姆电极图案指的是光刻胶图案层5上的图案能够完全体现出源漏极欧姆电极的图案，在去除掉光刻胶图案层5之后，遗留在顶层4的上表面的图案即为源漏极欧姆电极图案。
可理解的是，在一些实施例中，光刻胶图案是用光刻胶形成的图案。
S200步骤，在外延片具有光刻胶图案的一侧依次形成Ta xAl y合金金属层和Au金属层；其中，x＞0且y≥0。
在一些实施例中，光刻胶图案层5的上表面为远离顶层4的一面。外延片具有光刻胶图案层5的一侧指的是，顶层4的上表面中未被光刻胶图案层5覆盖的部分以及光刻胶图案层5的上表面。图3为本申请实施例在外延片具有光刻胶图案的一侧依次形成Ta xAl y合金金属层和Au金属层的结构示意图，依次形成如图3中所示的Ta xAl y合金金属层6和Au金属层7；其中，x＞0且y≥0，例如Ta xAl y合金金属层中Ta：Al的原子比例可以介于1：10-10：1之间，并且介于该比例区间的任意比例均可以实现本申请实施例的技术效果。
可选地，Ta xAl y合金金属层和Au金属层的厚度为20nm-200nm。在一些实施例中，形成的Ta xAl y合金金属层的厚度可以介于20nm-200nm之间，包括20nm和200nm，形成的Au金属层的厚度也可以介于20nm-200nm之间，包括20nm和200nm。若金属层的厚度小于20nm，金属本身的寄生电阻会比较大，厚度较大的金属层更有利于金属本身寄生电阻的下降；而当金属层的厚度大于200nm，则在对其进行后续的高温退火处理时，厚度过大的金属层会由于高温的作用使得其自身边缘变得粗糙，影响最终器件的稳定性及可靠性。
可选地，参考图3，在外延片具有光刻胶图案层5的一侧依次形成Ta xAl y合金金属层和Au金属层包括，在外延片具有光刻胶图案层的一侧利用磁控溅射工艺依次形成Ta xAl y合金金属层6和Au金属层7。在一些实施例中，将具有光刻胶图案层5的外延片放入磁控溅射设备真空传输室内，对外延片具有光刻胶图案层5的一侧进行镀膜工艺，依次采用Ta xAl y合金靶材溅射淀积Ta xAl y合金金属层6、采用Au金属靶材溅射淀积Au金属层7。其中，磁控溅射过程中使用的溅射气体可以为Ar气，溅射功率可介于100W-300W之间，包括100W和300W。
S300步骤，去除光刻胶以及光刻胶上的合金与金属，形成源漏极欧姆电极图案。
在一些实施例中，将外延片上的光刻胶以及光刻胶上的合金与金属全部去除，该合金与金属包括了光刻胶上的Ta xAl y合金金属层6、Au金属层7以及在依次形成Ta xAl y合金金属层和Au金属层过程中新生成的其它合金和金属等杂质，去除之后，形成源漏极欧姆电极图案。继续参考图3，将图3中的光刻胶图案层5以及位于光刻胶图案层5一侧的Ta xAl y合金金属层6、Au金属层7全部去除，遗留下的图案层即为源漏极欧姆电极膜层。
S400步骤，对形成有源漏极欧姆电极图案的外延片进行热退火工艺处理。
在一些实施例中，图4为本申请实施例提供的形成的源漏极欧姆电极的结构示意图，对形成有源漏极欧姆电极图案的外延片进行快速热退火处理，快速热退火之后，最终得到位于外延片的顶层4的上表面的如图4所示的源漏极欧姆电极。
可选地，热退火的气体氛围包括氮气、氨气、氮氢混合气体或氢氩混合气体。在一些实施例中，快速热退火过程中热退火的气体氛围可以选择氮气、氨气、氮氢混合气体或氢氩混合气体中的一种。
可选地，热退火的温度为700℃-1000℃；热退火的时间为10s-100s。在一些实施例中，快速热退火过程中热退火的的温度可以为700℃-1000℃，相应地，热退火的时间可以为10s-100s。
本申请实施例提供的一种半导体器件电极的制作方法，在外延片靠近AlGaN(InAlN)的一侧依次形成Ta xAl y合金金属层和Au金属层两层膜结构Ta xAl y/Au，代替相关技术中的四层膜结构Ti/Al/X/Au，也代替甚至具有五层的多层膜结构，使得在源漏极欧姆电极的制作过程中，仅需引入Ta xAl y合金及Au金属，若采用磁控溅射工艺依次形成Ta xAl y合金金属层和Au金属层，则仅需引入Ta xAl y合金靶材及Au金属靶材，相对于多层膜结构源漏极欧姆电极的制作过程，提高了源漏极欧姆电极形成过程的稳定性，避免交叉感染，更有利于产业化。相关技术中的四层膜结构Ti/Al/X/Au在热退火的过程中，Al层和Au层会发生互扩散的现象形成Al-Au合金从而增加了源漏极欧姆电极的表面粗糙度，本申请实施例中，形成Ta xAl y合金金属层的过程中，Ta、Al两种金属在淀积初始状态就充分均匀地混合，能够避免在热退火过程中金属之间过度的合金化而导致的粗糙度问题，且相对于Al-Au合金，Ta-Al具有更稳定的结合，因此能够 在退火过程中抑制Al外扩散，从而起到降低源漏极欧姆电极的表面粗糙度的作用，同时源漏极欧姆电极边缘区域的敏锐度得以提高，从而提高了器件的热稳定性、热可靠性及器件的良率，Au金属层则能够隔绝氧的侵入。采用Ta xAl y合金可以使得Ta、Al两种金属在热退火初始阶段就充分发挥各自作用，同时与外延片发生固相反应，更有利于欧姆接触电阻值的减小。据此，本申请实施例实现了在降低欧姆接触阻值的大小时，兼顾改善欧姆电极的表面粗糙程度及边缘敏锐度，从而提高GaN半导体器件的输出特性、热稳定性和器件良率，进而更加适用于短沟道射频器件，另外，仅需形成两层膜结构Ta xAl y/Au，减小了工艺的复杂程度，提高了源漏极欧姆电极制作过程中的稳定性，更有利于产业化。
实施例二
在上述实施例的基础上，图5为本申请实施例二提供的一种半导体器件电极的制作方法的示意图，如图5所示，该半导体器件电极的制作方法包括：
可选地，在S100步骤之前的S10步骤，依次使用丙酮和异丙醇对外延片进行表面清洁处理。
在一些实施例中，对外延片的表面依次使用丙酮超声清洗5-15mins，异丙醇清洗5-15mins，去离子水冲洗5-15mins，用氮气吹干的表面清洁处理。
S100步骤，在AlGaN(InAlN)/GaN外延片上形成光刻胶图案，图案定义出源漏极欧姆电极图案。
可选地，在S200步骤之前的S20步骤，去除外延片具有光刻胶图案的一侧的表面氧化物。
在一些实施例中，将外延片具有光刻胶图案层5的一侧浸没于稀释盐酸溶液中1mins-5mins，然后用去离子水冲洗5-15mins，氮气吹干，以去除外延片具有光刻胶图案层5的一侧表面氧化物；其中，稀盐酸的浓度比例可以是HCl:H 2O＝1:4。
S200步骤，在外延片具有光刻胶图案的一侧依次形成Ta xAl y合金金属层和Au金属层；其中，x＞0且y≥0。
可选地，S300步骤包括步骤S30，将在具有光刻胶图案的一侧依次形成有Ta xAl y合金金属层和Au金属层的外延片，以有机溶剂70℃-90℃水浴浸没的方法去除光刻胶以及光刻胶上的合金与金属，形成源漏极欧姆电极图案。
需要说明的是，本实施例中，有机溶剂70℃-90℃水浴浸没的方法是指，将 在具有光刻胶图案的一侧依次形成有Ta xAl y合金金属层和Au金属层的外延片浸没在有机溶剂中，而所述有机溶剂为通过水浴维持在70℃至90℃之间。
在一些实施例中，可以将如图3中所示的具有光刻胶图案层5的一侧依次形成有Ta xAl y合金金属层和Au金属层的外延片，以有机溶剂70℃-90℃水浴浸没的方法去除光刻胶以及光刻胶上的合金与金属。
S300步骤，去除光刻胶以及光刻胶上的合金与金属，形成源漏极欧姆电极图案。
S400步骤，对形成有源漏极欧姆电极图案的外延片进行热退火工艺处理。
本申请实施例提供的一种半导体器件电极的制作方法，依次通过：对AlGaN(InAlN)/GaN外延片的表面依次使用丙酮超声清洗5-15mins，异丙醇清洗5-15mins，去离子水冲洗5-15mins，用氮气吹干的表面清洁处理。在外延片的顶层4的上表面依次进行匀胶、前烘、光刻、显影、后烘的工艺步骤，得到如图2所示的位于顶层4的上表面的光刻胶图案层5，且光刻胶图案层5定义出源漏极欧姆电极图案。将外延片具有光刻胶图案层5的一侧浸没于稀释盐酸溶液中1mins-5mins，然后用去离子水冲洗5-15mins，氮气吹干，以去除外延片具有光刻胶图案层5的一侧表面氧化物。在外延片具有光刻胶图案层的一侧利用磁控溅射工艺依次形成Ta xAl y合金金属层和Au金属层。将具有光刻胶图案层5的一侧依次形成有Ta xAl y合金金属层和Au金属层的外延片，以有机溶剂70℃-90℃水浴浸没的方法去除光刻胶以及光刻胶上的合金与金属。对形成有源漏极欧姆电极图案的外延片进行快速热退火处理，快速热退火之后，最终得到位于外延片的顶层4的上表面的源漏极欧姆电极。
据此，本申请实施例的技术方案，一方面直接采用Ta xAl y/Au膜层替代传统Ti/Al/X/Au多层膜结构，减小了工艺的复杂性，提高了磁控溅射淀积腔室的稳定性，避免交叉污染。另一方面在膜层淀积初始阶段Ta、Al两种金属充分均匀地混合，有利于降低由于热退火而导致的合金化所引起的源漏极欧姆电极的表面粗糙度问题，相对于Al-Au，Ta-Al具有更好的热稳定性，能够抑制Al层的外扩散，因此即使在很高的热退火温度下，源漏极欧姆电极的表面仍能够维持良好的表面形貌且其边缘区域很难横向扩散，提高了器件的输出特性、热稳定性以及器件良率，工艺步骤简单可靠，更有利于提高产业化效率。不仅如此，采用Ta xAl y合金欧姆接触层可以使得Ta、Al两种金属在退火初始阶段就充分发挥各自作用，同时与衬底发生固相反应，更有利于欧姆接触电阻的减小。从而，本 申请实施例提供的一种半导体器件电极的制作方法，能够在降低欧姆接触值大小的同时，兼顾改善源漏极欧姆电极的表面形貌以及边缘区域敏锐度，提高器件的输出特性、热稳定性和器件良率，更有利于AlGaN(InAlN)/GaN功率及射频器件的产业化。
经实验多次验证，Ta 5Al 1合金金属层的厚度为60nm且Au金属层的厚度为60nm时，在热退火过程中，热退火气氛可为N 2，热退火时间可为60s，热退火温度可为900℃；Ta 10Al 1合金金属层的厚度为60nm且Au金属层的厚度为60nm时，在热退火过程中，热退火气氛可为3％H 2/Ar，热退火时间可为45s，热退火温度可为920℃；Ta 1Al 1合金金属层的厚度为60nm且Au金属层的厚度为60nm时，在热退火过程中，热退火气氛可为3％H 2/Ar，热退火时间可为80s，热退火温度可为870℃；Ta 1Al 5合金金属层的厚度为60nm且Au金属层的厚度为60nm时，在热退火过程中，热退火气氛可为N 2，热退火时间可为30s，热退火温度可为950℃；Ta 1Al 10合金金属层的厚度为60nm且Au金属层的厚度为60nm时，在热退火过程中，热退火气氛可为NH 3，热退火时间可为40s，热退火温度可为750℃。
实施例三
图6为本申请实施例提供的一种半导体欧姆接触结构的结构示意图，该半导体欧姆接触结构能够运用到涉及高电子迁移率晶体管的大功率器件或高频器件中，该半导体欧姆接触结构可以由上述实施例所述的任一半导体器件电极的制作方法制作而成，该半导体欧姆接触结构包括：AlGaN(InAlN)/GaN外延片10、位于外延片一侧的Ta xAl y合金金属层20，以及位于Ta xAl y合金金属层远离外延片一侧的Au金属层30，其中，x＞0且y≥0。
可选地，参考图6，Ta xAl y合金金属层20和Au金属层30的厚度为20nm-200nm。
本申请实施例提供的一种半导体欧姆接触结构，即Ta xAl y/Au双层金属薄膜结构，能够降低欧姆接触值大小的同时，兼顾改善源漏极欧姆电极的表面形貌以及边缘区域敏锐度，进而提高了器件的输出特性、热稳定性和器件良率，非常有利于AlGaN(InAlN)/GaN功率及射频器件的产业化。
本申请实施例提供的半导体器件电极的制作方法；在AlGaN(InAlN)/GaN外 延片上形成光刻胶图案，图案定义出源漏极欧姆电极图案；通过在外延片具有光刻胶图案的一侧依次形成Ta xAl y合金金属层和Au金属层；去除光刻胶以及光刻胶上的合金与金属，形成源漏极欧姆电极图案；对形成有源漏极欧姆电极图案的外延片进行热退火工艺处理；解决了在达到低欧姆接触电阻值的情况下，无法同时兼顾欧姆电极的表面形貌以及边缘敏锐度的问题，实现了在降低欧姆接触阻值的大小时，兼顾改善欧姆电极的表面粗糙程度及边缘敏锐度，从而提高GaN半导体器件的输出特性、热稳定性和器件良率。

Claims (10)

  1. 一种半导体器件电极的制作方法，包括：
    在AlGaN(InAlN)/GaN外延片上形成光刻胶图案，所述光刻胶图案用于定义出源漏极欧姆电极图案；
    在所述AlGaN(InAlN)/GaN外延片具有所述光刻胶图案的一侧依次形成Ta xAl y合金金属层和Au金属层；其中，x＞0且y≥0；
    去除光刻胶以及所述光刻胶上的合金与金属，形成所述源漏极欧姆电极图案；
    对形成有所述源漏极欧姆电极图案的所述AlGaN(InAlN)/GaN外延片进行热退火工艺处理。
  2. 根据权利要求1所述的半导体器件电极的制作方法，其中，所述在所述AlGaN(InAlN)/GaN外延片具有所述光刻胶图案的一侧依次形成Ta xAl y合金金属层和Au金属层包括：
    在所述AlGaN(InAlN)/GaN外延片具有所述光刻胶图案的一侧，利用磁控溅射工艺依次形成所述Ta xAl y合金金属层和所述Au金属层。
  3. 根据权利要求1所述的半导体器件电极的制作方法，其中，所述Ta xAl y合金金属层和所述Au金属层的厚度为20nm-200nm。
  4. 根据权利要求1所述的半导体器件电极的制作方法，其中，所述热退火为在气体氛围中进行，所述气体氛围包括氮气、氨气、氮氢混合气体或氢氩混合气体。
  5. 根据权利要求4所述的半导体器件电极的制作方法，其中，所述热退火的温度为700℃-1000℃；所述热退火的时间为10s-100s。
  6. 根据权利要求1所述的半导体器件电极的制作方法，在所述在AlGaN(InAlN)/GaN外延片上形成光刻胶图案，所述光刻胶图案用于定义出源漏极欧姆电极图案之前，所述半导体器件电极的制作方法还包括：
    依次使用丙酮和异丙醇对所述AlGaN(InAlN)/GaN外延片进行表面清洁处理。
  7. 根据权利要求1所述的半导体器件电极的制作方法，在所述在所述AlGaN(InAlN)/GaN外延片具有所述光刻胶图案的一侧依次形成Ta xAl y合金金属层和Au金属层之前，所述半导体器件电极的制作方法还包括：去除所述AlGaN(InAlN)/GaN外延片具有所述光刻胶图案的一侧的表面氧化物。
  8. 根据权利要求1所述的半导体器件电极的制作方法，其中，所述去除光 刻胶以及所述光刻胶上的合金与金属，形成所述源漏极欧姆电极图案包括：
    将在具有所述光刻胶图案的一侧依次形成有所述Ta xAl y合金金属层和所述Au金属层的所述AlGaN(InAlN)/GaN外延片，以有机溶剂70℃-90℃水浴浸没的方法去除所述光刻胶以及所述光刻胶上的所述合金与所述金属，形成所述源漏极欧姆电极图案。
  9. 一种半导体欧姆接触结构，所述半导体欧姆接触结构为由权利要求1-8任一所述的半导体器件电极的制作方法制作而成，所述半导体欧姆接触结构包括：
    AlGaN(InAlN)/GaN外延片、位于所述AlGaN(InAlN)/GaN外延片一侧的Ta xAl y合金金属层，以及位于所述Ta xAl y合金金属层远离所述AlGaN(InAlN)/GaN外延片一侧的Au金属层，其中，x＞0且y≥0。
  10. 根据权利要求9所述的半导体欧姆接触结构，其中，所述Ta xAl y合金金属层和所述Au金属层的厚度为20nm-200nm。
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