WO2021189586A1 - 驱动电路及显示面板 - Google Patents

驱动电路及显示面板 Download PDF

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Publication number
WO2021189586A1
WO2021189586A1 PCT/CN2020/086345 CN2020086345W WO2021189586A1 WO 2021189586 A1 WO2021189586 A1 WO 2021189586A1 CN 2020086345 W CN2020086345 W CN 2020086345W WO 2021189586 A1 WO2021189586 A1 WO 2021189586A1
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WO
WIPO (PCT)
Prior art keywords
signal line
clock signal
redundant
driving circuit
high frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/086345
Other languages
English (en)
French (fr)
Inventor
徐志达
金一坤
赵斌
张鑫
赵军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/767,136 priority Critical patent/US11443668B2/en
Publication of WO2021189586A1 publication Critical patent/WO2021189586A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, in particular to a driving circuit and a display panel.
  • the embodiments of the present application provide a driving circuit and a display panel to solve the conventional technical problem of poor horizontal lines of the display panel caused by different loads of clock signal lines.
  • An embodiment of the present application provides a driving circuit, which includes:
  • a clock signal line group includes a plurality of clock signal lines, the input end of the clock signal line is electrically connected to the signal generator, and the output end of the clock signal line is electrically connected to The drive circuit unit; a plurality of the clock signal lines are arranged side by side, and there is a first interval between two adjacent clock signal lines;
  • a non-high frequency signal line the input end of the non-high frequency signal line is electrically connected to the signal generator, and the non-high frequency signal line is arranged on both sides of the clock signal line group;
  • a redundant clock signal line the input end of the redundant clock signal line is electrically connected to the signal generator; the redundant clock signal line is arranged in the clock signal line group and the non-high frequency signal line Between; the redundant clock signal line and the adjacent clock signal line have a second distance; the second distance is equal to the first distance, the frequency of the signal connected to the redundant clock signal line and The amplitude is the same as the frequency and amplitude of the signal connected to the clock signal line.
  • the width of the redundant clock signal line is less than or equal to the width of the clock signal line.
  • the material of the redundant clock signal line is the same as the material of the clock signal line.
  • the material of the redundant clock signal line is one of metal, metal alloy, and metal oxide.
  • the non-high frequency signal line and the adjacent redundant clock signal line have a third distance, and the third distance is equal to the second distance.
  • the non-high frequency signal line is a low frequency signal line or a direct current signal line.
  • the non-high frequency signal line is a low frequency signal line, and the output end of the low frequency signal line is electrically connected to the driving circuit unit or the common electrode.
  • the present application also relates to a display panel, which includes a drive circuit provided in a non-display area of the display panel, wherein the drive circuit includes:
  • a clock signal line group includes a plurality of clock signal lines, the input end of the clock signal line is electrically connected to the signal generator, and the output end of the clock signal line is electrically connected to The drive circuit unit; a plurality of the clock signal lines are arranged side by side, and there is a first interval between two adjacent clock signal lines;
  • a non-high frequency signal line the input end of the non-high frequency signal line is electrically connected to the signal generator, and the non-high frequency signal line is arranged on both sides of the clock signal line group;
  • a redundant clock signal line the input end of the redundant clock signal line is electrically connected to the signal generator, and the output end of the redundant clock signal line is empty; the redundant clock signal line is arranged at the clock Between the signal line group and the non-high frequency signal line; the redundant clock signal line has a second distance from the adjacent clock signal line; the second distance is equal to the first distance, the The frequency and amplitude of the signal connected to the redundant clock signal line are the same as the frequency and amplitude of the signal connected to the clock signal line.
  • the width of the redundant clock signal line is less than or equal to the width of the clock signal line.
  • the material of the redundant clock signal line is the same as the material of the clock signal line.
  • the material of the redundant clock signal line is the same as the material of the clock signal line.
  • the material of the redundant clock signal line is one of metal, metal alloy and metal oxide.
  • the non-high frequency signal line and the adjacent redundant clock signal line have a third distance, and the third distance is equal to the second distance.
  • the non-high frequency signal line is a low frequency signal line or a direct current signal line.
  • the non-high frequency signal line is a low frequency signal line, and the output end of the low frequency signal line is electrically connected to the driving circuit unit or the common electrode.
  • the driving circuit and the display panel of the present application add redundant clock signal lines between the clock signal line group and the non-high frequency signal line, and the frequency and amplitude of the signal connected to the redundant clock signal line and the signal connected to the clock signal line The same, and do not connect to the plane; this setting makes the clock signal lines in the clock signal line group receive the same lateral capacitive coupling, achieving the effect of balancing the load of each clock signal line, and the screen shows no horizontal line defects Purpose.
  • FIG. 1 is a schematic diagram of a partial structure of a signal line wiring of a driving circuit in the prior art
  • FIG. 2 is a schematic structural diagram of a driving circuit according to an embodiment of the application.
  • Figure 3 is an enlarged view of part B of Figure 2;
  • Fig. 4 is a schematic cross-sectional view of line AA in Fig. 3;
  • FIG. 5 is a schematic structural diagram of a display panel according to an embodiment of the application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, “multiple” means two or more than two, unless otherwise specifically defined.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relation.
  • an intermediate medium it can be the internal communication of two components or the interaction of two components relation.
  • the "above” or “below” of the first feature of the second feature may include direct contact between the first and second features, or may include the first and second features Not in direct contact but through other features between them.
  • the "above”, “above” and “above” of the first feature on the second feature include the first feature directly above and obliquely above the second feature, or it simply means that the first feature is higher in level than the second feature.
  • the “below”, “below” and “below” of the second feature of the first feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • FIG. 2 is a schematic structural diagram of the driving circuit structure according to an embodiment of the application
  • FIG. 3 is an enlarged view of part B in FIG. 2.
  • the embodiment of the present application provides a driving circuit 100, which includes a signal generator 11, a driving circuit unit 12, a clock signal line group 13, a non-high frequency signal line 14, and a redundant clock signal line 15.
  • the clock signal line group 13 includes a plurality of clock signal lines 131, and the plurality of clock signal lines 131 are arranged side by side, and there is a first distance D1 between two adjacent clock signal lines 131.
  • the input end of the clock signal line 131 is electrically connected to the signal generator 11, and the output end of the clock signal line 131 is electrically connected to the driving circuit unit 12.
  • the input end of the non-high frequency signal line 14 is electrically connected to the signal generator 11.
  • the non-high frequency signal lines 14 are arranged on both sides of the clock signal line group 13.
  • the input end of the redundant clock signal line 15 is electrically connected to the signal generator 11, and the output end of the redundant clock signal line 15 is empty.
  • the redundant clock signal line 15 is arranged between the clock signal line group 13 and the non-high frequency signal line 14.
  • the redundant clock signal line 15 and the adjacent clock signal line 131 have a second distance D2.
  • the second distance D2 is equal to the first distance D1.
  • the frequency and amplitude of the signal connected to the redundant clock signal line 15 are the same as the frequency and amplitude of the signal connected to the clock signal line 131.
  • a redundant clock signal line 15 is added between the clock signal line group 13 and the non-high frequency signal line 14, so that the first interval D1 is equal to the second interval D2, and the redundant clock signal line 15
  • the input signal has the same frequency and amplitude as the signal connected to the clock signal line 131, and does not enter the plane. Since the lateral coupling capacitance is related to the distance between the two signal lines and the access voltage of the signal line, that is, under the same other conditions, the greater the distance between the two, the smaller the coupling capacitance; in other conditions In the same situation, the larger the voltage signal connected to the two, the larger the coupling capacitance.
  • a redundant clock signal line 15 is added to make the distance between each clock signal line 131 and its adjacent two signal lines equal, and the redundant clock signal line 15 and the clock signal line 131 are connected to the same connection.
  • Input voltage to ensure that the lateral capacitive coupling conditions of the clock signal lines 131 in the clock signal line group 13 are all the same, so as to achieve the effect of load balancing of the clock signal lines 131 and the screen display without horizontal line defects.
  • the output end of the redundant clock signal line 15 may also be connected to other elements or circuits. As long as the signal connected to the redundant clock signal line 15 does not affect the entire circuit structure.
  • the width of the redundant clock signal line 15 is less than or equal to the width of the clock signal line 131. Since the redundant clock signal line 15 and the clock signal line group 13 are both arranged in the frame area of the driving circuit 100, the arrangement of the redundant clock signal line 15 is convenient to shorten the frame width. In this embodiment, the width of the redundant clock signal line 15 is smaller than the width of the clock signal line 131, which further shortens the width of the frame.
  • the material of the redundant clock signal line 15 is the same as the material of the clock signal line 131.
  • the consistency of the two materials promotes the coupling effect of the clock signal line 131 to be more the same, so that the load of each clock signal line 15 tends to be the same .
  • the material of the redundant clock signal line 15 is one of metal, metal alloy and metal oxide.
  • metal metal alloy and metal oxide.
  • metal oxide for example, copper, molybdenum alloy and indium tin oxide, etc.
  • the thickness of the redundant clock signal line 15 and the clock signal line 131 are set to be equal, so that the area of the opposite surface of each clock signal line 131 and its adjacent signal line tends to be equal, so that each clock signal line
  • the signal line 131 has the same coupling capacitance as its adjacent signal line.
  • the clock signal line 131 closest to a redundant clock signal line 15 is set as the first clock signal line, and the clock signal line 131 closest to the first clock signal line is set as the second clock signal String.
  • the redundant clock signal line 15 may be facing
  • the shape and area of the side of the first clock signal line are equal to the shape and area of the side of the first clock signal line facing the second clock signal line.
  • the shape and area of the two sides of the redundant clock signal line 15 are correspondingly the same as the shape and area of the two sides of the clock signal line 131.
  • the non-high frequency signal line 14 and the adjacent redundant clock signal line 15 have a third distance D3, and the third distance D3 is equal to the second distance D2.
  • the second distance D2 is generally the minimum distance. This setting ensures that the third distance D3 is the minimum distance, so as to further shorten the width of the frame.
  • the third distance D3 may also be greater than the second distance D2 to prevent the non-high-frequency signal line 14 from affecting the outermost clock signal line 131.
  • the non-high frequency signal line 14 is a low frequency signal line or a direct current signal line.
  • the non-high frequency signal line 14 is a low frequency signal line
  • the driving circuit unit 12 is a gate driving circuit unit
  • the output end of the low frequency signal line 14 is electrically connected to the gate.
  • the driving circuit unit 12 or the common electrode (not shown in the figure).
  • the component connected to the output end of the low-frequency signal line 14 may also be other, for example, it may be a pixel electrode, and so on.
  • the driving circuit unit 12 may also be a source driving circuit unit.
  • the number of clock signal lines 131 is six and the number of redundant clock signal lines 15 is two as an example, but it is not limited to this. As long as there is at least one redundant clock signal line 15 on each side of the clock signal line group 13.
  • the signal generator 11 generates a clock signal of the same frequency and amplitude to each clock signal line 131 and the redundant clock signal line 15, and generates a low frequency signal to the non-high frequency signal line 14.
  • the clock signal line 131 transmits the clock signal to the gate driving circuit unit 12, and the clock signal in the redundant clock signal line 15 is not connected to the gate driving circuit unit 12.
  • the present application also relates to a display panel 1000.
  • the display panel 1000 is provided with a display area AA and a non-display area NA arranged around the display area AA.
  • the area NA is provided with a driving circuit 200, wherein the driving circuit 200 includes:
  • a clock signal line group includes a plurality of clock signal lines, the input end of the clock signal line is electrically connected to the signal generator, and the output end of the clock signal line is electrically connected to The drive circuit unit; a plurality of the clock signal lines are arranged side by side, and there is a first interval between two adjacent clock signal lines;
  • a non-high frequency signal line the input end of the non-high frequency signal line is electrically connected to the signal generator, and the non-high frequency signal line is arranged on both sides of the clock signal line group;
  • a redundant clock signal line the input end of the redundant clock signal is electrically connected to the signal generator, and the output end of the redundant clock signal is empty; the redundant clock signal line is arranged on the clock signal line Between the group and the non-high frequency signal line; the redundant clock signal line and the adjacent clock signal line have a second interval; the second interval is equal to the first interval, and the redundancy
  • the frequency and amplitude of the signal connected to the clock signal line are the same as the frequency and amplitude of the signal connected to the clock signal line.
  • the width of the redundant clock signal line is less than or equal to the width of the clock signal line.
  • the material of the redundant clock signal line is the same as the material of the clock signal line.
  • the structure of the driving circuit 200 of the display panel 1000 of this embodiment is the same as the structure of the driving circuit 100 of the above-mentioned embodiment.
  • the driving circuit and the display panel of the present application add redundant clock signal lines between the clock signal line group and the non-high frequency signal line, and the frequency amplitude of the signal connected to the redundant clock signal line and the signal connected to the clock signal line The same, and do not connect to the plane; this setting makes the clock signal lines in the clock signal line group receive the same lateral capacitive coupling, achieving the effect of balancing the load of each clock signal line, and the screen shows no horizontal line defects Purpose.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种驱动电路(100)及显示面板，在驱动电路结构中，时钟信号线群组(13)包括多条时钟信号线(131)，多条时钟信号线(131)并排设置，相邻两时钟信号线(131)之间具有第一间距(D1)；非高频信号线(14)设置在时钟信号线群组(13)的两侧；冗余时钟信号线(15)设置在时钟信号线群组(13)和非高频信号线(14)之间；冗余时钟信号线(15)接入的信号与时钟信号线(131)接入的信号的频率和振幅相同。

Description

驱动电路及显示面板 技术领域
本申请涉及一种显示技术领域，特别涉及一种驱动电路及显示面板。
 背景技术
在现有1Gate 1Data（同一行子像素和同一条扫描线连接，同一列子像素与同一条数据线连接）架构的8K（分辨率为7680*4320）显示面板对信号变化的敏感性极高，而目前8K显示面板中时钟信号线一般竖直排布在面板两侧，左右两侧的时钟信号线的旁边设置有低频信号线A或直流信号线。如图1所示，时钟信号线CK1与时钟信号线CK6所受的侧向耦合效应与中间时钟信号线CK2到时钟信号线CK5信号线不完全一致，因此会出现两侧时钟信号线信号线负载与中间时钟信号线负载不同的情况，进而导致显示面板的水平线类不良。
 技术问题
本申请实施例提供一种驱动电路及显示面板，以解决现有的时钟信号线负载不同导致显示面板的水平线类不良的技术问题。
 技术解决方案
本申请实施例提供一种驱动电路，其包括：
信号发生器；
驱动电路单元；
时钟信号线群组，所述时钟信号线群组包括多条时钟信号线，所述时钟信号线的输入端电性连接于所述信号发生器，所述时钟信号线的输出端电性连接于所述驱动电路单元；多条所述时钟信号线并排设置，相邻的两所述时钟信号线之间具有第一间距；
非高频信号线，所述非高频信号线的输入端电性连接于所述信号发生器，所述非高频信号线设置在所述时钟信号线群组的两侧；以及
冗余时钟信号线，所述冗余时钟信号线的输入端电性连接于所述信号发生器；所述冗余时钟信号线设置在所述时钟信号线群组和所述非高频信号线之间；所述冗余时钟信号线与相邻的所述时钟信号线具有第二间距；所述第二间距等于所述第一间距，所述冗余时钟信号线接入的信号的频率和振幅与所述时钟信号线接入的信号的频率和振幅相同。
在本申请实施例的所述驱动电路中，所述冗余时钟信号线的宽度小于或等于所述时钟信号线的宽度。
在本申请实施例的所述驱动电路中，所述冗余时钟信号线的材料和所述时钟信号线的材料一致。
在本申请实施例的所述驱动电路中，所述冗余时钟信号线的材料为金属、金属合金和金属氧化物中的一种。
在本申请实施例的所述驱动电路中，所述非高频信号线与相邻的所述冗余时钟信号线具有第三间距，所述第三间距等于第二间距。
在本申请实施例的所述驱动电路中，所述非高频信号线为低频信号线或直流信号线。
在本申请实施例的所述驱动电路中，所述非高频信号线为低频信号线，所述低频信号线的输出端电性连接于所述驱动电路单元或公共电极。
本申请还涉及一种显示面板，其包括驱动电路，所述驱动电路设于所述显示面板的非显示区，其中，所述驱动电路包括：
信号发生器；
驱动电路单元；
时钟信号线群组，所述时钟信号线群组包括多条时钟信号线，所述时钟信号线的输入端电性连接于所述信号发生器，所述时钟信号线的输出端电性连接于所述驱动电路单元；多条所述时钟信号线并排设置，相邻的两所述时钟信号线之间具有第一间距；
非高频信号线，所述非高频信号线的输入端电性连接于所述信号发生器，所述非高频信号线设置在所述时钟信号线群组的两侧；以及
冗余时钟信号线，所述冗余时钟信号线的输入端电性连接于所述信号发生器，所述冗余时钟信号线的输出端空置；所述冗余时钟信号线设置在所述时钟信号线群组和所述非高频信号线之间；所述冗余时钟信号线与相邻的所述时钟信号线具有第二间距；所述第二间距等于所述第一间距，所述冗余时钟信号线接入的信号的频率和振幅与所述时钟信号线接入的信号的频率和振幅相同。
在本申请实施例的所述的显示面板中，所述冗余时钟信号线的宽度小于或等于所述时钟信号线的宽度。
在本申请实施例的所述的显示面板中，所述冗余时钟信号线的材料和所述时钟信号线的材料一致。
在本申请实施例的所述显示面板中，所述冗余时钟信号线的材料和所述时钟信号线的材料一致。
在本申请实施例的所述显示面板中，所述冗余时钟信号线的材料为金属、金属合金和金属氧化物中的一种。
在本申请实施例的所述显示面板中，所述非高频信号线与相邻的所述冗余时钟信号线具有第三间距，所述第三间距等于第二间距。
在本申请实施例的所述显示面板中，所述非高频信号线为低频信号线或直流信号线。
在本申请实施例的所述显示面板中，所述非高频信号线为低频信号线，所述低频信号线的输出端电性连接于所述驱动电路单元或公共电极。
需要说明的是，本实施例的显示面板的驱动电路的结构与上述实施例的驱动电路的结构一致。
 有益效果
本申请的驱动电路及显示面板通过在时钟信号线群组和非高频信号线之间增设冗余时钟信号线，冗余时钟信号线接入的信号与时钟信号线接入的信号的频率振幅相同，且不接入面内；这样的设置使得时钟信号线群组中的时钟信号线受到的侧向电容耦合情况均相同，达到各个时钟信号线负载平衡的效果，且画面显示无水平线不良的目的。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面对实施例中所需要使用的附图作简单的介绍。下面描述中的附图仅为本申请的部分实施例，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1为现有技术的驱动电路的信号线布线的部分结构示意图；
图2为本申请实施例的驱动电路的结构示意图；
图3为图2中B部分的放大图;
图4为图3中AA线的截面示意图；
图5为本申请实施例的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参照图2和图3，图2为本申请实施例的驱动电路结构的结构示意图；图3为图2中B部分的放大图。
本申请实施例提供一种驱动电路100，其包括信号发生器11、驱动电路单元12、时钟信号线群组13、非高频信号线14和冗余时钟信号线15。
时钟信号线群组13包括多条时钟信号线131，多条时钟信号线131并排设置，相邻的两所述时钟信号线131之间具有第一间距D1。时钟信号线131的输入端电性连接于信号发生器11，时钟信号线131的输出端电性连接于驱动电路单元12。
非高频信号线14的输入端电性连接于信号发生器11。非高频信号线14设置在所述时钟信号线群组13的两侧。
冗余时钟信号线15的输入端电性连接于所述信号发生器11，冗余时钟信号线15的输出端空置。所述冗余时钟信号线15设置在时钟信号线群组13和非高频信号线14之间。冗余时钟信号线15与相邻的时钟信号线131具有第二间距D2。
第二间距D2等于第一间距D1。冗余时钟信号线15接入的信号的频率和振幅与时钟信号线接入131的信号的频率和振幅相同。
本申请实施例的驱动电路100通过在时钟信号线群组13和非高频信号线14之间增设冗余时钟信号线15，使得第一间距D1等于第二间距D2，冗余时钟信号线15接入的信号与时钟信号线131接入的信号的频率振幅相同，且不接入面内。由于侧向耦合电容跟两个信号线之间的距离以及信号线的接入电压有关，即在其他条件相同的情况下，二者之间的距离越大，其耦合电容越小；在其他条件相同的情况下，二者接入的电压信号越大，其耦合电容越大。因此增设了冗余时钟信号线15，以使每个时钟信号线131与其相邻的两个信号线之间的距离均相等，以及冗余时钟信号线15和时钟信号线131接入相同的接入电压，以确保时钟信号线群组13中的时钟信号线131受到的侧向电容耦合情况均相同，达到各个时钟信号线131负载平衡的效果，且画面显示无水平线不良的目的。
在一些实施例中，冗余时钟信号线15的输出端也可以连接其他元件或电路。只要冗余时钟信号线15接入的信号不影响整个电路结构即可。
在本申请实施例的驱动电路100中，所述冗余时钟信号线15的宽度小于或等于所述时钟信号线131的宽度。由于冗余时钟信号线15、时钟信号线群组13均设置在驱动电路100的边框区，因此冗余时钟信号线15的设置便于缩短边框宽度。在本实施例中，冗余时钟信号线15的宽度小于时钟信号线131的宽度，进一步缩短边框的宽度。
另外，冗余时钟信号线15的材料和所述时钟信号线131的材料一致。当冗余时钟信号线15和时钟信号线131均处于信号传输状态时，二者材料的一致性促使时钟信号线131的耦合效应更加趋于相同，从而使得各时钟信号线15的负载趋于相同。
可选的，冗余时钟信号线15的材料为金属、金属合金和金属氧化物中的一种。比如，铜、钼合金和氧化铟锡等。
在本实施例中，由于侧向耦合电容的大小还涉及二者相对面的面积大小，面积越大侧向耦合电容的大小越大。请参照图4，因此设置冗余时钟信号线15和时钟信号线131的厚度相等，以使每条时钟信号线131与其相邻的信号线的相对面的面积趋于相等，进而使得每条时钟信号线131与其相邻的信号线的耦合电容相同。
具体的，将与一冗余时钟信号线15距离最近的时钟信号线131设定为第一时钟信号线，将与该第一时钟信号线距离最近的时钟信号线131设定为第二时钟信号线。为了使冗余时钟信号线15和第一时钟信号线之间的电容耦合效应，与相邻的两条时钟信号线131之间的电容耦合效应趋于相同，可以将冗余时钟信号线15面向第一时钟信号线一侧的形状和面积大小等同于第一时钟信号线面向第二时钟信号线一侧的形状和面积大小。
进一步的，冗余时钟信号线15两个侧面的形状和面积大小与时钟信号线131两个侧面的形状和面积大小均对应相同。
在本申请实施例的驱动电路100中，所述非高频信号线14与相邻的冗余时钟信号线15具有第三间距D3，第三间距D3等于第二间距D2。在实现窄边框时，第二间距D2一般为最小距离，这样的设置保证第三距离D3为最小距离，以进一步缩短边框宽度。
在一些实施例中，第三间距D3也可以是大于第二间距D2，避免非高频信号线14影响最边缘的时钟信号线131。
可选的，所述非高频信号线14为低频信号线或直流信号线。在本申请实施例的驱动电路100中，所述非高频信号线14为低频信号线，驱动电路单元12为栅极驱动电路单元，所述低频信号线14的输出端电性连接于栅极驱动电路单元12或公共电极（图中未示出）。当然低频信号线14的输出端连接的元件也可以是其他，比如可以是像素电极，等等。
当然在一些实施例中，驱动电路单元12也可以是源极驱动电路单元。
另外，在本实施例以时钟信号线131的数量为六条，冗余时钟信号线15的数量为两条为例进行展示，但并不限于此。只要时钟信号线群组13的两侧至少各有一条冗余时钟信号线15即可。
在本实施例的工作过程中，信号发生器11向每个时钟信号线131和冗余时钟信号线15发生相同频率和振幅的时钟信号，且向非高频信号线14发生低频信号。
此时，由于第一间距D1和第二间距D2相等，因此每个时钟信号线131受到的侧向电容耦合趋于相同，进而使得每个时钟信号线131的负载趋于平衡。
最后，时钟信号线131将时钟信号传输至栅极驱动电路单元12，冗余时钟信号线15中的时钟信号不接入栅极驱动电路单元12。
本申请还涉及一种显示面板1000，在本实施例中，如附图5，所述显示面板1000设有显示区AA以及围绕所述显示区AA设置的非显示区NA，在所述非显示区NA设置有驱动电路200，其中，所述驱动电路200包括：
信号发生器；
驱动电路单元；
时钟信号线群组，所述时钟信号线群组包括多条时钟信号线，所述时钟信号线的输入端电性连接于所述信号发生器，所述时钟信号线的输出端电性连接于所述驱动电路单元；多条所述时钟信号线并排设置，相邻的两所述时钟信号线之间具有第一间距；
非高频信号线，所述非高频信号线的输入端电性连接于所述信号发生器，所述非高频信号线设置在所述时钟信号线群组的两侧；以及
冗余时钟信号线，所述冗余时钟信号的输入端电性连接于所述信号发生器，所述冗余时钟信号的输出端空置；所述冗余时钟信号线设置在所述时钟信号线群组和所述非高频信号线之间；所述冗余时钟信号线与相邻的所述时钟信号线具有第二间距；所述第二间距等于所述第一间距，所述冗余时钟信号线接入的信号的频率和振幅与所述时钟信号线接入的信号的频率和振幅相同。
在本申请实施例的所述的显示面板1000中，所述冗余时钟信号线的宽度小于或等于所述时钟信号线的宽度。
在本申请实施例的所述的显示面板1000中，所述冗余时钟信号线的材料和所述时钟信号线的材料一致。
需要说明的是，本实施例的显示面板1000的驱动电路200的结构与上述实施例的驱动电路100的结构一致。
本申请的驱动电路及显示面板通过在时钟信号线群组和非高频信号线之间增设冗余时钟信号线，冗余时钟信号线接入的信号与时钟信号线接入的信号的频率振幅相同，且不接入面内；这样的设置使得时钟信号线群组中的时钟信号线受到的侧向电容耦合情况均相同，达到各个时钟信号线负载平衡的效果，且画面显示无水平线不良的目的。
以上对本申请实施例所提供的一种驱动电路及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (17)

  1. 一种驱动电路，其包括：
    信号发生器；
    驱动电路单元；
    时钟信号线群组，所述时钟信号线群组包括多条时钟信号线，所述时钟信号线的输入端电性连接于所述信号发生器，所述时钟信号线的输出端电性连接于所述驱动电路单元，多条所述时钟信号线并排设置，相邻的两所述时钟信号线之间具有第一间距；
    非高频信号线，所述非高频信号线的输入端电性连接于所述信号发生器，所述非高频信号线设置在所述时钟信号线群组的两侧；以及
    冗余时钟信号线，所述冗余时钟信号线的输入端电性连接于所述信号发生器；所述冗余时钟信号线设置在所述时钟信号线群组和所述非高频信号线之间；所述冗余时钟信号线接入的信号的频率和振幅与所述时钟信号线接入的信号的频率和振幅相同。
  2. 根据权利要求1所述的驱动电路，其中，所述冗余时钟信号线与相邻的所述时钟信号线具有第二间距，所述第二间距等于所述第一间距。
  3. 根据权利要求1所述的驱动电路，其中，所述冗余时钟信号线与所述时钟信号线的厚度相等。
  4. 根据权利要求2所述的驱动电路，其中，所述冗余时钟信号线与所述时钟信号线的厚度相等。
  5. 根据权利要求1所述的驱动电路，其中，所述冗余时钟信号线的宽度小于或等于所述时钟信号线的宽度。
  6. 根据权利要求1所述的驱动电路，其中，所述冗余时钟信号线的材料和所述时钟信号线的材料一致。
  7. 根据权利要求1所述的驱动电路，其中，所述非高频信号线与相邻的所述冗余时钟信号线具有第三间距，所述第三间距等于第二间距。
  8. 根据权利要求1所述的驱动电路，其中，所述非高频信号线为低频信号线或直流信号线。
  9. 根据权利要求8所述的驱动电路，其中，所述非高频信号线为低频信号线，所述低频信号线的输出端电性连接于所述驱动电路单元或公共电极。
  10. 一种显示面板，其包括驱动电路，所述驱动电路设于所述显示面板的非显示区，其中所述驱动电路包括：
    信号发生器；
    驱动电路单元；
    时钟信号线群组，所述时钟信号线群组包括多条时钟信号线，所述时钟信号线的输入端电性连接于所述信号发生器，所述时钟信号线的输出端电性连接于所述驱动电路单元；多条所述时钟信号线并排设置，相邻的两所述时钟信号线之间具有第一间距；
    非高频信号线，所述非高频信号线的输入端电性连接于所述信号发生器，所述非高频信号线设置在所述时钟信号线群组的两侧；以及
    冗余时钟信号线，所述冗余时钟信号线的输入端电性连接于所述信号发生器；所述冗余时钟信号线设置在所述时钟信号线群组和所述非高频信号线之间；所述冗余时钟信号线接入的信号的频率和振幅与所述时钟信号线接入的信号的频率和振幅相同。
  11. 根据权利要求10所述的显示面板，其中，所述冗余时钟信号线与相邻的所述时钟信号线具有第二间距，所述第二间距等于所述第一间距。
  12. 根据权利要求10所述的显示面板，其中，所述冗余时钟信号线与所述时钟信号线的厚度相等。
  13. 根据权利要求10所述的显示面板，其中，所述冗余时钟信号线的宽度小于或等于所述时钟信号线的宽度。
  14. 根据权利要求10所述的显示面板，其中，所述冗余时钟信号线的材料和所述时钟信号线的材料一致。
  15. 根据权利要求10所述的显示面板，其中，所述非高频信号线与相邻的所述冗余时钟信号线具有第三间距，所述第三间距等于第二间距。
  16. 根据权利要求10所述的显示面板，其中，所述非高频信号线为低频信号线或直流信号线。
  17. 根据权利要求16所述的显示面板，其中，所述非高频信号线为低频信号线，所述低频信号线的输出端电性连接于所述驱动电路单元或公共电极。
PCT/CN2020/086345 2020-03-22 2020-04-23 驱动电路及显示面板 Ceased WO2021189586A1 (zh)

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