WO2021184906A1 - 阵列基板、显示装置 - Google Patents

阵列基板、显示装置 Download PDF

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Publication number
WO2021184906A1
WO2021184906A1 PCT/CN2020/140831 CN2020140831W WO2021184906A1 WO 2021184906 A1 WO2021184906 A1 WO 2021184906A1 CN 2020140831 W CN2020140831 W CN 2020140831W WO 2021184906 A1 WO2021184906 A1 WO 2021184906A1
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Prior art keywords
pixel electrode
electrodes
electrode
array substrate
base substrate
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PCT/CN2020/140831
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English (en)
French (fr)
Inventor
赵重阳
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US17/418,364 priority Critical patent/US12032249B2/en
Publication of WO2021184906A1 publication Critical patent/WO2021184906A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a display device.
  • LCD display has occupied a leading position in the display industry.
  • products with ADS Advanced Super Dimension Switch, advanced super dimensional field conversion technology
  • ADS Advanced Super Dimension Switch, advanced super dimensional field conversion technology
  • the display panel of the ADS structure needs to provide notches on part of the pixel electrodes.
  • the notches will affect the display effect of the display panel.
  • an array substrate which includes: a base substrate, a plurality of data lines, and a plurality of pixel electrodes.
  • the plurality of data lines include adjacent first data lines and second data lines;
  • the plurality of pixel electrodes include at least one bridge pixel electrode, and the orthographic projection of the bridge pixel electrode on the base substrate is located on the first data line And the second data line are between the orthographic projection of the base substrate; wherein a first notch is provided on the side of the bridge pixel electrode close to the first data line, and the bridge pixel electrode is close to the second A second gap is provided on one side of the data line.
  • the plurality of bridge pixel electrodes include a first bridge pixel electrode and a second bridge pixel electrode located in adjacent rows, and the array substrate is also Including: multiple common sub-electrodes, common connecting wires, and connecting electrodes.
  • the common sub-electrodes and the pixel electrodes are arranged in a one-to-one correspondence, and the corresponding common sub-electrodes and the pixel electrodes are at least partially overlapped with the orthographic projection of the pixel electrodes on the array substrate;
  • the common sub-electrode; the connecting electrode includes a first connecting block and a second connecting block that are connected, and the orthographic projection of the first connecting block on the base substrate is located in the first bridging pixel electrode and the first gap is in the Within the orthographic projection range of the base substrate, the orthographic projection of the second connection block on the base substrate is located within the orthographic projection range of the first notch of the second bridge pixel electrode on the base substrate.
  • the first connection block is electrically connected to a common sub-electrode corresponding to the first bridge pixel electrode through a via hole
  • the second connection block is electrically connected to a common sub-electrode through a via hole.
  • the line is electrically connected
  • the common connection line is electrically connected to the common sub-electrode corresponding to the second bridged pixel electrode.
  • the first connection block is electrically connected to the common sub-electrode corresponding to the first bridge pixel electrode through a via hole
  • the second connection block is electrically connected to the common sub-electrode through the via hole.
  • the common sub-electrode corresponding to the second bridge pixel electrode is electrically connected.
  • the array substrate further includes a data line extending in the second direction, and the common connection line includes electrically connected lead parts and bridge parts.
  • the lead portion extends along the first direction; the orthographic projection of the bridge portion on the base substrate is located within the range of the orthographic projection of the second bridge pixel electrode on the first notch of the base substrate, and The width of the connecting portion in the second direction is greater than the width of the lead portion in the second direction, and the second connecting block is electrically connected to the common connecting line through the bridging portion.
  • the array substrate further includes a gate line extending in a first direction, and the first bridge pixel electrode and the second bridge pixel electrode are respectively located on one of the gate lines On both sides of the gate line, the first gaps of the first bridging pixel electrode and the second bridging pixel electrode are located close to the gate line.
  • the first bridging pixel electrode and the second bridging pixel electrode are located in the same column; the array substrate further includes a gate line, and the gate line is located on the base substrate.
  • the orthographic projection is located between the orthographic projections of the common sub-electrodes in adjacent rows on the base substrate, and the grid lines include electrically connected wiring portions and gate portions; the grid portion is in the orthographic projection of the base substrate Located between adjacent data lines on the orthographic projection of the base substrate, and the width of the gate portion is greater than the width of the wiring portion.
  • the array substrate further includes a thin film transistor, and the common connecting line is provided in the same layer as the gate layer of the thin film transistor; the common sub-electrode is provided on the gate of the thin film transistor.
  • the electrode layer faces the side of the base substrate; the pixel electrode is arranged on the side of the thin film transistor source and drain layer away from the base substrate; the array substrate includes a sub-pixel unit for forming multiple colors
  • the pixel electrodes and pixel electrodes corresponding to at least one color are all the bridged pixel electrodes.
  • the pixel electrodes of the same column form sub-pixel units of the same color
  • the pixel electrode corresponding to the first color is arranged as a bridge pixel electrode
  • the first common sub-electrode is arranged corresponding to the bridge pixel electrode; wherein ,
  • the first common sub-electrodes located in the same row and adjacent columns are respectively connected to the common sub-electrodes of the upper row and the common sub-electrodes of the lower row through the connecting electrodes.
  • a display device including the above-mentioned array substrate.
  • FIG. 1 is a schematic diagram of the structure of an array substrate in the related art
  • FIG. 2 is a schematic structural diagram of an exemplary embodiment of an array substrate of the present disclosure
  • FIG. 3 is a schematic structural diagram of another exemplary embodiment of the array substrate of the present disclosure.
  • Figure 4 is a cross-sectional view at the dotted line 6 in Figure 3;
  • FIG. 5 is a schematic structural diagram of an exemplary embodiment of the array substrate of the present disclosure.
  • Fig. 6 is a partial enlarged view of Fig. 5.
  • FIG. 1 it is a schematic diagram of the structure of an array substrate in the related art.
  • the array substrate includes a plurality of pixel electrodes (141, 142 in FIG. 1) and common sub-electrodes (111, 112 in FIG. 1) distributed in an array.
  • the pixel electrodes and the common sub-electrodes are arranged opposite to each other, and the corresponding pixel electrodes At least partially overlap with the orthographic projection of the common sub-electrode on the array substrate.
  • the common sub-electrodes located in the same row are electrically connected by a common connecting line. As shown in FIG.
  • the electrodes are electrically connected through the common connection line 122.
  • the connecting electrode 15 is located in the pixel electrode layer. Electrical connection, thereby connecting the common sub-electrodes of adjacent rows. As shown in FIG. 1, since the connecting electrode 15 needs to be provided, corresponding notches need to be provided at the lower left of the pixel electrode 141 and the upper left of the pixel electrode 142.
  • the connecting electrode 15 can be electrically connected to the common sub-electrode through a via hole at the position of the notch. .
  • a pixel electrode provided with a gap can be called a bridge pixel electrode.
  • the bridge pixel electrode and the left and right data lines 161, 162 have different lateral field capacitances, which leads to voltage crosstalk (V -crosstalk), display horizontal stripes and other problems.
  • the exemplary embodiment provides an array substrate, as shown in FIG. 2, which is a schematic structural diagram of an exemplary embodiment of the array substrate of the present disclosure.
  • the array substrate includes: a base substrate 401, a plurality of data lines 11, 12, and 13, and a plurality of pixel electrodes 21, 22, 23, and 24.
  • a plurality of data lines extend along the second direction X and include adjacent first data lines 11 and second data lines 12; the plurality of pixel electrodes include bridging pixel electrodes 21, and the bridging pixel electrodes 21 are on the base substrate
  • the orthographic projection of 401 is located between the orthographic projection of the first data line 11 and the second data line 12 on the base substrate; wherein, the bridge pixel electrode 21 is arranged on a side close to the first data line 11
  • There is a first notch 211, and a second notch 212 is provided on the side of the bridging pixel electrode 21 close to the second data line 12.
  • the array substrate is provided with notches on both sides of the bridge pixel electrode, wherein the first notch can be used to provide the connecting electrode, the first notch is disposed close to the first data line 11, and the second notch is disposed close to the second data line 12, so
  • the bridging pixel electrode and the data lines on both sides have similar lateral field capacitances, thereby reducing the problem of voltage crosstalk (V-crosstalk) of the bridging pixel electrode and improving the display effect.
  • V-crosstalk voltage crosstalk
  • the area of the first gap and the area of the second gap may be equal or similar.
  • the second notch can be provided at any position of the bridged pixel electrode close to the second data line 12. As shown in FIG. 2, the second notch can be provided at the upper right of the bridged pixel electrode. To bridge the lower right and other positions of the pixel electrode, there may also be multiple second gaps.
  • FIG. 3 it is a schematic structural diagram of another exemplary embodiment of the array substrate of the present disclosure.
  • the plurality of bridge pixel electrodes include a first bridge pixel electrode 21 and a second bridge pixel electrode 22 located in adjacent rows
  • the array substrate may further include: a plurality of common sub-electrodes (Figure 3 shows the common sub-electrodes 31 and 32 as an example) and the connecting electrode 4.
  • the common sub-electrodes and the pixel electrodes are arranged in a one-to-one correspondence, and the corresponding common sub-electrodes and the pixel electrodes are at least partially overlapped with the orthographic projection of the pixel electrodes on the base substrate, for example, the common sub-electrodes 31 and the first bridge pixels
  • the electrodes 21 are arranged correspondingly, the common sub-electrodes 32 and the second bridge pixel electrodes 22 are arranged correspondingly, and the common sub-electrodes located in the same row are electrically connected by a common connecting line.
  • the common sub-electrodes in the row where the common sub-electrodes 31 are located pass The connecting wire 51 is electrically connected, and the common sub-electrodes in the row of the common sub-electrode 32 are electrically connected through the common connecting wire 52.
  • the common connection line may be directly formed on the side of the common sub-electrode away from the base substrate, and the common connection line directly overlaps the common sub-electrode, thereby electrically connecting the common sub-electrodes in the same row; or in other embodiments
  • an insulating layer may be provided between the common connection line and the common sub-electrode, and the two are electrically connected through a via hole penetrating the insulating layer.
  • the connecting electrode 4 includes a first connecting block 41 and a second connecting block 42 connected to each other.
  • the orthographic projection of the first connecting block 41 on the base substrate 401 is located in the first gap of the first bridging pixel electrode 21.
  • the orthographic projection of the second connecting block 42 on the base substrate is located at the first notch of the second bridging pixel electrode 22 in the orthographic projection range of the base substrate Inside.
  • the connecting electrode 4 may be formed in the same layer as the pixel electrode, that is, formed by the same patterning process, and the material is the same, but not necessarily on the same plane or the same height. It should be understood that in other exemplary embodiments, the connection electrode may also be located on other conductive layers.
  • FIG. 4 is a cross-sectional view at the dotted line 6 in FIG. 3.
  • the array substrate may include: common sub-electrodes 31, 32, common connection lines 51, 52, data line 11, a first insulating layer 402, a second insulating layer 403, and a connection electrode 4.
  • the common sub-electrodes 31, 32 are arranged on the substrate.
  • the common connection lines 51, 52 are arranged on the side of the common sub-electrodes 31, 32 away from the base substrate 401, and the first insulating layer 402 is located on the side of the common connection lines 51, 52 away from the base substrate.
  • the data line 11 is arranged on the side of the first insulating layer 402 away from the base substrate, the second insulating layer 403 is arranged on the side of the data line 11 away from the base substrate, and the connecting electrode 4 is arranged on the second insulating layer 403 away from the base substrate On the side.
  • the array substrate may include thin film transistors, and the common connecting lines 51, 52 may be arranged in the same layer as the gate of the thin film transistor, that is, formed by a patterning process; the data line 11 may be arranged in the same layer as the source and drain of the thin film transistor , Which is formed by a patterning process.
  • the first connection block 41 may be electrically connected to the common sub-electrode 31 corresponding to the first bridge pixel electrode 21 through a via hole
  • the second connection block 42 may be electrically connected to a common connection line 52 through a via hole
  • the common connecting line 52 is electrically connected to the common sub-electrode 32 corresponding to the second bridged pixel electrode 42.
  • the pixel electrode layer and the common electrode layer may be formed of indium tin oxide, and the indium tin oxide has a certain degree of transparency to improve the light output rate of the display panel.
  • the gate layer may be formed of a metal or alloy.
  • the gate layer may be formed of a metal such as copper, aluminum, silver, or an alloy thereof.
  • connecting the second connection block 42 and the common sub-electrode 32 through the common connection line 52 can reduce the resistance between the second connection block 42 and the common sub-electrode 32, thereby increasing The uniformity of the voltage on each common sub-electrode.
  • the first connection block may also be electrically connected to a common sub-electrode corresponding to the first bridge pixel electrode through a via hole
  • the second connection block may also directly pass through a via hole and a common sub-electrode.
  • the common sub-electrode corresponding to the second bridge pixel electrode is electrically connected.
  • the common connection line 52 may include electrically connected: a lead part 521 and a jumper part 522.
  • the lead portion 521 may extend along the first direction Y, the orthographic projection of the bridging portion 522 on the base substrate is located within the range of the first gap of the second bridging pixel electrode 22, and the bridging portion 522 is located in the second gap.
  • the width of the direction X is greater than the width of the lead portion 521 in the second direction X, and the second connection block 42 is electrically connected to the common connection line 52 through the jumper 522. Wherein, providing the lead portion 521 with a smaller width can reduce the parasitic capacitance between the lead portion 521 and the data line.
  • the first bridge pixel electrode 21 and the second bridge pixel electrode 22 may be located in the same column.
  • the first gaps of the first bridging pixel electrode 21 and the second bridging pixel electrode 22 are both arranged close to the gate line located between them.
  • the first notch of the first bridging pixel electrode 21 is provided at the lower left of the first bridging pixel electrode 21, and the first notch of the second bridging pixel electrode 22 is provided at the upper left of the second bridging pixel electrode 22
  • the connecting electrode can be electrically connected to the common sub-electrode through the via hole at the position of the gap.
  • first bridge pixel electrode 21 and the second bridge pixel electrode 22 may be located in different columns.
  • the first notch of the first bridging pixel electrode 21 and the first notch of the second bridging pixel electrode 22 may be arranged in other positions.
  • connection electrodes may only electrically connect part of the common sub-electrodes to achieve electrical connection of all the common sub-electrodes in the column direction.
  • the pixel electrodes need to be configured as the above-mentioned bridge pixel electrodes (ie, pixel electrodes provided with gaps), and the other pixel electrodes are normal pixel electrodes (ie, pixel electrodes without gaps).
  • the array substrate may include pixel electrodes corresponding to multiple colors, and the pixel electrodes of at least one color are all the bridge pixel electrodes.
  • this setting sets the pixel electrodes of the same color sub-pixel unit as the bridge pixel electrode, which can make the pixel electrodes of the same color sub-pixel unit have the same area, thereby avoiding The sub-pixel units of the same color emit light unevenly.
  • FIG. 5 it is a schematic structural diagram of an exemplary embodiment of the array substrate of the present disclosure.
  • the line extends in the second direction X.
  • the array substrate may include three-color sub-pixel units, the n+1th column of pixel electrodes is located in the first color sub-pixel unit, the n+2th column of pixel electrodes is located in the second color sub-pixel unit, and the n+3th column of pixel electrodes Located in the third color sub-pixel unit.
  • the pixel electrode 71 corresponding to the first color is located in the n+1th column, and the pixel electrode 71 and the common sub-electrode 72 are arranged correspondingly.
  • the pixel electrodes 71 are all bridging pixel electrodes.
  • the common sub-electrodes 72 located in the same row and adjacent columns are respectively connected to the common sub-electrodes of the upper row and the common sub-electrodes of the lower row through the connecting electrodes 73.
  • the common sub-electrodes 72 in the third row and the first column are electrically connected to the common sub-electrodes 72 in the second row and the first column
  • the common sub-electrodes 72 in the third row and the fourth column are electrically connected to the common sub-electrodes 72 in the third row and the fourth column.
  • the common sub-electrode 72 is electrically connected.
  • the bridge pixel electrodes may be located in sub-pixel units of the same color, thereby avoiding uneven light emission of the sub-pixel units of the same color.
  • the connecting electrodes are spaced apart along the first direction Y and the second direction X.
  • the first direction Y may be a row direction
  • the second direction X may be a column direction.
  • adjacent connecting electrodes Located in different columns and in the column direction, adjacent connecting electrodes are located in different rows. This arrangement can avoid the problem of uneven voltage on the common sub-electrode caused by the charge on the common sub-electrode extending in the same column direction.
  • FIG. 6 is a partial enlarged view of FIG. 5.
  • the array substrate further includes a grid line 501, the orthographic projection of the grid line 501 on the base substrate is located between the orthographic projections of the common sub-electrodes in adjacent rows on the base substrate, and the grid lines 501 include traces.
  • Portion 81, gate portion 82, the orthographic projection of the gate portion 82 on the base substrate is located between the orthographic projections of adjacent data lines 502 on the base substrate, and the width of the gate portion 82 in the direction in which the data lines extend It is larger than the width of the wiring portion 81 in the extending direction of the data line.
  • the gate portion 82 may form the gate of a thin film transistor that controls pixel switching.
  • the thin film transistor further includes an active layer 83, a first electrode 85, and a second electrode 84.
  • the active layer 83 is located at the gate portion. 82 is away from the side of the base substrate, and the orthographic projection of the active layer 83 on the base substrate is located on the orthographic projection of the gate portion 82 on the base substrate.
  • the active layer 83 includes a channel region, a first source-drain contact portion, and a second source-drain contact portion.
  • the first electrode 85 of the thin film transistor is connected to the data line 502, and the first electrode 85 and the first source-drain contact portion are on the substrate.
  • the orthographic projection of the substrate is at least partially overlapped, the first electrode 85 is electrically connected to the first source/drain contact portion through the via hole; the second electrode 84 of the thin film transistor is electrically connected to the pixel electrode, and the second electrode 84 is connected to the second source/drain contact portion.
  • the orthographic projections of the base substrate at least partially overlap, and the second electrode 84 is electrically connected to the second source/drain contact portion through the via hole.
  • the exemplary embodiment also provides a display panel including the above-mentioned array substrate.
  • the display panel has the same technical features and working principles as the above-mentioned array substrate, which will not be repeated here.
  • This exemplary embodiment also provides a display device including the above-mentioned array substrate.
  • the display device may be a display device such as a mobile phone, a TV, a tablet computer, etc.

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Abstract

一种阵列基板，包括：衬底基板（401）、多条数据线（11、12、13）、多个像素电极。多条数据线（11、12、13）包括相邻的第一数据线（11、12、13）和第二数据线（11、12、13）；多个像素电极括至少一个桥接像素电极（21），桥接像素电极（21）在衬底基板（401）的正投影位于第一数据线（11）和第二数据线（12）在衬底基板（401）的正投影之间；其中，桥接像素电极（21）靠近第一数据线（11）的一侧设置有第一缺口（211），桥接像素电极（21）靠近第二数据线（12）的一侧设置有第二缺口（212）。阵列基板的桥接像素电极（21）与两侧数据线具有相近的侧向场电容，从而减弱了桥接像素电极（21）电压串扰的问题，改善了显示效果。还公开包括阵列面板的显示装置。

Description

阵列基板、显示装置
相关申请的交叉引用
本申请要求于2020年03月18日递交的、名称为《阵列基板、显示装置》的中国专利申请第202010191556.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示装置。
背景技术
随着显示技术的不断发展，LCD显示已经占据了显示行业的主导地位。而采用ADS(Advanced Super Dimension Switch，高级超维场转换技术)结构的产品因具有宽视角、响应速度快和对比度高等优点成为了主流的显示模式。相关技术中，ADS结构的显示面板需要在部分像素电极上设置缺口，然而，该缺口会影响显示面板的显示效果。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种阵列基板，该阵列基板包括：衬底基板、多条数据线、多个像素电极。多条数据线包括相邻的第一数据线和第二数据线；多个像素电极包括至少一个桥接像素电极，所述桥接像素电极在所述衬底基板的正投影位于所述第一数据线和第二数据线在所述衬底基板的正投影之间；其中，所述桥接像素电极靠近所述第一数据线的一侧设置有第一缺口，所述桥接像素电极靠近所述第二数据线的一侧设置有第二缺口。
本公开的一种示例性实施例中，所述桥接像素电极为多个，多个所述桥接像素电极包括位于相邻行的第一桥接像素电极和第二桥接像素电极，所述阵列基板还包括：多个公共子电极、公共连接线、连接电极。所述公共子电极与所述像素电极一一对应设置，相对应的所述公共子电极与所述像素电极在阵列基板的正投影至少部分重合；公共连接线用于电连接位于同一行的所述公共子电极；连接电极包括相连接的第一连接块和第二连接块，所述第一连接块在所述衬底基板的正投影位于所述第一桥接像素电极第一缺口在所述衬底基板的正投影范围内，所述第二连接块在所述衬底基板的正投影位于所述第二桥接像素电极第一缺口在所述衬底基板的正投影范围内。
本公开的一种示例性实施例中，所述第一连接块通过过孔和与所述第一桥接像素电极 对应的公共子电极电连接，所述第二连接块通过过孔和一公共连接线电连接，该公共连接线电连接与所述第二桥接像素电极对应的公共子电极。
本公开的一种示例性实施例中，所述第一连接块通过过孔和与所述第一桥接像素电极对应的公共子电极电连接，所述第二连接块通过过孔和与所述第二桥接像素电极对应的公共子电极电连接。
本公开的一种示例性实施例中，所述阵列基板还包括沿第二方向延伸的数据线，所述公共连接线包括电连接的引线部、跨接部。引线部沿第一方向延伸；所述跨接部在所述衬底基板的正投影位于所述第二桥接像素电极的第一缺口在所述衬底基板的正投影范围内，且所述跨接部的在第二方向的宽度大于所述引线部在第二方向的宽度，所述第二连接块通过所述跨接部与所述公共连接线电连接。
本公开的一种示例性实施例中，所述阵列基板还包括沿第一方向延伸的栅线，所述所述第一桥接像素电极和所述第二桥接像素电极分别位于一所述栅线的两侧，所述第一桥接像素电极和所述第二桥接像素电极的第一缺口均靠近该栅线设置。
本公开的一种示例性实施例中，所述第一桥接像素电极和所述第二桥接像素电极位于同一列；所述阵列基板还包括栅线，所述栅线在所述衬底基板的正投影位于相邻行的所述公共子电极在所述衬底基板的正投影之间，所述栅线包括电连接的走线部、栅极部；栅极部在衬底基板的正投影位于相邻数据线在衬底基板的正投影之间，且所述栅极部的宽度大于所述走线部的宽度。
本公开的一种示例性实施例中，所述阵列基板还包括薄膜晶体管，所述公共连接线与所述薄膜晶体管的栅极层同层设置；所述公共子电极设置于所述薄膜晶体管栅极层面向所述衬底基板的一侧；所述像素电极设置于所述薄膜晶体管源漏层背离所述衬底基板的一侧；所述阵列基板包括用于形成多种颜色子像素单元的像素电极，至少对应一种颜色的像素电极均为所述桥接像素电极。
本公开的一种示例性实施例中，同一列像素电极形成同一颜色的子像素单元，与第一颜色对应的像素电极设置为桥接像素电极，第一公共子电极与桥接像素电极对应设置；其中，位于同一行且相邻列的第一公共子电极分别通过所述连接电极与上一行公共子电极、下一行公共子电极连接。
根据本公开的一个方面，提供一种显示装置，该显示装置包括上述的阵列基板。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中一种阵列基板的结构示意图；
图2为本公开阵列基板一种示例性实施例的结构示意图；
图3为本公开阵列基板另一种示例性实施例的结构示意图；
图4为图3中虚线6处的剖视图；
图5为本公开阵列基板一种示例性实施例的结构示意图；
图6为图5的局部放大图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
用语“一个”、“一”、“该”和“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
如图1所示，为相关技术中一种阵列基板的结构示意图。该阵列基板包括多个阵列分 布的像素电极(如图1中141、142)和公共子电极(如图1中111、112)，像素电极和公共子电极一一相对设置，相对应的像素电极和公共子电极在阵列基板上的正投影至少部分重合。位于同一行的公共子电极通过一公共连接线电连接，如图1所示，公共子电极111所在行的所有公共子电极通过公共连接线121电连接，公共子电极112所在行的所有公共子电极通过公共连接线122电连接。其中，位于相邻行的公共子电极111和112通过连接电极15电连接，连接电极15位于像素电极层，一端通过过孔与公共子电极111电连接，另一端通过过孔与公共连接线122电连接，从而连接相邻行的公共子电极。如图1所示，由于需要设置连接电极15，像素电极141的左下方和像素电极142的左上方需要设置相应的缺口，连接电极15可以在该缺口位置处通过过孔与公共子电极电连接。设置有缺口的像素电极可以称为桥接像素电极，桥接像素电极与左右两侧数据线161、162具有不同的侧向场电容，从而导致数据线上电压变化时，桥接像素电极存在电压串扰(V-crosstalk)、出现显示横纹等问题。
基于此，本示例性实施例提供一种阵列基板，如图2所示，为本公开阵列基板一种示例性实施例的结构示意图。该阵列基板包括：衬底基板401、多条数据线11、12、13、多个像素电极21、22、23、24。多条数据线沿第二方向X延伸，且包括相邻的第一数据线11和第二数据线12；多个像素电极包括桥接像素电极21，所述桥接像素电极21在所述衬底基板401的正投影位于所述第一数据线11和第二数据线12在所述衬底基板的正投影之间；其中，所述桥接像素电极21靠近所述第一数据线11的一侧设置有第一缺口211，所述桥接像素电极21靠近所述第二数据线12的一侧设置有第二缺口212。
该阵列基板在桥接像素电极的两侧均设置缺口，其中，第一缺口可以用于设置连接电极，第一缺口靠近第一数据线11设置，第二缺口靠近第二数据线12设置，从而使得桥接像素电极与两侧数据线具有相近的侧向场电容，进而减弱了桥接像素电极电压串扰(V-crosstalk)的问题，改善了显示效果。
其中，第一缺口和第二缺口的面积可以相等或相近。第二缺口可以设置于桥接像素电极靠近第二数据线12的任意位置，如图2所示，第二缺口可以设置于桥接像素电极的右上方，应该理解的是，第二缺口还可以设置于桥接像素电极的右下方等位置，第二缺口还可以为多个。
本示例性实施例中，如图3所示，为本公开阵列基板另一种示例性实施例的结构示意图。所述桥接像素电极可以为多个，多个所述桥接像素电极包括位于相邻行的第一桥接像素电极21和第二桥接像素电极22，所述阵列基板还可以包括：多个公共子电极(图3示例性的给出了公共子电极31、32)、连接电极4。所述公共子电极与所述像素电极一一对应设置，相对应的所述公共子电极与所述像素电极在衬底基板的正投影至少部分重合，例 如，公共子电极31和第一桥接像素电极21对应设置，公共子电极32和第二桥接像素电极22对应设置，且位于同一行的所述公共子电极通过公共连接线电连接，例如，公共子电极31所在行的公共子电极通过公共连接线51电连接，公共子电极32所在行的公共子电极通过公共连接线52电连接。示例性的，公共连接线可以直接形成于公共子电极背离衬底基板的一侧，公共连接线直接和公共子电极搭接，从而将位于同一行的公共子电极电连接；或者在其他实施例中，公共连接线和公共子电极之间可以设置绝缘层，二者通过贯穿绝缘层的过孔电连接。连接电极4包括相连接的第一连接块41和第二连接块42，所述第一连接块41在所述衬底基板401的正投影位于所述第一桥接像素电极21的第一缺口在所述衬底基板的正投影范围内，所述第二连接块42在所述衬底基板的正投影位于所述第二桥接像素电极22的第一缺口在所述衬底基板的正投影范围内。其中，连接电极4可以与所述像素电极同层，即通过同一构图工艺形成，且材料相同，但不一定位于相同平面或相同高度。应该理解的是，在其他示例性实施例中，连接电极还可以位于其他导电层。
本示例性实施例中，如图3、4所示，图4为图3中虚线6处的剖视图。所述阵列基板可以包括：公共子电极31、32、公共连接线51、52、数据线11、第一绝缘层402、第二绝缘层403、连接电极4，公共子电极31、32设置于衬底基板401的一侧，公共连接线51、52设置于公共子电极31、32背离衬底基板401的一侧，第一绝缘层402位于公共连接线51、52背离衬底基板的一侧，数据线11设置于第一绝缘层402背离衬底基板的一侧，第二绝缘层403设置于数据线11背离衬底基板的一侧，连接电极4设置于第二绝缘层403背离衬底基板的一侧。该阵列基板可以包括薄膜晶体管，所述公共连接线51、52可以与所述薄膜晶体管的栅极同层设置，即通过一次构图工艺形成；数据线11可以与薄膜晶体管的源漏极同层设置，即通过一次构图工艺形成。所述第一连接块41可以通过过孔和与所述第一桥接像素电极21对应的公共子电极31电连接，所述第二连接块42可以通过过孔和一公共连接线52电连接，该公共连接线52电连接与所述第二桥接像素电极42对应的公共子电极32。其中，像素电极层和公共电极层可以由氧化铟锡形成，氧化铟锡具有一定的透明度可以提高显示面板的出光率。栅极层可以由金属或合金形成，例如，栅极层可以由铜、铝、银等金属或其合金形成。由于金属的导电率一般大于氧化铟锡的导电率，通过公共连接线52连接第二连接块42和公共子电极32可以减小第二连接块42和公共子电极32之间的电阻，从而提高各个公共子电极上电压的均一性。
在其他示例性实施例中，所述第一连接块还可以通过过孔和与所述第一桥接像素电极对应的公共子电极电连接，所述第二连接块还可以直接通过过孔和与所述第二桥接像素电极对应的公共子电极电连接。这些都属于本公开的保护范围。
本示例性实施例中，如图3所示，所述公共连接线52可以包括电连接的：引线部521 和跨接部522。引线部521可以沿第一方向Y延伸，所述跨接部522在衬底基板的正投影位于所述第二桥接像素电极22的第一缺口范围内，且所述跨接部522在第二方向X的宽度大于所述引线部521在第二方向X的宽度，所述第二连接块42通过所述跨接部522与所述公共连接线52电连接。其中，设置较小宽度的引线部521可以减小引线部521和数据线之间的寄生电容。
本示例性实施例中，如图3所示，所述第一桥接像素电极21和所述第二桥接像素电极22可以位于同一列。所述第一桥接像素电极21和所述第二桥接像素电极22的第一缺口均靠近位于其之间的栅线设置。例如，如图3所示，第一桥接像素电极21的第一缺口设置于第一桥接像素电极21的左下方，第二桥接像素电极22的第一缺口设置于第二桥接像素电极22的左上方，连接电极可以在该缺口位置处通过过孔与公共子电极电连接。该设置可以减小连接电极的延伸长度，从而减小延伸电极和其他结构层之间产生的寄生电容。应该理解的是，在其他示例性实施例中，所述第一桥接像素电极21和所述第二桥接像素电极22可以位于不同列。所述第一桥接像素电极21的第一缺口和所述第二桥接像素电极22的第一缺口可以设置于其他位置。
本示例性实施例中，连接电极可以仅电连接部分公共子电极即可实现在列方向上电连接所有公共子电极。相应的，像素电极中仅需要将部分像素电极设置为上述的桥接像素电极(即设置有缺口的像素电极)，其他像素电极为正常像素电极(即没有设置缺口的像素电极)。本示例性实施例中，所述阵列基板可以包括对应多种颜色的像素电极，至少一种颜色的像素电极均为所述桥接像素电极。由于桥接像素电极与其他正常像素电极具有不同的面积，该设置将同一颜色子像素单元的像素电极均设置为桥接像素电极，可以使得同一颜色子像素单元的像素电极具有相同的面积，从而避免了同一颜色子像素单元发光不均匀。
本示例性实施例中，如图5所示，为本公开阵列基板一种示例性实施例的结构示意图，其中，501为栅线，502为数据线，栅线沿第一方向Y延伸，数据线沿第二方向X延伸。该阵列基板可以包括三种颜色的子像素单元，第n+1列像素电极位于第一颜色子像素单元，第n+2列像素电极位于第二颜色子像素单元，第n+3列像素电极位于第三颜色子像素单元。对应第一颜色的像素电极71位于第n+1列，像素电极71与公共子电极72对应设置。其中，像素电极71均为桥接像素电极。位于同一行且相邻列的公共子电极72分别通过所述连接电极73与上一行公共子电极、下一行公共子电极连接。如图5所示，第三行第一列的公共子电极72与第二行第一列的公共子电极72电连接，第三行第四列的公共子电极72与第四行第四列的公共子电极72电连接。本示例性实施例中，桥接像素电极可以位于同一种颜色的子像素单元，从而避免了同一颜色子像素单元发光不均匀。此外，由图5可以看出，连接电极沿第一方向Y和第二方向X间隔分布，第一方向Y可以行方向，第二方 向X可以为列方向，在行方向上，相邻的连接电极位于不同列，在列方向上，相邻连接电极位于不同行，该设置可以避免由于公共子电极上的电荷沿同一列方向延伸，从而造成的公共子电极上电压不均匀的问题。
本示例性实施例中，如图5、6所示，图6为图5的局部放大图。所述阵列基板还包括栅线501，所述栅线501在衬底基板的正投影位于相邻行的所述公共子电极在衬底基板的正投影之间，所述栅线501包括走线部81、栅极部82，栅极部82在衬底基板的正投影位于相邻数据线502在衬底基板的正投影之间，且所述栅极部82的在数据线延伸方向的宽度大于所述走线部81在数据线在延伸方向的宽度。栅极部82可以形成控制像素开关的薄膜晶体管的栅极，如图6所示，该薄膜晶体管还包括有源层83、第一极85、第二极84，有源层83位于栅极部82背离所述衬底基板的一侧，且有源层83在衬底基板的正投影位于栅极部82在衬底基板的正投影上。有源层83包括沟道区、第一源漏接触部以及第二源漏接触部，薄膜晶体管的第一极85连接数据线502，且第一极85与第一源漏接触部在衬底基板的正投影至少部分重合，第一极85通过过孔与第一源漏接触部电连接；薄膜晶体管的第二极84电连接像素电极，且第二极84与第二源漏接触部在衬底基板的正投影至少部分重合，第二极84通过过孔与第二源漏接触部电连接。设置较小宽度的走线部81可以减小走线部81和数据线502之间的寄生电容。
本示例性实施例还提供一种显示面板，该显示面板包括上述的阵列基板。该显示面板与上述的阵列基板具有相同的技术特征和工作原理，此处不再赘述。
本示例性实施例还提供一种显示装置，该显示装置包括上述的阵列基板。该显示装置可以为手机、电视、平板电脑等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (10)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    多条数据线，包括相邻的第一数据线和第二数据线；
    多个像素电极，包括至少一个桥接像素电极，所述桥接像素电极在所述衬底基板的正投影位于所述第一数据线和第二数据线在所述衬底基板的正投影之间；
    其中，所述桥接像素电极靠近所述第一数据线的一侧设置有第一缺口，所述桥接像素电极靠近所述第二数据线的一侧设置有第二缺口。
  2. 根据权利要求1所述的阵列基板，其中，所述桥接像素电极为多个，多个所述桥接像素电极包括位于相邻行的第一桥接像素电极和第二桥接像素电极，所述阵列基板还包括：
    多个公共子电极，所述公共子电极与所述像素电极一一对应设置，相对应的所述公共子电极与所述像素电极在阵列基板的正投影至少部分重合；
    公共连接线，用于电连接所述公共子电极；
    连接电极，包括相连接的第一连接块和第二连接块，所述第一连接块在所述衬底基板的正投影位于所述第一桥接像素电极第一缺口在所述衬底基板的正投影范围内，所述第二连接块在所述衬底基板的正投影位于所述第二桥接像素电极第一缺口在所述衬底基板的正投影范围内。
  3. 根据权利要求2所述的阵列基板，其中，
    所述第一连接块通过过孔和与所述第一桥接像素电极对应的公共子电极电连接，所述第二连接块通过过孔和一公共连接线电连接，该公共连接线电连接与所述第二桥接像素电极对应的公共子电极。
  4. 根据权利要求2所述的阵列基板，其中，所述第一连接块通过过孔和与所述第一桥接像素电极对应的公共子电极电连接，所述第二连接块通过过孔和与所述第二桥接像素电极对应的公共子电极电连接。
  5. 根据权利要求3所述的阵列基板，其中，所述阵列基板还包括沿第二方向延伸的数据线，所述公共连接线包括电连接的：
    引线部，沿第一方向延伸，所述第一方向与第二方向不同；
    跨接部，所述跨接部在所述衬底基板的正投影位于所述第二桥接像素电极的第一缺口在所述衬底基板的正投影范围内，且所述跨接部的在第二方向的宽度大于所述引线部在第二方向的宽度，所述第二连接块通过所述跨接部与所述公共连接线电连接。
  6. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括沿第一方向延伸的栅线，所述第一桥接像素电极和所述第二桥接像素电极分别位于一所述栅线的两侧，所述第一桥接像素电极和所述第二桥接像素电极的第一缺口均靠近该栅线设置。
  7. 根据权利要求2所述的阵列基板，其中，所述第一桥接像素电极和所述第二桥接像素电极位于同一列；
    所述阵列基板还包括沿第一方向延伸的栅线和沿第二方向延伸的数据线，所述第一方向与第二方向不同；
    所述栅线在所述衬底基板的正投影位于相邻行的所述公共子电极在所述衬底基板的正投影之间，所述栅线包括电连接的：
    走线部；
    栅极部，在所述衬底基板的正投影位于相邻数据线在所述衬底基板的正投影之间，且所述栅极部在所述第二方向上的宽度大于所述走线部在所述第二方向上的宽度。
  8. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括，薄膜晶体管，所述公共连接线与所述薄膜晶体管的栅极同层设置；
    所述公共子电极设置于所述薄膜晶体管栅极面向所述衬底基板的一侧；
    所述像素电极设置于所述薄膜晶体管源漏极背离所述衬底基板的一侧；
    所述阵列基板包括用于形成多种颜色子像素单元的像素电极，至少对应一种颜色的像素电极均为所述桥接像素电极。
  9. 根据权利要求8所述的阵列基板，其中，同一列像素电极形成同一颜色的子像素单元，与第一颜色对应的像素电极设置为桥接像素电极，第一公共子电极与桥接像素电极对应设置；
    其中，位于同一行且相邻列的第一公共子电极分别通过所述连接电极与上一行公共子电极、下一行公共子电极连接。
  10. 一种显示装置，其中，包括权利要求1-9任一项所述的阵列基板。
PCT/CN2020/140831 2020-03-18 2020-12-29 阵列基板、显示装置 WO2021184906A1 (zh)

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