WO2020207466A1 - 阵列基板及其制造方法、显示面板及显示装置 - Google Patents

阵列基板及其制造方法、显示面板及显示装置 Download PDF

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Publication number
WO2020207466A1
WO2020207466A1 PCT/CN2020/084177 CN2020084177W WO2020207466A1 WO 2020207466 A1 WO2020207466 A1 WO 2020207466A1 CN 2020084177 W CN2020084177 W CN 2020084177W WO 2020207466 A1 WO2020207466 A1 WO 2020207466A1
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Prior art keywords
array substrate
layer
shielding layer
emitting device
pixel
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PCT/CN2020/084177
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English (en)
French (fr)
Inventor
王丽
刘利宾
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京东方科技集团股份有限公司
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Priority to US17/044,182 priority Critical patent/US11581383B2/en
Publication of WO2020207466A1 publication Critical patent/WO2020207466A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, in particular to an array substrate, a display panel and a display device.
  • OLED display panels have the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed, and have begun to be applied to display fields such as mobile phones, tablet computers, and digital cameras.
  • an OLED display panel uses a pixel driving circuit to drive the OLED to emit light.
  • An embodiment of the present disclosure provides an array substrate, including: a substrate, and a plurality of pixel units on the substrate; each pixel unit includes at least a driving transistor and a light emitting device; wherein, the array substrate further includes: a shield The layer is located between the layer where the gate of the driving transistor of each pixel unit is located and the layer where the first electrode of each light-emitting device is located.
  • the projection of the gate of at least a part of the driving transistor on the substrate and the projection of the first electrode of the corresponding light-emitting device on the substrate at least partially overlap; and the shielding layer is at least disposed on the substrate. Between the overlap area between the gate of the driving transistor and the first electrode of the light emitting device.
  • the shielding layer includes a planar structure, and the orthographic projection of the shielding layer on the substrate covers the orthographic projection of the gate of each driving transistor and the first electrode of each light-emitting device on the substrate.
  • the shielding layer includes a plurality of shielding electrodes; wherein, the plurality of shielding electrodes are in one-to-one correspondence with the gates of the driving transistors of each pixel unit.
  • the shielding layer includes a plurality of shielding electrodes; wherein, the plurality of shielding electrodes are in one-to-one correspondence with the first electrodes of the light-emitting devices of each pixel unit.
  • the shield electrode includes a conductive material
  • the array substrate further includes a power supply voltage terminal; wherein the shield electrode is connected to the power supply voltage terminal.
  • the shielding layer is located on the side of the layer where the source and drain of the driving transistor are away from the substrate.
  • the conductive material includes metal.
  • the array substrate further includes a drive control circuit on the substrate; wherein, each element in the drive control circuit is located in the area where the pixel unit is located.
  • An embodiment of the present disclosure provides a display panel including the above-mentioned array substrate.
  • An embodiment of the present disclosure provides a display device including the above-mentioned display panel.
  • An embodiment of the present disclosure provides a method for manufacturing the above-mentioned array substrate.
  • the manufacturing method includes: providing a substrate; forming a plurality of pixel units on the substrate; A shielding layer is formed between the layers where the first pole of each light-emitting device is located.
  • FIG. 1 is a schematic structural diagram of a pixel circuit in the related art
  • FIG. 2 is a schematic diagram of a related art organic light emitting display panel
  • FIG. 3 is a schematic diagram of a related art organic light emitting display panel
  • FIG. 4 is a schematic diagram of a related art organic light emitting display panel
  • FIG. 5 is a schematic diagram of the structure of a related art drive control circuit
  • FIG. 6 is a schematic structural diagram of an array substrate according to an embodiment of the disclosure.
  • FIG. 7 is a plan view showing the layout design of the shielding layer and the driving transistor in the array substrate of FIG. 6;
  • FIG. 8 is a schematic structural diagram of an array substrate according to an embodiment of the disclosure.
  • FIG. 9 is a plan view showing the layout design of the shielding layer and the driving transistor in the array substrate of FIG. 8;
  • FIG. 10 is a schematic structural diagram of an array substrate according to an embodiment of the disclosure.
  • FIG. 11 is a flowchart of a method of manufacturing an array substrate according to an embodiment of the disclosure.
  • the pixel driving part (usually including a driving transistor, a switching transistor, and a storage capacitor) and a light emitting device (OLED device) in each pixel unit are separately arranged, and the size of the pixel driving part and the light emitting device are also different .
  • the array substrate includes a base; a plurality of gate lines and a plurality of data lines are arranged on the base; a plurality of gate lines and a plurality of data lines are arranged crosswise to define a plurality of pixel units arranged in an array; each pixel unit A pixel circuit is provided in each of them; as shown in Figure 1, a basic pixel circuit structure is provided.
  • the pixel circuit includes: a switching transistor M1, a driving transistor M2, a storage capacitor C1, and a light-emitting device (OLED device) D1;
  • the gate 1 of the switching transistor M1 is connected to the scan line (ie, the gate line), the source is connected to the data line, and the drain is connected to the first end of the storage capacitor C1 and the gate 1 of the driving transistor M2; the source of the driving transistor M2 is connected to storage The second terminal of the capacitor C1 and the power supply voltage terminal VDD, the drain is connected to the first pole (anode 2) of the light emitting device D1, and the second pole (cathode) of the light emitting device D1 is grounded.
  • the driving control circuit is provided in the pixel unit of the array substrate, for example, the organic light emitting display panel shown in FIGS. 2 to 4.
  • the organic light emitting display panel may include: a base substrate 100, a plurality of pixel driving circuits 110 located on one side of the base substrate 100, and a display area AA of the base substrate 100 and connected to each pixel driving circuit 110
  • One-to-one correspondence of top emission type light emitting devices 120 ie, the aforementioned light emitting device D1
  • each top emission type light emitting device 120 is located on the side of the pixel drive circuit 110 away from the base substrate 100
  • each top emission type light emitting device 120 is located The area of is smaller than the area of the corresponding pixel driving circuit 110.
  • each top-emission light-emitting device 120 may include an anode 121, a light-emitting layer 122, and a cathode 123 that are sequentially stacked; wherein, the anode 121 of each top-emission light-emitting device 120 is connected to a corresponding pixel driving circuit through a first connection line 130. 110 electrical connection.
  • gate lines may also be included.
  • the pixel driving circuit is used to drive the top emission type light emitting device 120 to emit light.
  • the driving control circuit may include a gate driving circuit to provide a gate scan signal to the scan control transistor through a gate line in the organic light emitting display panel.
  • the organic light-emitting display panel shown in FIG. 2 can make the area of the area where the top-emission light-emitting device corresponding to each pixel drive circuit is smaller than the area of the area where the corresponding pixel drive circuit is located.
  • the area of the layout space of the top emission type light emitting device can be reduced, so that the number of top emission type light emitting devices per inch can be increased, thereby increasing the PPI of the organic light emitting display panel, which is beneficial to Realize high-resolution organic light-emitting display panels.
  • top-emission light-emitting devices due to the reduced area of the area where the top-emission light-emitting device is located, there may be situations where there is no direct overlap area between the top-emission light-emitting device and the corresponding pixel drive circuit, that is, for example, the rightmost column in FIG.
  • the top emission type light emitting device 120 of the column only has an overlapping area with the pixel driving circuit 110 of the fifth column, which results in a misalignment. Therefore, the anode of each top emission type light-emitting device 120 can be electrically connected to the corresponding pixel driving circuit 110 through the first connection line 130, so as to achieve driving display.
  • the use of top-emission light-emitting devices can also avoid the influence of the pixel driving circuit on light emission.
  • the organic light emitting display panel may further include: a drive control circuit 140 located in the non-display area of the base substrate; and, the area where all the pixel drive circuits 110 are located is on the base substrate 100 and the orthographic projection and drive control circuit 140 The orthographic projection of the base substrate 100 has no overlapping area.
  • the organic light emitting display panel as shown in FIG. 3 may adopt single-side driving or bilateral driving.
  • the driving control circuit may include a light emission control circuit to provide a light emission control signal to the light emission control transistor through a light emission control signal line in the organic light emitting display panel.
  • the organic light emitting display panel may have four sides, so that the shape of the organic light emitting display panel is rectangular, and the display area may be located at one side of the organic light emitting display panel.
  • the display area may also have four sides, and each side of the display area may respectively correspond to a side of the organic light emitting display panel, and the display area and the corresponding sides of the organic light emitting display panel are parallel.
  • the organic light emitting display panel shown in FIG. 4 may include: a base substrate 200, a plurality of pixel driving circuits 210 and a driving control circuit 220 located in the display area AA of the base substrate 200, and the base substrate 200 covering the display area AA.
  • the organic light emitting display panel may further include: a metal shielding layer 270 located between the film layer where the second connection line 240 is located and the film layer where the data line 260 is located; wherein the metal shielding layer 270 is located on the base substrate 200
  • the orthographic projection covers the orthographic projection of the overlapped area of the power trace and the data line 260 with the second connecting line 240 on the base substrate 200.
  • the metal shielding layer 270 is also electrically connected to the power traces through via holes to achieve the function of electric field shielding.
  • the organic light-emitting display panel shown in FIGS. 2 to 4 by arranging the pixel driving circuit and the driving control circuit in the display area of the base substrate, and dividing the shift register in the driving control circuit into multiple sub-units, and These sub-units are arranged in the gap between two adjacent pixel driving circuits, so that the driving control circuit and the pixel driving circuit are not overlapped with each other. And because the top-emission light-emitting device in the display area of the base substrate can cover the pixel drive circuit and the drive control circuit, it is equivalent to reducing the drive of each pixel without changing the area occupied by the original layout space of the top-emission light-emitting device.
  • the area occupied by the layout space of the circuit releases the frame space occupied by the drive control circuit to ensure that all circuits in the display area are covered by the top-emitting light-emitting device.
  • the layout space of the pixel drive circuit separately from the layout space of the top-emission light-emitting device, it can be ensured that if there is enough layout space for the drive control circuit and the pixel drive circuit in the display area, the frame can be omitted.
  • the various elements of the drive control circuit are to be arranged in the pixel unit of the display panel, a certain space needs to be provided for these elements in the pixel unit, which will cause the position of the drive transistor in some pixel units to change, thereby causing The gate of the driving transistor and the anode of the light-emitting device in the adjacent pixel unit spatially overlap, thereby generating a coupling capacitance. Since the gates of the driving transistors in different pixel units may have different overlapping areas with the anodes of the light-emitting devices in the adjacent pixel units, the size of the coupling capacitors generated is also different, resulting in uneven display of the display panel.
  • a driving control circuit in the related art which includes 9 thin film transistors and 1 storage capacitor C1.
  • the output terminal of each drive control circuit is connected to a gate line. Therefore, to install the drive control circuit in the pixel unit, 9 thin film transistors and 1 storage capacitor C1 of each drive control circuit need to be distributed in multiple Pixel unit. At this time, it is necessary to adjust the position of the transistors (switching transistor T1 and driving transistor T2) in the pixel circuit of each row of pixel units, and this will cause some driving transistors T2 to interfere with the light emitting device D1 in the pixel unit adjacent to the pixel unit.
  • the anode 2 overlaps, which creates a coupling capacitance.
  • the overlapping area of the driving transistor T2 and the anode 2 of the light emitting device D1 at different positions may also be different, and therefore, the size of the generated coupling capacitance is also different.
  • the driving currents in different pixel units are affected differently, which may cause uneven display of the display panel.
  • a shielding layer is provided in the array substrate of the embodiment of the present disclosure, and the shielding layer is provided at least between the overlap area between the gate of the driving transistor and the first electrode of the light emitting device.
  • the specific structure of the following array substrate is specifically provided for description.
  • the light-emitting device D1 is an OLED device
  • the first electrode of the light-emitting device D1 is the anode 2 and the second electrode is the cathode.
  • an embodiment of the present disclosure provides an array substrate, which includes a substrate and a plurality of pixel units on the substrate.
  • Each pixel unit includes at least a driving transistor M2 and a light emitting device D1, wherein at least the projections of the gate 1 of the driving transistor M2 and the first electrode of the light emitting device D1 on the substrate at least partially overlap.
  • a shielding layer 3 with a planar structure is provided, and the orthographic projection of the shielding layer 3 on the substrate.
  • the orthographic projection of the gate 1 of each driving transistor M2 and the first electrode of the light emitting device D1 on the substrate is shown in FIG. 7.
  • the shielding layer 3 is used for shielding the coupling capacitance between the gate 1 of the driving transistor M2 and the first electrode of the light emitting device D1 where the orthographic projection on the substrate at least partially overlaps.
  • the driving transistor can be a thin-film transistor or a field-effect transistor or other switching devices with the same characteristics.
  • the thin-film transistors are all described here.
  • the active layer (channel region) of the driving transistor is made of semiconductor materials, such as polysilicon (such as low temperature). Polysilicon or high-temperature polysilicon), amorphous silicon, indium gallium tin oxide (IGZO), etc., while the gate, source, and drain are made of metal materials, such as metal aluminum or aluminum alloy.
  • the shielding layer may include a conductive material
  • the conductive material may include, but is not limited to, titanium, titanium alloy, aluminum, aluminum alloy, copper, copper alloy, or any other suitable composite material, which is not limited in the embodiment of the present disclosure.
  • FIG. 7 is a plan view showing the layout design of the shielding layer and the driving transistor in the array substrate of FIG. 6.
  • the shielding layer is represented by a gray shaded part
  • the driving transistor M2 is represented by a shaded part filled with an inverted S-shaped diagonal line.
  • the shielding layer may be located above the layer where the driving transistor is located and completely cover the driving transistor, that is, the projection of the shielding layer on the substrate may completely overlap the orthographic projection of the gate of the driving transistor on the substrate.
  • the shielding layer 3 is a planar electrode, in order to prevent the anode 2 of the light-emitting device D1 from being electrically connected to the shielding layer 3 when it is connected to the drain of the driving transistor M2,
  • the layer 3 is hollowed out at the position where the anode 2 of the light emitting device D1 is connected to the drain of the driving transistor M2.
  • the shielding layer 3 is provided in the array substrate according to the embodiment of the present disclosure, the shielding layer 3 is provided between the layer where the gate 1 of the driving transistor M2 is located and the layer where the anode 2 of the light-emitting device D1 is located.
  • the shielding layer 3 can shield the difference between the two. The resulting coupling capacitance. Therefore, the problem of uneven display due to the existence of the coupling capacitor can be avoided.
  • the shielding layer 3 can generate a coupling capacitance with the gate 1 of each driving transistor M2 and the first pole of each light emitting device D1. Since the shielding layer 3 has a planar structure, and the orthographic projection on the substrate covers the orthographic projection of the gate 1 of each driving transistor M2 and the first pole of each light-emitting device D1 on the substrate, therefore, the shielding layer 3 and each The overlap area of the gate 1 of the driving transistor M2 in each pixel unit is the same, and the overlap area with the first pole of each light-emitting device D1 is also the same. Therefore, for each pixel unit, the generated coupling capacitance is the same, so the display uniformity of the display panel will not be affected.
  • the source of the driving transistor M2 in each pixel unit is connected to the power supply voltage terminal VDD (not shown).
  • the shield electrode includes a conductive material, and the shield electrode 31 is connected to the power supply voltage terminal VDD in the layer where the source and drain of the driving transistor M2 are located through a through hole, so that the power supply voltage signal provided by the power supply voltage terminal VDD can be used as a shielding signal of the shield electrode 31. Therefore, the shielding layer 3 and the gate 1 of the driving transistor M2 can generate a coupling capacitor, and the generated coupling capacitor can also be used as the storage capacitor C1 in the pixel unit to improve the performance of the array substrate.
  • the driving transistor M2 may be a top gate type thin film transistor or a bottom gate type thin film transistor.
  • Figure 6 shows a top-gate thin film transistor as an example, where each driving transistor M2 includes an active layer, a gate insulating layer, a gate 1, and an interlayer insulation arranged in sequence along a direction away from the substrate. Layer, source and drain.
  • the shielding layer 3 in the embodiment according to the present disclosure is located on the side of the layer where the source electrode and the drain electrode are located away from the substrate. It should be understood that the materials forming the shielding layer 3 and the source and drain are all conductive materials.
  • the layer where the source and drain are located is connected to the shielding electrode 31
  • An insulating layer is arranged between the layers.
  • the thickness of the insulating layer between them is designed to be greater than 1 ⁇ m, preferably 1 to 3 ⁇ m, thereby Maintain the coupling capacitance generated between the two layers at a low level.
  • the material forming the shielding layer 3 in the embodiment according to the present disclosure includes a metal material.
  • the shielding electrode 31 in the embodiment of the present disclosure may also be formed of other conductive materials, which will not be illustrated here.
  • an array substrate is provided.
  • the structure of the array substrate is substantially the same as the structure of the array substrate described above.
  • the difference between the two lies in the structure of the shielding layer 3.
  • the shielding layer 3 in this embodiment includes a plurality of shielding electrodes 31, and each shielding electrode 31 is arranged in a one-to-one correspondence with the gate 1 of the driving transistor M2 in each pixel unit, and The orthographic projection of each shield electrode 31 on the substrate overlaps the orthographic projection of the gate 1 of the corresponding driving transistor M2 on the substrate.
  • FIG. 9 is a plan view showing the layout design of the shielding layer and the driving transistor in the array substrate of FIG. 8.
  • the shielding layer includes a plurality of shielding electrodes represented by gray shaded parts, and the driving transistor M2 is represented by an inverted S-shaped hatched portion filled with diagonal lines.
  • the shielding layer where the shielding electrode is located may be located above the layer where the driving transistor is located, and respectively cover all the corresponding driving transistors.
  • each shield electrode 31 in the shield layer 3 is arranged in a one-to-one correspondence with the gate 1 of the driving transistor M2, each shield electrode 31 can be connected to the corresponding driving transistor M2.
  • a coupling capacitance shield is generated between the gate 1 and the anode 2 of the light emitting device D1 in the pixel unit adjacent to the driving transistor M2.
  • each shield electrode 31 is only provided corresponding to the gate 1 of the driving transistor M2.
  • an embodiment of the present disclosure provides an array substrate.
  • the structure of the array substrate is substantially the same as that of the array substrate shown in FIG. 6 or FIG. 8.
  • the difference lies in the structure of the shielding layer 3.
  • the shielding layer 3 in this embodiment includes a plurality of shielding electrodes 31, each shielding electrode 31 is arranged in a one-to-one correspondence with the anode 2 of the light emitting device D1 in each pixel unit, and each shielding electrode 31 is on the substrate.
  • the orthographic projection of is partially overlapped with the orthographic projection of the gate 1 of the corresponding driving transistor M2 on the substrate.
  • each shielding electrode 31 in the shielding layer 3 and the anode 2 of the light emitting device D1 are arranged in a one-to-one correspondence, each shielding electrode 31 can be driven in a corresponding manner.
  • a coupling capacitance shield is generated between the gate 1 of the transistor M2 and the anode 2 of the light-emitting device D1 in the pixel unit adjacent to the driving transistor M2.
  • each shielding electrode 31 is only provided corresponding to the anode 2 of the light-emitting device D1.
  • the shielding layer 3 and other conductive structures located on the side of the shielding layer 3 close to the substrate for example, source, drain, data
  • a coupling capacitance is generated between the line and the gate line, so as to ensure the ability to write data voltage on the data line and the driving ability of the drive control circuit.
  • a shielding layer may be provided between the overlapping area between the gate of the driving transistor and the first electrode (anode) of the light emitting device, and the shape and size of the shielding layer are not particularly limited.
  • a flowchart of a method of manufacturing an array substrate is provided according to an embodiment of the present disclosure.
  • the structure of the array substrate according to the embodiment of the present disclosure may be the same as the structure of the array substrate with reference to FIGS. 3 to 5, and will not be repeated here.
  • a substrate is provided in step 601.
  • a plurality of pixel units are formed on the substrate.
  • a shielding layer is formed between the layer where the gate of the driving transistor of each pixel unit is located and the layer where the first electrode of each light-emitting device is located.
  • Embodiments of the present disclosure provide a display panel and a display device, wherein the display panel includes any one of the array substrates described above, so the display effect of the display panel is uniform.
  • the display device in the embodiment according to the present disclosure includes the display panel as described above.
  • the display device can be: electronic paper, OLED panel, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator and other products or components with display function.

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Abstract

一种阵列基板及其制造方法、显示面板及显示装置。阵列基板包括：基底，和位于基底上的多个像素单元；每个像素单元至少包括驱动晶体管（M2）和发光器件（D1）；其中，所述阵列基板还包括：屏蔽层（3），其位于每个像素单元的驱动晶体管（M2）的栅极（1）所在层与每个发光器件（D1）的第一极所在层之间。

Description

阵列基板及其制造方法、显示面板及显示装置
相关公开的交叉引用
本公开要求于2019年4月10日提交的中国专利公开No.201910285721.4的优先权，所公开的内容以引用的方式合并于此。
技术领域
本公开涉及显示技术领域，具体涉及阵列基板、显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示面板具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点，已经开始应用于手机、平板电脑、数码相机等显示领域。一般OLED显示面板采用像素驱动电路驱动OLED发光显示。
发明内容
本公开的一个实施例提供了一种阵列基板，包括：基底，和位于基底上的多个像素单元；每个像素单元至少包括驱动晶体管和发光器件；；其中，所述阵列基板还包括：屏蔽层，其位于每个像素单元的驱动晶体管的栅极所在层与每个发光器件的第一极所在层之间。
在一些实施方式中，至少一部分驱动晶体管的栅极在所述基底上的投影和对应的发光器件的第一极在所述基底上的投影至少部分地重叠；并且所述屏蔽层至少设置在所述驱动晶体管的栅极和所述发光器件的第一极之间的重叠区域之间。
在一些实施方式中，屏蔽层包括面状结构，且屏蔽层在基底上的正投影覆盖每个驱动晶体管的栅极和每个发光器件的第一极在基底上的正投影。
在一些实施方式中，屏蔽层包括多个屏蔽电极；其中，多个屏蔽电极与各个像素单元的驱动晶体管的栅极一一对应。
在一些实施方式中，屏蔽层包括多个屏蔽电极；其中，多个屏蔽电极与各个像素单元的发光器件的第一极一一对应。
在一些实施方式中，屏蔽电极包括导电材料，并且阵列基板还包括电源电压端；其中，屏蔽电极与电源电压端连接。
在一些实施方式中，屏蔽层位于驱动晶体管的源极和漏极所在层的远离基底的一侧。
在一些实施方式中，导电材料包括金属。
在一些实施方式中，阵列基板还包括位于基底上的驱动控制电路；其中，驱动控制电路中的各个元件位于像素单元所在区域中。
本公开的一个实施例提供了一种显示面板，包括上述的阵列基板。
本公开的一个实施例提供了一种显示装置，包括上述的显示面板。
本公开的一个实施例提供了一种上述的阵列基板的制造方法，所述制造方法包括：提供基底；在基底上形成多个像素单元；在每个像素单元的驱动晶体管的栅极所在层与每个发光器件的第一极所在层之间形成屏蔽层。
附图说明
图1为相关技术的像素电路的结构示意图；
图2为相关技术的有机发光显示面板的示意图；
图3为相关技术的有机发光显示面板的示意图；
图4为相关技术的有机发光显示面板的示意图；
图5为相关技术的驱动控制电路的结构示意图；
图6为本公开的一个实施例的阵列基板的结构示意图；
图7为示出图6的阵列基板中的屏蔽层与驱动晶体管的布局设计的俯视图；
图8为本公开的一个实施例的阵列基板的结构示意图；
图9为示出图8的阵列基板中的屏蔽层与驱动晶体管的布局设计的俯视图；
图10为本公开的一个实施例的阵列基板的结构示意图；
图11为本公开的一个实施例的制造阵列基板的方法的流程图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
在相关技术的显示面板中，每个像素单元中的像素驱动部分(通常包括驱动晶体管、开关晶体管及存储电容)和发光器件(OLED器件)分开设置，且像素驱动部分和发光器件的尺寸也不同。
为了更清楚本公开实施例所提供的技术方案，对阵列基板上的基本结构进行简述。通常，阵列基板包括基底；在基底上设置有多条栅线和多条数据线；多条栅线和多条数据线交叉设置，限定出呈阵列排布的多个像素单元；每个像素单元中均设置有像素电路；如图1所示，提供一种最基本的像素电路结构，该像素电路包括：开关晶体管M1、驱动晶体管M2、存储电容C1、发光器件(OLED器件)D1；其中，开关晶体管M1的栅极1连接扫描线(即，栅线)，源极连接数据线，漏极连接存储电容C1的第一端和驱动晶体管M2的栅极1；驱动晶体管M2的源极连接存储电容C1的第二端和电源电压端VDD，漏极连接发光器件D1的第一极(阳极2)，发光器件D1的第二极(阴极)接地。
为了实现显示面板的窄边框化，相关技术中将驱动控制电路设置在阵列基板的像素单元，例如，如图2至图4所示的有机发光显示面板。如图2所示，有机发光显示面板可以包括：衬底基板100，位于衬底基板100一侧的多个像素驱动电路110，以及位于衬底基板100的显示区AA且与各像素驱动电路110一一对应的顶发射型发光器件120(即，前述的发光器件D1)；各顶发射型发光器件120位于像素驱动电路110背离衬底基板100一侧；每一个顶发射型发光器件120所在区域的面积小于对应的像素驱动电路110所在区域的面积。并且，各顶发射型发光器件120可以包括：依次层叠设置的阳极121，发光层122和阴极123；其中，各顶发射型发光器件120的阳极121通过 第一连接线130与对应的像素驱动电路110电连接。在有机发光显示面板为中，还可以包括栅线。其中，像素驱动电路用于驱动顶发射型发光器件120发光。驱动控制电路可以包括栅极驱动电路，以通过有机发光显示面板中的栅线向扫描控制晶体管提供栅极扫描信号。
如图2所示的有机发光显示面板，通过使与各像素驱动电路一一对应的顶发射型发光器件所在区域的面积小于对应的像素驱动电路所在区域的面积，可以在不改变像素驱动电路的原布局空间的面积的情况下，降低顶发射型发光器件的布局空间的面积，从而可以使每英寸中所拥有的顶发射型发光器件的数目提高，进而提高有机发光显示面板的PPI，有利于实现高分辨率的有机发光显示面板。并且，由于顶发射型发光器件所在区域的面积降低，可能会存在顶发射型发光器件与对应的像素驱动电路不存在直接的交叠区域的情况，即例如图2中最右列，即第六列的顶发射型发光器件120仅与第五列的像素驱动电路110具有交叠区域，而形成错位的情况。因此，可以使各顶发射型发光器件120的阳极通过第一连接线130与对应的像素驱动电路110电连接，以实现驱动显示。并且由于采用顶发射型发光器件还可以避免像素驱动电路对发光的影响。
如图3所示，有机发光显示面板还可以包括：位于衬底基板非显示区的驱动控制电路140；并且，全部像素驱动电路110所在区域在衬底基板100的正投影与驱动控制电路140在衬底基板100的正投影无交叠区域。在相关技术中，如图3所示的有机发光显示面板可以采用单边驱动或双边驱动。驱动控制电路可以包括发光控制电路，以通过有机发光显示面板中的发光控制信号线向发光控制晶体管提供发光控制信号。
在如图3所示的有机发光显示面板中，有机发光显示面板可以具有四个侧边，以使有机发光显示面板的形状为矩形，显示区可以位于有机发光显示面板的一个侧边处。在相关技术中，显示区也可以具有四个侧边，并且显示区的每一个侧边可以分别对应有机发光显示面板的一个侧边，且显示区与有机发光显示面板相互对应的侧边平行。
如图4所示的有机发光显示面板可以包括：衬底基板200，位于 衬底基板200显示区AA的多个像素驱动电路210和驱动控制电路220，以及位于衬底基板200显示区AA且覆盖像素驱动电路210和驱动控制电路220的多个顶发射型发光器件230。驱动控制电路220可以包括：级联的多个移位寄存器单元220_m(m＝1、2、3…M；其中M为驱动控制电路包括的移位寄存器单元的总数。图4以M＝4为例)；其中，移位寄存器单元220_m分为多个子单元221，各子单元221位于相邻两个像素驱动电路之间的间隙处；同一移位寄存器单元220_m中的不同子单元221位于的间隙处不同，且同一移位寄存器单元220_m中的各子单元221之间通过第二连接线240电连接。如图4所示，有机发光显示面板还可以包括：位于第二连接线240所在膜层与数据线260所在膜层之间的金属屏蔽层270；其中，金属屏蔽层270在衬底基板200的正投影覆盖电源走线和数据线260分别与第二连接线240的交叠区域在衬底基板200的正投影。并且，在实际应用中，金属屏蔽层270还通过过孔与电源走线电连接，以实现电场屏蔽的功能。
如图2至图4所示的有机发光显示面板，通过将像素驱动电路和驱动控制电路设置于衬底基板的显示区，且将驱动控制电路中的移位寄存器分为多个子单元，并将这些子单元设置于相邻的两个像素驱动电路之间的间隙处，可以使驱动控制电路与像素驱动电路所在区域互不重叠。并且由于在衬底基板显示区的顶发射型发光器件可以覆盖像素驱动电路和驱动控制电路，相当于在不改变顶发射型发光器件的原布局空间所占的面积的情况下，降低各像素驱动电路的布局空间所占的面积，释放驱动控制电路所占的边框空间，以保证在显示区内的所有电路均被顶发射型发光器件所覆盖。这样通过将像素驱动电路的布局空间与顶发射型发光器件的布局空间分开设计，可以保证在显示区中驱动控制电路和像素驱动电路均有足够的布局空间的情况下，可以省去边框处用于设置驱动控制电路的布局空间，从而可以实现超窄边框甚至是无边框设计的有机发光显示面板。
然而，由于要将驱动控制电路的各个元件布置在显示面板的像素单元中，则像素单元中需要给这些元件提供一定的空间，因此会导致一些像素单元中的驱动晶体管的位置发生改变，从而造成驱动晶体 管的栅极与之相邻像素单元中的发光器件的阳极发生空间上的重叠，从而产生耦合电容。由于不同像素单元中的驱动晶体管的栅极与之相邻像素单元中的发光器件的阳极的重叠面积可能不同，故所产生的耦合电容的大小也就不同，从而造成显示面板的显示不均匀。
如图5所示，提供一种相关技术中的驱动控制电路，其包括9个薄膜晶体管和1个存储电容C1。每个驱动控制电路的输出端是连接一条栅线的，因此，要将驱动控制电路设置在像素单元中，需要将每个驱动控制电路的9个薄膜晶体管和1个存储电容C1分布在多个像素单元中。此时，需要调整原本每行像素单元的像素电路中的晶体管(开关晶体管T1和驱动晶体管T2)的位置，而这会造成有些驱动晶体管T2与本像素单元相邻像素单元中的发光器件D1的阳极2存在重叠，从而产生耦合电容。并且，不同位置处的驱动晶体管T2与发光器件D1的阳极2的重叠面积也可能是不同，因此，所产生的耦合电容的大小也不同。从而使得不同像素单元中的驱动电流受到的影响不同，因此会造成显示面板的显示不均匀。
为解决上述技术问题，在本公开实施例的阵列基板中设置屏蔽层，该屏蔽层至少设置在驱动晶体管的栅极和发光器件的第一极之间的重叠区域之间。具体提供以下阵列基板的具体结构进行说明。且在下述实施例中，以发光器件D1为OLED器件，发光器件D1的第一极为阳极2，第二极为阴极为例进行说明。
如图6所示，本公开的一个实施例提供一种阵列基板，包括：基底，和位于基底上的多个像素单元。每个像素单元至少包括驱动晶体管M2和发光器件D1，其中，至少驱动晶体管M2的栅极1和发光器件D1的第一极在基底上的投影至少部分地重叠。特别的是，在每个像素单元的驱动晶体管M2的栅极1所在层与发光器件D1的阳极2所在层之间设置有面状结构的屏蔽层3，且屏蔽层3在基底上的正投影覆盖每个驱动晶体管M2的栅极1和发光器件D1的第一极在基底上的正投影，如图7所示。其中，屏蔽层3用于屏蔽在基底上的正投影至少部分重叠的驱动晶体管M2的栅极1和发光器件D1的第一极之间的耦合电容。
驱动晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，这里均以薄膜晶体管为例进行说明，例如驱动晶体管的有源层(沟道区)采用半导体材料，例如，多晶硅(例如低温多晶硅或高温多晶硅)、非晶硅、氧化铟镓锡(IGZO)等，而栅极、源极、漏极等则采用金属材料，例如金属铝或铝合金。
例如，屏蔽层可以包括导电材料，导电材料可以包括但不限于钛、钛合金、铝、铝合金、铜、铜合金或其他任意适合的复合材料，本公开的实施例对此不作限定。
图7为示出图6的阵列基板中的屏蔽层与驱动晶体管的布局设计的俯视图。在图7的实施例中，屏蔽层由灰色阴影部分表示，驱动晶体管M2由倒置的S形的斜线填充的阴影部分表示。如图7所示，屏蔽层可以位于驱动晶体管所在的层的上方，并将驱动晶体管全部覆盖，即，屏蔽层在基底上的投影可以与驱动晶体管的栅极在基底上的正投影完全重叠。
其中，应当理解的是，虽然根据本公开的实施例的屏蔽层3为面状电极，但是为了避免发光器件D1的阳极2在与驱动晶体管M2的漏极连接时与屏蔽层3电连接，屏蔽层3在发光器件D1的阳极2在与驱动晶体管M2的漏极连接位置处是被挖空的。
由于在根据本公开的实施例的阵列基板中设置屏蔽层3，屏蔽层3设置在驱动晶体管M2的栅极1所在层和发光器件D1的阳极2所在层之间，这样一来，即使某一像素单元的驱动晶体管M2的栅极1和与该像素单元相邻的像素单元中的发光器件D1的阳极2在基底上的正投影存在重叠，此时，屏蔽层3可以屏蔽二者之间所产生的耦合电容。因此，可以避免由于该耦合电容的存在，导致显示不均匀的问题。
在此需要说明的是，在本实施例中，屏蔽层3可以与每个驱动晶体管M2的栅极1和每个发光器件D1的第一极产生耦合电容。由于屏蔽层3为面状结构，且在基底上的正投影覆盖每个驱动晶体管M2的栅极1和每个发光器件D1的第一极在基底上的正投影，因此，屏蔽层3与每个像素单元中的驱动晶体管M2的栅极1的重叠面积相同，与各个发光器件D1的第一极的重叠面积也是相同。因此，对于每个 像素单元，所产生的耦合电容均是相同的，因此不会影响显示面板的显示均匀性。
在根据本公开的实施例中，每个像素单元中的驱动晶体管M2的源极均连接电源电压端VDD(未示出)，在根据本公开的实施例中，屏蔽电极包括导电材料，屏蔽电极31通过通孔与位于驱动晶体管M2的源极和漏极所在层中的电源电压端VDD连接，使得电源电压端VDD提供的电源电压信号可以作为屏蔽电极31的屏蔽信号。因此，屏蔽层3与驱动晶体管M2的栅极1可以产生耦合电容，产生的耦合电容还可以用作像素单元中的存储电容C1，以提高阵列基板的性能。
在根据本公开的实施例中，驱动晶体管M2可以是顶栅型薄膜晶体管，也可以是底栅型薄膜晶体管。图6所示的是以顶栅型薄膜晶体管为例进行说明的，其中，每个驱动晶体管M2均包括沿远离基底方向依次设置的有源层、栅极绝缘层、栅极1、层间绝缘层、源极和漏极。根据本公开的实施例中的屏蔽层3位于源极和漏极所在层的远离基底的一侧。应当理解的是，形成屏蔽层3和源极、漏极的材料均为导电材料，因此，为防止屏蔽层3和源极端与漏极端电连接，在源极和漏极所在层与屏蔽电极31所在层之间设置有绝缘层。为了防止屏蔽电极31和源极与漏极所在层之间的导电材料所产生的耦合电容影响显示效果，因此，将它们之间的绝缘层的厚度设计为大于1μm,优选在1至3μm，从而将在这两层之间产生的耦合电容维持在一个较低水平。
形成根据本公开的实施例中的屏蔽层3的材料包括金属材料。当然，根据本公开的实施例中的屏蔽电极31也可以由其它导电材料形成，在此不再一一举例说明。
如图8和图9所示，根据本公开的实施例提供一种阵列基板，该阵列基板的结构与如上所述的阵列基板的结构大致相同，二者的区别在于屏蔽层3的结构不同。如图8和图9所示，本实施例中的屏蔽层3包括多个屏蔽电极31，每个屏蔽电极31与每个像素单元中的驱动晶体管M2的栅极1一一对应地设置，并且每个屏蔽电极31在基底上的正投影与与其对应的驱动晶体管M2的栅极1在基底上的正投影 重叠。
图9为示出图8的阵列基板中的屏蔽层与驱动晶体管的布局设计的俯视图。在图9的实施例中，屏蔽层包括由灰色阴影部分表示的多个屏蔽电极，驱动晶体管M2由倒置的S形的斜线填充的阴影部分表示。如图9所示，屏蔽电极所在的屏蔽层可以位于驱动晶体管所在的层的上方，并分别将对应的驱动晶体管全部覆盖。
由于在本实施例的阵列基板中，屏蔽层3中的各屏蔽电极31与驱动晶体管M2的栅极1一一对应地设置，因此，每个屏蔽电极31均可以将与其对应的驱动晶体管M2的栅极1和与该驱动晶体管M2相邻像素单元中的发光器件D1的阳极2之间产生耦合电容屏蔽。并且，每个屏蔽电极31仅与驱动晶体管M2的栅极1对应地设置，因此，可以避免屏蔽层3与位于屏蔽层3的靠近基底一侧的其它导电结构(例如，源极、漏极、数据线、栅线)之间产生耦合电容，从而保证数据线上写入数据电压的能力和驱动控制电路的驱动能力。
对于根据本公开的实施例的阵列基板中的其余结构可以与如上文所述的结构相同，在此不再赘述。
如图10所示，本公开的一个实施例提供一种阵列基板，该阵列基板的结构与图6或图8所示的阵列基板的结构大致相同，它们的区别在于屏蔽层3的结构不同，具体的，本实施例中屏蔽层3包括多个屏蔽电极31，每个屏蔽电极31与每个像素单元中的发光器件D1的阳极2一一对应地设置，并且每个屏蔽电极31在基底上的正投影与与其对应的驱动晶体管M2的栅极1在基底上的正投影部分地重叠。
由于在根据本公开的实施例的阵列基板中，屏蔽层3中的屏蔽电极31与发光器件D1的阳极2一一对应地设置，因此，每个屏蔽电极31均可以将在与之对应的驱动晶体管M2的栅极1和与该驱动晶体管M2相邻的像素单元中的发光器件D1的阳极2之间产生耦合电容屏蔽。并且，每个屏蔽电极31仅与发光器件D1的阳极2对应地设置，因此，可以降低屏蔽层3与位于屏蔽层3的靠近基底一侧的其它导电结构(例如，源极、漏极、数据线、栅线)之间产生耦合电容，从而保证数据线上写入数据电压的能力和驱动控制电路的驱动能力。
对于根据本公开的实施例阵列基板中的其余结构可以与如上文所述的结构相同，在此不再赘述。
根据本公开的实施例的屏蔽层与驱动晶体管在俯视图中的重叠关系不限于参照图7和图9所示的实施例。根据本公开的实施例，可以在驱动晶体管的栅极和发光器件的第一极(阳极)之间的重叠区域之间设置屏蔽层，而对屏蔽层的形状和尺寸没有特别的限制。
如图11所示，根据本公开的实施例提供一种制造阵列基板的方法的流程图。根据本公开的实施例的阵列基板的结构可以与参照图3至图5中的阵列基板的结构相同，在此不再赘述。如图11所示，在步骤601中，提供基底。在步骤602中，在基底上形成多个像素单元。在步骤603中，在每个像素单元的驱动晶体管的栅极所在层与每个发光器件的第一极所在层之间形成屏蔽层。
根据本公开的实施例提供一种显示面板和显示装置，其中，显示面板包括如上所述的阵列基板中的任意一种阵列基板，因此该显示面板的显示效果的均匀性好。
根据本公开的实施例中的显示装置包括如上所述的显示面板。
显示装置可以为：电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (26)

  1. 一种阵列基板，包括：基底，和位于所述基底上的多个像素单元；每个像素单元至少包括驱动晶体管和发光器件；其中，所述阵列基板还包括：
    第一屏蔽层，其位于每个像素单元的驱动晶体管的栅极所在层与每个发光器件的第一极所在层之间。
  2. 根据权利要求1所述的阵列基板，其中，所述第一极是发光器件的阳极。
  3. 根据权利要求1所述的阵列基板，其中，至少一部分驱动晶体管的栅极在所述基底上的投影和对应的发光器件的第一极在所述基底上的投影至少部分地重叠；并且所述第一屏蔽层在所述基底上的投影与所述驱动晶体管的栅极和所述发光器件的第一极在所述基底上的投影均至少部分地重叠。
  4. 根据权利要求1所述的阵列基板，其中，所述第一屏蔽层包括面状结构，且所述第一屏蔽层在所述基底上的正投影覆盖每个驱动晶体管的栅极和每个发光器件的第一极在所述基底上的正投影。
  5. 根据权利要求1或3所述的阵列基板，其中，所述第一屏蔽层包括多个屏蔽电极，其中，
    所述多个屏蔽电极与所述多个像素单元的驱动晶体管的栅极一一对应。
  6. 根据权利要求1或3所述的阵列基板，其中，所述第一屏蔽层包括多个屏蔽电极，其中，
    所述多个屏蔽电极与所述多个像素单元的发光器件的第一极一一对应。
  7. 根据权利要求5或6所述的阵列基板，其中，所述屏蔽电极包括导电材料，其中，所述第一屏蔽层通过通孔与位于所述驱动晶体管的源极和漏极所在层中的电源电压端连接。
  8. 根据权利要求1至7中任一项所述的阵列基板，其中，所述第一屏蔽层位于所述驱动晶体管的源极和漏极所在层的远离所述基底的一侧。
  9. 根据权利要求3所述的阵列基板，其中，所述第一屏蔽层包括导电材料，其中，所述第一屏蔽层通过通孔与位于所述驱动晶体管的源极和漏极所在层中的电源电压端连接。
  10. 根据权利要求7或9所述的阵列基板，其中，所述导电材料包括钛、钛合金、铝、铝合金、铜、铜合金。
  11. 根据权利要求1所述的阵列基板，其中，在驱动晶体管的源极和漏极所在层与第一屏蔽层所在层之间设置有绝缘层，所述绝缘层的厚度大于1μm且小于3μm。
  12. 根据权利要求1至11中任一项所述的阵列基板，其中，所述阵列基板包括显示区，所述阵列基板还包括位于所述基底上的驱动控制电路；其中，
    所述驱动控制电路和所述多个像素单元位于所述显示区。
  13. 根据权利要求12所述的阵列基板，还包括位于所述显示区的多个像素驱动电路，其中，所述发光器件位于所述阵列基板显示区且覆盖所述像素驱动电路和所述驱动控制电路；
    所述驱动控制电路包括：级联的多个移位寄存器单元；其中，所述移位寄存器单元分为多个子单元，各所述子单元位于相邻两个像 素驱动电路之间的间隙处；同一所述移位寄存器单元中的不同子单元位于的间隙处不同，所述发光器件的阳极通过第一连接线与对应的像素驱动电路电连接，且同一所述移位寄存器单元中的各子单元之间通过第二连接线电连接。
  14. 根据权利要求13所述的阵列基板，其中，同一所述移位寄存器单元中的各子单元位于同一行中。
  15. 如权利要求14所述的阵列基板，还包括：同层设置的沿列方向延伸的多条电源走线与多条数据线；各所述电源走线与各所述数据线均与所述第二连接线绝缘设置，且同一行对应的第二连接线与部分电源走线和部分数据线具有交叠区域；
    所述阵列基板还包括：位于所述第二连接线所在膜层与所述数据线所在膜层之间的第二屏蔽层；其中，所述第二屏蔽层在所述阵列基板的正投影覆盖所述电源走线和所述数据线分别与所述第二连接线的交叠区域在所述衬底基板的正投影。
  16. 一种显示装置，包括权利要求1-15任一所述的阵列基板和盖板。
  17. 一种阵列基板的制造方法，所述阵列基板包括基底和位于所述基底上的多个像素单元，每个像素单元包括驱动晶体管和发光器件，其中，所述阵列基板还包括屏蔽层，其位于每个像素单元的驱动晶体管的栅极所在层与对应的发光器件的第一极所在层之间，并且其中，所述制造方法包括：
    提供基底；
    在基底上形成所述多个像素单元；
    在每个像素单元的驱动晶体管的栅极所在层与每个发光器件的第一极所在层之间形成屏蔽层。
  18. 根据权利要求17所述的制造方法，其中，至少一部分驱动晶体管的栅极在所述基底上的投影和对应的发光器件的第一极在所述基底上的投影至少部分地重叠，并且其中
    在每个像素单元的驱动晶体管的栅极所在层与每个发光器件的第一极所在层之间形成屏蔽层进一步包括：
    至少在所述驱动晶体管的栅极和所述发光器件的第一极的重叠区域之间形成所述屏蔽层。
  19. 根据权利要求17或18所述的制造方法，其中，所述屏蔽层形成为面状结构，且所述屏蔽层在所述基底上的正投影覆盖每个驱动晶体管的栅极和每个发光器件的第一极在所述基底上的正投影。
  20. 根据权利要求17或18所述的制造方法，其中，所述屏蔽层形成为包括多个屏蔽电极，所述多个屏蔽电极与各个像素单元的驱动晶体管的栅极一一对应地形成。
  21. 根据权利要求17或18所述的制造方法，其中，所述屏蔽层形成为包括多个屏蔽电极，所述多个屏蔽电极与各个像素单元的发光器件的第一极一一对应地形成。
  22. 根据权利要求20或21所述的制造方法，其中，所述屏蔽电极由导电材料制成，并且所述阵列基板还包括电源电压端，其中，所述屏电极形成为与所述电源电压端连接。
  23. 根据权利要求17或18所述的制造方法，其中，所述屏蔽层形成为位于所述驱动晶体管的源极和漏极所在层的远离所述基底的一侧。
  24. 根据权利要求17所述的制造方法，其中，所述阵列基板包括显示区，所述制造方法还包括在所述基底上形成驱动控制电路，其 中，所述驱动控制电路和所述多个像素单元位于所述显示区，
    其中，所述制造方法还包括：形成位于所述显示区的多个像素驱动电路，其中，所述发光器件位于所述阵列基板显示区且覆盖所述像素驱动电路和所述驱动控制电路；
    其中，所述驱动控制电路包括：级联的多个移位寄存器单元；其中，所述移位寄存器单元分为多个子单元，各所述子单元位于相邻两个像素驱动电路之间的间隙处；同一所述移位寄存器单元中的不同子单元位于的间隙处不同，所述发光器件的阳极通过第一连接线与对应的像素驱动电路电连接，且同一所述移位寄存器单元中的各子单元之间通过第二连接线电连接。
  25. 根据权利要求24所述的制造方法，还包括：将同一所述移位寄存器单元中的各子单元形成在同一行中。
  26. 如权利要求24所述的制造方法，其中，所述阵列基板还包括：同层设置的沿列方向延伸的多条电源走线与多条数据线；各所述电源走线与各所述数据线均与所述第二连接线绝缘设置，且同一行对应的第二连接线与部分电源走线和部分数据线具有交叠区域，所述制造方法还包括：
    在所述第二连接线所在膜层与所述数据线所在膜层之间形成第二屏蔽层，并且其中，所述第二屏蔽层在所述阵列基板的正投影覆盖所述电源走线和所述数据线分别与所述第二连接线的交叠区域在所述衬底基板的正投影。
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CN105139806A (zh) * 2015-10-21 2015-12-09 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
CN107369700A (zh) * 2017-07-13 2017-11-21 京东方科技集团股份有限公司 一种阵列基板、其制备方法、显示面板及显示装置
CN108010944A (zh) * 2017-11-28 2018-05-08 武汉天马微电子有限公司 一种阵列基板及显示装置
CN109887985A (zh) * 2019-04-10 2019-06-14 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置

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