WO2021179291A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2021179291A1
WO2021179291A1 PCT/CN2020/079229 CN2020079229W WO2021179291A1 WO 2021179291 A1 WO2021179291 A1 WO 2021179291A1 CN 2020079229 W CN2020079229 W CN 2020079229W WO 2021179291 A1 WO2021179291 A1 WO 2021179291A1
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WO
WIPO (PCT)
Prior art keywords
lead
compensation
display panel
line
sub
Prior art date
Application number
PCT/CN2020/079229
Other languages
English (en)
French (fr)
Inventor
姜晓峰
韩林宏
杨慧娟
李慧君
张鑫
张猛
杨路路
代洁
白露
王思雨
王予
和玉鹏
屈忆
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/079229 priority Critical patent/WO2021179291A1/zh
Priority to US17/432,202 priority patent/US20220344449A1/en
Priority to EP20924749.3A priority patent/EP4120011A4/en
Priority to CN202080000273.XA priority patent/CN113692554B/zh
Publication of WO2021179291A1 publication Critical patent/WO2021179291A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the embodiment of the present disclosure relates to a display panel and a display device.
  • AMOLED active-matrix organic light-emitting diode
  • the embodiment of the present disclosure provides a display panel and a display device.
  • At least one embodiment of the present disclosure provides a display panel including: a display portion including a plurality of data lines and a plurality of pixels, the plurality of data lines are electrically connected to the plurality of sub-pixels, and the plurality of data lines are Is configured to provide data signals to the plurality of sub-pixels;
  • the expansion portion includes a plurality of expansion lines, at least part of the expansion lines extend in a different direction from the extension direction of the data line;
  • the lead portion includes a plurality of first leads, so The plurality of first leads and the plurality of data lines are respectively connected by the plurality of expansion lines, and the plurality of expansion lines are expanded and arranged between the lead part and the display part, and the first lead
  • the extension direction is the same as the extension direction of the data lines, and the spacing between adjacent data lines in the plurality of data lines is greater than the spacing between adjacent first leads in the plurality of first leads;
  • Each of the first leads includes a first lead sub-part and a compensation part to form a plurality
  • the included angle between at least one of the plurality of data lines and at least one of the plurality of expansion lines is an obtuse angle.
  • the first lead sub-portion is closer to the expansion portion than the compensation portion, and the width of the first lead sub-portion is smaller than the width of the compensation portion.
  • adjacent compensation parts have the same width.
  • adjacent compensation parts have different lengths along the extension direction of the first lead.
  • the length of the plurality of compensation parts gradually changes.
  • the number of the plurality of first leads is n
  • the length of the compensation section with the largest length among the plurality of compensation sections is H
  • the length of the plurality of compensation sections The amount of gradual change is ⁇ (H/n).
  • the display panel has a center line, and the extension direction of the center line is the same as the extension direction of the first lead, from the edge of the display panel to the center line. In the direction of, the length of the plurality of compensation parts gradually decreases.
  • the display panel has a center line, and the extension direction of the center line is the same as the extension direction of the first lead, from the edge of the display panel to the center line. In the direction of, the lengths of the multiple compensation parts gradually decrease and then gradually increase.
  • the lengths of the plurality of compensation parts in the extending direction of the first lead are the same, and the widths of the plurality of compensation parts gradually change.
  • the length of the plurality of compensation parts along the extension direction of the first lead gradually changes, and the width of the plurality of compensation parts gradually changes.
  • the first lead further includes a second lead sub-part, the second lead sub-part is connected to the compensation part, and the width of the second lead sub-part is smaller than the width of the second lead sub-part. According to the width of the compensation portion, the second lead sub-portion is located on a side of the compensation portion away from the display portion.
  • the display panel further includes a plurality of second leads, and the width of the second leads is the same everywhere.
  • the display panel further includes a pad portion configured to be connected to an external circuit, and the pad portion includes a plurality of pads and is located at the lead portion On the side away from the unfolding portion, the plurality of pads are electrically connected to the plurality of first leads.
  • the lead portions are provided in plural, and the multiple lead portions are symmetrically arranged with respect to the center line of the display panel.
  • the plurality of lead parts include a first lead part and a second lead part, and the sum of the area of the plurality of compensation parts of the first lead part is the same as that of the second lead part. The sum of the areas of the compensation parts of the part is different.
  • the sum of the areas of the plurality of compensation parts of the lead part gradually increases.
  • the sum of the areas of the plurality of compensation parts of the lead part close to the center line is greater than that of the compensation part away from the center line.
  • the sum of the areas of the plurality of compensation portions of the lead portion of the center line is greater than that of the compensation part away from the center line.
  • the display panel further includes a first power bus, and the first power bus is located on one side of the display portion and at least partially overlaps the plurality of expansion lines.
  • a power bus includes a first part, a second part, and a connecting line connecting the first part and the second part, and the connecting line overlaps the space.
  • the second part of the first power bus is located on a side of the first part of the first power bus away from the display part.
  • the display panel further includes a plurality of first power lines extending from the first power bus, wherein the plurality of first power lines extend to the display part, It is configured to provide a first power signal to the plurality of sub-pixels.
  • the display panel further includes a second power signal line surrounding the display part, at least part of the second power signal line overlaps the interval, and the second power source
  • the signal line is configured to provide a second power signal to the plurality of sub-pixels.
  • the plurality of expansion lines include a plurality of first expansion lines and a plurality of second expansion lines that are alternately arranged, and the plurality of first expansion lines and the plurality of second expansion lines
  • the two expansion lines are located in different layers
  • the plurality of first leads include a plurality of first leads of a first type and a plurality of first leads of a second type that are alternately arranged, and the plurality of first leads of the first type are respectively arranged
  • the plurality of second-type first leads are respectively connected to the plurality of second expansion lines and are connected to The plurality of second expansion lines are located on the same layer.
  • At least one of the plurality of sub-pixels includes a thin film transistor and a storage capacitor; the thin film transistor includes an active layer on the base substrate, and The first gate insulating layer on the side away from the base substrate, the gate located on the side of the first gate insulating layer away from the base substrate, and the gate located on the side away from the base substrate.
  • the storage capacitor includes a first plate and a second plate, the first plate and the gate are located in the same layer, and the second plate is located between the second gate insulating layer and the layer Between the insulating layers; the plurality of first expansion lines, the gate and the first electrode plate are located in the same layer, and the plurality of second expansion lines and the second electrode plate are located in the same layer.
  • At least one embodiment of the present disclosure also provides a display device including any of the above-mentioned display panels.
  • FIG. 1 is a schematic diagram of a peripheral area of a display panel
  • FIG. 2 is a schematic diagram of a peripheral area of a display panel
  • Figure 3 is a schematic diagram of a display panel
  • FIG. 4 is a schematic diagram of resistance distribution of data lines of a display panel
  • Figure 5 is a plan view of a display panel
  • FIG. 6 is a plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 7 is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of the lead part on the left side of the center line in FIG. 7;
  • FIG. 9 is a schematic diagram of the resistance distribution of the data lines of the display panel provided by an embodiment of the present disclosure.
  • FIG. 10 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • FIG. 11 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • FIG. 12 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • FIG. 13 is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 14 is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • 15 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • FIG. 16 is a plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 17 is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 18 is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 19 is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 20 is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 21 is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • Fig. 22 is an enlarged schematic diagram of the data selector in Fig. 21.
  • FIG. 23 is a cross-sectional view of a display panel provided by an embodiment of the disclosure.
  • Gamma correction is usually used to adjust the display screen. However, due to the limitation of technical conditions, the adjustment ability of Gamma correction is limited.
  • FIG. 1 is a schematic diagram of a peripheral area of a display panel.
  • the peripheral area includes a lead area WR and a fan out area FR.
  • Figure 1 shows eight expanded sub-regions: sub-region A, sub-region B, sub-region C, sub-region D, sub-region E, sub-region F, sub-region G, and sub-region H.
  • the expansion area FR is divided into a plurality of expansion sub-areas, thereby reducing the vertical frame. There are gaps between the leads corresponding to adjacent sub-regions.
  • Fig. 1 shows 7 gaps: gap 1, gap 2, gap 3, gap 4, gap 5, gap 6, and gap 7.
  • the position of the resistance of the data line abruptly changes at interval 1, interval 2, interval 3, interval 4, interval 5, interval 6 and interval 7.
  • the resistance at these places will show abrupt changes when it is not compensated.
  • the spaced position can be used to set a part of the power line, which can reduce the parasitic capacitance.
  • the power line includes at least one of the first power signal line and the second power signal line mentioned later.
  • FIG. 2 is a schematic diagram of a peripheral area of a display panel.
  • FIG. 2 shows the development line FL in the development region FR and the lead WRG in the lead region WR. For clarity of illustration, all the development lines FL and all the leads WRG are not shown in FIG. 2.
  • the number of the expansion line FL and the lead WRG can be determined according to needs.
  • Fig. 3 is a schematic diagram of a display panel.
  • the display panel includes a display area DR, an expansion area FR, and a lead area WR.
  • the display area DR includes the data line DL.
  • the expansion area FR includes the expansion line FL.
  • the lead area WR includes the lead WRG.
  • the expansion line FL is connected to the data line DL of the display area DR, and the display area DR is located on the side of the expansion area FR away from the lead area WR. That is, the expansion area FR is located between the display area DR and the lead area WR.
  • each lead WRG in each expanded sub-region the width of each lead WRG is about 2 ⁇ m, and the distance between adjacent leads WRG is about 16 ⁇ m, but it is not limited to this .
  • FIG. 4 is a schematic diagram of the resistance distribution of a data line of a display panel. As shown in FIG. 4, at the 7 spaced positions, the resistance of the data lines is quite different, which is likely to cause redness of the display screen and bright lines in the column direction, which affects the display effect of the display screen.
  • Fig. 5 is a plan view of a display panel.
  • the display panel DPN includes a display area DR, an expansion area FR, a lead area WR, and a pad area PDR.
  • the display area DR is provided with a display portion DP
  • the display portion DP includes a data line DL
  • the expansion area FR is provided with an expansion portion FP
  • the expansion portion FP includes an expansion line FL
  • the lead area WR is provided with a lead portion WP
  • the lead portion WP includes a lead WRG.
  • the lead region WR includes a plurality of leads WRG
  • the expansion region FR includes a plurality of expansion lines FL
  • the plurality of leads WRG of the lead region WR are respectively connected by the plurality of expansion lines FL of the expansion region FR.
  • FL is connected to a plurality of data lines DL in the display area DR, respectively.
  • the plurality of development lines FL are gradually dispersed from a position close to the lead portion WP to a position close to the display portion DP. That is, the plurality of expansion lines FL gradually converge from a position close to the display portion DP to a position close to the lead portion WP.
  • the display panel includes a base substrate BS.
  • the data line DL, the expansion line FL and the lead WRG are arranged on the base substrate BS.
  • the data line DL is located in the display area DR.
  • the data line DL passes through the expansion line FL and the lead WRG.
  • the lead WRG extends to the pad area PDR.
  • a plurality of lead wires WRG are sequentially arranged along the X direction.
  • the X direction crosses the Y direction.
  • the X direction is perpendicular to the Y direction.
  • the X direction and the Y direction are perpendicular to each other as an example for description.
  • the lead WRG extends in the Y direction
  • the data line DL extends in the Y direction.
  • a plurality of data lines DL are parallel to each other, but it is not limited thereto.
  • a plurality of lead wires WRG are arranged along the X direction, and each lead wire WRG extends along the Y direction.
  • the plurality of leads WRG are parallel to each other, but it is not limited thereto.
  • the dimension of the lead WRG along the X direction is the width
  • the dimension of the lead WRG along the Y direction is the length.
  • a plurality of data lines DL are arranged along the X direction, and each data line DL extends along the Y direction.
  • the multiple data lines DL have the same width and the same length, but it is not limited thereto.
  • the expansion line FL is not parallel to the Y direction and is not parallel to the X direction.
  • the display panel may also have an expansion line FL parallel to the Y direction.
  • the display portion DP further includes a sub-pixel SP, and the sub-pixel SP is connected to the data line DL.
  • the display panel DPN includes a plurality of sub-pixels SP.
  • One data line DL is connected to a column of sub-pixels SP.
  • the plurality of sub-pixels SP are arranged in an array, but it is not limited to this.
  • a plurality of sub-pixels SP are arranged in a matrix as an example for description.
  • FIG. 6 is a plan view of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes a display portion DP, an unfolding portion FP, and a lead portion WP.
  • the display portion DP is located in the display area DR
  • the expansion portion FP is located in the expansion area FR
  • the lead portion WP is located in the lead area WR.
  • the display part DP includes a plurality of data lines DL.
  • the expansion part FP includes a plurality of expansion lines FL.
  • the lead part WP includes a plurality of first leads WRG1.
  • the plurality of first leads WRG1 and the plurality of data lines DL are respectively connected through a plurality of expansion lines FL.
  • a plurality of spread lines FL are spread out between the lead part WP and the display part DP.
  • the extending direction of the first lead WRG1 is the same as the extending direction of the data line DL.
  • the extension direction of the two wires is the same, and the extension direction of the two wires is exactly the same and substantially the same.
  • a plurality of development lines FL are distributed from the lead part WP to the direction of the display part DP.
  • the plurality of development lines FL are gradually dispersed from a position close to the lead portion WP to a position close to the display portion DP.
  • the lengths of a plurality of expansion lines corresponding to the same lead part WP are different, but it is not limited to this.
  • the expansion area FR includes 8 expansion sub-areas: sub-area A, sub-area B, sub-area C, sub-area D, sub-area E, sub-area F, sub-area G, and sub-area H.
  • each of the plurality of first leads WRG1 includes a first lead sub-part WS1 and a compensation part CMP to form a plurality of first lead sub-parts WS1 and a plurality of compensation parts CMP, and the plurality of first lead sub-parts WS1 is connected to a plurality of compensation parts CMP respectively.
  • the width of the first lead sub-part WS1 and the width of the compensation part CMP are different.
  • the width of the first lead sub-portion WS1 is different from the width of the compensation portion CMP, so that the compensation portion CMP can compensate the resistance of the data line, which effectively reduces the resistance difference of the data line.
  • the resistance compensation is performed where the change is large to reduce the resistance difference of the data line in the resistance sudden change area, so that the resistance change of the data line tends to be smooth, which is beneficial to the uniformity of the display screen, thereby obtaining a better user experience.
  • a plurality of first leads WRG1 are sequentially arranged along the X direction.
  • the X direction crosses the Y direction.
  • the X direction is perpendicular to the Y direction.
  • the X direction and the Y direction are perpendicular to each other as an example for description.
  • the first lead WRG1 extends in the Y direction.
  • the dimension of the first lead WRG1 along the X direction is the width
  • the dimension of the first lead WRG1 along the Y direction is the length.
  • a plurality of data lines DL are arranged along the X direction, and each data line DL extends along the Y direction.
  • the data line DL is configured to input data signals to the sub-pixels.
  • the data signal includes voltage.
  • the data line DL is connected to the source or drain of the thin film transistor, and is configured to input a data signal to the source or drain of the thin film transistor.
  • the data line DL is formed integrally with the source electrode
  • the data line DL and the drain electrode are integrally formed.
  • the data line DL is configured to input a data voltage to the source or drain of the data writing transistor.
  • the display panel includes a plurality of sub-pixels, a plurality of data lines DL and a plurality of sub-pixels are electrically connected, and each data line is connected to a column of sub-pixels and is configured to provide data signals to the sub-pixels.
  • each data line is configured to provide a data signal to the turned-on sub-pixels.
  • a plurality of sub-pixels are formed into multiple rows and multiple columns.
  • the display panel is an organic light emitting diode display panel, including capacitors, multiple thin film transistors, and multiple light emitting units.
  • the display panel can be a display panel with a structure such as 7T1C, but is not limited thereto.
  • the light emitting unit includes an organic light emitting diode.
  • the organic light-emitting diode includes a cathode, a light-emitting functional layer and an anode, and the light-emitting functional layer is located between the cathode and the anode.
  • the anode is connected to one of the source and drain of the data writing transistor.
  • the light-emitting functional layer includes at least a light-emitting layer, and may also include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.
  • the expansion line FL is not parallel to the Y direction and is not parallel to the X direction.
  • the display panel may also have an expansion line FL parallel to the Y direction.
  • the extension direction of at least a part of the expansion line FL and the extension direction of the data line DL are different.
  • the extending direction of the line is a direction perpendicular to its width direction, but it is not limited thereto.
  • the extension direction of the line can be determined according to the overall extension trend of the line.
  • the extension direction of the line can be determined according to the connection between the initial end and the end of the line, but it is not limited to this.
  • the display panel includes a plurality of lead parts WP.
  • FIG. 6 takes the display panel including 8 lead parts as an example for description.
  • the eight lead parts are the first lead part WP1, the second lead part WP2, the third lead part WP3, the fourth lead part WP4, the fifth lead part WP5, the sixth lead part WP6, the seventh lead part WP7, and the eighth lead part.
  • Lead part WP8 is the first lead part WP1, the second lead part WP2, the third lead part WP3, the fourth lead part WP4, the fifth lead part WP5, the sixth lead part WP6, the seventh lead part WP7, and the eighth lead part.
  • the number of leads of the first lead part WP1, the second lead part WP2, the third lead part WP3, and the fourth lead part WP4 increase sequentially, and the fifth lead part WP5, the sixth lead part WP6, and the seventh lead part WP4
  • the number of leads of the lead portion WP7 and the eighth lead portion WP8 decreases in order.
  • the number of leads in each lead part may not have the above rule, and it can be determined according to needs.
  • the first lead sub-part WS1 is closer to the expansion part FP than the compensation part CMP, and the width of the first lead sub-part WS1 is smaller than the width of the compensation part CMP.
  • the compensation part CMP has a large width to help reduce the resistance of the data line.
  • the display panel provided by some embodiments of the present disclosure utilizes increased line width to reduce the resistance of the data line.
  • adjacent compensation portions CMP have the same width.
  • the width of the compensation portion CMP is the same.
  • the width of the compensation part CMP is the same for the production and the calculation of the compensation amount.
  • adjacent compensation parts CMP have different lengths along the extending direction of the first lead WRG1.
  • the display panel shown in FIG. 6 may also have adjacent compensation parts CMP with the same length.
  • the length of the plurality of compensation portions CMP gradually changes along the arrangement direction of the plurality of first wires WRG1.
  • the display panel provided by some embodiments of the present disclosure performs resistance compensation in a gradual manner to avoid sudden changes in the resistance of the data line. In this way, the resistance of the data line changes smoothly, and the resistance difference becomes smaller.
  • the number of the plurality of first leads WRG1 is n
  • the length of the compensation part CMP with the largest length among the plurality of compensation parts CMP is H
  • the length gradient of the plurality of compensation parts CMP is ⁇ (H/n).
  • the display panel has a center line CL, and the extension direction of the center line CL is the same as the extension direction of the first lead WRG1.
  • the seventh lead portion WP7, and the eighth lead portion WP8 except for the fourth lead portion WP4 and the lead portion WP of the fifth lead portion WP5
  • the distance from the edge of the display panel to the center line CL In the direction D0, the length of the plurality of compensation parts CMP gradually decreases.
  • the length of the plurality of compensation portions CMP gradually decreases and then gradually increases in the direction D0 from the edge of the display panel to the center line CL.
  • the first lead WRG1 further includes a second lead sub-portion WS2.
  • the second lead sub-portion WS2 is connected to the compensation portion CMP.
  • the width of the second lead sub-portion WS2 is smaller than the width of the compensation portion CMP.
  • the lead sub-part WS2 and the first lead sub-part WS1 are respectively disposed on both sides of the compensation part CMP.
  • the second lead sub-part WS2 is located on the side of the compensation part CMP away from the display part. The provision of the second lead sub-part WS2 facilitates the production of the compensation part CMP.
  • interval INT between adjacent lead parts WP, and the width of the interval INT is greater than the distance between adjacent first leads WRG1 in any one of the adjacent lead parts WP.
  • the distance between adjacent first leads WRG1 in the lead portion WP is the distance between adjacent first leads WRG1, and is the distance between adjacent first leads WRG1 in the X direction.
  • FIG. 6 shows seven intervals INT, and the sizes of different intervals INT in the X direction may be the same or different.
  • the width of each lead WRG except for the compensation part CMP is about 2 ⁇ m, and the width of the compensation part CMP is about 12 ⁇ m.
  • the distance between adjacent lead wires WRG except for the compensation part CMP is about 16 ⁇ m, and the distance between adjacent compensation parts CMP is about 6 ⁇ m, but it is not limited to this.
  • each lead WRG is about 900 ⁇ m
  • the maximum length of the compensation part CMP is about 800 ⁇ m, but it is not limited to this.
  • the plurality of first lead wires WRG1 are insulated from each other, and signals can be inputted separately.
  • a plurality of compensation portions CMP overlap in the X direction.
  • the plurality of compensation parts CMP at least partially overlap in the X direction.
  • the first lead WRG1 is a straight line
  • the data line DL is a straight line
  • the expansion line FL is shown in the form of a straight line in FIG. 6, but it is not limited to this.
  • the expansion line FL is not limited to a straight line, and may also be a line of other forms such as a curve, an arc, and the like. Referring to FIG. 7, on the left and right sides of the display panel, the expansion line FL is in the form of an arc.
  • the lead part WP near the edge of the display panel may not be subjected to resistance compensation.
  • the leads in the first lead part WP1 and the eighth lead part WP8 are not subjected to resistance compensation, that is, each lead in the first lead part WP1 and the eighth lead part WP8 is in X
  • the width in the direction is the same everywhere.
  • the leads in the first lead part WP1 and the eighth lead part WP8 are the second lead WRG2 mentioned later.
  • the included angle is greater than 90 degrees and less than 180 degrees, that is, the included angle is an obtuse angle.
  • the extension direction of the data line DL is the same as the extension direction of the first lead WRG1.
  • the included angle is also greater than 90 degrees and less than 180 degrees.
  • the expansion line FL is expanded in the expansion area FR, the distance between two adjacent expansion lines FL is gradually reduced from the display area to the lead area. For example, as shown in FIG.
  • the spacing between every two adjacent data lines DL is equal, and the spacing between every two adjacent first leads WRG1 is equal.
  • the angle between at least one of the plurality of data lines DL and at least one of the plurality of expansion lines FL is an obtuse angle.
  • the expansion line FL is used as a straight line for a schematic description.
  • the expansion line FL can also be a curve.
  • the angle between the data line DL and the expansion line FL is in the form of the data line DL and the curve.
  • the included angle of the tangent to the development line FL As shown in FIG. 6, the spacing between adjacent data lines DL among the plurality of data lines DL is greater than the spacing between adjacent first leads WRG1 among the plurality of first leads WRG1.
  • FIG. 7 is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure. For clarity of illustration, FIG. 7 does not show the display area and the components in the display area.
  • the sum of the areas of the compensation parts CMP of the first lead part WP1 is A1
  • the sum of the areas of the compensation parts CMP of the second lead part WP2 is A2
  • the sum of the areas of the third lead part WP2 is A2.
  • the sum of the areas of the compensation parts CMP of the part WP3 is A3, and the sum of the areas of the compensation parts CMP of the fourth lead part WP4 is A4. It can be seen from FIG. 6 and FIG. 7 that A1, A2, A3, A4 Increase in turn.
  • the sum of the areas of the compensation parts CMP of the fifth lead part WP5 is A5
  • the sum of the areas of the compensation parts CMP of the sixth lead part WP6 is A6
  • the seventh lead The sum of the areas of the compensation parts CMP of the part WP7 is A7
  • the sum of the areas of the compensation parts CMP of the eighth lead part WP8 is A8. It can be seen from Fig. 6 and Fig. 7 that A5, A6, A7, A8 Decrease in order.
  • the plurality of lead portions WP are symmetrically arranged with respect to the center line CL of the display panel.
  • the sum of the areas of the plurality of compensation parts CMP gradually increases in the first lead part WP1 to the fourth lead part WP4 . That is, A1, A2, A3, and A4 increase in order.
  • the sum of the areas of the multiple compensation parts CMP of the lead part WP close to the center line CL is larger than that of the leads far away from the center line CL
  • the sum of the areas of the compensation parts CMP of the part WP is larger than that of the leads far away from the center line CL.
  • the width of the compensation portion CMP is the same.
  • each lead portion The length of the compensating part CMP having the largest length in CMP increases successively.
  • the compensation part CMP with the largest length in the first lead part WP1 is the compensation part CMP farthest from the center line CL
  • the compensation part CMP with the largest length in the second lead part WP2 is the distance from the center
  • the compensation part CMP with the largest length in the third lead part WP3 is the compensation part CMP farthest from the center line CL
  • the compensation part CMP with the largest length in the fourth lead part WP4 is the distance from the center Compensation part CMP closest to line CL. Since the display panel is arranged symmetrically with respect to the center line CL, it can be inferred that the compensation part CMP having the largest length among the fifth lead part WP5 to the eighth lead part WP8 can be correspondingly inferred.
  • FIG. 8 is a schematic diagram of the lead part on the left side of the center line in Fig. 7.
  • FIG. 8 also shows the interval INT between adjacent lead portions.
  • FIG. 9 is a schematic diagram of the resistance distribution of the data lines of the display panel provided by an embodiment of the disclosure.
  • the resistance distribution of the data line after compensation is shown in FIG. 9.
  • the overall resistance difference of the compensated data line becomes smaller.
  • the resistance change tends to be smooth at 7 spaced positions, the resistance difference of the data line is small, the compensation effect is significant, and the display screen is prevented from being reddened. And bright lines in the column direction to improve the display effect of the display screen.
  • FIG. 10 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • FIG. 10 is a plan view of the second lead portion WP2 and the third lead portion WP3. It can be seen from FIG. 10 that the width of the compensation portion CMP is the same. From the edge of the display panel to the center line CL in the direction D0, in the second lead portion WP2, the length of the compensation portion CMP decreases sequentially, and from the display panel In the direction D0 from the edge to the center line CL, in the third lead portion WP3, the length of the compensation portion CMP decreases sequentially. As shown in FIG.
  • the length of the compensation part CMP having the largest length in each lead part increases in order.
  • the length of the compensation portion CMP having the largest length in the third lead portion WP3 is greater than the length of the compensation portion CMP having the largest length in the second lead portion WP2.
  • the second lead part WP2 and the third lead part WP3 in FIG. 10 can be replaced with the first lead part WP1 and the second lead part WP2, respectively.
  • FIG. 11 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • FIG. 11 is a plan view of the fourth lead portion WP4. It can be seen from FIG. 11 that the width of the compensation portion CMP is the same. From the edge of the display panel to the center line CL in the direction D0, in the fourth lead portion WP4, the length of the compensation portion CMP decreases and then increases successively. The length of the compensation part CMP on the left is smaller than the length of the compensation part CMP on the rightmost side.
  • FIG. 12 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • the fourth lead part WR4 further includes a second lead WRG2.
  • the width of the second lead WRG2 is the same everywhere, that is, the second lead WRG2 does not have a compensation part.
  • FIG. 12 shows one second lead WRG2, but the number of second leads WRG2 is not limited to this.
  • the number of second leads WRG2 can be determined according to needs.
  • the display panel further includes a plurality of second leads WRG2, and the width of each second lead WRG2 is the same everywhere.
  • a plurality of second leads WRG2 may be arranged in sequence, and no leads with compensation parts are provided between adjacent second leads WRG2.
  • each second lead WRG2 is connected to the data line of the display area through an expansion line.
  • FIG. 13 is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • the display panel further includes a pad portion PDP, which is configured to be connected to an external circuit.
  • the pad portion PDP includes a plurality of pads PD, which are located in the pad area PDR and located on the side of the lead portion WP away from the unfolding portion FP.
  • the external circuit is configured to input signals to the multiple data lines respectively through the multiple pads PD.
  • the multiple pads PD are electrically connected to the multiple first leads WRG1.
  • the display panel may also include the pad portion PDP. That is, the pad PD is provided on the side of each lead away from the data line DL.
  • Some embodiments of the present disclosure provide a display panel, and the compensation part adopts a constant width and length gradual method to compensate, so as to facilitate the compensation of the data line resistance and reduce the difference in the resistance of the data line.
  • the display panel of this structure is described in detail below.
  • the resistance difference of the data line generally originates from the difference in the length of the expansion line in the expansion area, so that the resistance compensation for the data line can also be regarded as the resistance compensation for the expansion line in the expansion area.
  • FIG. 14 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • FIG. 14 shows the interval INT between the adjacent lead portions WP, and the interval INT may be a plan view at any position of the interval 1, the interval 2, and the interval 3 in FIG. 6 or FIG. 7.
  • the lead part WP on the right side includes a plurality of first leads WRG1.
  • the first lead WRG1 includes a first lead sub-part WS1, a compensation part CMP, and a second lead sub-part WS2.
  • the compensation part CMP of the plurality of first leads WRG1 uses a compensation method of equal width and gradual change in length to compensate the resistance of the data line.
  • the lead part WP on the left side includes a second lead WRG2.
  • the second lead WRG2 does not have a compensation part, and has the same width everywhere.
  • FIG. 15 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • the lead part shown in FIG. 15 may be the fourth lead part WP4 in FIG. 6 or FIG. 7.
  • the fourth lead part WP4 includes a plurality of first leads WRG1, and the first lead WRG1 includes a first lead sub-part WS1, a compensation part CMP, and a second lead sub-part WS2.
  • Two compensation units CP1 and CP2 are shown in FIG. 15. Between the two compensation units CP1 and CP2, there is a second lead WRG2 having the same width everywhere.
  • the compensation part of the compensation unit CP1 and the compensation unit CP2 both uses a compensation method of equal width and gradually gradual length to compensate the resistance of the data line. In the compensation unit CP1, the length of the compensation part gradually decreases, and in the compensation unit CP2, the length of the compensation part gradually increases. That is, in the fourth lead portion WP4, the length of the compensation portion gradually decreases and then gradually increases.
  • the embodiment of the present disclosure takes as an example the resistance compensation of the data line corresponding to the expansion line in the sub-area A to the sub-area H (see FIG. 6).
  • This kind of resistance compensation method is that the width of the compensation part is equal and the length is gradually changed.
  • the compensation for the data line corresponding to the expanded line in sub-area A starts the compensation from the first data line from the left, starting with the maximum resistance that can be compensated, but not limited to this, the initial compensation amount It can also be less than the maximum resistance that can be compensated.
  • the maximum resistance that can be compensated can be determined according to the width and length of the lead located in the lead area. That is, the maximum resistance that can be compensated is obtained according to the maximum length of the lead and the maximum width of the lead under the process permitting condition.
  • the compensation part adopts the same width.
  • the line width of the compensation part is W.
  • the line length of the compensation part with the largest length is H1, the number of data lines corresponding to the sub-area A is n1, and the gradual change of the line length for successive compensation is ⁇ (H1/n1).
  • the line width of the first compensation part in the first lead part corresponding to subarea A is W
  • the line length is H1
  • the line width of the second compensation part is W
  • the line length is H1- ⁇ (H1/n1)
  • the line width of the three compensation parts is W
  • the line length is H1-2* ⁇ (H1/n1)
  • the line width of the kth compensation part is W
  • the line length is H1-(k-1)* ⁇ (H1/ n1).
  • the first data line from the left is compensated, starting with the maximum resistance that can be compensated.
  • the maximum resistance of compensation is the resistance difference of the two data lines closest to the interval 1 between adjacent lead parts (the first lead part and the second lead part) without compensation.
  • the maximum compensation resistance is the resistance difference R1 of the data lines corresponding to the leads on the left and right sides at the interval 1 position of the sudden change in resistance.
  • the compensation part adopts the same width.
  • the line width of the compensation part is W.
  • the line length of the compensation part with the largest length is H2
  • the number of data lines corresponding to the sub-area B is n2
  • the line length gradient of the compensation in sequence is ⁇ (H2/n2).
  • the line width of the first compensation part from the left in the second lead part corresponding to subarea B is W
  • the line length is H2
  • the line width of the second compensation part is W
  • the line length is H2- ⁇ (H2/n2)
  • the line width of the third compensation part is W
  • the line length is H2-2* ⁇ (H2/n2)
  • the line width of the kth compensation part is W
  • the line length is H2-(k-1)* ⁇ ( H2/n2).
  • the compensation part adopts the same width.
  • the line width of the compensation part is W.
  • the line length of the compensation part with the largest length is H3.
  • the number of data lines corresponding to the sub-area C is n3, and the gradual change of the line length compensated in sequence is ⁇ (H3/n3).
  • the line width of the compensation part corresponding to the first data line from the left in the third lead part corresponding to subarea C is W
  • the line length is H3
  • the line width of the second compensation part is W
  • the line length is H3- ⁇ (H3/n3)
  • the line width of the third compensation part is W
  • the line length is H3-2* ⁇ (H3/n3)
  • the line width of the kth compensation is W
  • the line length is H3-(k-1 )* ⁇ (H3/n3).
  • the size of the resistance is the resistance difference R3 of the data line corresponding to the leads on the left and right sides at the interval 3 of the resistance sudden change.
  • the line width of the compensation part is W and the line length is H4;
  • the compensation resistance starts with the maximum resistance that can be compensated.
  • the compensation line width is W and the line length is H5.
  • the number of data lines from the left to the middle resistance of the sub-area D is n4, and the compensation lines are sequentially compensated.
  • the amount of long gradient is ⁇ (H4/n4).
  • the line width of the first compensation part from the left in the fourth lead part corresponding to subarea D is W, the line length is H4, the line width of the second compensation part is W, and the line length is H4- ⁇ (H4/n4 ), the line width of the third compensation part is W, the line length is H4-2* ⁇ (H4/n4), the line width of the kth compensation is W, and the line length is H4-(k-1)* ⁇ ( H4/n4), in a similar manner, sequentially compensate up to the n4th compensation part; the number of data lines from the right to the middle of the sub-area D where the resistance is the smallest is n5, and the successive compensation line length gradient is ⁇ (H5 /n5).
  • the line width of the first compensation part from the right of the fourth lead part corresponding to subarea D is W, the line length is H5, the line width of the second compensation part is W, and the line length is H5- ⁇ (H5/n5) ,
  • the line width of the third compensation part is W, the line length is H5-2* ⁇ (H5/n5), the line width of the kth compensation part is W, and the line length is H5-(k-1)* ⁇ ( H5/n5), in a similar way up to the n5th compensation part. Then, the resistance compensation of the data line corresponding to the sub-area D can be completed.
  • the compensation part in the fourth lead part corresponding to the sub-area D can be mirror-symmetrical with respect to the center line of the display panel.
  • the compensation part in the third lead part corresponding to the sub-area C can be mirror-symmetrical with respect to the center line of the display panel.
  • the compensation portion in the second lead portion corresponding to the sub-region B can be mirrored and symmetric with respect to the center line of the display panel.
  • the compensation portion in the first lead portion corresponding to the sub-area A can be mirror-symmetrical with respect to the center line of the display panel.
  • resistance compensation can be performed in the same compensation manner.
  • all the compensation parts in the display panel have the same width. That is, the widths of the compensation parts in different lead parts are the same.
  • the line length relationship of the compensation part with the longest length is as follows: H1 ⁇ H2 ⁇ H3 ⁇ H4 ⁇ H5.
  • the method of making a lead WRG includes: forming a conductive layer, forming a photoresist layer on the conductive layer, exposing and developing the photoresist layer to obtain a photoresist pattern, and using the photoresist pattern as a mask to align the conductive layer Perform etching to obtain leads. Since the embodiment of the present disclosure has the lead wire provided with the compensation part, the mask can be designed according to the configuration of the compensation part.
  • the resistance compensation of the data line is performed in a way that the line width is constant and the line length is gradually changed.
  • the mask is easy to manufacture, which is more conducive to process realization.
  • FIG. 16 is a plan view of a display panel provided by an embodiment of the disclosure. Compared with the display panel shown in FIG. 6, the display panel shown in FIG. 16 is different in that the compensation method of the compensation part is changed. In the display panel shown in FIG. 16, in the same lead part, the compensation part is compensated in a way that the length of the compensation part is equal and the width is gradually changed.
  • the width of the plurality of compensation portions CMP gradually decreases in the direction D0 from the edge of the display panel to the center line CL. small.
  • the width of the plurality of compensation portions CMP gradually decreases and then gradually increases.
  • the display panel provided by some embodiments of the present disclosure performs resistance compensation in a manner of equal line length and gradual line width.
  • the following describes the display panel of this structure.
  • Compensation for the data line corresponding to the expansion line in the sub-area A start the compensation from the first data line from the left, starting with the maximum resistance that can be compensated.
  • the line width of the compensation part in the first lead part corresponding to the first data line from the left is W1
  • the line length is H1
  • the number of data lines in sub-area A is n1
  • the successive compensation line width gradient is ⁇ ((W1-w)/n1), where w is the line width of the data line.
  • the line width of the first compensation part is W1, the line length is H1, the line width of the second compensation part is W1- ⁇ ((W1-w)/n1), the line length is H1, the line of the third compensation part
  • the width is W1-2* ⁇ ((W1-w)/n1), the line length is H1
  • the line width of the kth compensation part is W1-(k-1)* ⁇ ((W1-w)/n1)
  • the line length is H1. Compensation is carried out in sequence until the n1 compensation part, and then the resistance compensation of the data line corresponding to the sub-area A can be completed.
  • Compensation for the data line corresponding to the expanded line in sub-area B Compensation starts from the first data line from the left.
  • the size of the compensation resistance of the leftmost compensation part in the second lead part corresponding to sub-area B It is the resistance difference R1 between the left and right data lines at interval 1 where the resistance changes.
  • the line width of the compensation part corresponding to the first data line from the left is W2
  • the line length is H2
  • the number of data lines corresponding to sub-area B is n2
  • the line length gradient of the compensation in turn is ⁇ ((W2-w) /n2), where w is the line width of the data line.
  • the line width of the first compensation part from the left in the second lead part corresponding to subarea B is W2, the line length is H2, and the line width of the second compensation part is W- ⁇ ((W2-w)/n2),
  • the line length is H2
  • the line width of the third compensation part is W2-2* ⁇ ((W2-w)/n2)
  • the line length is H2
  • the line width of the k-th compensation is W-(k-1)* ⁇ ((W2-w)/n2), the line length is H2.
  • Compensation for the data line corresponding to the expanded line in sub-area C Compensation starts from the first data line from the left, and the compensation resistance of the leftmost compensation part in the third lead part corresponding to sub-area C It is the resistance difference R2 of the data line corresponding to the leads on the left and right sides at the interval 3 where the resistance changes.
  • the compensation line width is W3
  • the line length is H3
  • the number of data lines corresponding to sub-area C is n3
  • the successive compensation line width gradient is ⁇ ((W3-w)/n3), where w is the data line Line width.
  • the line width of the first compensation part from the left of subarea C is W3, the line length is H3, the line width of the second compensation part is W- ⁇ ((W3-w)/n3), the line length is H3, and the third
  • the line width of each compensation part is W3-2* ⁇ ((W3-w)/n3), the line length is H3, and the line width of the k-th compensation part is W3-(k-1)* ⁇ ((W3-w )/n3), the line length is H3. Compensation is carried out in sequence until the n3th line to complete the resistance compensation of the data line corresponding to the sub-area C.
  • compensation resistance of the leftmost compensation part in the part is the resistance difference R3 of the data lines corresponding to the leads on the left and right sides at the interval 3 of the resistance sudden change, and the leftmost part of the fourth lead part corresponding to sub-area D
  • the line width of the compensation part is W4, and the line length is H4.
  • the compensation resistance of the rightmost compensation part in the fourth lead part that corresponds to the fourth lead part corresponding to the sub-area D starts with the maximum resistance that can be compensated.
  • the compensation line width is W5 and the line length is H5.
  • the number of data lines corresponding to sub-area D from the left to the lowest resistance in the middle is n4, and the successive compensation line width gradient is ⁇ ((W4-w)/n4), where w is the line width of the data line.
  • the line width of the first compensation part from the left of subarea D is W4, the line length is H4, the line width of the second compensation part is W4- ⁇ ((W4-w)/n4), the line length is H4, and the third
  • the line width of each compensation part is W4-2* ⁇ ((W4-w)/n4), the line length is H4, and the line width of the k-th compensation part is W4-(k-1)* ⁇ ((W4-w )/n4), the line length is H4, and it is compensated to the n4th in turn;
  • the number of data lines corresponding to sub-area D from the right to the lowest resistance in the middle is n5, and the successive compensation line width gradient is ⁇ (( W5-w)/n5), where w is the line width of the data line.
  • the line width of the first compensation part from the right in the fourth lead part corresponding to subarea D is W5, the line length is H5, and the line width of the second compensation part is W5- ⁇ ((W5-w)/n5),
  • the line length is H5
  • the line width of the third compensation part is W5-2* ⁇ ((W5-w)/n5)
  • the line length is H5
  • the line width of the kth compensation part is W5-(k-1) * ⁇ ((W5-w)/n5)
  • the line length is H5, and the compensation is performed in a similar manner up to the n5th compensation part to complete the resistance compensation of the data line corresponding to sub-area D.
  • the compensation part in the fourth lead part corresponding to the sub-area D can be mirror-symmetrical with respect to the center line of the display panel.
  • the compensation part in the third lead part corresponding to the sub-area C can be mirror-symmetrical with respect to the center line of the display panel.
  • the compensation portion in the second lead portion corresponding to the sub-region B can be mirrored and symmetric with respect to the center line of the display panel.
  • the compensation portion in the first lead portion corresponding to the sub-area A can be mirror-symmetrical with respect to the center line of the display panel.
  • the same compensation method can be used to compensate the resistance compensation of the expansion lines of the remaining sub-areas.
  • the lengths of all compensation parts in the display panel are equal. That is, the lengths of the compensation parts in different lead parts are the same.
  • the lengths of the plurality of compensation parts CMP in the extending direction of the first lead WRG1 are the same, and the widths of the plurality of compensation parts CMP are gradually changed.
  • the line width relationship of the compensation part with the largest width is as follows: W1 ⁇ W2 ⁇ W3 ⁇ W4 ⁇ W5.
  • FIG. 17 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • FIG. 17 shows the interval INT between the adjacent lead portions WP, and the interval INT may be a plan view at any position of the interval 1, the interval 2, and the interval 3 in FIG. 16.
  • the lead part WP on the right side includes a plurality of first leads WRG1.
  • the first lead WRG1 includes a first lead sub-part WS1, a compensation part CMP, and a second lead sub-part WS2.
  • the compensation part CMP of the plurality of first leads WRG1 uses a compensation method with a width gradient and an equal length to compensate the resistance of the data line.
  • the lead part WP on the left side includes a second lead WRG2.
  • the second lead WRG2 does not have a compensation part, and has the same width everywhere.
  • FIG. 18 is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • the lead part shown in FIG. 18 may be the fourth lead part WP4 in FIG. 16.
  • the fourth lead part WP4 includes a plurality of first leads WRG1, and the first lead WRG1 includes a first lead sub-part WS1 and a compensation part CMP.
  • Two compensation units CP1 and CP2 are shown in FIG. 18. Between the two compensation units CP1 and CP2, there is a second lead WRG2 having the same width everywhere.
  • the compensation part in the compensation unit CP1 and the compensation unit CP2 both uses a compensation method with a gradual width and equal length to compensate the resistance of the data line.
  • the width of the compensation portion gradually decreases, and in the compensation unit CP2, the width of the compensation portion gradually increases. That is, in the fourth lead part WP4, along the arrangement direction of the leads, the width of the compensation part first gradually decreases and then gradually increases.
  • the display panels provided by other embodiments of the present disclosure perform resistance compensation in a manner of gradual line length and line width gradual change.
  • the following describes the display panel of this structure.
  • Compensation for the data line corresponding to the expansion line in the sub-area A start the compensation from the first data line from the left, starting with the maximum resistance that can be compensated.
  • the line width of the compensation part is W1
  • the line length is H1
  • the number of data lines corresponding to sub-area A is n1
  • the line width gradient of the compensation is ⁇ ((W1-w)/n1), where w is the data
  • the line width of the line; the line length gradient is ⁇ (H1/n1).
  • the line width of the first compensation part is W1
  • the line length is H1
  • the line width of the second compensation part is W1- ⁇ ((W1-w)/n1)
  • the line The length is H1- ⁇ (H1/n1)
  • the line width of the third compensation part is W1-2* ⁇ ((W1-w)/n1)
  • the line length is H1-2* ⁇ (H1/n1)
  • the line width of the k compensation parts is W1-(k-1)* ⁇ ((W1-w)/n1)
  • the line length is H1-(k-1)* ⁇ (H1/n1). Compensation is carried out in sequence until the n1 compensation part, and then the resistance compensation of the data line corresponding to the sub-area A can be completed.
  • Compensation for the data line corresponding to the expansion line in sub-area B Compensation starts from the first data line from the left.
  • the size of the compensation resistor is the data line corresponding to the leads on the left and right sides at the interval 1 where the resistance changes suddenly.
  • the resistance difference R1 The line width of the compensation part is W2, the line length is H2, the number of data lines corresponding to sub-area B is n2, and the line length gradient of the compensation is ⁇ ((W2-w)/n2), where w is the data
  • the line width of the line; the line length gradient is ⁇ (H2/n2).
  • the line width of the first compensation part from the left is W2, the line length is H2, and the line width of the second compensation part is W- ⁇ ((W2-w)/n2) ,
  • the line length is H2- ⁇ (H2/n2)
  • the line width of the third compensation part is W-2* ⁇ ((W2-w)/n2)
  • the line length is H2-2* ⁇ (H2/n2)
  • the line width of the k-th compensation part is W2-(k-1)* ⁇ ((W2-w)/n2)
  • the line length is H2-(k-1)* ⁇ (H2/n2).
  • the first data line from the left is compensated.
  • the size of the compensation resistor is the interval of the sudden change in resistance.
  • the data line corresponding to the leads on the left and right sides at the position The resistance difference R2.
  • the line width of the compensation part is W3, the line length is H3, the number of data lines corresponding to sub-area C is n3, and the line width gradient of the compensation in turn is ⁇ ((W3-w)/n3), where w is the data
  • the line width of the line; the line length gradient is ⁇ (H3/n3).
  • the line width of the first compensation part from the left is W3, the line length is H3, and the line width of the second compensation part is W- ⁇ ((W3-w)/n3) ,
  • the line length is H3- ⁇ (H3/n3)
  • the line width of the third compensation part is W3-2* ⁇ ((W3-w)/n3)
  • the line length is H3-2* ⁇ (H3/n3)
  • the line width of the k-th compensation part is W3-(k-1)* ⁇ ((W3-w)/n3)
  • the line length is H3-(k-1)* ⁇ (H3/n3).
  • Compensation for the data line corresponding to the expansion line in sub-area D start with the data lines on the left and right sides of sub-area D, and compensate to the data line with the smallest resistance in the middle of sub-area D, corresponding to the left side of sub-area D
  • the size of the compensation resistance of the data line is the resistance difference R3 of the data line corresponding to the leads on the left and right sides at the interval 3 of the resistance sudden change.
  • the line width of the compensation part of the data line is W4, and the line length is H4;
  • the compensation resistance of the data line on the right side of D starts with the maximum resistance that can be compensated.
  • the compensation line width is W5 and the line length is H5.
  • the number is n4, and the successive compensation line width gradient is ⁇ ((W4-w)/n4), where w is the line width of the data line; the line length gradient is ⁇ (H4/n4).
  • the line width of the first compensation part from the left is W4
  • the line length is H4
  • the line width of the second compensation part is W4- ⁇ ((W4-w)/n4)
  • the line length is H4- ⁇ (H4/n4)
  • the line width of the third compensation part is W4-2* ⁇ ((W4-w)/n4)
  • the line length is H4-2* ⁇ (H4/n4)
  • the line width of the k-th compensation part is W4-(k-1)* ⁇ ((W4-w)/n4)
  • the line length is H4-(k-1)* ⁇ (H4/n4), in a similar way Compensate sequentially up to the n4th compensation part; the number of data lines corresponding to sub-area D
  • the line width of the first compensation part from the right is W5, the line length is H5, and the line width of the second compensation part is W5- ⁇ ((W5-w)/n5) ,
  • the line length is H5- ⁇ (H5/n5)
  • the line width of the third compensation part is W5-2* ⁇ ((W5-w)/n5)
  • the line length is H5-2* ⁇ (H5/n5)
  • the line width of the k-th compensation part is W5-(k-1)* ⁇ ((W5-w)/n5)
  • the line length is H5-(k-1)* ⁇ (H5/n5)
  • the compensation part in the fourth lead part corresponding to the sub-area D can be mirror-symmetrical with respect to the center line of the display panel.
  • the compensation part in the wire part corresponding to the sub-area C can be mirrored and symmetrical with respect to the center line of the display panel.
  • the compensation portion in the second lead portion corresponding to the sub-region B can be mirrored and symmetric with respect to the center line of the display panel.
  • the compensation part in the fourth lead part corresponding to the sub-area A can be mirror-symmetrical with respect to the center line of the display panel.
  • the same compensation method can be used to compensate the resistance compensation of the expansion lines of the remaining sub-areas.
  • FIG. 19 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • FIG. 19 shows the interval INT between adjacent lead portions WP.
  • the interval INT can be a plan view at any position of the interval 1, interval 2, and interval 3 in FIG. 6 or FIG. 16.
  • the structure and diagram of the compensation portion 6 and Figure 16 are different.
  • the lead part WP on the right side includes a plurality of first leads WRG1.
  • the first lead WRG1 includes a first lead sub-part WS1, a compensation part CMP, and a second lead sub-part WS2.
  • the compensation portion CMP of the plurality of first leads WRG1 uses a compensation method of gradual width and gradual length to compensate the resistance of the data line. As shown in FIG.
  • the lead part WP on the left side includes a second lead WRG2.
  • the second lead WRG2 does not have a compensation part, and has the same width everywhere.
  • FIG. 20 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • the lead portion shown in FIG. 20 may be the fourth lead portion WP4 in FIG. 6 or FIG. 16.
  • the fourth lead part WP4 includes a plurality of first leads WRG1, and the first lead WRG1 includes a first lead sub-part WS1 and a compensation part CMP.
  • Two compensation units CP1 and CP2 are shown in Fig. 20.
  • the compensation part of the compensation unit CP1 and the compensation unit CP2 both uses a compensation method of gradual width and gradual length to compensate the resistance of the data line. As shown in FIG.
  • the second lead WRG2 having the same width everywhere.
  • the length and width of the compensation portion gradually decrease, and in the compensation unit CP2, the width and length of the compensation portion gradually increase. That is, in the fourth lead portion, the width of the compensation portion first gradually decreases and then gradually increases, and the length of the compensation portion first gradually decreases and then gradually increases.
  • the leads of the unfolding area may also be arranged symmetrically with respect to the center line CL.
  • the leads WRG in the embodiment of the present disclosure may all be the first lead WRG1, excluding the second lead WRG2, that is, the resistance compensation is performed on each data line, but it is not limited thereto.
  • the lead WRG includes a first lead WRG1 and a second lead WRG2.
  • FIG. 21 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • the display panel shown in FIG. 21 only shows the lower part of the left side of the center line CL, and the right part of the display panel and the left side are symmetrically arranged with respect to the center line CL. In addition, for clarity of illustration, the display area and all components therein are not shown.
  • the display panel shown in FIG. 21 shows the pad area PDR and the pad portion PDP located therein, and each pad PD is connected to at least one expansion line FL.
  • FIG. 21 also shows the bending region BR and the unfolding region FR2 located on the side of the bending region BR away from the lead region WR.
  • the expansion area FR2 may also be referred to as the second expansion area, and accordingly, the expansion area FR may be referred to as the first expansion area.
  • An expansion line FL2 is provided in the expansion area FR2.
  • the plurality of expansion lines FL2 are respectively connected to the plurality of expansion lines FL in the expansion area FR, and further connected to the data line DL of the display area.
  • the pad PD is configured to be bound to the pins of the integrated circuit.
  • other units may be provided between the expansion area FR2 and the pad area PDR, for example, a test (Cell Test, CT) unit, etc., which are not shown in FIG. 21 for clarity of illustration.
  • the expansion line FL is connected to the expansion area FR3 through the data selection unit MUX, and the expansion area FR3 can also be referred to as a third expansion area.
  • the expansion area FR3 includes a plurality of expansion lines FL3, and the plurality of expansion lines FL3 are respectively connected to a plurality of pads PD.
  • the plurality of expansion lines FL3 are respectively connected to the plurality of pads PD through the plurality of leads WRG33.
  • the multiple wires WRG33 may also be provided with the compensation portion CMP3.
  • the multiple wires WRG33 are provided with the compensation portion CMP3 as an example for description.
  • the arrangement of the compensation part CMP3 can refer to the arrangement of the compensation part CMP1, which will not be repeated here.
  • each pad PD is respectively connected to two leads WRG through the data selector MUX, and is further electrically connected to two data lines DL.
  • the first signal line L1 and the second signal line L2 are controlled to be turned on at different time periods, so that the data signal is transmitted to the two data lines DL connected to the data selector MUX.
  • the setting method of the data selector MUX can refer to the usual design.
  • the data selector MUX is not limited to connecting two data lines DL, and the number of data lines DL connected to the data selector MUX can be determined according to needs.
  • the display panel further includes a wire CDL, for example, the wire CDL is used for binding with the flexible circuit board.
  • the wire CDL includes a first power signal line CDL1 and a second power signal line CDL2.
  • the first power supply signal line CDL1 is configured to provide a first power supply voltage to the sub-pixels
  • the second power supply signal line CDL2 is configured to provide a second power supply voltage to the sub-pixels.
  • the first power supply signal line CDL1 is a VDD line
  • the second power supply signal line CDL2 is a VSS line.
  • the second power signal line CDL2 is connected to the cathode of the light emitting diode.
  • FIG. 21 also shows the gate line GL.
  • the gate line GL extends in the X direction, the plurality of gate lines GL and the plurality of data lines DL are insulated from each other, and the plurality of gate lines GL and the plurality of data lines DL cross each other to define a plurality of sub-pixels SP.
  • the size of the interval INT at position 1 in the X direction is about 1800 ⁇ m, but it is not limited to this.
  • the size of the interval INT at position 2 in the X direction is about 1800 ⁇ m, but it is not limited to this.
  • the size of the interval INT at position 3 in the X direction is about 1800 ⁇ m, but it is not limited to this.
  • the expansion line FL includes a first expansion line FL11 and a second expansion line FL12.
  • the first expansion line FL11 and the second expansion line FL12 are arranged adjacently, and the first expansion line FL11 is located at the On the first floor LY1, the second unfolding line FL12 is located on the second floor LY2.
  • a plurality of first expansion lines FL11 and a plurality of second expansion lines FL12 are alternately arranged.
  • the plurality of expansion lines FL includes a plurality of first expansion lines FL11 and a plurality of second expansion lines FL12 arranged alternately, and the plurality of first expansion lines FL11 and the plurality of second expansion lines FL12 are located in different layers.
  • the plurality of first leads WRG1 includes a plurality of first-type first leads and a plurality of second-type first leads alternately arranged, and the plurality of first-type first leads are connected to the plurality of first leads respectively.
  • a first expansion line FL11 is connected and is located on the same layer with a plurality of first expansion lines FL11, and a plurality of second-type first leads are respectively connected to a plurality of second expansion lines FL12, and are connected to a plurality of second expansion lines FL12. Located on the same floor.
  • the display panel includes an unfolding portion FP2.
  • the unfolding line FL2 includes a first unfolding line FL21 and a second unfolding line FL22.
  • the first unfolding line FL21 and the second unfolding line FL22 are arranged adjacent to each other.
  • FL21 is located on the first layer LY1
  • the second expansion line FL22 is located on the second layer LY2.
  • a plurality of first expansion lines FL21 and a plurality of second expansion lines FL22 are alternately arranged.
  • the first power signal line CDL1 is located on the third layer LY3, and the second power signal line CDL2 is located on the third layer LY3.
  • the second power signal line CDL2 can be connected to the cathode of the light-emitting diode through an adapter element provided on the same layer as the anode of the light-emitting diode.
  • the anode of the light-emitting diode and the switching element are formed by the same film layer using the same patterning process and are spaced apart from each other.
  • the second lead WRG2 is also located on the third layer LY3.
  • the first layer LY1 is formed from the same film layer using the same patterning process
  • the second layer LY2 is formed from the same film layer using the same patterning process
  • the third layer LY3 is formed from the same film layer using the same patterning process.
  • the first layer LY1 is a first gate layer
  • the second layer LY2 is a second gate layer
  • the third layer LY3 is a source and drain layer.
  • the first layer LY1 further includes gate lines GL located in the display area
  • the second layer LY2 further includes initial signal lines located in the display area
  • the third layer LY3 further includes source and drain electrodes located in the display area.
  • the gate line is configured to provide a scan signal to the sub-pixel
  • the initialization signal line is configured to provide an initialization signal to the sub-pixel.
  • the gray dots and the black dots both indicate that two sub-lines are connected through a via hole, and the two sub-lines are located at different ones.
  • the second power signal line CDL2 is not electrically connected to the line crossing it shown in FIG. 21.
  • the first power signal line CDL1 is not electrically connected to the line crossing it shown in FIG. 21. Therefore, the integrated circuits bound to the pad PD can respectively transmit signals to the data lines DL in the display area, and the flexible circuit boards bound to the conductive wires CDL can respectively transmit signals to the conductive wires CDL.
  • the base substrate adopts a flexible substrate, so as to provide the bending area BR, but it is not limited thereto.
  • the leads of the bending area BR are made of conductive material forming the third layer LY3.
  • the first layer LY1, the second layer LY2, and the third layer LY3 are all made of a conductive material.
  • the conductive material includes at least one of a metal or an alloy.
  • the material forming the first layer LY1 and the second layer LY2 includes nickel, but is not limited thereto.
  • the metal forming the third layer LY3 includes Ti-Al-Ti, which has good bending resistance.
  • the first power signal line CDL1 includes a first power bus BL1
  • the first power bus BL1 is located at one side of the display portion DP and at least partially overlaps the plurality of expansion lines FL
  • the first power bus BL1 includes The first part BL11, the second part BL12, and the connecting line BL13 connecting the first part BL11 and the second part BL12, and the connecting line BL13 overlaps the space INT. That is, the connecting line BL13 is located within the interval INT.
  • the first portion BL11 extends in the X direction
  • the second portion BL12 extends in the X direction
  • the connecting line BL13 extends in the Y direction.
  • the first part BL11 is parallel to the second part BL12
  • the first part BL11 is perpendicular to the connecting line BL13.
  • the second portion BL12 of the first power bus BL1 is located on the side of the first portion BL11 of the first power bus BL1 away from the display portion DP.
  • the first power supply signal line CDL1 further includes a plurality of first power supply lines LN1 extending from the first power bus BL1, and the plurality of first power supply lines LN1 extend to the display portion DP, and are configured to provide the first power supply lines LN1 to the plurality of sub-pixels SP.
  • the first power signal includes a first power voltage.
  • the second power signal line CDL2 overlaps the interval INT, and the second power signal line CDL2 is configured to provide the second power signal to the plurality of sub-pixels SP.
  • the second power signal includes a second power voltage, and the second power voltage is less than the first power voltage.
  • the second power signal line CDL2 may surround the display part DP and have an opening at the bottom end.
  • FIG. 21 shows three rows of sub-pixels SP.
  • the number of sub-pixels SP included in the display panel is not limited to this, and the number of sub-pixels SP can be determined according to needs.
  • FIG. 21 shows the development region FR2, the lead region WR2, the development region FR3, and the lead region WR33.
  • the unfolding part FP2 is located in the unfolding area FR2, and includes a plurality of unfolding lines FL2.
  • the unfolding part FP3 is located in the unfolding area FR3, and includes a plurality of unfolding lines FL3.
  • the lead part WP22 is located in the lead region WR2 and includes a plurality of leads WRG22.
  • the lead part WP33 is located in the lead region WR3 and includes a plurality of leads WRG33.
  • the multiple lead wires WRG22 can also be provided with a compensation part, and the setting method can refer to the setting method of the compensation part in any lead part.
  • the lead WRG22 may be located on the same layer as the expansion line FL2 connected to it. That is, the multiple lead wires WRG22 include multiple lead wires located on the first layer and multiple lead wires located on the second layer.
  • the part above the expansion line FL may be referred to as the data line DL, that is, in FIG. 21, the part extending in the Y direction connected to the expansion line FL above the expansion line FL is the data line DL.
  • the data line DL includes a portion located in the third layer Y3 and a portion located in the first layer LY1 or LY2, but is not limited thereto.
  • each data selector MUX includes an active layer ACTL.
  • the portion of the active layer ACTL covered by the first signal line L1 and the second signal line L2 is a channel region.
  • the part covered by the first signal line L1 and the second signal line L2 is a conductor.
  • the first end of the active layer ACTL is connected to a data line DL
  • the second end of the active layer ACTL is connected to another data line DL
  • the third end of the active layer ACTL is connected to the pad PD through the wire WRG33.
  • the first end, the second end, and the third end of the active layer ACTL are all located in the conductor part of the active layer ACTL, and can be connected to the active layer ACTL through the adapter located on the third layer.
  • the expansion line FL3 may be located on the first layer LY1, or on the second layer LY2, or include a portion located on the first layer LY1 and a portion located on the second layer LY2.
  • the expansion line FL3 can also be located on the third layer LY3.
  • the lead WRG33 can refer to the expansion line FL3 connected to it.
  • FIG. 23 is a cross-sectional view of a display panel provided by an embodiment of the disclosure.
  • at least one of the plurality of sub-pixels SP includes a thin film transistor T0 and a storage capacitor Cst.
  • the thin film transistor T0 is the data writing transistor.
  • the thin film transistor T0 includes an active layer ATL located on the base substrate BS, a first gate insulating layer GI1 located on the side of the active layer ATL away from the base substrate BS, and located on the side of the first gate insulating layer GI1 away from the base substrate BS
  • the gate GE is located on the second gate insulating layer GI2 on the side of the gate GE away from the base substrate BS, the interlayer insulating layer ILD located on the side of the second gate insulating layer GI2 away from the base substrate, and the interlayer insulating layer
  • the first electrode ET1 and the second electrode ET2 on the side of the ILD away from the base substrate BS; the storage capacitor Cst includes a first electrode plate Ca and a second electrode plate Cb.
  • the first layer LY1 and the second electrode plate Cb are located between the second gate insulating layer GI2 and the interlayer insulating layer ILD, and are located on the second layer LY2.
  • a plurality of first expansion lines FL11, a gate GE, and a first electrode plate Ca are located in the same layer, all of which are located in the first layer LY1, and a plurality of second expansion lines FL12 and the second electrode plate Cb are located
  • the same floor is located on the second floor LY2.
  • One of the first electrode ET1 and the second electrode ET2 is a source, and the other of the first electrode ET1 and the second electrode ET2 is a drain. Referring to FIG. 21 and FIG.
  • the display panel 23 also includes a passivation layer PVX and a planarization layer PLN. In the case where the display panel includes a bending area, the leads located in the bending area are located on the third layer LY3.
  • the display panel also includes a light-emitting unit EMU.
  • the light-emitting unit EMU includes an anode ADE, a light-emitting functional layer EML, and a cathode CDE.
  • the first pole ET1 is connected to the data line, for example, the first pole ET1 is formed integrally with the data line.
  • the display panel further includes an encapsulation layer CPS.
  • the encapsulation layer CPS includes a first encapsulation layer CPS1, a second encapsulation layer CPS2, and a third encapsulation layer CPS3.
  • the first encapsulation layer CPS1 and the third encapsulation layer CPS3 are inorganic material layers
  • the second encapsulation layer CPS2 is an organic material layer.
  • the display panel further includes a pixel definition layer PDL and spacers PS.
  • the pixel definition layer PDL is configured to define the opening of the sub-pixel
  • the spacer PS is configured to support the fine metal mask when forming the light emitting function layer EML.
  • one of the anode and the cathode of the light emitting unit EMU is electrically connected to a driving transistor, and the driving transistor is configured to provide the light emitting unit EMU with a driving current for driving the light emitting unit EMU to emit light.
  • the data line is configured to input a data signal to the sub-pixel
  • the first power supply signal line is configured to input a first power supply voltage to the driving transistor.
  • the second power supply signal line is configured to input the second power supply voltage to the sub-pixels.
  • the first power supply voltage is a constant voltage
  • the second power supply voltage is a constant voltage.
  • the first power supply voltage is a positive voltage
  • the second power supply voltage is a negative voltage, but it is not limited thereto.
  • the first power supply voltage is a positive voltage
  • the second power supply signal line is grounded.
  • the display panel may also include other transistors such as light emission control transistors, reset transistors, etc.
  • the pixel circuit of the display panel may be 7T1C (that is, seven transistors and one transistor).
  • the structure of the capacitor may also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors. .
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure.
  • one pole is directly described as the first pole and the other pole is the second pole. Therefore, all or part of the transistors in the embodiments of the present disclosure have the first pole and the second pole.
  • the first pole and the second pole are interchangeable as needed.
  • the embodiment of the present disclosure also provides a display device including any of the above-mentioned display panels.
  • the display device includes an OLED display device, but is not limited thereto.
  • the display device may also include a liquid crystal display device.
  • display devices include OLED display devices, liquid crystal display devices, or computers, mobile phones, watches, electronic picture frames, navigators, and other products or devices with display functions that include these display devices.

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Abstract

一种显示面板(DPN)和显示装置，显示面板(DPN)，包括：显示部(DP)，包括多条数据线(DL)；展开部(FP)，包括多条展开线(FL)；以及引线部(WP)，包括多条第一引线(WRG1)，多条第一引线(WRG1)与多条数据线(DL)分别通过多条展开线(FL)相连，多条展开线(FL)在引线部(WP)和显示部(DP)之间展开设置；多条第一引线(WRG1)的每个包括第一引线子部(WS1)和补偿部(CMP)以形成多个第一引线子部(WS1)和多个补偿部(CMP)，多个第一引线子部(WS1)与多个补偿部(CMP)分别相连，在显示面板(DPN)的平面图中，在垂直于第一引线(WRG1)的延伸方向的方向上，第一引线子部(WS1)的宽度和补偿部(CMP)的宽度不同。

Description

显示面板和显示装置 技术领域
本公开的实施例涉及一种显示面板和显示装置。
背景技术
随着有源矩阵有机发光二极管(Active-matrix organic light-emitting diode，AMOLED)在显示领域的迅猛发展，良率的提升迫在眉睫。
发明内容
本公开的实施例提供一种显示面板和显示装置。
本公开的至少一实施例提供一种显示面板，包括：显示部，包括多条数据线和多个像素，所述多条数据线和所述多个子像素电连接，所述多条数据线被配置为向所述多个子像素提供数据信号；展开部，包括多条展开线，至少部分展开线的延伸方向和所述数据线的延伸方向不同；以及引线部，包括多条第一引线，所述多条第一引线与所述多条数据线分别通过所述多条展开线相连，所述多条展开线在所述引线部和所述显示部之间展开设置，所述第一引线的延伸方向与所述数据线的延伸方向相同，所述多条数据线中相邻数据线之间的间距大于所述多条第一引线中相邻第一引线之间的间距；所述多条第一引线的每个包括第一引线子部和补偿部以形成多个第一引线子部和多个补偿部，所述多个第一引线子部与所述多个补偿部分别相连，在所述显示面板的平面图中，在垂直于所述第一引线的延伸方向的方向上，所述第一引线子部的宽度和所述补偿部的宽度不同。
在本公开的一个或多个实施例中，所述多条数据线中的至少一条与所述多条展开线中的至少一条的夹角为钝角。
在本公开的一个或多个实施例中，所述第一引线子部比所述补偿部更靠近所述展开部，所述第一引线子部的宽度小于所述补偿部的宽度。
在本公开的一个或多个实施例中，相邻的补偿部的宽度相同。
在本公开的一个或多个实施例中，相邻的补偿部在沿所述第一引线的延伸方向上的长度不同。
在本公开的一个或多个实施例中，沿着所述多条第一引线的排列方向，所述多个补偿部的长度逐渐变化。
在本公开的一个或多个实施例中，所述多条第一引线的个数为n，所述多个补偿部中长度最大的补偿部的长度为H，所述多个补偿部的长度渐变量为Δ(H/n)。
在本公开的一个或多个实施例中，所述显示面板具有中心线，所述中心线的延伸方向与所述第一引线的延伸方向相同，从所述显示面板的边缘到所述中心线的方向上，所述多个补偿部的长度逐渐减小。
在本公开的一个或多个实施例中，所述显示面板具有中心线，所述中心线的延伸方向与所述第一引线的延伸方向相同，从所述显示面板的边缘到所述中心线的方向上，所述多个补偿部的长度逐渐减小再逐渐增大。
在本公开的一个或多个实施例中，所述多个补偿部在沿所述第一引线的延伸方向上的长度相同，并且所述多个补偿部的宽度逐渐变化。
在本公开的一个或多个实施例中，所述多个补偿部在沿所述第一引线的延伸方向上的长度逐渐变化，并且所述多个补偿部的宽度逐渐变化。
在本公开的一个或多个实施例中，所述第一引线还包括第二引线子部，所述第二引线子部与所述补偿部相连，所述第二引线子部的宽度小于所述补偿部的宽度，所述第二引线子部位于所述补偿部远离所述显示部的一侧。
在本公开的一个或多个实施例中，显示面板还包括多条第二引线，所述第二引线的宽度各处相同。
在本公开的一个或多个实施例中，显示面板还包括接垫部，所述接垫部被配置为与外接电路相连，所述接垫部包括多个接垫，并位于所述引线部的远离所述展开部的一侧，所述多个接垫与所述多条第一引线电连接。
在本公开的一个或多个实施例中，所述引线部提供为多个，所述多个引线部相对于所述显示面板的中心线对称设置。
在本公开的一个或多个实施例中，所述多个引线部包括第一引线部和第二引线部，所述第一引线部的多个补偿部的面积之和与所述第二引线部的多个补偿部的面积之和不同。
在本公开的一个或多个实施例中，从所述显示面板的边缘到所述中心线的方向上，所述引线部的所述多个补偿部的面积之和逐渐增大。
在本公开的一个或多个实施例中，从所述显示面板的边缘到指向所述中心线的方向上，靠近所述中心线的引线部的所述多个补偿部的面积之和大于远离所述中心线的引线部的所述多个补偿部的面积之和。
在本公开的一个或多个实施例中，相邻引线部之间具有间隔，所述间隔的宽度大于所述引线部中相邻的第一引线之间的间距。
在本公开的一个或多个实施例中，显示面板还包括第一电源总线，所述第一电源总线位于所述显示部的一侧且与所述多条展开线至少部分重叠，所述第一电源总线包括第一部分、第二部分以及连接所述第一部分和所述第二部分的连接线，所述连接线与所述间隔重叠。
在本公开的一个或多个实施例中，所述第一电源总线的所述第二部分位于所述第一电源总线的所述第一部分的远离所述显示部的一侧。
在本公开的一个或多个实施例中，显示面板还包括从所述第一电源总线延伸出的多条第一电源线，其中，所述多条第一电源线延伸到所述显示部，被配置为向所述多个子像素提供第一电源信号。
在本公开的一个或多个实施例中，显示面板还包括围绕所述显示部的第二电源信号线，所述第二电源信号线中的至少部分与所述间隔重叠，所述第二电源信号线被配置为向所述多个子像素提供第二电源信号。
在本公开的一个或多个实施例中，所述多条展开线包括交替设置的多条第一展开线和多条第二展开线，所述多条第一展开线和所述多条第二展开线位于不同层，所述多条第一引线包括交替设置的多条第一类型的第一引线和多条第二类型的第一引线，所述多条第一类型的第一引线分别与所述多条第一展开线相连，并与所述多条第一展开线位于同一层，所述多条第二类型的第一引线分别与所述多条第二展开线相连，并与所述多条第二展开线位于同一层。
在本公开的一个或多个实施例中，所述多个子像素中的至少一个包括薄膜晶体管和存储电容；所述薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的第一栅绝缘层，位于所述第一栅绝缘层远离所述衬底基板一侧的栅极，位于所述栅极远离所述衬底基板一侧的第二栅绝缘层，位于所述第二栅绝缘层远离所述衬底基板一侧的层间绝缘层，以及位于所述层间绝缘层远离所述衬底基板一侧的源极和漏极；所述存储电容包括第一极板和第二极板，所述第一极板和所述栅极位于同一层，所述第 二极板位于所述第二栅绝缘层和所述层间绝缘层之间；所述多条第一展开线、所述栅极以及所述第一极板位于同一层，所述多条第二展开线与所述第二极板位于同一层。
本公开的至少一实施例还提供一种显示装置，包括上述任一显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示面板的周边区的示意图；
图2为一种显示面板的周边区的示意图；
图3为一种显示面板的示意图；
图4为一种显示面板的数据线的电阻分布示意图；
图5为一种显示面板的平面图；
图6是本公开一实施例提供的一种显示面板的平面图；
图7为本公开一实施例提供的一种显示面板的局部示意图；
图8为图7中的中心线左侧的引线部的示意图；
图9为本公开的实施例提供的显示面板的数据线的电阻分布示意图；
图10为本公开的实施例提供的显示面板的局部平面图；
图11为本公开的实施例提供的显示面板的局部平面图；
图12为本公开的实施例提供的显示面板的局部平面图；
图13为本公开的实施例提供的一种显示面板的局部平面图；
图14为本公开的实施例提供的一种显示面板的局部平面图；
图15为本公开的实施例提供的一种显示面板的局部平面图；
图16为本公开的实施例提供的一种显示面板的平面图；
图17为本公开的实施例提供的一种显示面板的局部平面图；
图18为本公开的实施例提供的一种显示面板的局部平面图；
图19为本公开的实施例提供的一种显示面板的局部平面图；
图20为本公开的实施例提供的一种显示面板的局部平面图；
图21为本公开的实施例提供的一种显示面板的局部平面图；
图22为图21中数据选择器的放大示意图；以及
图23为本公开一实施例提供的显示面板的剖视图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
由于AMOLED的集成电路(integrated circuit，IC)驱动技术还不成熟，源极(Source)线之间的电阻差异，会影响显示画面的显示效果，表现为显示画面发红以及列方向的亮线。
通常通过Gamma校正来调控显示画面。但由于技术条件的限制，Gamma校正的调节能力有限。
因此，需要在版图设计中就要考虑数据线之间的电阻差异给画面显示带来的负面影响。在面板设计过程中可在数据线变化差异较大的地方做补偿，使得电阻变化趋于平缓，这样有利于显示画面的均一性，能获得更佳的用户体验。
图1为一种显示面板的周边区的示意图。周边区包括引线区WR和展开(Fan out)区FR。图1示出了8个展开子区：子区A、子区B、子区C、子区D、子区E、子区F、子区G和子区H。展开区FR分成多个展开子区，从而，减小纵向边框。相邻子区对应的引线之间具有间隔，图1示出了7个 间隔：间隔1、间隔2、间隔3、间隔4、间隔5、间隔6和间隔7。数据线的电阻突变的位置在间隔1、间隔2、间隔3、间隔4、间隔5、间隔6和间隔7处。在未进行补偿时这几处的电阻会表现出突变。例如，间隔位置处可用于设置电源线的一部分，能减小寄生电容。电源线包括后续提及的第一电源信号线和第二电源信号线至少之一。
图2为一种显示面板的周边区的示意图。图2示出了展开区FR内的展开线FL和引线区WR内的引线WRG。为了图示清晰，图2中未示出全部的展开线FL和全部的引线WRG。展开线FL和引线WRG的个数可根据需要而定。
图3为一种显示面板的示意图。如图3所示，显示面板包括显示区DR、展开区FR和引线区WR。显示区DR包括数据线DL。展开区FR包括展开线FL。引线区WR包括引线WRG。展开线FL与显示区DR的数据线DL相连，显示区DR位于展开区FR的远离引线区WR的一侧。即展开区FR位于显示区DR和引线区WR之间。
例如，如图2和图3所示，每个展开子区的多条引线WRG中，每条引线WRG的宽度为2μm左右，相邻的引线WRG之间的间距为16μm左右，但不限于此。
图4为一种显示面板的数据线的电阻分布示意图。如图4所示，在7个间隔位置处，数据线的电阻差异较大，容易产生显示画面发红以及列方向的亮线，影响显示画面的显示效果。
因此，在版图设计中需要考虑数据线之间的电阻差异给画面显示带来的负面影响。在本公开的实施例提供的显示面板中，在面板设计中，在数据线电阻变化差异较大的地方做补偿，使得数据线的电阻变化趋于平缓，这样有利于显示画面的均一性，能获得更佳的用户体验。
图5为一种显示面板的平面图。如图5所示，显示面板DPN包括显示区DR、展开区FR、引线区WR和接垫区PDR。沿Y方向，显示区DR、展开区FR、引线区WR和接垫区PDR依次设置。显示区DR设有显示部DP，显示部DP包括数据线DL，展开区FR设有展开部FP，展开部FP包括展开线FL，引线区WR设有引线部WP，引线部WP包括引线WRG。
如图5所示，引线区WR包括多条引线WRG，展开区FR包括多条展开 线FL，引线区WR的多条引线WRG通过展开区FR的多条展开线FL分别相连，多条展开线FL与显示区DR的多条数据线DL分别相连。多条展开线FL从靠近引线部WP的位置处向靠近显示部DP的位置处逐渐分散。即，多条展开线FL从靠近显示部DP的位置处向靠近引线部WP的位置处逐渐靠拢。
如图5所示，显示面板包括衬底基板BS，数据线DL、展开线FL和引线WRG设置在衬底基板BS上，数据线DL位于显示区DR，数据线DL通过展开线FL与引线WRG相连，引线WRG延伸至接垫区PDR。如图5所示，多条引线WRG沿X方向依次设置。例如，X方向与Y方向交叉。进一步例如，X方向与Y方向垂直。本公开的实施例以X方向与Y方向垂直为例进行说明。如图5所示，引线WRG沿Y方向延伸，数据线DL沿Y方向延伸。例如，多条数据线DL彼此平行，但不限于此。
如图5所示，多条引线WRG沿X方向排列，每条引线WRG沿Y方向延伸。例如，多条引线WRG彼此平行，但不限于此。本公开的实施例中，引线WRG沿X方向的尺寸为宽度，引线WRG沿Y方向的尺寸为长度。
如图5所示，多条数据线DL沿X方向排列，每条数据线DL沿Y方向延伸。例如，多条数据线DL的宽度相同，且长度相同，但不限于此。
如图5所示，展开线FL与Y方向不平行，并且与X方向不平行。当然，在其他的实施例中，显示面板也可以具有与Y方向平行的展开线FL。
如图5所示，在显示面板DPN中，显示部DP还包括子像素SP，子像素SP与数据线DL相连。如图5所示，显示面板DPN包括多个子像素SP。一条数据线DL与一列子像素SP相连。例如，多个子像素SP呈阵列排列，但不限于此。图5中以多个子像素SP呈矩阵排列为例进行说明。
图6是本公开一实施例提供的一种显示面板的平面图。如图6所示，显示面板包括显示部DP、展开部FP和引线部WP。显示部DP位于显示区DR，展开部FP位于展开区FR，引线部WP位于引线区WR。显示部DP包括多条数据线DL。展开部FP包括多条展开线FL。引线部WP包括多条第一引线WRG1。多条第一引线WRG1与多条数据线DL分别通过多条展开线FL分别相连。多条展开线FL在引线部WP和显示部DP之间展开设置。例如，第一引线WRG1的延伸方向与数据线DL的延伸方向相同。本公开的实施例 中，两条线的延伸方向相同包括两条线的延伸方向完全相同和大致相同，以下有关描述，可参照此处说明。多条展开线FL从引线部WP至显示部DP的方向分散设置。多条展开线FL从靠近引线部WP的位置处向靠近显示部DP位置处逐渐分散。例如，同一引线部WP对应的多条展开线的长度不同，但不限于此。
如图6所示，展开区FR包括8个展开子区：子区A、子区B、子区C、子区D、子区E、子区F、子区G和子区H。
如图6所示，多条第一引线WRG1的每个包括第一引线子部WS1和补偿部CMP以形成多个第一引线子部WS1和多个补偿部CMP，多个第一引线子部WS1与多个补偿部CMP分别相连，在显示面板的平面图中，在垂直于第一引线WRG1的延伸方向的方向上，第一引线子部WS1的宽度和补偿部CMP的宽度不同。
本公开的实施例中，第一引线子部WS1的宽度和补偿部CMP的宽度不同，可以使补偿部CMP对数据线的电阻进行补偿，有效的减少数据线的电阻差异，在数据线的电阻变化差异较大的地方做电阻补偿，减小电阻突变区域的数据线的电阻的差值，使得数据线的电阻变化趋于平缓，有利于显示画面的均一性，从而获得更佳的用户体验。
如图6所示，多条第一引线WRG1沿X方向依次设置。例如，X方向与Y方向交叉。进一步例如，X方向与Y方向垂直。本公开的实施例以X方向与Y方向垂直为例进行说明。
如图6所示，第一引线WRG1沿Y方向延伸。本公开的实施例中，第一引线WRG1沿X方向的尺寸为宽度，第一引线WRG1沿Y方向的尺寸为长度。
如图6所示，多条数据线DL沿X方向排列，每条数据线DL沿Y方向延伸。例如，数据线DL被配置为向子像素输入数据信号。例如，数据信号包括电压。例如，数据线DL与薄膜晶体管的源极或者漏极相连，并被配置为向薄膜晶体管的源极或漏极输入数据信号。例如，在数据线DL与源极相连的情况下，数据线DL与源极一体形成，在数据线DL与漏极相连的情况下，数据线DL与漏极一体形成。例如，数据线DL被配置为向数据写入晶体管的源极或漏极输入数据电压。例如，显示面板包括多个子像素，多条数 据线DL和多个子像素电连接，每条数据线与一列子像素相连，并被配置为向子像素提供数据信号。例如，每条数据线被配置为向开启的子像素提供数据信号。例如，多个子像素形成为多行和多列。例如，显示面板为有机发光二极管显示面板，包括电容、多个薄膜晶体管以及多个发光单元，例如，显示面板可采用7T1C等结构的显示面板，但不限于此。例如，发光单元包括有机发光二极管。有机发光二极管包括阴极、发光功能层和阳极，发光功能层位于阴极和阳极之间。阳极与数据写入晶体管的源极和漏极之一相连。发光功能层至少包括发光层，还可以包括空穴传输层、空穴注入层，电子传输层、电子注入层至少之一。
如图6所示，展开线FL与Y方向不平行，并且与X方向不平行。当然，在其他的实施例中，显示面板也可以具有与Y方向平行的展开线FL。如图6所示，至少部分展开线FL的延伸方向和数据线DL的延伸方向不同。
例如，本公开的实施例中，线的延伸方向为垂直于其宽度方向的方向，但不限于此。当线不为直线时，可依据该条线的总体延伸趋势来确定其延伸方向。例如，可根据该条线的初始端和末端之间的连线来确定其延伸方向，但不限于此。
如图6所示，显示面板包括多个引线部WP。图6以显示面板包括8个引线部为例进行说明。8个引线部分别为第一引线部WP1、第二引线部WP2、第三引线部WP3、第四引线部WP4、第五引线部WP5、第六引线部WP6、第七引线部WP7和第八引线部WP8。
如图6所示，第一引线部WP1、第二引线部WP2、第三引线部WP3、第四引线部WP4的引线数量依次增大，第五引线部WP5、第六引线部WP6、第七引线部WP7和第八引线部WP8的引线数量依次减小。当然，在其他的实施例中，每个引线部中的引线数量也可不具有上述规律，可根据需要而定。
如图6所示，第一引线子部WS1比补偿部CMP更靠近展开部FP，第一引线子部WS1的宽度小于补偿部CMP的宽度。补偿部CMP的宽度大以利于减小数据线的电阻。本公开的一些实施例提供的显示面板利用增加线宽来减小数据线的电阻。
例如，在同一引线部WP中，相邻的补偿部CMP的宽度相同。例如，在所有的引线部WP中，补偿部CMP的宽度均相同。补偿部CMP的宽度相 同利于制作，利于补偿量的计算。
例如，如图6所示，相邻的补偿部CMP在沿第一引线WRG1的延伸方向上的长度不同。当然，图6所示的显示面板也可以具有长度相同的相邻的补偿部CMP。
例如，在第一引线部WP1、第二引线部WP2、第三引线部WP3、第六引线部WP6、第七引线部WP7和第八引线部WP8(除了第四引线部WP4和第五引线部WP5的引线部WP)中任一个中，沿着多条第一引线WRG1的排列方向，多个补偿部CMP的长度逐渐变化。本公开的一些实施例提供的显示面板通过长度渐变的方式进行电阻补偿以避免数据线的电阻突变。从而实现数据线的电阻变化平缓，电阻差值变小。
例如，多条第一引线WRG1的个数为n，多个补偿部CMP中长度最大的补偿部CMP的长度为H，多个补偿部CMP的长度渐变量为Δ(H/n)。
例如，如图6所示，显示面板具有中心线CL，中心线CL的延伸方向与第一引线WRG1的延伸方向相同，在第一引线部WP1、第二引线部WP2、第三引线部WP3、第六引线部WP6、第七引线部WP7和第八引线部WP8(除了第四引线部WP4和第五引线部WP5的引线部WP)中任一个中，从显示面板的边缘到中心线CL的方向D0上，多个补偿部CMP的长度逐渐减小。
例如，在第四引线部WP4和第五引线部WP5任一个中，从显示面板的边缘到中心线CL的方向D0上，多个补偿部CMP的长度逐渐减小再逐渐增大。
例如，如图6所示，第一引线WRG1还包括第二引线子部WS2，第二引线子部WS2与补偿部CMP相连，第二引线子部WS2的宽度小于补偿部CMP的宽度，第二引线子部WS2和第一引线子部WS1分别设置在补偿部CMP的两侧。第二引线子部WS2位于补偿部CMP远离显示部的一侧。设置第二引线子部WS2利于补偿部CMP的制作。
例如，如图6所示，相邻引线部WP之间具有间隔INT，间隔INT的宽度大于该相邻引线部WP中任一个之中的相邻的第一引线WRG1之间的距离。引线部WP中的相邻的第一引线WRG1之间的距离为相邻的第一引线WRG1之间的间距，为相邻的第一引线WRG1在X方向上的距离。
例如，图6示出了7个间隔INT，不同的间隔INT在X方向上的尺寸可相同，也可以不同。
例如，如图6所示，每个展开子区的多条引线WRG中，每条引线WRG除了补偿部CMP之外的部分的宽度为2μm左右，补偿部CMP的宽度为12μm左右。相邻的引线WRG除了补偿部CMP之外的部分之间的间距为16μm左右，相邻补偿部CMP之间的间距为6μm左右，但不限于此。
例如，如图6所示，每条引线WRG的长度约为900μm左右，补偿部CMP的最大长度为800μm左右，但不限于此。
例如，如图6所示，多个第一引线WRG1彼此绝缘，可被分别输入信号。
例如，如图6所示，为了减小补偿部CMP沿Y方向上的面积以减小显示面板的下边框，多个补偿部CMP在X方向上重叠。例如，多个补偿部CMP在X方向上至少部分重叠。
例如，如图6所示，第一引线WRG1为直线，数据线DL为直线，但不限于此。图6中以直线形式表示展开线FL，但并不限于此，展开线FL不限于直线，还可以为曲线、弧线等其他形式的线。参照图7，在显示面板的左右两侧，展开线FL为弧线形式。
在其他的实施例中，靠近显示面板边缘的引线部WP也可以不进行电阻补偿。例如，图6所示的显示面板中，第一引线部WP1和第八引线部WP8中的引线不进行电阻补偿，即，第一引线部WP1和第八引线部WP8中的每条引线在X方向上的宽度在各处均相同。第一引线部WP1和第八引线部WP8中的引线为后续提及的第二引线WRG2。
如图6所示，数据线DL与展开线FL之间具有夹角，该夹角大于90度，且小于180度，即该夹角为钝角。相应地，因数据线DL的延伸方向与第一引线WRG1的延伸方向相同。第一引线WRG1与展开线FL之间也具有夹角，该夹角也大于90度，且小于180度。如图6所示，因展开线FL在展开区FR展开，从而，相邻两条展开线FL之间的间距从显示区指向引线区的方向上逐渐减小。例如，如图6所示，同一个展开子区内，每相邻两条数据线DL之间的间距相等，每相邻两条第一引线WRG1之间的间距相等。多条数据线DL中的至少一条与多条展开线FL中的至少一条的夹角为钝角。图6中以展开线FL为直线示意性描述，展开线FL也可以为曲线，当展开线FL为曲线 的情况下，数据线DL与展开线FL之间的夹角为数据线DL与曲线形式的展开线FL的切线的夹角。如图6所示，多条数据线DL中相邻数据线DL之间的间距大于多条第一引线WRG1中相邻第一引线WRG1之间的间距。
图7为本公开一实施例提供的一种显示面板的局部示意图。为了图示清晰，图7没有示出显示区及显示区内的部件。
例如，如图6和图7所示，第一引线部WP1的多个补偿部CMP的面积之和为A1，第二引线部WP2的多个补偿部CMP的面积之和为A2，第三引线部WP3的多个补偿部CMP的面积之和为A3，第四引线部WP4的多个补偿部CMP的面积之和为A4，从图6和图7可以看出，A1、A2、A3、A4依次增大。
例如，如图6和图7所示，第五引线部WP5的多个补偿部CMP的面积之和为A5，第六引线部WP6的多个补偿部CMP的面积之和为A6，第七引线部WP7的多个补偿部CMP的面积之和为A7，第八引线部WP8的多个补偿部CMP的面积之和为A8，从图6和图7可以看出，A5、A6、A7、A8依次减小。
例如，如图6和图7所示，多个引线部WP相对于显示面板的中心线CL对称设置。此情况下，A1＝A8，A2＝A7，A3＝A6，A4＝A5。
例如，如图6和图7所示，从显示面板的边缘到中心线CL的方向D0上，第一引线部WP1至第四引线部WP4中，多个补偿部CMP的面积之和逐渐增大。即，A1、A2、A3、A4依次增大。
例如，如图6和图7所示，从显示面板的边缘到中心线CL的方向D0上，从第五引线部WP5至第八引线部WP8中，多个补偿部CMP的面积之和逐渐减小。即，A8、A7、A6、A5依次增大。
例如，如图6和图7所示，从显示面板的边缘到指向中心线CL的方向上，靠近中心线CL的引线部WP的多个补偿部CMP的面积之和大于远离中心线CL的引线部WP的多个补偿部CMP的面积之和。例如，A4＞A3＞A2＞A1。例如，A5＞A6＞A7＞A8。
例如，如图6和图7所示，第一引线部WP1至第四引线部WP4中，补偿部CMP的宽度均相同，从显示面板的边缘到中心线CL的方向D0上，每个引线部中具有最大长度的补偿部CMP的长度依次增大。如图6和图7所示，第一引线部WP1中具有最大长度的补偿部CMP为距离中心线CL最远 的补偿部CMP，第二引线部WP2中具有最大长度的补偿部CMP为距离中心线CL最远的补偿部CMP，第三引线部WP3中具有最大长度的补偿部CMP为距离中心线CL最远的补偿部CMP，第四引线部WP4中具有最大长度的补偿部CMP为距离中心线CL最近的补偿部CMP。因显示面板相对于中心线CL对称设置，由此可相应推知第五引线部WP5至第八引线部WP8中具有最大长度的补偿部CMP的情况。
图8为图7中的中心线左侧的引线部的示意图。图8还示出了相邻引线部之间的间隔INT。
图9为本公开的实施例提供的显示面板的数据线的电阻分布示意图。通过补偿之后的数据线电阻分布如图9所示，与图4未经电阻补偿的显示面板对比，经过补偿的数据线的整体电阻差异变小。如图9所示，在本公开的实施例提供的显示面板中，在7个间隔位置处，电阻变化也趋于平缓，数据线的电阻差异较小，补偿效果显著，避免产生显示画面发红以及列方向的亮线，提高显示画面的显示效果。
图10为本公开的实施例提供的显示面板的局部平面图。例如，图10为第二引线部WP2和第三引线部WP3的平面图。从图10可以看出，补偿部CMP的宽度均相同，从显示面板的边缘到中心线CL的方向D0上，第二引线部WP2中，补偿部CMP的长度依次减小，并且从显示面板的边缘到中心线CL的方向D0上，第三引线部WP3中，补偿部CMP的长度依次减小。如图10所示，从显示面板的边缘到中心线CL的方向D0上，每个引线部中具有最大长度的补偿部CMP的长度依次增大。第三引线部WP3中具有最大长度的补偿部CMP的长度大于第二引线部WP2中具有最大长度的补偿部CMP的长度。当然，图10中的第二引线部WP2和第三引线部WP3可分别替换为第一引线部WP1和第二引线部WP2。
图11为本公开的实施例提供的显示面板的局部平面图。例如，图11为第四引线部WP4的平面图。从图11可以看出，补偿部CMP的宽度均相同，从显示面板的边缘到中心线CL的方向D0上，第四引线部WP4中，补偿部CMP的长度依次减小再依次增大，最左侧的补偿部CMP的长度小于最右侧的补偿部CMP的长度。
图12为本公开的实施例提供的显示面板的局部平面图。与图11相比， 第四引线部WR4还包括第二引线WRG2。第二引线WRG2的宽度各处相同，即，第二引线WRG2不具有补偿部。图12示出了一个第二引线WRG2，但第二引线WRG2的个数不限于此。第二引线WRG2的个数可根据需要而定。例如，显示面板还包括多条第二引线WRG2，每个第二引线WRG2的宽度各处相同。例如，多条第二引线WRG2可依次排列，相邻的第二引线WRG2之间不设置具有补偿部的引线。例如，每条第二引线WRG2通过展开线与显示区的数据线相连。
图13为本公开的实施例提供的一种显示面板的局部平面图。与图11相比，显示面板还包括接垫部PDP，接垫部PDP被配置为与外接电路相连。接垫部PDP包括多个接垫PD，位于接垫区PDR，并位于引线部WP的远离展开部FP的一侧。外接电路被配置为通过多个接垫PD向多条数据线分别输入信号。多个接垫PD与多条第一引线WRG1电连接。在其他的实施例中，显示面板也可以包括接垫部PDP。即，在每条引线的远离数据线DL的一侧设置接垫PD。
本公开一些实施例提供一种显示面板，补偿部采用等宽度长度渐变的方式进行补偿，以利于数据线电阻的补偿，减小数据线电阻的差异。以下对该结构的显示面板进行详细介绍。例如，数据线的电阻差异大体源于展开区内的展开线的长度的差异，从而对数据线的电阻补偿也可看作是对展开区的展开线的电阻补偿。
图14为本公开的实施例提供的一种显示面板的局部平面图。图14示出了相邻的引线部WP之间的间隔INT，该间隔INT可为图6或图7中间隔1、间隔2、间隔3任一位置处的平面图。如图14所示，位于右侧的引线部WP包括多条第一引线WRG1。第一引线WRG1包括第一引线子部WS1、补偿部CMP和第二引线子部WS2。多条第一引线WRG1的补偿部CMP采用宽度相等长度渐变的补偿方式对数据线进行电阻补偿。如图14所示，位于左侧的引线部WP包括第二引线WRG2。第二引线WRG2不具有补偿部，在各处宽度相等。
图15为本公开的实施例提供的一种显示面板的局部平面图。图15所示的引线部可为图6或图7中的第四引线部WP4。第四引线部WP4包括多条第一引线WRG1，第一引线WRG1包括第一引线子部WS1、补偿部CMP和 第二引线子部WS2。图15中示出了两个补偿单元CP1和CP2。两个补偿单元CP1和CP2之间具有在各处宽度相等的第二引线WRG2。补偿单元CP1和补偿单元CP2中补偿部均采用宽度相等长度渐变的补偿方式对数据线进行电阻补偿。补偿单元CP1中，补偿部的长度逐渐减小，补偿单元CP2中，补偿部的长度逐渐增大。即在第四引线部WP4中，补偿部的长度先逐渐减小再逐渐增大。
本公开的实施例以对子区A至子区H(参见图6)内的展开线对应的数据线进行电阻补偿为例。该种电阻补偿的方式为补偿部的宽度相等长度渐变。
1.对子区A内的展开线对应的数据线的补偿，从左起第一条数据线开始做补偿，以可以补偿的最大电阻为起始补偿，但不限于此，起始补偿的量也可以小于可以补偿的最大电阻。可以补偿的最大电阻可根据位于引线区的引线的宽度和长度进行确定。即，根据引线的最大长度以及工艺允许条件下的引线的最大宽度获得可以补偿的最大电阻。补偿部采用相同的宽度。补偿部的线宽为W。长度最大的补偿部的线长为H1，子区A对应的数据线的条数为n1，依次补偿的线长渐变量为Δ(H1/n1)。子区A对应的第一引线部中第1个补偿部的线宽为W，线长为H1，第2个补偿部的线宽为W，线长为H1-Δ(H1/n1)，第3个补偿部的线宽为W，线长为H1-2*Δ(H1/n1)，第k个补偿部的线宽为W，线长为H1-(k-1)*Δ(H1/n1)，以类似的方式依次补偿一直到第n1个补偿部，即可完成子区A对应的数据线的电阻补偿。
2.对子区B内的展开线对应的数据线的补偿，从左起第一条数据线开始做补偿，以可以补偿的最大电阻为起始补偿。例如，补偿的最大电阻为未进行补偿的情况下相邻引线部(第一引线部和第二引线部)的最靠近其间的间隔1的两条数据线的电阻差值。例如，最大补偿电阻为在电阻突变的间隔1位置处，左右两侧的引线对应的数据线的电阻差值R1。补偿部采用相同的宽度。补偿部的线宽为W。长度最大的补偿部的线长为H2，子区B对应的数据线的条数为n2，依次补偿的线长渐变量为Δ(H2/n2)。子区B对应的第二引线部中左起第1个补偿部的线宽为W，线长为H2，第2个补偿部的线宽为W，线长为H2-Δ(H2/n2)，第3个补偿部的线宽为W，线长为H2-2*Δ(H2/n2)，第k个补偿部的线宽为W，线长为H2-(k-1)*Δ(H2/n2)。以类似的方式依次补偿一直到第n2个补偿部，即可完成子区B对应的数据线 的电阻补偿。
3.对子区C内的展开线对应的数据线的补偿，从左起第一条数据线开始做补偿，以可以补偿的最大电阻为起始补偿。例如，补偿的最大电阻为未进行补偿的情况下相邻引线部(第二引线部和第三引线部)的最靠近其间的间隔2的两条数据线的电阻差值。例如，最大补偿电阻为在电阻突变的间隔2位置处，左右两侧的引线对应的数据线的电阻差值R2。补偿部采用相同的宽度。补偿部的线宽为W。长度最大的补偿部的线长为H3。子区C对应的数据线的条数为n3，依次补偿的线长渐变量为Δ(H3/n3)。子区C对应的第三引线部中从左起第一条数据线对应的补偿部的线宽为W，线长为H3，第2个补偿部的线宽为W，线长为H3-Δ(H3/n3)，第3个补偿部的线宽为W，线长为H3-2*Δ(H3/n3)，第k个补偿的线宽为W，线长为H3-(k-1)*Δ(H3/n3)。依次一直到第n3个补偿部，即可完成子区C对应的数据线的电阻补偿。
4.对子区D内的展开线对应的数据线的补偿，从子区D左右两边数据线开始做补偿，补偿到子区D中间电阻最小处，子区D左侧对应的数据线的补偿电阻的大小为电阻突变的间隔3位置处左右两侧的引线对应的数据线的电阻差值R3，该补偿部的线宽为W，线长为H4；子区D右侧对应的数据线的补偿电阻以可以补偿的最大电阻为起始补偿，该补偿线宽为W，线长为H5，子区D对应的数据线从左侧到中间电阻最小处的个数为n4，依次补偿的线长渐变量为Δ(H4/n4)。子区D对应的第四引线部中的左起第1个补偿部的线宽为W，线长为H4，第2个补偿部的线宽为W，线长为H4-Δ(H4/n4)，第3个补偿部的线宽为W，线长为H4-2*Δ(H4/n4)，第k个补偿的线宽为W，线长为H4-(k-1)*Δ(H4/n4)，以类似的方式依次补偿一直到第n4个补偿部；子区D的数据线从右侧到中间电阻最小处的个数为n5，依次补偿的线长渐变量为Δ(H5/n5)。子区D对应的第四引线部的右起第1个补偿部的线宽为W，线长为H5，第2个补偿部的线宽为W，线长为H5-Δ(H5/n5)，第3个补偿部的线宽为W，线长为H5-2*Δ(H5/n5)，第k个补偿部的线宽为W，线长为H5-(k-1)*Δ(H5/n5)，以类似的方式依次一直到第n5个补偿部。即可完成子区D对应的数据线的电阻补偿。
5.对子区E内的展开线对应的数据线的补偿：子区D对应的第四引线 部中的补偿部关于显示面板的中心线做镜像对称即可。
6.对子区F内的展开线对应的数据线的补偿：子区C对应的第三引线部中的补偿部关于显示面板的中心线做镜像对称即可。
7.对子区G内的展开线对应的数据线的补偿：子区B对应的第二引线部中的补偿部关于显示面板的中心线做镜像对称即可。
8.对子区H内的展开线对应的数据线的补偿：子区A对应的第一引线部中的补偿部关于显示面板的中心线做镜像对称即可。
当显示面板的展开区包括其他数量的子区时，可以相同的补偿方式进行电阻补偿。
例如，显示面板中所有的补偿部的宽度均相等。即，不同的引线部中的补偿部的宽度相等。
例如，各个引线部中，长度最长的补偿部的线长关系如下：H1＜H2＜H3＜H4＜H5。
例如，引线WRG制作的方法包括：形成导电层，在导电层上形成光刻胶层，对光刻胶层进行曝光、显影获得光刻胶图案，以光刻胶图案为掩膜版对导电层进行刻蚀，以获得引线。因为本公开的实施例具有设置补偿部的引线，可根据补偿部的构造设计掩膜版。
本公开的一些实施例提供的显示面板通过线宽不变线长渐变的方式来进行数据线的电阻补偿，掩膜版易于制作，更有利于工艺实现。
图16为本公开的实施例提供的一种显示面板的平面图。图16所示的显示面板与图6所示的显示面板相比，区别在于补偿部的补偿方式有变化。图16所示的显示面板在同一引线部中，采用补偿部的长度相等宽度渐变的方式进行补偿。
例如，如图16所示，显示面板中，除了第四引线部WP4和第五引线部WP5之外，从显示面板的边缘到中心线CL的方向D0上，多个补偿部CMP的宽度逐渐减小。
例如，在第四引线部WP4和第五引线部WP5任一个中，从显示面板的边缘到中心线CL的方向D0上，多个补偿部CMP的宽度逐渐减小再逐渐增大。
本公开的一些实施例提供的显示面板采用线长度相等且线宽渐变的方式进行电阻补偿。以下对该结构的显示面板进行介绍。
1.对子区A内的展开线对应的数据线的补偿，从左起第一条数据线开始做补偿，以可以补偿的最大电阻为起始补偿。左起第一条数据线对应的第一引线部中的补偿部的线宽为W1，线长为H1，子区A内的数据线的条数为n1，依次补偿的线宽渐变量为Δ((W1-w)/n1)，其中w为数据线的线宽。第1个补偿部的线宽为W1，线长为H1，第2个补偿部的线宽为W1-Δ((W1-w)/n1)，线长为H1，第3个补偿部的线宽为W1-2*Δ((W1-w)/n1)，线长为H1，第k个补偿部的线宽为W1-(k-1)*Δ((W1-w)/n1)，线长为H1。依次补偿一直到第n1个补偿部，即可完成子区A对应的数据线的电阻补偿。
2.对子区B内的展开线对应的数据线的补偿，从左起第一条数据线开始做补偿，子区B对应的第二引线部中最左侧的补偿部的补偿电阻的大小为电阻突变的间隔1处左右两侧数据线的电阻差值R1。左起第一条数据线对应的补偿部的线宽为W2，线长为H2，子区B对应的数据线的条数为n2，依次补偿的线长渐变量为Δ((W2-w)/n2)，其中w为数据线的线宽。子区B对应的第二引线部中左起第1个补偿部的线宽为W2，线长为H2，第2个补偿部的线宽为W-Δ((W2-w)/n2)，线长为H2，第3个补偿部的线宽为W2-2*Δ((W2-w)/n2)，线长为H2，第k个补偿的线宽为W-(k-1)*Δ((W2-w)/n2)，线长为H2。以类似方式依次补偿一直到第n2个补偿部，即可完成子区B对应的数据线的电阻补偿。
3.对子区C内的展开线对应的数据线的补偿，从左起第一条数据线开始做补偿，子区C对应的第三引线部中最左侧的补偿部的补偿电阻的大小为电阻突变的间隔3位置处左右两侧的引线对应的数据线的电阻差值R2。该补偿线宽为W3，线长为H3，子区C对应的数据线的个数为n3，依次补偿的线宽渐变量为Δ((W3-w)/n3)，其中w为数据线的线宽。子区C左起第1个补偿部的线宽为W3，线长为H3，第2个补偿部的线宽为W-Δ((W3-w)/n3)，线长为H3，第3个补偿部的线宽为W3-2*Δ((W3-w)/n3)，线长为H3，第k个补偿部的线宽为W3-(k-1)*Δ((W3-w)/n3)，线长为H3。依次一直补偿到第n3根即可完成子区C对应的数据线的电阻补偿。
4.对子区D内的展开线对应的数据线的补偿，从子区D左右两边数据线开始做补偿，补偿到子区D中间电阻最小处的数据线，子区D对应的第四 引线部中最左侧的补偿部的补偿电阻的大小为电阻突变的间隔3位置处左右两侧的引线对应的数据线的电阻差值R3，子区D对应的第四引线部中最左侧的补偿部的线宽为W4，线长为H4。子区D对应的第四引线部中最对应的第四引线部中最右侧的补偿部的补偿电阻以可以补偿的最大电阻为起始补偿，该补偿线宽为W5，线长为H5，子区D对应的数据线从左侧到中间电阻最小处的个数为n4，依次补偿的线宽渐变量为Δ((W4-w)/n4)，其中w为数据线的线宽。子区D左起第1个补偿部的线宽为W4，线长为H4，第2个补偿部的线宽为W4-Δ((W4-w)/n4)，线长为H4，第3个补偿部的线宽为W4-2*Δ((W4-w)/n4)，线长为H4，第k个补偿部的线宽为W4-(k-1)*Δ((W4-w)/n4)，线长为H4，依次一直补偿到第n4根；子区D对应的数据线从右侧到中间电阻最小处的个数为n5，依次补偿的线宽渐变量为Δ((W5-w)/n5)，其中w为数据线的线宽。子区D对应的第四引线部中右起第1个补偿部的线宽为W5，线长为H5，第2个补偿部的线宽为W5-Δ((W5-w)/n5)，线长为H5，第3个补偿部的线宽为W5-2*Δ((W5-w)/n5)，线长为H5，第k个补偿部的线宽为W5-(k-1)*Δ((W5-w)/n5)，线长为H5，以类似方式依次补偿一直到第n5个补偿部，即可完成子区D对应的数据线的电阻补偿。
5.对子区E内的展开线对应的数据线的补偿：子区D对应的第四引线部中的补偿部关于显示面板的中心线做镜像对称即可。
6.对子区F内的展开线对应的数据线的补偿：子区C对应的第三引线部中的补偿部关于显示面板的中心线做镜像对称即可。
7.对子区G内的展开线对应的数据线的补偿：子区B对应的第二引线部中的补偿部关于显示面板的中心线做镜像对称即可。
8.对子区H内的展开线对应的数据线的补偿：子区A对应的第一引线部中的补偿部关于显示面板的中心线做镜像对称即可。
9.若显示面板包括更多的子区，以相同的补偿方式补偿其余子区的展开线的电阻补偿即可。
例如，显示面板中所有的补偿部的长度均相等。即，不同的引线部中的补偿部的长度相等。
例如，多个补偿部CMP在沿第一引线WRG1的延伸方向上的长度相同，多个补偿部CMP的宽度渐变。例如，不同的引线部中，最大宽度的补偿部 的线宽关系如下：W1＜W2＜W3＜W4＜W5。
图17为本公开的实施例提供的一种显示面板的局部平面图。图17示出了相邻的引线部WP之间的间隔INT，该间隔INT可为图16中间隔1、间隔2、间隔3任一位置处的平面图。如图17所示，位于右侧的引线部WP包括多条第一引线WRG1。第一引线WRG1包括第一引线子部WS1、补偿部CMP和第二引线子部WS2。多条第一引线WRG1的补偿部CMP采用宽度渐变长度相等的补偿方式对数据线进行电阻补偿。如图17所示，位于左侧的引线部WP包括第二引线WRG2。第二引线WRG2不具有补偿部，在各处宽度相等。
图18为本公开的实施例提供的一种显示面板的局部平面图。图18所示的引线部可为图16中的第四引线部WP4。第四引线部WP4包括多条第一引线WRG1，第一引线WRG1包括第一引线子部WS1和补偿部CMP。图18中示出了两个补偿单元CP1和CP2。两个补偿单元CP1和CP2之间具有在各处宽度相等的第二引线WRG2。补偿单元CP1和补偿单元CP2中补偿部均采用宽度渐变且长度相等的补偿方式对数据线进行电阻补偿。补偿单元CP1中，补偿部的宽度逐渐减小，补偿单元CP2中，补偿部的宽度逐渐增大。即在第四引线部WP4中，沿着引线的排列方向，补偿部的宽度先逐渐减小再逐渐增大。
本公开的另一些实施例提供的显示面板采用线长渐变且线宽渐变的方式进行电阻补偿。以下对该结构的显示面板进行介绍。
1.对子区A内的展开线对应的数据线的补偿，从左起第一条数据线开始做补偿，以可以补偿的最大电阻为起始补偿。该补偿部的线宽为W1，线长为H1，子区A对应的数据线的条数为n1，依次补偿的线宽渐变量为Δ((W1-w)/n1)，其中w为数据线的线宽；线长渐变量为Δ(H1/n1)。子区A对应的第一引线部中，第1个补偿部的线宽为W1，线长为H1，第2个补偿部的线宽为W1-Δ((W1-w)/n1)，线长为H1-Δ(H1/n1)，第3个补偿部的线宽为W1-2*Δ((W1-w)/n1)，线长为H1-2*Δ(H1/n1)，第k个补偿部的线宽为W1-(k-1)*Δ((W1-w)/n1)，线长为H1-(k-1)*Δ(H1/n1)。依次补偿一直到第n1个补偿部，即可完成子区A对应的数据线的电阻补偿。
2.对子区B内的展开线对应的数据线的补偿，从左起第一条数据线开始做补偿，补偿电阻的大小为电阻突变的间隔1位置处左右两侧的引线对应的数据线的电阻差值R1。该补偿部的线宽为W2，线长为H2，子区B对应的 数据线的条数为n2，依次补偿的线长渐变量为Δ((W2-w)/n2)，其中w为数据线的线宽；线长渐变量为Δ(H2/n2)。子区B对应的第二引线部中，左起第1个补偿部的线宽为W2，线长为H2，第2个补偿部的线宽为W-Δ((W2-w)/n2)，线长为H2-Δ(H2/n2)，第3个补偿部的线宽为W-2*Δ((W2-w)/n2)，线长为H2-2*Δ(H2/n2)，第k个补偿部的线宽为W2-(k-1)*Δ((W2-w)/n2)，线长为H2-(k-1)*Δ(H2/n2)。以类似方式依次补偿一直到第n2个补偿部，即可完成子区B对应的数据线的电阻补偿。
3.对子区C内的展开线对应的数据线的补偿，从左起第一条数据线开始做补偿，补偿电阻的大小为电阻突变的间隔2位置处左右两侧的引线对应的数据线的电阻差值R2。该补偿部的线宽为W3，线长为H3，子区C对应的数据线的个数为n3，依次补偿的线宽渐变量为Δ((W3-w)/n3)，其中w为数据线的线宽；线长渐变量为Δ(H3/n3)。子区C对应的第三引线部中，左起第1个补偿部的线宽为W3，线长为H3，第2个补偿部的线宽为W-Δ((W3-w)/n3)，线长为H3-Δ(H3/n3)，第3个补偿部的线宽为W3-2*Δ((W3-w)/n3)，线长为H3-2*Δ(H3/n3)，第k个补偿部的线宽为W3-(k-1)*Δ((W3-w)/n3)，线长为H3-(k-1)*Δ(H3/n3)。以类似方式依次补偿一直到第n3个补偿部，即可完成子区C对应的数据线的电阻补偿。
4.对子区D内的展开线对应的数据线的补偿，从子区D左右两边数据线开始做补偿，补偿到子区D中间处对应的电阻最小的数据线，子区D左侧对应的数据线的补偿电阻的大小为电阻突变的间隔3位置处左右两侧的引线对应的数据线的电阻差值R3，该数据线的补偿部的线宽为W4，线长为H4；子区D右侧对应的数据线的补偿电阻以可以补偿的最大电阻为起始补偿，该补偿线宽为W5，线长为H5，子区D对应的数据线从左侧到中间电阻最小处的个数为n4，依次补偿的线宽渐变量为Δ((W4-w)/n4)其中w为数据线的线宽；线长渐变量为Δ(H4/n4)。子区D对应的第四引线部中，左起第1个补偿部的线宽为W4，线长为H4，第2个补偿部的线宽为W4-Δ((W4-w)/n4)，线长为H4-Δ(H4/n4)，第3个补偿部的线宽为W4-2*Δ((W4-w)/n4)，线长为H4-2*Δ(H4/n4)，第k个补偿部的线宽为W4-(k-1)*Δ((W4-w)/n4)，线长为H4-(k-1)*Δ(H4/n4)，以类似方式依次补偿一直到第n4个补偿部；子区D对应的数据线从右侧到中间电阻最小处的个数为n5，依次补偿 的线宽渐变量为Δ((W5-w)/n5)其中w为数据线的线宽；线长渐变量为Δ(H5/n5)。子区D对应的第四引线部中，右起第1个补偿部的线宽为W5，线长为H5，第2个补偿部的线宽为W5-Δ((W5-w)/n5)，线长为H5-Δ(H5/n5)，第3个补偿部的线宽为W5-2*Δ((W5-w)/n5)，线长为H5-2*Δ(H5/n5)，第k个补偿部的线宽为W5-(k-1)*Δ((W5-w)/n5)，线长为H5-(k-1)*Δ(H5/n5)，以类似方式依次补偿一直到第n5个补偿部，即可完成子区D对应的数据线的电阻补偿。
5.对子区E内的展开线对应的数据线的补偿：子区D对应的第四引线部中的补偿部关于显示面板的中心线做镜像对称即可。
6.对子区F内的展开线对应的数据线的补偿：子区C对应的导线部中的补偿部关于显示面板的中心线做镜像对称即可。
7.对子区G内的展开线对应的数据线的补偿：子区B对应的第二引线部中的补偿部关于显示面板的中心线做镜像对称即可。
8.对子区H内的展开线对应的数据线的补偿：子区A对应的第四引线部中的补偿部关于显示面板的中心线做镜像对称即可。
9.若显示面板包括更多的子区，以相同的补偿方式补偿其余子区的展开线的电阻补偿即可。
图19为本公开的实施例提供的一种显示面板的局部平面图。图19示出了相邻的引线部WP之间的间隔INT，该间隔INT可为图6或图16中间隔1、间隔2、间隔3任一位置处的平面图，当然补偿部的结构与图6和图16均不同。如图19所示，位于右侧的引线部WP包括多条第一引线WRG1。第一引线WRG1包括第一引线子部WS1、补偿部CMP和第二引线子部WS2。多条第一引线WRG1的补偿部CMP采用宽度渐变且长度渐变的补偿方式对数据线进行电阻补偿。如图19所示，从左至右的方向上，补偿部的宽度逐渐减小且长度逐渐减小。如图19所示，位于左侧的引线部WP包括第二引线WRG2。第二引线WRG2不具有补偿部，在各处宽度相等。
图20为本公开的实施例提供的一种显示面板的局部平面图。图20所示的引线部可为图6或图16中的第四引线部WP4，，当然补偿部的补偿方式与图6和图16均不同。第四引线部WP4包括多条第一引线WRG1，第一引线WRG1包括第一引线子部WS1和补偿部CMP。图20中示出了两个补偿单元 CP1和CP2。补偿单元CP1和补偿单元CP2中补偿部均采用宽度渐变且长度渐变的补偿方式对数据线进行电阻补偿。如图20所示，两个补偿单元CP1和CP2之间具有在各处宽度相等的第二引线WRG2。补偿单元CP1中，补偿部的长度逐渐减小且宽度逐渐减小，补偿单元CP2中，补偿部的宽度逐渐增大且长度逐渐增大。即在第四引线部中，补偿部的宽度先逐渐减小再逐渐增大，补偿部的长度先逐渐减小再逐渐增大。
本公开的实施例中的展开区的引线也可以相对于中心线CL对称设置。本公开的实施例中的引线WRG可以均为第一引线WRG1，不包括第二引线WRG2，即对每条数据线均进行电阻补偿，但不限于此。在一些实施例中，引线WRG包括第一引线WRG1和第二引线WRG2。
图21为本公开的实施例提供的一种显示面板的局部平面图。图21所示的显示面板只示出了中心线CL的左侧的下方的部分，显示面板的右侧的部分与左侧相对于中心线CL对称设置。并且为了图示清晰，没有示出显示区以及其内的全部部件。图21所示的显示面板示出了接垫区PDR以及位于其内的接垫部PDP，每个接垫PD与至少一条展开线FL相连。图21还示出了弯折区BR以及位于弯折区BR的远离引线区WR的一侧的展开区FR2。展开区FR2也可称作第二展开区，相应地，展开区FR可称作第一展开区。展开区FR2内设置有展开线FL2。多条展开线FL2分别与展开区FR内的多条展开线FL相连，进而连接至显示区的数据线DL。
如图21所示，接垫PD被配置为与集成电路的引脚绑定。参考图21，在展开区FR2与接垫区PDR之间还可以设置其他的单元，例如，测试(Cell Test，CT)单元等，为了图示清晰，图21中并未示出。
如图21所示，展开线FL通过数据选择单元MUX与展开区FR3相连，展开区FR3也可称作第三展开区。展开区FR3包括多条展开线FL3，多条展开线FL3分别与多个接垫PD相连。如图21所示，多条展开线FL3分别通过多条引线WRG33与多个接垫PD相连。例如，为了对数据线的电阻进行补偿，多条引线WRG33也可以设置补偿部CMP3，图21中以多条引线WRG33设置补偿部CMP3为例进行说明。补偿部CMP3的设置方式可参照补偿部CMP1的设置方式，在此不再赘述。
如图21所示，每个接垫PD通过数据选择器MUX分别与两条引线WRG 相连，进而分别与两条数据线DL电连接。例如，数据信号到达数据选择器MUX后，通过在不同时段分别控制第一信号线L1和第二信号线L2打开，使数据信号分别传输到与该数据选择器MUX相连的两条数据线DL上。数据选择器MUX的设置方式可参照通常设计。数据选择器MUX不限于连接两条数据线DL，数据选择器MUX连接的数据线DL的数量可根据需要而定。
如图21所示，显示面板还包括导线CDL，例如，导线CDL用于与柔性电路板绑定。如图21所示，导线CDL包括第一电源信号线CDL1、第二电源信号线CDL2。第一电源信号线CDL1被配置为向子像素提供第一电源电压，第二电源信号线CDL2被配置为向子像素提供第二电源电压。例如，第一电源信号线CDL1为VDD线，第二电源信号线CDL2为VSS线。例如，第二电源信号线CDL2与发光二极管的阴极相连。图21还示出了栅线GL。栅线GL沿X方向延伸，多条栅线GL与多条数据线DL彼此绝缘，多条栅线GL与多条数据线DL相互交叉以限定多个子像素SP。
例如，如图21所示，位置1处的间隔INT在X方向上的尺寸为1800μm左右，但不限于此。例如，位置2处的间隔INT在X方向上的尺寸为1800μm左右，但不限于此。例如，位置3处的间隔INT在X方向上的尺寸为1800μm左右，但不限于此。
例如，如图21所示，显示面板中，展开线FL包括第一展开线FL11和第二展开线FL12，第一展开线FL11和第二展开线FL12相邻设置，第一展开线FL11位于第一层LY1，第二展开线FL12位于第二层LY2。例如，多条第一展开线FL11和多条第二展开线FL12交替设置。例如，多条展开线FL包括交替设置的多条第一展开线FL11和多条第二展开线FL12，多条第一展开线FL11和多条第二展开线FL12位于不同层。
如图21所示，多条第一引线WRG1包括交替设置的多条第一类型的第一引线和多条第二类型的第一引线，多条第一类型的第一引线分别与所述多条第一展开线FL11相连，并与多条第一展开线FL11位于同一层，多条第二类型的第一引线分别与多条第二展开线FL12相连，并与多条第二展开线FL12位于同一层。
例如，如图21所示，显示面板包括展开部FP2，展开线FL2包括第一展开线FL21和第二展开线FL22，第一展开线FL21和第二展开线FL22相邻 设置，第一展开线FL21位于第一层LY1，第二展开线FL22位于第二层LY2。例如，多条第一展开线FL21和多条第二展开线FL22交替设置。
例如，如图21所示，第一电源信号线CDL1位于第三层LY3，第二电源信号线CDL2位于第三层LY3。例如，第二电源信号线CDL2可以通过与发光二极管的阳极同层设置的转接元件与发光二极管的阴极相连。发光二极管的阳极与转接元件由同一膜层采用同一构图工艺形成且彼此间隔。
当显示面板包括第二引线WRG2时，第二引线WRG2也位于第三层LY3。第一层LY1由同一膜层采用同一构图工艺形成，第二层LY2由同一膜层采用同一构图工艺形成，第三层LY3由同一膜层采用同一构图工艺形成。例如，第一层LY1为第一栅层，第二层LY2为第二栅层，第三层LY3为源漏极层。例如，第一层LY1还包括位于显示区的栅线GL，第二层LY2还包括位于显示区的初始信号线，第三层LY3还包括位于显示区的源极和漏极。栅线被配置为向子像素提供扫描信号，初始化信号线被配置为向子像素提供初始化信号。
例如，如图21所示，灰色的圆点和黑色的圆点均表示两条子线通过过孔相连，而该两条子线位于不同的那个。因同一条线采用不同的层的子线通过过孔连接的方式形成或同一条线具有位于不同层的部分，第二电源信号线CDL2不与图21中示出的与其交叉的线电连接，第一电源信号线CDL1不与图21中示出的与其交叉的线电连接。从而，通过与接垫PD绑定的集成电路可分别向显示区的数据线DL传输信号，通过与导线CDL绑定的柔性电路板可分别向导线CDL传输信号。
例如，如图21所示，在一些实施例中，衬底基板采用柔性基板，从而设置弯折区BR，但不限于此。弯折区BR的引线采用形成第三层LY3的导电材料制作。
例如，第一层LY1、第二层LY2、第三层LY3均采用导电材料制作，例如，导电材料包括金属或合金至少之一。形成第一层LY1和第二层LY2的材料包括镍，但不限于此。例如，形成第三层LY3的金属包括Ti-Al-Ti，耐弯折性能好。
例如，如图21所示，第一电源信号线CDL1包括第一电源总线BL1，第一电源总线BL1位于显示部DP的一侧且与多条展开线FL至少部分重叠， 第一电源总线BL1包括第一部分BL11、第二部分BL12以及连接第一部分BL11和第二部分BL12的连接线BL13，连接线BL13与间隔INT重叠。即，连接线BL13位于间隔INT内。
例如，如图21所示，第一部分BL11沿X方向延伸，第二部分BL12沿X方向延伸，连接线BL13沿Y方向延伸。例如，第一部分BL11平行于第二部分BL12，第一部分BL11垂直于连接线BL13。
例如，如图21所示，第一电源总线BL1的第二部分BL12位于第一电源总线BL1的第一部分BL11的远离显示部DP的一侧。
例如，第一电源信号线CDL1还包括从第一电源总线BL1延伸出的多条第一电源线LN1，多条第一电源线LN1延伸到显示部DP，被配置为向多个子像素SP提供第一电源信号。例如，第一电源信号包括第一电源电压。
例如，第二电源信号线CDL2中的至少部分与间隔INT重叠，第二电源信号线CDL2被配置为向多个子像素SP提供第二电源信号。例如，第二电源信号包括第二电源电压，第二电源电压小于第一电源电压。例如，第二电源信号线CDL2可围绕显示部DP，并在底端具有开口。
图21示出了三行子像素SP，显示面板包括的子像素SP的个数不限于此，子像素SP的个数可根据需要而定。
图21示出了展开区FR2、引线区WR2、展开区FR3和引线区WR33。展开部FP2位于展开区FR2，包括多条展开线FL2。展开部FP3位于展开区FR3，包括多条展开线FL3。引线部WP22位于引线区WR2，包括多条引线WRG22。引线部WP33位于引线区WR3，包括多条引线WRG33。多条引线WRG22也可以设置补偿部，其设置方法可参照任一引线部中的补偿部的设置方式。引线WRG22可和与其相连的展开线FL2位于同一层，即，多条引线WRG22包括多条位于第一层的引线和多条位于第二层的引线。
图21中，在展开线FL上方的部分可被称作数据线DL，即，图21中，在展开线FL上方与展开线FL相连的沿着Y方向延伸的部分为数据线DL。例如，数据线DL包括位于第三层Y3的部分以及位于第一层LY1或者LY2的部分，但不限于此。
图22为图21中数据选择器的放大示意图。参考图21和图22，每个数据选择器MUX包括有源层ACTL，有源层ACTL的被第一信号线L1和第二信号线L2覆盖的部分为沟道区，有源层ACTL的未被第一信号线L1和第二 信号线L2覆盖的部分为导体。有源层ACTL的第一端与一条数据线DL相连，有源层ACTL的第二端与另一条数据线DL相连，有源层ACTL的第三端通过引线WRG33与接垫PD相连。有源层ACTL的第一端、第二端和第三端均位于有源层ACTL的导体部分，并可通过位于第三层的转接头与有源层ACTL相连。展开线FL3可位于第一层LY1，也可位于第二层LY2，或者包括位于第一层LY1的部分以及位于第二层LY2的部分。展开线FL3也可位于第三层LY3。引线WRG33可参照与其相连的展开线FL3。
图23为本公开一实施例提供的显示面板的剖视图。例如，如图23所示，多个子像素SP中的至少一个包括薄膜晶体管T0和存储电容Cst。薄膜晶体管T0即为数据写入晶体管。薄膜晶体管T0包括位于衬底基板BS上的有源层ATL，位于有源层ATL远离衬底基板BS一侧的第一栅绝缘层GI1，位于第一栅绝缘层GI1远离衬底基板BS一侧的栅极GE，位于栅极GE远离衬底基板BS一侧的第二栅绝缘层GI2，位于第二栅绝缘层GI2远离衬底基板一侧的层间绝缘层ILD，以及位于层间绝缘层ILD远离衬底基板BS一侧的第一极ET1和第二极ET2；存储电容Cst包括第一极板Ca和第二极板Cb，第一极板Ca和栅极GE位于同一层，均位于第一层LY1，第二极板Cb位于第二栅绝缘层GI2和层间绝缘层ILD之间，位于第二层LY2。参考图21和图23，多条第一展开线FL11、栅极GE以及第一极板Ca位于同一层，均位于第一层LY1，并且多条第二展开线FL12与第二极板Cb位于同一层，均位于第二层LY2。第一极ET1和第二极ET2之一为源极，第一极ET1和第二极ET2之另一为漏极。参考图21和图23，第一极ET1、第二极ET2、引线WRG位于第三层LY3。显示面板还包括钝化层PVX和平坦化层PLN。在显示面板包括弯折区的情况下，位于弯折区的引线位于第三层LY3。
如图23所示，显示面板还包括发光单元EMU，发光单元EMU包括阳极ADE、发光功能层EML和阴极CDE，阳极ADE通过贯穿钝化层PVX和平坦化层PLN的过孔与第二极ET2相连。第一极ET1与数据线相连，例如，第一极ET1与数据线一体形成。显示面板还包括封装层CPS，封装层CPS包括第一封装层CPS1、第二封装层CPS2以及第三封装层CPS3。例如，第一封装层CPS1和第三封装层CPS3为无机材料层，第二封装层CPS2为有机材料层。
如图23所示，显示面板还包括像素定义层PDL和隔垫物PS。像素定义 层PDL被配置为限定子像素的开口，隔垫物PS被配置为在形成发光功能层EML时支撑精细金属掩膜。
例如，发光单元EMU的阳极和阴极之一与驱动晶体管电连接，驱动晶体管被配置为向发光单元EMU提供驱动发光单元EMU发光的驱动电流。
数据线被配置为向子像素输入数据信号，第一电源信号线被配置为向驱动晶体管的输入第一电源电压。第二电源信号线被配置为向子像素输入第二电源电压。第一电源电压为恒定电压，第二电源电压为恒定电压，例如，第一电源电压为正电压，第二电源电压为负电压，但不限于此。例如，在一些实施例中，第一电源电压为正电压，第二电源信号线接地。
在一些实施例中，显示面板除了包括驱动晶体管和数据写入晶体管之外，还可以包括发光控制晶体管、复位晶体管等其他晶体管，例如，显示面板的像素电路可为7T1C(即七个晶体管和一个电容)的结构，还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
本公开的实施例还提供一种显示装置，包括上述任一显示面板。例如，显示装置包括OLED显示装置，但不限于此。显示装置还可包括液晶显示装置。
例如，显示装置包括OLED显示装置、液晶显示装置或包括这些显示装置的电脑、手机、手表、电子画框、导航仪等任何具有显示功能的产品或器件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护 范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种显示面板，包括：
    显示部，包括多条数据线和多个子像素，所述多条数据线和所述多个子像素电连接，所述多条数据线被配置为向所述多个子像素提供数据信号；
    展开部，包括多条展开线，至少部分展开线的延伸方向和所述数据线的延伸方向不同；以及
    引线部，包括多条第一引线，所述多条第一引线与所述多条数据线分别通过所述多条展开线相连，所述多条展开线在所述引线部和所述显示部之间展开设置，所述第一引线的延伸方向与所述数据线的延伸方向相同，所述多条数据线中相邻数据线之间的间距大于所述多条第一引线中相邻第一引线之间的间距，
    其中，所述多条第一引线的每个包括第一引线子部和补偿部以形成多个第一引线子部和多个补偿部，所述多个第一引线子部与所述多个补偿部分别相连，在所述显示面板的平面图中，在垂直于所述第一引线的延伸方向的方向上，所述第一引线子部的宽度和所述补偿部的宽度不同。
  2. 根据权利要求1所述的显示面板，其中，所述多条数据线中的至少一条与所述多条展开线中的至少一条的夹角为钝角。
  3. 根据权利要求1或2所述的显示面板，其中，所述第一引线子部比所述补偿部更靠近所述展开部，所述第一引线子部的宽度小于所述补偿部的宽度。
  4. 根据权利要求1-3任一项所述的显示面板，其中，相邻的补偿部的宽度相同。
  5. 根据权利要求1-4任一项所述的显示面板，其中，相邻的补偿部在沿所述第一引线的延伸方向上的长度不同。
  6. 根据权利要求1-5任一项所述的显示面板，其中，沿着所述多条第一引线的排列方向，所述多个补偿部的长度逐渐变化。
  7. 根据权利要求6所述的显示面板，其中，所述多条第一引线的个数为n，所述多个补偿部中长度最大的补偿部的长度为H，所述多个补偿部的长度渐变量为Δ(H/n)。
  8. 根据权利要求1-7任一项所述的显示面板，其中，所述显示面板具有中心线，所述中心线的延伸方向与所述第一引线的延伸方向相同，从所述显示面板的边缘到所述中心线的方向上，所述多个补偿部的长度逐渐减小。
  9. 根据权利要求1-8任一项所述的显示面板，其中，所述显示面板具有中心线，所述中心线的延伸方向与所述第一引线的延伸方向相同，从所述显示面板的边缘到所述中心线的方向上，所述多个补偿部的长度逐渐减小再逐渐增大。
  10. 根据权利要求1-3任一项所述的显示面板，其中，所述多个补偿部在沿所述第一引线的延伸方向上的长度相同，并且所述多个补偿部的宽度逐渐变化。
  11. 根据权利要求1-3任一项所述的显示面板，其中，所述多个补偿部在沿所述第一引线的延伸方向上的长度逐渐变化，并且所述多个补偿部的宽度逐渐变化。
  12. 根据权利要求1-11任一项所述的显示面板，其中，所述第一引线还包括第二引线子部，所述第二引线子部与所述补偿部相连，所述第二引线子部的宽度小于所述补偿部的宽度，所述第二引线子部位于所述补偿部远离所述显示部的一侧。
  13. 根据权利要求1-12任一项所述的显示面板，还包括多条第二引线，其中，所述第二引线的宽度各处相同。
  14. 根据权利要求1-11任一项所述的显示面板，还包括接垫部，其中，所述接垫部被配置为与外接电路相连，所述接垫部包括多个接垫，并位于所述引线部的远离所述展开部的一侧，所述多个接垫与所述多条第一引线电连接。
  15. 根据权利要求1-14任一项所述的显示面板，其中，所述引线部提供为多个，所述多个引线部相对于所述显示面板的中心线对称设置。
  16. 根据权利要求15所述的显示面板，其中，所述多个引线部包括第一引线部和第二引线部，所述第一引线部的多个补偿部的面积之和与所述第二引线部的多个补偿部的面积之和不同。
  17. 根据权利要求15或16所述的显示面板，其中，从所述显示面板的边缘到所述中心线的方向上，所述引线部的所述多个补偿部的面积之和逐渐 增大。
  18. 根据权利要求15-17任一项所述的显示面板，其中，从所述显示面板的边缘到指向所述中心线的方向上，靠近所述中心线的引线部的所述多个补偿部的面积之和大于远离所述中心线的引线部的所述多个补偿部的面积之和。
  19. 根据权利要求15-18任一项所述的显示面板，其中，相邻引线部之间具有间隔，所述间隔的宽度大于所述引线部中相邻的第一引线之间的间距。
  20. 根据权利要求19所述的显示面板，还包括第一电源总线，其中，所述第一电源总线位于所述显示部的一侧且与所述多条展开线至少部分重叠，所述第一电源总线包括第一部分、第二部分以及连接所述第一部分和所述第二部分的连接线，所述连接线与所述间隔重叠。
  21. 根据权利要求20所述的显示面板，其中，所述第一电源总线的所述第二部分位于所述第一电源总线的所述第一部分的远离所述显示部的一侧。
  22. 根据权利要求20-21任一项所述的显示面板，还包括从所述第一电源总线延伸出的多条第一电源线，其中，所述多条第一电源线延伸到所述显示部，被配置为向所述多个子像素提供第一电源信号。
  23. 根据权利要求19-22任一项所述的显示面板，还包括围绕所述显示部的第二电源信号线，其中，所述第二电源信号线中的至少部分与所述间隔重叠，所述第二电源信号线被配置为向所述多个子像素提供第二电源信号。
  24. 根据权利要求1-23任一项所述的显示面板，其中，所述多条展开线包括交替设置的多条第一展开线和多条第二展开线，所述多条第一展开线和所述多条第二展开线位于不同层，所述多条第一引线包括交替设置的多条第一类型的第一引线和多条第二类型的第一引线，所述多条第一类型的第一引线分别与所述多条第一展开线相连，并与所述多条第一展开线位于同一层，所述多条第二类型的第一引线分别与所述多条第二展开线相连，并与所述多条第二展开线位于同一层。
  25. 根据权利要求24所述的显示面板，其中，所述多个子像素中的至少一个包括薄膜晶体管和存储电容；
    所述薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的第一栅绝缘层，位于所述第一栅绝缘层远离所述衬底基板一侧的栅极，位于所述栅极远离所述衬底基板一侧的第二栅绝缘层，位 于所述第二栅绝缘层远离所述衬底基板一侧的层间绝缘层，以及位于所述层间绝缘层远离所述衬底基板一侧的源极和漏极；
    所述存储电容包括第一极板和第二极板，所述第一极板和所述栅极位于同一层，所述第二极板位于所述第二栅绝缘层和所述层间绝缘层之间；
    所述多条第一展开线、所述多条第一类型的第一引线、所述栅极以及所述第一极板位于同一层，所述多条第二展开线、所述多条第二类型的第一引线与所述第二极板位于同一层。
  26. 一种显示装置，包括权利要求1-25任一项所述的显示面板。
PCT/CN2020/079229 2020-03-13 2020-03-13 显示面板和显示装置 WO2021179291A1 (zh)

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