WO2021175157A1 - 有源区阵列的形成方法及半导体结构 - Google Patents

有源区阵列的形成方法及半导体结构 Download PDF

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WO2021175157A1
WO2021175157A1 PCT/CN2021/078068 CN2021078068W WO2021175157A1 WO 2021175157 A1 WO2021175157 A1 WO 2021175157A1 CN 2021078068 W CN2021078068 W CN 2021078068W WO 2021175157 A1 WO2021175157 A1 WO 2021175157A1
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mask layer
etching pattern
forming
etching
substrate
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PCT/CN2021/078068
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English (en)
French (fr)
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平尔萱
周震
刘洋浩
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长鑫存储技术有限公司
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Priority to US17/372,878 priority Critical patent/US11887859B2/en
Publication of WO2021175157A1 publication Critical patent/WO2021175157A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Definitions

  • This application relates to the field of semiconductor manufacturing technology, and in particular to a method for forming an active area array and a semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • each memory cell usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the opening and closing of the transistor, so that the storage can be read through the bit line Data information in the capacitor, or write data information into the capacitor.
  • the substrate of a semiconductor structure there are a plurality of active regions arranged in an array to form an active region array.
  • the formation of the active area The auxiliary line of the active area is divided into an active area island structure by a circular pattern, and then the substrate is etched using the active area island structure as a mask to form a plurality of arrays.
  • the active area of the cloth mainly relies on single-pattern or double-lithography (Lithography etch lithography etch, LELE). As the size of the node shrinks, the process of forming the active area array using the LELE process will encounter the limitation of the accuracy of the photolithography process.
  • the present application provides a method for forming an active area array and a semiconductor structure to solve the current problem that the size of the active area cannot be further reduced, so as to increase the arrangement density of the active area in the active area array and improve the semiconductor structure Performance.
  • the present application provides a method for forming an active area array, which includes the following steps:
  • the substrate is etched along the first etching pattern and the fourth etching pattern to form a plurality of active regions in the substrate.
  • the specific steps of forming a first mask layer on the surface of the substrate include:
  • the first mask layer is etched to form a plurality of first etching patterns, and the first etching pattern divides the first mask layer into a plurality of first active lines.
  • the specific steps of forming a second mask layer covering the surface of the first mask layer include:
  • the specific steps of forming a third mask layer with a second etching pattern on the surface of the second mask layer include:
  • the third mask layer is etched along the opening, and a second etching pattern is formed in the third mask layer.
  • the specific steps of forming a fourth etching pattern in the first mask layer include:
  • the second mask layer, the sixth mask layer, and the first mask layer are sequentially etched along the third etching pattern to form the fourth mask layer exposing the fifth mask layer.
  • An etching pattern, the fourth etching pattern cuts one of the first active lines into multiple segments.
  • the specific steps of etching the substrate along the first etching pattern and the fourth etching pattern include:
  • the fifth mask layer is etched along the first etching pattern and the fourth etching pattern, and a fifth etching pattern and a sixth etching pattern are respectively formed in the fifth mask layer, so The fifth etching pattern and the sixth etching pattern divide the fifth mask layer into a plurality of second active lines.
  • the specific step of etching the substrate along the first etching pattern and the fourth etching pattern further includes:
  • the fifth etching pattern and the sixth etching pattern sequentially etch the fourth mask layer and the substrate to form a plurality of active regions in the substrate.
  • the material of the coating layer is the same as the material of the fifth mask layer.
  • the first etching pattern and the third etching pattern are both trenches, and the width of the third etching pattern is greater than that of the first etching pattern.
  • this application also provides a semiconductor structure, including:
  • the active area array is formed by the method for forming the active area array as described in any one of the above.
  • the second etching layer is successively formed on the surface of the first mask layer.
  • the pattern and the third etching pattern that is, the first mask layer is divided by self-aligned double imaging (Self-aligned Double Pattern, SADP), which avoids the lithography accuracy of a single lithography pattern or a double lithography pattern.
  • SADP Self-aligned Double Pattern
  • the size of the active area is limited, so that the size of the active area can be further reduced, and the density of the active area array inside the substrate can be further increased, so as to improve the performance of the semiconductor structure.
  • Fig. 1 is a flowchart of a method for forming an active area array in a specific embodiment of the present application
  • 2A-2N are schematic diagrams of main process cross-sections in the process of forming the active area array in the specific embodiment of the present application;
  • FIG. 3 is a schematic diagram of the shape change of the active region mask during the etching process in the specific embodiment of the present application.
  • FIG. 1 is a flowchart of the method for forming an active area array in the specific embodiment of the application.
  • the method for forming an active area array provided by this embodiment includes the following steps:
  • step S11 a substrate 20 is provided, as shown in FIG. 2A.
  • step S12 a first mask layer is formed on the surface of the substrate 20.
  • the first mask layer has a first etching pattern 231.
  • the first etching pattern 231 is shown in FIG. 2I.
  • the specific steps of forming a first mask layer on the surface of the substrate 20 include:
  • the first mask layer is etched to form a plurality of first etching patterns 231, which divide the first mask layer into a plurality of first active lines 23, as shown in FIG. 2A
  • Fig. 2B is a schematic top view of the structure shown in Fig. 2A.
  • the material of the substrate 20 may be but not limited to silicon.
  • the substrate 20 is used to form the active area array in a subsequent process.
  • the fourth mask layer may be sequentially formed on the surface of the substrate 20 before the first mask layer is formed on the substrate 20 21 and the fifth mask layer 22 covering the surface of the fourth mask layer 21 away from the substrate 20.
  • the fourth mask layer 21 and the fifth mask layer 22 should have a relatively high etching selection ratio, for example, the etching selection ratio is greater than 3, so as to facilitate subsequent comparison of the fourth mask layer. 21 Carry out selective etching.
  • the material of the fourth mask layer 21 may be, but is not limited to, an oxide material, such as silicon oxide; the material of the fifth mask layer 22 may be, but is not limited to, a polysilicon material.
  • the first mask layer may be etched by photolithography and etching processes to form a plurality of the first mask layers.
  • the etching pattern 231, for example, the first etching pattern 231 is a trench that penetrates the first mask layer in a direction perpendicular to the substrate 20.
  • the first etching pattern 231 divides the first mask layer into a plurality of the first active lines 23 independent of each other.
  • the first active lines 23 extend along a first direction D1, and a plurality of the first active lines 23 are arranged in parallel along a second direction D2 that intersects the first direction D1.
  • the intersection described in this specific embodiment may be a vertical intersection or an oblique intersection.
  • the plurality is two or more, and the plurality is two or more.
  • Step S13 forming a second mask layer 25 covering the surface of the first mask layer, as shown in FIG. 2A.
  • the specific steps of forming the second mask layer 25 covering the surface of the first mask layer include:
  • the second mask layer 25 is deposited on the surface of the sixth mask layer 24, as shown in FIG. 2A.
  • a chemical vapor deposition, physical vapor deposition, or atomic layer deposition process may be used to form the first etching pattern 231 that fills the first etching pattern 231 and covers the first mask layer.
  • the sixth mask layer 24 and the second mask layer 25 should have a higher etching selection ratio to facilitate subsequent selective etching, for example, the etching selection ratio is greater than 3.
  • the material of the sixth mask layer 24 may be an organic mask layer material, such as spin-on carbon material; the material of the second mask layer 25 may be a nitride material, such as silicon nitride.
  • Step S14 forming a third mask layer 26 with a second etching pattern 30 on the surface of the second mask layer 25, as shown in FIG. 2C.
  • the specific steps of forming the third mask layer 26 with the second etching pattern 30 on the surface of the second mask layer 25 include:
  • a third mask layer 26 is deposited on the surface of the second mask layer 25 along a direction perpendicular to the substrate 20, as shown in FIG. 2A;
  • the photoresist layer 28 has an opening 29, as shown in FIG. 2A;
  • the third mask layer 26 is etched along the opening 29 to form a second etching pattern 30 in the third mask layer 26.
  • the third mask layer 26 and the seventh mask layer 27 are sequentially formed along a direction perpendicular to the substrate 20, and are applied to the second mask layer.
  • the photoresist layer 28 with the opening 29 is formed on the surface of the seven mask layer 27, as shown in FIG. 2A and FIG. 2B. At the angle shown in FIG. 2B, the first active line 23 is not visible, so it is represented by a dashed line.
  • the material of the third mask layer 26 may be an organic mask material, and the material of the seventh mask layer 27 may be a nitride material.
  • the seventh mask layer 27 and the third mask layer 26 are sequentially etched along the opening 29 to form the second etching pattern 30 in the third mask layer 26.
  • the third etching pattern 30 may be a trench that penetrates the third mask layer 26 in a direction perpendicular to the substrate 20.
  • Step S15 forming sidewall spacers 31 covering the sidewalls of the second etching pattern 30, as shown in FIG. 2D.
  • an oxide material is deposited on the inner wall of the second etching pattern 30 and the third mask using a chemical vapor deposition, physical vapor deposition or atomic layer deposition process.
  • the oxide material of the wall serves as the side wall 31.
  • Step S16 the third mask layer 26 is removed, and a third etching pattern 32 is formed between the adjacent sidewall spacers 31, as shown in FIG. 2E and FIG. 2F.
  • FIG. 2F is a top view of the structure shown in FIG. 2E. Schematic.
  • the etching selection ratio is greater than 3.
  • the trenches formed between adjacent sidewall spacers 31 that expose the second mask layer 25 are the third etching patterns 32.
  • Those skilled in the art can adjust the thickness of the sidewall 31 according to actual needs, and then adjust the width of the third etching pattern 32, so as to adjust the interval between adjacent active regions later.
  • the first etching pattern 231 and the third etching pattern 32 are both trenches, and the width of the third etching pattern 32 is greater than that of the first etching pattern 231.
  • the relative proportional relationship between the first etching pattern 231 and the third etching pattern 32 can be adjusted.
  • Setting the width of the third etching pattern 32 to be greater than that of the first etching pattern 231 can enable the first active line 23 to be sufficiently cut off in the subsequent process.
  • Step S17 the first mask layer is etched along the third etching pattern 32, and a fourth etching pattern 232 is formed in the first mask layer, as shown in FIG. 2I, FIG. 2J, and FIG. 2J It is a schematic top view of the structure shown in FIG. 2I.
  • the specific steps of forming the fourth etching pattern 232 in the first mask layer include:
  • the second mask layer 25, the sixth mask layer 24, and the first mask layer are etched in sequence along the third etching pattern 32 to form all areas exposing the fifth mask layer 22.
  • the fourth etching pattern 232, the fourth etching pattern 232 cuts one of the first active lines 23 into multiple segments.
  • FIG. 2H is a schematic top view of the structure shown in FIG. 2G.
  • the exposed part of the first active line 23 is removed by an etching process, so that the first active line 23 is cut into multiple independent sections, that is, the first active line 23 passes through the first active line 23.
  • the four etching patterns 232 are divided into multiple segments, as shown in FIG. 2I and FIG. 2J.
  • FIG. 3 is a schematic diagram of the shape change of the active region mask during the etching process in the specific embodiment of the present application.
  • the first active line 23 is divided into a plurality of long and narrow parallelogram shapes, as shown in a diagram in FIG. 3.
  • Step S18 the substrate 20 is etched along the first etching pattern 231 and the fourth etching pattern 232 to form a plurality of active regions 36 in the substrate 20, as shown in FIG. 2M and FIG. 2N 2N is a schematic top view of the structure shown in FIG. 2M.
  • the specific steps of etching the substrate 20 along the first etching pattern 231 and the fourth etching pattern 232 include:
  • the fifth mask layer 22 is etched along the first etching pattern 231 and the fourth etching pattern 232, and a fifth etching pattern 34 and a sixth etching pattern 34 are formed in the fifth mask layer 22, respectively.
  • An etching pattern 33, the fifth etching pattern 34 and the sixth etching pattern 33 divide the fifth mask layer into a plurality of second active lines 221.
  • the specific steps of etching the substrate 20 along the first etching pattern 231 and the fourth etching pattern 232 further include:
  • FIG. 2K is a schematic top view of the structure shown in FIG. 2K;
  • the fifth etching pattern 34 and the sixth etching pattern 33 sequentially etch the fourth mask layer 21 and the substrate 20 to form a plurality of active regions 36 in the substrate 20.
  • the material of the coating layer 35 is the same as the material of the fifth mask layer 22.
  • the first etching pattern 231 and the fourth etching pattern 232 are etched along the first etching pattern 232.
  • a fifth etching pattern 34 corresponding to the first etching pattern 231 and a sixth etching pattern 232 corresponding to the fourth etching pattern 232 are formed in the fifth mask layer 22 Figure 33.
  • the fifth mask layer 22 is divided into a plurality of second active lines 221 by the fifth etching pattern 34 and the sixth etching pattern 33.
  • the elongated parallelogram becomes a relatively round island shape , As shown in figure b in Figure 3.
  • an atomic layer deposition process is used to form the cladding layer 35 covering the surface of the second active line 221, as shown in FIG. 2K and FIG. 2L.
  • the pattern of the active region can be enlarged, and the finally formed active region can be further rounded, as shown in the c diagram in FIG. 3.
  • the fourth mask layer 21 and the substrate 20 are sequentially etched using the fifth etching pattern 34 and the sixth etching pattern 33 to form a plurality of active regions 36 in the substrate 20 , As shown in Figure 2M and Figure 2N.
  • the multiple active regions 36 are arranged in an array in the substrate 20.
  • this specific embodiment also provides a semiconductor structure, and the schematic diagram of the semiconductor structure can be seen in FIG. 2M and FIG. 2N.
  • the semiconductor structure includes:
  • the active area array is formed by the method for forming the active area array as described in any one of the above.
  • the second mask layer is successively formed on the surface of the first mask layer.
  • the etched pattern and the third etched pattern that is, the first mask layer is divided by self-aligned double patterning (SADP), which avoids the lithography of a single lithography pattern or a double lithography pattern.
  • SADP self-aligned double patterning

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Abstract

一种有源区（36）阵列的形成方法及半导体结构，有源区（36）阵列的形成方法包括如下步骤：步骤S11，提供一衬底（20）；步骤S12，形成第一掩膜层于衬底（20）表面，第一掩膜层中具有第一刻蚀图形（231）；步骤S13，形成覆盖于第一掩膜层表面的第二掩膜层（25）；步骤S14，形成具有第二刻蚀图形（30）的第三掩膜层（26）于第二掩膜层（25）表面；步骤S15，形成覆盖第二刻蚀图形（30）侧壁的侧墙（31）；步骤S16，去除第三掩膜层（26），于相邻侧墙（31）之间形成第三刻蚀图形（32）；步骤S17，沿第三刻蚀图形（32）刻蚀第一掩膜层，于第一掩膜层中形成第四刻蚀图形（232）；步骤S18，沿第一刻蚀图形（231）和第四刻蚀图形（232）刻蚀衬底（20），于衬底（20）内形成多个有源区（36）。该形成方法避免了光刻精度对有源区（36）尺寸的限制，使得有源区（36）的尺寸可以进一步的缩小，衬底（20）内部有源区（36）阵列的密度进一步增大。

Description

有源区阵列的形成方法及半导体结构
相关申请引用说明
本申请要求于2020年3月2日递交的中国专利申请号202010134688.8、申请名为“有源区阵列的形成方法及半导体结构”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种有源区阵列的形成方法及半导体结构。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体结构，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启与关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
在DRAM等半导体结构的衬底中，具有呈阵列排布的多个有源区，形成有源区阵列。有源区的形成通过圆形的图形将有源区辅助线分割为一个一个的有源区岛状结构，然后以有源区岛状结构为掩膜刻蚀衬底，形成多个呈阵列排布的有源区。但是，圆形图形的形成主要依赖于单一光刻图形(single-pattern)或者双重光刻图形(Lithography etch lithography etch，LELE)。随着节点尺寸的缩小，利用LELE工艺形成有源区阵列的过程中会遇到光刻工艺精度的限制。
因此，如何进一步缩小有源区的尺寸，从而提高有源区阵列中有源区的排布密度，是当前亟待解决的技术问题。
发明内容
本申请提供一种有源区阵列的形成方法及半导体结构，用于解决当前无法将有源区的尺寸进一步缩小的问题，以提高有源区阵列中有源区的排布密度，改善半导体结构的性能。
为了解决上述问题，本申请提供了一种有源区阵列的形成方法，包括如下步骤：
提供一衬底；
形成第一掩膜层于所述衬底表面，所述第一掩膜层中具有第一刻蚀图形；
形成覆盖于所述第一掩膜层表面的第二掩膜层；
形成具有第二刻蚀图形的第三掩膜层于所述第二掩膜层表面；
形成覆盖所述第二刻蚀图形侧壁的侧墙；
去除所述第三掩膜层，于相邻所述侧墙之间形成第三刻蚀图形；
沿所述第三刻蚀图形刻蚀所述第一掩膜层，于所述第一掩膜层中形成第四刻蚀图形；
沿所述第一刻蚀图形和所述第四刻蚀图形刻蚀所述衬底，于衬底内形成多个有源区。
可选的，形成第一掩膜层于所述衬底表面的具体步骤包括：
依次形成第四掩膜层以及覆盖于所述第四掩膜层表面的第五掩膜层于所述衬底表面；
形成覆盖于所述第五掩膜层表面的所述第一掩膜层；
刻蚀所述第一掩膜层，形成多个第一刻蚀图形，所述第一刻蚀图形将所述第一掩膜层分割为多条第一有源线。
可选的，形成覆盖于所述第一掩膜层表面的第二掩膜层的具体步骤包括：
沉积填充满所述第一刻蚀图形并覆盖所述第一掩膜层表面的第六掩膜层；
沉积所述第二掩膜层于所述第六掩膜层表面。
可选的，形成具有第二刻蚀图形的第三掩膜层于所述第二掩膜层表面的具体步骤包括：
沿垂直于所述衬底的方向沉积第三掩膜层于所述第二掩膜层表面；
形成光阻层于所述第三掩膜层表面，所述光阻层中具有开口；
沿所述开口刻蚀所述第三掩膜层，于所述第三掩膜层中形成第二刻蚀图形。
可选的，于所述第一掩膜层中形成第四刻蚀图形的具体步骤包括：
沿所述第三刻蚀图形依次刻蚀所述第二掩膜层、所述第六掩膜层和所述第一掩膜层，形成暴露所述第五掩膜层的所述第四刻蚀图形，所述第四刻蚀图形将一条所述第一有源线切割为多段。
可选的，沿所述第一刻蚀图形和所述第四刻蚀图形刻蚀所述衬底的具体步骤包括：
沿所述第一刻蚀图形和所述第四刻蚀图形刻蚀所述第五掩膜层，于所述第五掩膜层中分别形成第五刻蚀图形和第六刻蚀图形，所述第五刻蚀图形和所述第六刻蚀图形将所述第五掩膜层分割为多条第二有源线。
可选的，沿所述第一刻蚀图形和所述第四刻蚀图形刻蚀所述衬底的具体步骤还包括：
形成包覆所述第二有源线的包覆层；
所述第五刻蚀图形和所述第六刻蚀图形依次刻蚀所述第四掩膜层和所述衬底，于衬底内形成多个有源区。
可选的，所述包覆层的材料与所述第五掩膜层的材料相同。
可选的，所述第一刻蚀图形和所述第三刻蚀图形均为沟槽，且所述第三刻蚀图形的宽度大于所述第一刻蚀图形。
为了解决上述问题，本申请还提供了一种半导体结构，包括：
衬底；
有源区阵列，所述有源区阵列采用如上述任一项所述的有源区阵列的形成方法形成。
本申请提供的有源区阵列的形成方法及半导体结构，在衬底上形成具有第一刻蚀图形的第一掩膜层之后，通过于所述第一掩膜层表面先后形成第二刻蚀图形和第三刻蚀图形，即通过自对准双重成像(Self-aligned Double Patterning，SADP)来分割所述第一掩膜层，避免了单一光刻图形或者双重光刻图形的光刻精度对有源区尺寸的限制，使得有源区的尺寸可以进一步的缩小，所述衬底内部有源区阵列的密度可以进一步增大，从而实现对半导体结构性能的改善。
附图说明
附图1是本申请具体实施方式中有源区阵列的形成方法流程图；
附图2A-2N是本申请具体实施方式在形成有源区阵列的过程中主要的工艺截面示意图；
附图3是本申请具体实施方式在刻蚀过程中有源区掩膜的形状变化示意图。
具体实施方式
下面结合附图对本申请提供的有源区阵列的形成方法及半导体结构的具体实施方式做详细说明。
本具体实施方式提供了一种有源区阵列的形成方法，附图1是本申请具体实施方式中有源区阵列的形成方法流程图，附图2A-2N是本申请具体实施方式在形成有源区阵列的过程中主要的工艺截面示意图。如图1、图2A-图2N所示，本具体实施方式提供的有源区阵列的形成方法，包括如下步骤：
步骤S11，提供一衬底20，如图2A所示。
步骤S12，形成第一掩膜层于所述衬底20表面，所述第一掩膜层中具有第一刻蚀图形231，图2I中示出了第一刻蚀图形231。
可选的，形成第一掩膜层于所述衬底20表面的具体步骤包括：
依次形成第四掩膜层21以及覆盖于所述第四掩膜层21表面的第五掩膜层22于所述衬底20表面；
形成覆盖于所述第五掩膜层22表面的所述第一掩膜层；
刻蚀所述第一掩膜层，形成多个第一刻蚀图形231，所述第一刻蚀图形231将所述第一掩膜层分割为多条第一有源线23，如图2A、图2B所示，图2B是图2A所示结构的俯视结构示意图。
具体来说，所述衬底20的材料可以是但不限于硅。所述衬底20用于在后续工艺中形成所述有源区阵列。为了避免掩膜层的形成工艺对所述衬底20的损伤，在形成第一掩膜层于所述衬底20之前，还可以在所述衬底20表面依次形成所述第四掩膜层21和覆盖于所述第四掩膜层21背离所述衬底20表面的所述第五掩膜层22。其中，所述第四掩膜层21与所述第五掩膜层22之间应该具有较高的刻蚀选择比，例如刻蚀选择比大于3，以便于后续对所述第四掩膜层21进行选择性刻蚀。所述第四掩膜层21的材料可以为但不限于氧化物材料，例如氧化硅；所述第五掩膜层22的材料可以是但不限于多晶硅材料。
形成覆盖于所述第五掩膜层22表面的所述第一掩膜层之后，可以采用光刻、刻蚀工艺对所述第一掩膜层进行刻蚀，以形成多个所述第一刻蚀图形231，例如，所述第一刻蚀图形231为沿垂直于所述衬底20的方向贯穿所述第一掩膜层的沟槽。所述第一刻蚀图形231将所述第一掩膜层分割为多条相互独立的 所述第一有源线23。所述第一有源线23沿第一方向D1延伸，且多条所述第一有源线23沿与所述第一方向D1相交的第二方向D2平行排列。本具体实施方式中所述的相交可以为垂直相交，也可以为倾斜相交。在本具体实施方式中所述的多个为两个以上、多条为两条以上。
步骤S13，形成覆盖于所述第一掩膜层表面的第二掩膜层25，如图2A所示。
可选的，形成覆盖于所述第一掩膜层表面的第二掩膜层25的具体步骤包括：
沉积填充满所述第一刻蚀图形231并覆盖所述第一掩膜层表面的第六掩膜层24；
沉积所述第二掩膜层25于所述第六掩膜层24表面，如图2A所示。
具体来说，在形成所述第一刻蚀图形231之后，可以采用化学气相沉积、物理气相沉积或者原子层沉积工艺形成填充满所述第一刻蚀图形231并覆盖所述第一掩膜层表面的第六掩膜层24。所述第六掩膜层24与所述第二掩膜层25应具有较高的刻蚀选择比，以便于后续进行选择性刻蚀，例如刻蚀选择比大于3。所述第六掩膜层24的材料可以为有机掩膜层材料，例如旋涂碳材料；所述第二掩膜层25的材料可以为氮化物材料，例如氮化硅。
步骤S14，形成具有第二刻蚀图形30的第三掩膜层26于所述第二掩膜层25表面，如图2C所示。
可选的，形成具有第二刻蚀图形30的第三掩膜层26于所述第二掩膜层25表面的具体步骤包括：
沿垂直于所述衬底20的方向沉积第三掩膜层26于所述第二掩膜层25表面，如图2A所示；
形成光阻层28于所述第三掩膜层26表面，所述光阻层28中具有开口29，如图2A所示；
沿所述开口29刻蚀所述第三掩膜层26，于所述第三掩膜层26中形成第二刻蚀图形30。
具体来说，在形成覆盖所述第二掩膜层25之后，沿垂直于所述衬底20的方向依次形成所述第三掩膜层26和第七掩膜层27，并于所述第七掩膜层27 表面形成具有所述开口29的所述光阻层28，如图2A、图2B所示。在图2B所示的角度下，所述第一有源线23不可见，故以虚线表示。所述第三掩膜层26的材料可以为有机掩膜材料，所述第七掩膜层27的材料可以为氮化物材料。之后，沿所述开口29依次刻蚀所述第七掩膜层27和所述第三掩膜层26，于所述第三掩膜层26中形成所述第二刻蚀图形30。所述第三刻蚀图形30可以为沿垂直于所述衬底20的方向贯穿所述第三掩膜层26的沟槽。去除所述第七掩膜层27和所述光阻层28之后，得到如图2C所示的结构。
步骤S15，形成覆盖所述第二刻蚀图形30侧壁的侧墙31，如图2D所示。
具体来说，在形成所述第二刻蚀图形30之后，采用化学气相沉积、物理气相沉积或者原子层沉积工艺沉积氧化物材料于所述第二刻蚀图形30的内壁和所述第三掩膜层26的顶面；之后，去除所述第二刻蚀图形30底壁和所述第三掩膜层26顶面沉积的所述氧化物材料，残留于所述第二刻蚀图形30侧壁的所述氧化物材料作为所述侧墙31。
步骤S16，去除所述第三掩膜层26，于相邻所述侧墙31之间形成第三刻蚀图形32，如图2E、图2F所示，图2F是图2E所示结构的俯视结构示意图。
具体来说，形成所述侧墙31的材料与所述第三掩膜层26的材料之间应该具有较高的刻蚀选择比，以便于选择性的去除所述第三掩膜层26，例如刻蚀选择比大于3。去除所述第三掩膜层26之后，于相邻所述侧墙31之间形成的暴露所述第二掩膜层25的沟槽即为所述第三刻蚀图形32。本领域技术人员可以根据实际需要调整所述侧墙31的厚度，进而实现对所述第三刻蚀图形32宽度的调整，以便于后续实现对相邻有源区之间的间隔进行调整。
可选的，所述第一刻蚀图形231和所述第三刻蚀图形32均为沟槽，且所述第三刻蚀图形32的宽度大于所述第一刻蚀图形231。
具体来说，通过调整所述侧墙31的厚度，可以使得可以调整所述第一刻蚀图形231与所述第三刻蚀图形32之间的相对比例关系。将所述第三刻蚀图形32的宽度设置为大于所述第一刻蚀图形231，可以使得在后续工艺中能够充分将所述第一有源线23切断。
步骤S17，沿所述第三刻蚀图形32刻蚀所述第一掩膜层，于所述第一掩膜层中形成第四刻蚀图形232，如图2I、图2J所示，图2J是图2I所示结构的 俯视结构示意图。
可选的，于所述第一掩膜层中形成第四刻蚀图形232的具体步骤包括：
沿所述第三刻蚀图形32依次刻蚀所述第二掩膜层25、所述第六掩膜层24和所述第一掩膜层，形成暴露所述第五掩膜层22的所述第四刻蚀图形232，所述第四刻蚀图形232将一条所述第一有源线23切割为多段。
具体来说，首先，沿所述第四刻蚀图形232依次刻蚀所述第二掩膜层25和所述第六掩膜层24，暴露所述第一有源线23中的部分区域，如图2G、图2H所示，图2H是图2G所示结构的俯视结构示意图。之后，通过刻蚀工艺去除所述第一有源线23中暴露的部分，从而将所述第一有源线23切割为相互独立的多段，即所述第一有源线23通过所述第四刻蚀图形232分割为多段，如图2I、图2J所示。
附图3是本申请具体实施方式在刻蚀过程中有源区掩膜的形状变化示意图。通过本步骤的刻蚀，所述第一有源线23被分割为多个狭长的平行四边形形状，如图3中的a图所示。
步骤S18，沿所述第一刻蚀图形231和所述第四刻蚀图形232刻蚀所述衬底20，于衬底20内形成多个有源区36，如图2M、图2N所示，图2N是图2M所示结构的俯视结构示意图。
可选的，沿所述第一刻蚀图形231和所述第四刻蚀图形232刻蚀所述衬底20的具体步骤包括：
沿所述第一刻蚀图形231和所述第四刻蚀图形232刻蚀所述第五掩膜层22，于所述第五掩膜层22中分别形成第五刻蚀图形34和第六刻蚀图形33，所述第五刻蚀图形34和所述第六刻蚀图形33将所述第五掩膜层分割为多条第二有源线221。
可选的，沿所述第一刻蚀图形231和所述第四刻蚀图形232刻蚀所述衬底20的具体步骤还包括：
形成包覆所述第二有源线221的包覆层35，如图2K、图2L所示，图2L是图2K所示结构的俯视结构示意图；
所述第五刻蚀图形34和所述第六刻蚀图形33依次刻蚀所述第四掩膜层21和所述衬底20，于衬底20内形成多个有源区36。
可选的，所述包覆层35的材料与所述第五掩膜层22的材料相同。
具体来说，在形成所述第一刻蚀图形231和所述第四刻蚀图形232之后，首先，沿所述第一刻蚀图形231和所述第四刻蚀图形232刻蚀所述第五掩膜层22，于所述第五掩膜层22中形成与所述第一刻蚀图形231对应的第五刻蚀图形34以及与所述第四刻蚀图形232对应的第六刻蚀图形33。通过所述第五刻蚀图形34以及所述第六刻蚀图形33将所述第五掩膜层22分割为多条所述第二有源线221。在刻蚀所述第五掩膜层22的过程中，由于刻蚀的载入效应(Loading Effect)以及所述第五掩膜层22的消耗，狭长的平行四边形为变成较为圆润的岛状，如图3中的b图所示。接着，采用原子层沉积工艺形成覆盖所述第二有源线221表面的所述包覆层35，如图2K、图2L所示。通过形成所述包覆层35，可以在扩大有源区图案的同时，使得最终形成的有源区进一步圆润，如图3中的c图所示。然后，以所述第五刻蚀图形34和所述第六刻蚀图形33依次刻蚀所述第四掩膜层21和所述衬底20，于衬底20内形成多个有源区36，如图2M、图2N所示。多个所述有源区36在所述衬底20内呈阵列排布。
不仅如此，本具体实施方式还提供了一种半导体结构，所述半导体结构的示意图可参见图2M、图2N。所述半导体结构包括：
衬底；
有源区阵列，所述有源区阵列采用如上述任一项所述的有源区阵列的形成方法形成。
本具体实施方式提供的有源区阵列的形成方法及半导体结构，在衬底上形成具有第一刻蚀图形的第一掩膜层之后，通过于所述第一掩膜层表面先后形成第二刻蚀图形和第三刻蚀图形，即通过自对准双重成像(Self-aligned Double Patterning，SADP)来分割所述第一掩膜层，避免了单一光刻图形或者双重光刻图形的光刻精度对有源区尺寸的限制，使得有源区的尺寸可以进一步的缩小，所述衬底内部有源区阵列的密度可以进一步增大，从而实现对半导体结构性能的改善。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通 技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (10)

  1. 一种有源区阵列的形成方法，包括如下步骤：
    提供一衬底；
    形成第一掩膜层于所述衬底表面，所述第一掩膜层中具有第一刻蚀图形；
    形成覆盖于所述第一掩膜层表面的第二掩膜层；
    形成具有第二刻蚀图形的第三掩膜层于所述第二掩膜层表面；
    形成覆盖所述第二刻蚀图形侧壁的侧墙；
    去除所述第三掩膜层，于相邻所述侧墙之间形成第三刻蚀图形；
    沿所述第三刻蚀图形刻蚀所述第一掩膜层，于所述第一掩膜层中形成第四刻蚀图形；
    沿所述第一刻蚀图形和所述第四刻蚀图形刻蚀所述衬底，于衬底内形成多个有源区。
  2. 根据权利要求1所述的有源区阵列的形成方法，其中，形成第一掩膜层于所述衬底表面的具体步骤包括：
    依次形成第四掩膜层以及覆盖于所述第四掩膜层表面的第五掩膜层于所述衬底表面；
    形成覆盖于所述第五掩膜层表面的所述第一掩膜层；
    刻蚀所述第一掩膜层，形成多个第一刻蚀图形，所述第一刻蚀图形将所述第一掩膜层分割为多条第一有源线。
  3. 根据权利要求2所述的有源区阵列的形成方法，其中，形成覆盖于所述第一掩膜层表面的第二掩膜层的具体步骤包括：
    沉积填充满所述第一刻蚀图形并覆盖所述第一掩膜层表面的第六掩膜层；
    沉积所述第二掩膜层于所述第六掩膜层表面。
  4. 根据权利要求3所述的有源区阵列的形成方法，其中，形成具有第二刻蚀图形的第三掩膜层于所述第二掩膜层表面的具体步骤包括：
    沿垂直于所述衬底的方向沉积第三掩膜层于所述第二掩膜层表面；
    形成光阻层于所述第三掩膜层表面，所述光阻层中具有开口；
    沿所述开口刻蚀所述第三掩膜层，于所述第三掩膜层中形成第二刻蚀图形。
  5. 根据权利要求4所述的有源区阵列的形成方法，其中，于所述第一掩膜层中形成第四刻蚀图形的具体步骤包括：
    沿所述第三刻蚀图形依次刻蚀所述第二掩膜层、所述第六掩膜层和所述第一掩膜层，形成暴露所述第五掩膜层的所述第四刻蚀图形，所述第四刻蚀图形将一条所述第一有源线切割为多段。
  6. 根据权利要求2所述的有源区阵列的形成方法，其中，沿所述第一刻蚀图形和所述第四刻蚀图形刻蚀所述衬底的具体步骤包括：
    沿所述第一刻蚀图形和所述第四刻蚀图形刻蚀所述第五掩膜层，于所述第五掩膜层中分别形成第五刻蚀图形和第六刻蚀图形，所述第五刻蚀图形和所述第六刻蚀图形将所述第五掩膜层分割为多条第二有源线。
  7. 根据权利要求6所述的有源区阵列的形成方法，其中，沿所述第一刻蚀图形和所述第四刻蚀图形刻蚀所述衬底的具体步骤还包括：
    形成包覆所述第二有源线的包覆层；
    所述第五刻蚀图形和所述第六刻蚀图形依次刻蚀所述第四掩膜层和所述衬底，于衬底内形成多个有源区。
  8. 根据权利要求7所述的有源区阵列的形成方法，其中，所述包覆层的材料与所述第五掩膜层的材料相同。
  9. 根据权利要求1所述的有源区阵列的形成方法，其中，所述第一刻蚀图形和所述第三刻蚀图形均为沟槽，且所述第三刻蚀图形的宽度大于所述第一刻蚀图形。
  10. 一种半导体结构，包括：
    衬底；
    有源区阵列，所述有源区阵列采用如权利要求1-9中任一项所述的有源区阵列的形成方法形成。
PCT/CN2021/078068 2020-03-02 2021-02-26 有源区阵列的形成方法及半导体结构 WO2021175157A1 (zh)

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