WO2021169944A1 - 阵列基板、其制作方法、显示面板及显示装置 - Google Patents

阵列基板、其制作方法、显示面板及显示装置 Download PDF

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Publication number
WO2021169944A1
WO2021169944A1 PCT/CN2021/077437 CN2021077437W WO2021169944A1 WO 2021169944 A1 WO2021169944 A1 WO 2021169944A1 CN 2021077437 W CN2021077437 W CN 2021077437W WO 2021169944 A1 WO2021169944 A1 WO 2021169944A1
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Prior art keywords
base substrate
pixel defining
electrode layer
area
opening
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PCT/CN2021/077437
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English (en)
French (fr)
Inventor
舒适
徐传祥
黄海涛
姚琪
王铁石
徐智强
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京东方科技集团股份有限公司
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Priority to US17/777,808 priority Critical patent/US20220415981A1/en
Publication of WO2021169944A1 publication Critical patent/WO2021169944A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/822—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, a display panel and a display device.
  • the thickness of the circular polarizer in the array substrate accounts for a relatively large thickness in the entire array substrate.
  • the color filter is integrated on the encapsulation layer of the light emitting device, instead of the circular polarizer. Reduce the thickness of the module.
  • the cathode layer in each sub-pixel has a fixed reflection direction for the light irradiated on it, and the sub-pixels in different positions
  • the light reflected by the pixel is in a separated state, that is, the phenomenon of color separation of the reflected light occurs, which affects the user's experience of an absolutely black screen.
  • the embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, a display panel, and a display device to improve the color separation problem of the display panel.
  • an array substrate which includes:
  • a pixel defining layer is located on one side of the base substrate, the pixel defining layer has a plurality of opening regions, a peripheral region surrounding the opening region, and except for the opening region and the peripheral region Other areas outside;
  • the first electrode layer, the first electrode layer is located on the side of the pixel defining layer away from the base substrate; the surface roughness of the first electrode layer in the peripheral area away from the base substrate is greater than The surface roughness of the first electrode layer in the other area away from the base substrate;
  • the color filter portion is located on the side of the first electrode layer away from the base substrate, and is provided in a one-to-one correspondence with the opening area; the color filter portion is located on the front side of the base substrate
  • the projection covers the orthographic projection of the opening area on the base substrate, and the color filter portion is configured to filter light incident on the color filter portion from outside.
  • the peripheral area includes a slope area connected to the opening area and a transition area connected to the slope area.
  • the surface roughness of the pixel defining layer in the peripheral area away from the base substrate is greater than the surface roughness of the pixel defining layer in other areas away from the base substrate Spend;
  • the roughness of the first electrode layer in the peripheral area is approximately the same as the surface roughness of the pixel defining layer.
  • the pixel defining layer has a plurality of recesses respectively surrounding the opening area;
  • the depressed portions are arranged in sequence in the direction in which the opening area points to the peripheral area, and the distance between the depressed portions far away from the opening area and the base substrate is greater than that near the opening area. The distance between the recess and the base substrate.
  • the pixel defining layer has a plurality of recesses surrounding the opening region;
  • the recessed portions are arranged in sequence in the direction in which the opening area points to the peripheral area, and the distance between the recessed portion far away from the opening area and the base substrate is equal to the distance between the recessed portion close to the opening area The distance between the recess and the base substrate.
  • the shape of the figure enclosed by the orthographic projection of the recess on the base substrate is the same as the shape of the orthographic projection of the opening area on the base substrate.
  • the center point of the figure enclosed by the orthographic projection of each recess on the base substrate is approximately equal to the center point of the orthographic projection of the opening area on the base substrate. overlapping.
  • the width of the recess in the direction in which the opening area points to the peripheral area ranges from 0.5 ⁇ m to 2.5 ⁇ m;
  • the value range of the distance between each of the recesses is 0.5 ⁇ m to 2.5 ⁇ m.
  • the distance between the upper surface of the recessed portion and the lower surface of the recessed portion ranges from 0.2 ⁇ m to 1.0 ⁇ m.
  • the recessed portion includes a plurality of sub-recessed portions, and two adjacent sub-recessed portions are arranged at a predetermined distance apart;
  • the shape of the figure enclosed by the orthographic projection of all the sub-recesses on the base substrate is the same as the shape of the orthographic projection of the opening area on the base substrate.
  • the shape of the orthographic projection of the sub-recess on the base substrate includes a circle, a rectangle, or an ellipse.
  • the preset distance ranges from 0.5 ⁇ m to 2.5 ⁇ m.
  • the array substrate further includes a black matrix, the black matrix surrounds at least one of the color filter portions; corresponding to one of the opening regions, the peripheral region is on the base substrate There is an overlap area between the orthographic projection of the black matrix and the orthographic projection of the black matrix on the base substrate and the orthographic projection of the color filter on the base substrate.
  • the distance between the boundary on the side of the peripheral region away from the opening region and the boundary of the opening region ranges from 6 ⁇ m to 10 ⁇ m.
  • it further includes: a second electrode layer located between the base substrate and the pixel defining layer, and the orthographic projection of the second electrode layer on the base substrate covers all The orthographic projection of the opening area on the base substrate;
  • a light-emitting layer located between the first electrode layer and the second electrode layer, and the orthographic projection of the light-emitting layer on the base substrate covers the orthographic projection of the opening area on the base substrate.
  • the embodiment of the present disclosure also provides a manufacturing method of the array substrate provided in the embodiment of the present disclosure, which includes:
  • a pixel defining layer is formed on the base substrate, and the pixel defining layer is patterned so that the pixel defining layer forms a plurality of opening regions, surrounding the peripheral region of each of the opening regions, and removing the The opening area and other areas other than the peripheral area;
  • a first electrode layer is formed on the pixel defining layer, and the surface roughness of the first electrode layer in the peripheral area away from the base substrate is greater than that of the first electrode layer in other areas away from the base substrate.
  • a color filter is formed on the base substrate on which the first electrode layer is formed.
  • the patterning of the pixel defining layer specifically includes:
  • a preset mask to expose and develop the pixel defining layer to form the opening area and the pattern of the pixel defining layer in the peripheral area, wherein the preset mask includes the opening area and The corresponding figure of the recessed part.
  • the manufacturing method further includes :
  • a black matrix is formed on the base substrate on which the first electrode layer is formed.
  • the embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a display device, which includes the display panel provided in the embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of the structure of an array substrate in the related art
  • FIG. 2 is a schematic diagram of the structure of an array substrate provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of a cross-sectional structure of a pixel defining layer provided by an embodiment of the present disclosure
  • FIG. 4A is a schematic diagram of a top view structure of a pixel defining layer provided by an embodiment of the present disclosure
  • 4B is a schematic diagram of another top-view structure of the array substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of another top view structure of a pixel defining layer provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of another top view structure of the pixel defining layer provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of a top view structure of an entire pixel defining layer provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a display panel provided by an embodiment of the disclosure.
  • FIG. 1 The structure of the array substrate in the related art is shown in FIG. 1, including: a base substrate 01, a pixel driving circuit (including a semiconductor layer P, a gate layer G, and a source/drain electrode layer SD) on the base substrate 01, and The anode layer A electrically connected to the pixel driving circuit, the pixel defining layer 02 located on the anode layer A, the pixel defining layer 02 has an opening area, the light emitting layer L is located in the opening area, and the cathode layer 03 entirely covers the pixel defining layer 02 and the opening area.
  • a pixel driving circuit including a semiconductor layer P, a gate layer G, and a source/drain electrode layer SD
  • a black matrix layer BM and a color filter portion C are also provided, and the color filter portion C is provided in a one-to-one correspondence with the opening area.
  • the structure of the array substrate shown in FIG. 1 since there is no circular polarizer, when the external light is irradiated on the display panel in the off-screen state, the light is irradiated on the cathode layer 03 through the color filter part C, and the cathode layer 03 It will reflect the external light, and due to the shape and structure design of each sub-pixel, the light reflected by each sub-pixel will be emitted in a fixed direction.
  • the emitted light corresponds to the color of each sub-pixel, which leads to The light reflected by the sub-pixels in different positions is not mixed well, and the light of each color is separated and cannot be mixed into white light. This regular color separation phenomenon is easy to be noticed by human eyes and affects users The experience of absolutely black screen.
  • embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, a display panel, and a display device.
  • specific implementations of the array substrate, the manufacturing method thereof, the display panel, and the display device provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure. And if there is no conflict, the embodiments in the application and the features in the embodiments can be combined with each other.
  • an embodiment of the present disclosure provides an array substrate.
  • the array substrate includes:
  • the pixel defining layer 2 is located on one side of the base substrate 1.
  • the pixel defining layer 2 has a plurality of opening areas a and a peripheral area b surrounding the opening area a, and other than the opening area a and the peripheral area b. Other areas c;
  • the first electrode layer 3, the first electrode layer 3 is located on the side of the pixel defining layer 2 away from the base substrate 1; the surface roughness of the first electrode layer 3 in the peripheral area b away from the base substrate 1 is greater than that in other areas The surface roughness of an electrode layer 3 away from the base substrate 1;
  • the color filter portion C is located on the side of the first electrode layer 3 away from the base substrate 1, and the color filter portion C is provided in a one-to-one correspondence with the opening area a; the orthographic projection of the color filter portion C on the base substrate 1 Covering the orthographic projection of the opening area a on the base substrate 1, the color filter portion C is configured to filter light incident on the color filter portion C; specifically, for example, the color filter portion C may be a filter that filters out red light.
  • the red color filter portion may also be a green color filter portion that filters out green light, or may be a blue color filter portion that filters out blue light; the color of light filtered by the color filter portion C corresponding to different opening regions a may be different.
  • the reflected light of the external first electrode layer in a specific direction is reduced.
  • the light irradiated on the first electrode layer in the peripheral area is diffusely reflected, that is, the light reflection direction is changed, so that the emitted light is emitted from more directions, so that the emitted light of different directions of adjacent sub-pixels can be fully reflected.
  • the mixing of the chromaticity and the formation of white light thereby alleviating the color separation phenomenon that occurs in the array substrate in the related art.
  • the proposed opening area is the effective light-emitting area of each sub-pixel;
  • the peripheral area corresponding to each opening area means that it is adjacent to the boundary of the opening area, And it surrounds the area within a preset distance of the opening area, where the preset distance needs to be set according to the area covered by the black matrix, that is, it can be irradiated on the first electrode layer through the color filter, and
  • the area where the reflected light of the first electrode layer can exit through the color filter is all within the range of the peripheral area.
  • the array substrate further includes a black matrix BM.
  • the black matrix BM surrounds the black matrix BM of each color filter C; corresponding to an opening area a, the peripheral area b is on the base substrate 1. Both the projection and the orthographic projection of the black matrix BM on the base substrate 1 and the orthographic projection of the color filter C on the base substrate 1 have overlapping areas.
  • the overlap area between the orthographic projection of the black matrix on the base substrate and the orthographic projection of the color filter on the base substrate is taken as an example for illustration, but it is not limited to this.
  • the orthographic projection of the black matrix on the base substrate and the orthographic projection of the color filter on the base substrate may not overlap each other, that is, the boundary of the color filter and the boundary of the black matrix opening completely overlap.
  • the relative positional relationship between the black matrix and the color filter can be selected according to actual conditions, and is not specifically limited here.
  • the peripheral area b includes a slope area b1 connected with the opening area a, and a transition area b2 connected with the slope area b1.
  • the surface roughness of the pixel defining layer 2 in the peripheral area b far from the base substrate 1 is greater than that of the pixel defining layer in other areas.
  • the roughness of the first electrode layer 3 in the peripheral area b is approximately the same as the surface roughness of the pixel defining layer 2.
  • the first electrode layer is mostly a metal electrode, and in order to ensure that the light emitted by each sub-pixel for display can be emitted through the first electrode layer, it is necessary to
  • the first electrode layer is set as a semi-transmissive and semi-reverse electrode, and its thickness is relatively thin, and it is difficult to directly pattern it to change the roughness. Therefore, it can be passed under the first electrode layer and adjacent to the first electrode layer.
  • the pixel defining layer is patterned to change the surface roughness of the pixel defining layer, so that when the first electrode layer is formed on the pixel defining layer, the roughness of the first electrode layer is approximately the same as the surface roughness of the pixel defining layer.
  • the roughness of the first electrode layer is exactly the same as the surface roughness of the pixel defining layer, which is more difficult. Therefore, the roughness of the first electrode layer is equal to the surface roughness of the pixel defining layer. The same, it can be understood that the roughness of the first electrode layer is approximately the same as the surface roughness of the pixel defining layer.
  • the pixel defining layer 2 has surrounding openings.
  • the recesses 21 are arranged in sequence in the direction in which the opening area a points to the peripheral area b, and the distance between the recess 21 far away from the opening area a and the base substrate 1 is greater than or equal to the distance between the recess 21 near the opening area a and the substrate 1 The distance between the substrates 1. Specifically, for example, as shown in FIG. 4B, on the right side of the opening area a, in the direction in which the opening area a points to the peripheral area b, the distance h2 between the recess 21 closer to the opening area a and the base substrate 1 is greater than The distance h1 between the recess 21 farther from the opening area a and the base substrate 1.
  • a plurality of depressions can be formed on the surface of the pixel defining layer in the peripheral area to change the roughness of the pixel defining layer in the peripheral area, wherein each The depths of the recesses are set to the same depth. Since the pixel defining layer in the peripheral area includes the transitional slope area and the flat area, the distance between the recesses located in the transitional slope area and the base substrate is smaller than the recesses located in the flat area The distance between the part and the base substrate.
  • the depth of the recessed portion should not be set too large, because if it is set too much, the formed first electrode layer is prone to short-circuit, or the resistance of the first electrode layer is too large.
  • the depth of the depressed portion can be set to 0.2 ⁇ m to 1.0 ⁇ m, that is, the distance between the upper surface of the depressed portion and the lower surface of the depressed portion ranges from 0.2 ⁇ m to 1.0 ⁇ m. Specifically, 0.5 ⁇ m or 0.8 ⁇ m can be selected, which can be selected according to actual needs, and there is no specific limitation here.
  • the shape of the pattern enclosed by the orthographic projection of the recess 21 on the base substrate 1 and the opening area a are on the base substrate 1.
  • the shape of the orthographic projection is the same.
  • the shape of the orthographic projection of the recess on the base substrate can be set to be the same as the shape of the orthographic projection of the opening area on the base substrate, for example, the opening area is six. It is also possible to set the shape enclosed by the orthographic projection of the recess on the base substrate as a hexagon, so that the area of the peripheral area can be maximized, and more recesses can be set in the peripheral area to Increase the roughness of the pixel defining layer in the peripheral area.
  • the shape enclosed by the orthographic projection of the recess on the base substrate may also be different from the shape of the orthographic projection of the opening area on the base substrate, and can be selected according to actual needs, and is not specifically limited here.
  • the center point of the pattern enclosed by the orthographic projection of each recess 21 on the base substrate 1 and the opening area a are on the base substrate 1.
  • the center points of the orthographic projections roughly overlap. Specifically, due to actual process errors, the center point of the pattern enclosed by the orthographic projection of each recess 21 on the base substrate 1 and the center point of the orthographic projection of the opening area a on the base substrate 1 are completely overlapped, which is difficult.
  • the center point of the pattern enclosed by the orthographic projection of each recess 21 on the base substrate 1 overlaps the center point of the orthographic projection of the opening area a on the base substrate 1, which can be understood as making each recess
  • the center point of the figure enclosed by the orthographic projection of the portion 21 on the base substrate 1 approximately overlaps the center point of the orthographic projection of the opening area a on the base substrate 1.
  • the center point of the pattern enclosed by the orthographic projection of the recess on the base substrate and the center point of the orthographic projection of the opening area on the base substrate are set to be the same center Point, the roughness of the positions in the peripheral area with the same distance from the center point can be the same, so as to ensure that the direction of the reflected light at each position in the peripheral area is changed, and the direction of the reflected light is increased.
  • the width of the recess in the direction in which the opening area points to the peripheral area ranges from 0.5 ⁇ m to 2.5 ⁇ m;
  • the range of the spacing between the recesses is 0.5 ⁇ m to 2.5 ⁇ m.
  • the first electrode layer formed on the pixel defining layer can form a gentle wave structure, wherein the width of the recesses and the spacing between the recesses can be set to 0.5 ⁇ m to 2.5 ⁇ m, such as 0.8 ⁇ m or 0.8 ⁇ m. 1.5 ⁇ m, of course, its specific value can be selected according to actual needs, and is not specifically limited here.
  • the recess includes a plurality of sub-recesses 211, and two adjacent sub-recesses 211 are arranged at a predetermined distance apart;
  • the shape of the figure enclosed by the orthographic projection of all the sub-recesses 211 on the base substrate 1 is the same as the shape of the orthographic projection of the opening area a on the base substrate 1.
  • the structure of the recessed portion may be further designed, that is, the recessed portion is set to include a plurality of sub-recessed portions, The adjacent sub-recesses are separated by a predetermined distance.
  • This arrangement not only enables the surface of the pixel defining layer to form a wave-shaped topography in the direction in which the opening area points to the peripheral area, and is positioned along each recessed portion. Waves can also be formed in the direction of the surrounding shape, which can further increase the emission direction of the reflected light.
  • the shape of the orthographic projection of the sub-recess 211 on the base substrate 1 includes a circle, a rectangle, or an ellipse.
  • the sub-depressed portions can be set to the same shape, of course, they can be set to different shapes as needed, specifically, they can be circular, rectangular or arbitrary polygons. This is not specifically limited.
  • the value range of the distance between adjacent sub-recesses can be 0.5 ⁇ m ⁇ 2.5 ⁇ m.
  • the size of the sub-recesses can be set to be the same as the size of adjacent sub-recesses, which can increase the number of patterns formed. The uniformity is beneficial to the smooth transition of the first electrode formed later, and avoids the problem of disconnection.
  • the distance between the boundary on the side of the peripheral area away from the opening area and the boundary of the opening area ranges from 6 ⁇ m to 10 ⁇ m.
  • the width of the peripheral area may range from 6 ⁇ m to 10 ⁇ m, and the width is based on the boundary of the black matrix opening and the opening.
  • the separation distance between the region boundaries is set, that is, the separation distance between the boundary of the black matrix opening and the boundary of the opening area is generally 6 ⁇ m to 10 ⁇ m.
  • the peripheral area can be far away from the boundary on the side of the opening area.
  • the distance from the opening area is set to be greater than or equal to the separation distance between the boundary of the black matrix opening and the boundary of the opening area.
  • the specific value of the separation distance can be selected according to actual use conditions and is not specifically limited here.
  • the pixel defining layer includes an opening area a and a peripheral area b surrounding the opening area a, as well as other areas, such as The gap area between two adjacent peripheral areas b. 7 in order to show the relative positional relationship between the opening area a, the peripheral area b, and other areas, and does not show the specific structure in each area.
  • the specific structure design in the peripheral area b please refer to FIGS. 4A to 4A. The structure shown in 6 will not be repeated here.
  • the array substrate further includes: a second electrode layer A located between the base substrate 1 and the pixel defining layer 2, and the second electrode layer
  • the orthographic projection of A on the base substrate 1 covers the orthographic projection of the opening area a on the base substrate 1;
  • the light-emitting layer L located between the first electrode layer 3 and the second electrode layer A, the orthographic projection of the light-emitting layer L on the base substrate 1 covers the orthographic projection of the opening area a on the base substrate 1.
  • the second electrode layer corresponding to each opening area is arranged in blocks, connected to the corresponding pixel driving circuit, and the voltage applied to the second electrode layer and the first electrode layer In cooperation, the light-emitting layer is driven to emit light.
  • the light-emitting layer provided by the embodiment of the present disclosure may all emit white light, or the light-emitting layer corresponding to each opening area emits light corresponding to the color filter portion. It can be selected according to actual needs, and there is no specific limitation here.
  • the embodiments of the present disclosure also provide a manufacturing method of an array substrate, including:
  • a pixel defining layer on the base substrate, and patterning the pixel defining layer so that the pixel defining layer forms a plurality of opening regions, a peripheral region surrounding the opening region, and other regions except the opening region and the peripheral region;
  • a color filter is formed on the base substrate on which the first electrode layer is formed.
  • patterning the pixel defining layer may specifically include:
  • a preset mask is used to expose and develop the pixel defining layer to form an opening area and a pattern of the pixel defining layer in a peripheral area.
  • the preset mask includes an opening area and a pattern corresponding to the recessed portion.
  • the manufacturing method further includes: A black matrix is formed on the substrate.
  • the manufacturing method of the array substrate has all the advantages of the embodiments of the above-mentioned array substrate, and the functions and relative positional relationships of the respective film layers of the array substrate have been described in detail in the above-mentioned embodiments. Implementation, I will not repeat it here.
  • an embodiment of the present disclosure further provides a display panel, as shown in FIG. One side encapsulation layer 4, optical adhesive layer 5 and protective cover 6.
  • the display panel has all the advantages of the above-mentioned embodiments of the array substrate, and the functions and relative positional relationships of the respective film layers of the array substrate have been described in detail in the above-mentioned embodiments, which can be implemented with reference to the above-mentioned embodiments. Go into details again.
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the implementation of the display device can be referred to the embodiment of the above-mentioned display panel, and the repetition will not be repeated.
  • the embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, a display panel, and a display device.
  • the array substrate includes a base substrate, a pixel defining layer on the base substrate, and the pixel defining layer has a plurality of An opening area and a peripheral area surrounding each of the opening areas; further comprising: a first electrode layer located on the side of the pixel defining layer away from the base substrate; further including: located at the first electrode layer away from the On one side of the base substrate, a color filter section and a black matrix surrounding each of the color filter sections are provided in one-to-one correspondence with the opening area; the orthographic projection of the color filter section on the base substrate covers the An orthographic projection of an opening area on the base substrate, the color filter portion is configured to filter incident light from the outside; corresponding to one of the opening areas, the peripheral area is on the front of the base substrate There is an overlap area between the projection and the orthographic projection of the black matrix on the base substrate and the orthographic projection of the color filter on the base substrate;
  • the present disclosure makes the roughness of the first electrode layer in the peripheral area greater than the roughness of the first electrode layer in other areas, so that the light irradiated on the first electrode layer in the peripheral area is reflected in different directions, that is, through
  • the roughness of the first electrode layer in the peripheral area is designed to change the original light reflection direction. Since the reflected light of the first electrode layer is reflected in different directions, the reflected light corresponding to the sub-pixels of different colors The light can be mixed uniformly, thereby alleviating the phenomenon of color separation on the display panel, and improving the user's experience of the absolute black screen.

Abstract

本公开提供了一种阵列基板、其制作方法、显示面板及显示装置，该阵列基板包括：衬底基板，位于衬底基板上的像素界定层，像素界定层具有多个开口区域、围绕所述开口区域的周边区域，以及除所述开口区域和所述周边区域之外的其他区域；第一电极层，所述第一电极层位于所述像素界定层远离所述衬底基板的一侧；所述周边区域内的所述第一电极层远离所述衬底基板的表面粗糙度大于所述其他区域内的所述第一电极层远离所述衬底基板的表面粗糙度。通过使各周边区域内的第一电极层的粗糙度大于其他区域内第一电极层的粗糙度，来改变原有光的反射方向，从而可以使各不同颜色的子像素对应的反射光可以进行均匀的混光，以缓解了显示面板出现颜色分离的现象。

Description

阵列基板、其制作方法、显示面板及显示装置
相关申请的交叉引用
本申请要求在2020年02月27日提交中国专利局、申请号为202010125182.0、申请名称为“一种阵列基板、其制作方法、显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤指一种阵列基板、其制作方法、显示面板及显示装置。
背景技术
随着显示技术的发展，人们对显示面板的纤薄化及可弯曲性的需求日益增加，可通过减薄模组的厚度来满足这一需求。
相关技术中，阵列基板中的圆偏光片的厚度在整个阵列基板中的厚度占比较大，为解决该问题，将滤色部整合在发光器件封装层上，取代了圆偏光片，从而可以大幅降低了模组厚度。但是，针对上述阵列基板的结构，在熄屏状态，在外界光照射在显示面板上时，由于各子像素中的阴极层对照射在其上的光具有固定的反射方向，且不同位置的子像素所反射回的光呈分离状态，即发生了反射光颜色分离现象，影响用户对绝对黑画面的体验。
因此，如何缓解显示面板出现的颜色分离问题，成为本领域技术人员亟待解决的技术问题。
发明内容
有鉴于此，本公开实施例提供了一种阵列基板、其制作方法、显示面板及显示装置，用以改善显示面板出现的颜色分离的问题。
第一方面，本公开实施例提供了一种阵列基板，其中，包括：
衬底基板；
像素界定层，所述像素界定层位于所述衬底基板的一侧，所述像素界定层具有多个开口区域、围绕所述开口区域的周边区域，以及除所述开口区域和所述周边区域之外的其他区域；
第一电极层，所述第一电极层位于所述像素界定层远离所述衬底基板的一侧；所述周边区域内的所述第一电极层远离所述衬底基板的表面粗糙度大于所述其他区域内的所述第一电极层远离所述衬底基板的表面粗糙度；
滤色部，所述滤色部位于所述第一电极层远离所述衬底基板的一侧，与所述开口区域一一对应设置；所述滤色部在所述衬底基板上的正投影覆盖所述开口区域在所述衬底基板上的正投影，所述滤色部被配置为对外界入射所述滤色部的光进行滤光。
在一种可能的实施方式中，所述周边区域包括与所述开口区域连接坡面区域，以及与所述坡面区域衔接的过渡区域。
在一种可能的实施方式中，所述周边区域内的所述像素界定层的远离所述衬底基板的表面粗糙度大于其他区域内的所述像素界定层远离所述衬底基板的表面粗糙度；
在所述周边区域内所述第一电极层的粗糙度与所述像素界定层的表面粗糙度大致相同。
在一种可能的实施方式中，对应于一个所述开口区域，在围绕所述开口区域的周边区域内，所述像素界定层具有分别围绕所述开口区域的多个凹陷部；
所述凹陷部在所述开口区域指向所述周边区域的方向上依次排列，且远离所述开口区域的所述凹陷部与所述衬底基板之间的距离大于靠近所述开口区域的所述凹陷部与所述衬底基板之间的距离。
在一种可能的实施方式中，对应于一个所述开口区域，在围绕所述开口区域的周边区域内，所述像素界定层具有围绕所述开口区域的多个凹陷部；
所述凹陷部在所述开口区域指向所述周边区域的方向上依次排列，且远 离所述开口区域的所述凹陷部与所述衬底基板之间的距离等于靠近所述开口区域的所述凹陷部与所述衬底基板之间的距离。
在一种可能的实施方式中，所述凹陷部在所述衬底基板上的正投影所围成图形的形状与所述开口区域在所述衬底基板上的正投影的形状相同。
在一种可能的实施方式中，各所述凹陷部在所述衬底基板上的正投影所围成图形的中心点与所述开口区域在所述衬底基板上的正投影的中心点大致重叠。
在一种可能的实施方式中，所述凹陷部在所述开口区域指向所述周边区域的方向上的宽度的取值范围为0.5μm～2.5μm；
各所述凹陷部之间的间距的取值范围为0.5μm～2.5μm。
在一种可能的实施方式中，所述凹陷部的上表面与所述凹陷部的下表面之间的距离的取值范围为0.2μm～1.0μm。
在一种可能的实施方式中，所述凹陷部包括多个子凹陷部，相邻两个所述子凹陷部间隔预设距离设置；
全部所述子凹陷部在所述衬底基板上的正投影围成的图形的形状与所述开口区域在所述衬底基板上的正投影的形状相同。
在一种可能的实施方式中，所述子凹陷部在所述衬底基板上的正投影的形状包括圆形、长方形或椭圆形。
在一种可能的实施方式中，所述预设距离的取值范围为0.5μm～2.5μm。
在一种可能的实施方式中，所述阵列基板还包括黑矩阵，所述黑矩阵围绕至少一个所述滤色部；对应于一个所述开口区域，所述周边区域在所述衬底基板上的正投影与所述黑矩阵在所述衬底基板上的正投影和所述滤色部在所述衬底基板上的正投影均存在交叠区域。
在一种可能的实施方式中，所述周边区域远离所述开口区域一侧的边界与所述开口区域的边界之间距离的取值范围为6μm～10μm。
在一种可能的实施方式中，还包括：位于所述衬底基板与所述像素界定层之间的第二电极层，所述第二电极层在所述衬底基板上的正投影覆盖所述 开口区域在所述衬底基板上的正投影；
位于所述第一电极层与所述第二电极层之间的发光层，所述发光层在所述衬底基板上的正投影覆盖所述开口区域在所述衬底基板上的正投影。
本公开实施例还提供一种如本公开实施例提供的所述阵列基板的制作方法，其中，包括：
提供一衬底基板；
在所述衬底基板上形成像素界定层，并对所述像素界定层进行构图，以使所述像素界定层形成多个开口区域、围绕每个所述开口区域的周边区域，以及除所述开口区域和所述周边区域之外的其他区域；
在所述像素界定层上形成第一电极层，且所述周边区域内的所述第一电极层远离所述衬底基板的表面粗糙度大于其他区域内的所述第一电极层远离所述衬底基板的表面粗糙度；
在形成有所述第一电极层的衬底基板上形成滤色部。
在一种可能的实施方式中，所述对所述像素界定层进行构图具体包括：
在所述像素界定层上形成光刻胶；
利用预设掩膜版对所述像素界定层进行曝光显影，形成所述开口区域以及所述像素界定层在周边区域内的图形，其中，所述预设掩膜版包括所述开口区域以及与所述凹陷部对应的图形。
在一种可能的实施方式中，在所述像素界定层上形成第一电极层之后，以及在形成有所述第一电极层的衬底基板上形成滤色部之前，所述制作方法还包括：
在形成有所述第一电极层的衬底基板上形成黑矩阵。
本公开实施例还提供一种显示面板，其中，包括如本公开实施例提供的所述阵列基板。
本公开实施例还提供一种显示装置，其中，包括如本公开实施例提供的所述显示面板。
附图说明
图1为相关技术中阵列基板的结构示意图；
图2为本公开实施例提供的阵列基板的结构示意图；
图3为本公开实施例提供的像素界定层的剖面结构示意图；
图4A为本公开实施例提供的像素界定层的一种俯视结构示意图；
图4B为本公开实施例提供的阵列基板的另一种俯视结构示意图；
图5为本公开实施例提供的像素界定层的另一种俯视结构示意图；
图6为本公开实施例提供的像素界定层的又一种俯视结构示意图；
图7为本公开实施例提供的整层像素界定层的俯视结构示意图；
图8为本公开实施例提供的显示面板的结构示意图。
具体实施方式
相关技术中的阵列基板的结构如图1所示，包括：衬底基板01，位于衬底基板01上的像素驱动电路(包括半导体层P、栅极层G和源漏电极层SD)，以及与该像素驱动电路电连接的阳极层A，位于阳极层A上的像素界定层02，该像素界定层02具有开口区域，发光层L位于该开口区域内，阴极层03整面覆盖像素界定层02和开口区域，在阴极层03背离衬底基板01的一侧还设置有黑矩阵层BM和滤色部C，该滤色部C与开口区域一一对应设置。针对如图1所示的阵列基板的结构，由于没有设置圆偏光片，在熄屏状态下，外界光照射在显示面板上时，光线经过滤色部C照射在阴极层03上，阴极层03会对外界光产生反射，并且由于各子像素的形状及结构设计，会导致各子像素所反射的光会沿固定的方向出射，所出射的光与各子像素的颜色对应，这就导致了不同位置的子像素所反射回的光没有很好的进行混光，各颜色的光呈分离状态，不能很好的混合成白光，这种规律性的色分离现象容易被人眼察觉，影响用户对绝对黑画面的体验。
基于相关技术中的阵列基板存在的上述问题，本公开实施例提供了一种阵列基板、其制作方法、显示面板及显示装置。为了使本公开的目的，技术 方案和优点更加清楚，下面结合附图，对本公开实施例提供的阵列基板、其制作方法、显示面板及显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅用于说明和解释本公开，并不用于限定本公开。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
附图中各部件的形状和大小不反应真实比例，目的只是示意说明本公开内容。
具体地，本公开实施例提供了一种阵列基板，如图2所示，该阵列基板包括：
衬底基板1；
像素界定层2，像素界定层2位于衬底基板1的一侧，像素界定层2具有多个开口区域a以及围绕开口区域a的周边区域b，以及除开口区域a和周边区域b之外的其他区域c；
第一电极层3，第一电极层3位于像素界定层2远离衬底基板1的一侧；周边区域b内的第一电极层3远离衬底基板1的表面粗糙度大于其他区域内的第一电极层3远离衬底基板1的表面粗糙度；
滤色部C，滤色部C位于第一电极层3远离衬底基板1的一侧，与开口区域a一一对应设置滤色部C；滤色部C在衬底基板1上的正投影覆盖开口区域a在衬底基板1上的正投影，滤色部C被配置为对外界入射滤色部C的光进行滤光；具体的，例如，滤色部C可以为滤除红光的红色滤色部，也可以为滤除绿光的绿色滤色部，也可以为滤除蓝光的蓝色滤色部；与不同开口区域a对应的滤色部C滤除的光色可以不同。
具体地，在本公开实施例提供的阵列基板中，通过将周边区域内的第一电极层粗糙度设置为大于其他区域的粗糙度，降低外界第一电极层在某一特定方向上的反射光线，使照射在周边区域内第一电极层上的光发生漫反射，即改变光线反射方向，使出射光从更多的方向出射，从而使得相邻的子像素的不同方向的出射光能够进行充分的混合，形成白光，从而缓解相关技术中阵列基板出现的色分离现象。
需要说明的是，在本公开实施例提供的阵列基板中，所提出的开口区域即为各子像素的有效发光区域；每个开口区域对应的周边区域是指，与该开口区域的边界紧邻，且围绕该开口区域预设距离之内的区域，其中，该预设距离的设定需要根据黑矩阵覆盖的区域进行设定，也就是说能够通过滤色部照射在第一电极层上，且第一电极层的反射光能够通过滤色部出射的区域均在周边区域的范围内。通常需使得周边区域在衬底基板上的正投影与黑矩阵在衬底基板上的正投影和滤色部在衬底基板的正投影均存在交叠区域。
具体的，结合图2所示，阵列基板还包括黑矩阵BM，黑矩阵BM围绕每个滤色部C的黑矩阵BM；对应于一个开口区域a，周边区域b在衬底基板1上的正投影与黑矩阵BM在衬底基板1上的正投影和滤色部C在衬底基板1上的正投影均存在交叠区域。
其中，为保证各子像素用于显示的光能够均匀出射，需保证开口区域内的第一电极层保持平整。同时，保证除周边区域内的其他区域内的第一电极层平整，即避免第一电极大范围的不平整，是为了可以有效的降低第一电极的电阻，避免电阻过大形成显示不良。
需要说明的是，在图1中，是以黑矩阵在衬底基板上的正投影与滤色部在衬底基板上的正投影存在交叠区域为例进行示意的，但并不仅限于此，黑矩阵在衬底基板上的正投影与滤色部在衬底基板上的正投影也可以互不重叠，即使得滤色部的边界与黑矩阵开口的边界完全重叠。其中，黑矩阵和滤色部之间的相对位置关系，可根据实际情况进行选择，在此不作具体限定。
具体的，结合图2所示，周边区域b包括与开口区域a连接坡面区域b1，以及与坡面区域b1衔接的过渡区域b2。
可选地，在本公开实施例提供的阵列基板中，如图1和图2所示，周边区域b内的像素界定层2的远离衬底基板1的表面粗糙度大于其他区域内的像素界定层2远离衬底基板1的表面粗糙度；
在周边区域b内第一电极层3的粗糙度与像素界定层2的表面粗糙度大致相同。
具体地，在本公开实施例提供的阵列基板中，由于第一电极层多为金属电极，且为了保证各子像素所发出的用于显示的光能透过该第一电极层出射，需要将第一电极层设置为半透半反电极，其厚度较薄，直接对其构图以改变粗糙度存在一定的困难，因此，可以通过位于第一电极层下方，且与该第一电极层紧邻的像素界定层进行构图，改变像素界定层表面的粗糙度，从而使得再在像素界定层上形成第一电极层时，第一电极层的粗糙度则与像素界定层的表面粗糙度大致相同，从而降低了制作工艺的难度。具体的，由于实际工艺误差，使第一电极层的粗糙度与像素界定层的表面粗糙度完全严格相同，难度较大，因此，使第一电极层的粗糙度与像素界定层的表面粗糙度相同，可以理解为第一电极层的粗糙度与像素界定层的表面粗糙度大致相同。
可选地，在本公开实施例提供的阵列基板中，如图3和图4A所示，对应于一个开口区域a，在围绕开口区域a的周边区域b内，像素界定层2具有分别围绕开口区域a的多个凹陷部21；
该凹陷部21在开口区域a指向周边区域b的方向上依次排列，且远离开口区域a的凹陷部21与衬底基板1之间的距离大于或等于靠近开口区域a的凹陷部21与衬底基板1之间的距离。具体的，例如，结合图4B所示，开口区域a的右侧，在开口区域a指向周边区域b的方向上，离开口区域a较近的凹陷部21与衬底基板1的距离h2，大于离开口区域a较远的凹陷部21与衬底基板1的距离h1。
具体地，在本公开实施例提供的阵列基板中，可以通过在周边区域内，在像素界定层的表面形成多个凹陷部，以改变周边区域内像素界定层的粗糙度，其中，可以将各凹陷部的深度设置为相同深度，由于该周边区域内像素界定层包括斜坡过度区和平面区，因此导致位于斜坡过度区内的凹陷部与衬底基板之间的距离小于位于平面区内的凹陷部与衬底基板之间的距离。
其中，该凹陷部的深度不宜设置的过大，因为，设置过大会到这所形成的第一电极层容易出现短路，或者导致第一电极层的电阻过大。可以将凹陷部的深度设置为0.2μm～1.0μm，即该凹陷部的上表面与凹陷部的下表面之间 的距离的取值范围为0.2μm～1.0μm。具体可以选择0.5μm或0.8μm，可根据实际需要进行选择，在此不作具体限定。
可选地，在本公开实施例提供的阵列基板中，如图4A所示，该凹陷部21在衬底基板1上的正投影所围成图形的形状与开口区域a在衬底基板1上的正投影的形状相同。
具体地，在本公开实施例提供的阵列基板中，可以将凹陷部在衬底基板上的正投影的形状设置为与开口区域在衬底基板上正投影的形状相同，如，开口区域为六边形，也可以将凹陷部在衬底基板上的正投影围成的形状设置为六边形，这样可以最大化的利用周边区域的面积，可以在周边区域内设置较多的凹陷部，以增加像素界定层在周边区域的粗糙度。当然，该凹陷部在衬底基板上的正投影所围成的形状也可以与开口区域在衬底基板上的正投影的形状不同，可根据实际需要进行选择，在此不作具体限定。
可选地，在本公开实施例提供的阵列基板中，如图4A所示，各凹陷部21在衬底基板1上的正投影所围成图形的中心点与开口区域a在衬底基板1上的正投影的中心点大致重叠。具体的，由于实际工艺误差，使各凹陷部21在衬底基板1上的正投影所围成图形的中心点与开口区域a在衬底基板1上的正投影的中心点完全严格重叠，难度较大，因此，使各凹陷部21在衬底基板1上的正投影所围成图形的中心点与开口区域a在衬底基板1上的正投影的中心点重叠，可以理解为使各凹陷部21在衬底基板1上的正投影所围成图形的中心点与开口区域a在衬底基板1上的正投影的中心点大致重叠。
具体地，在本公开实施例提供的阵列基板中，将凹陷部在衬底基板上的正投影所围成图形的中心点与开口区域在衬底基板上的正投影的中心点设置为同一中心点，可以使周边区域内与中心点之间距离相同的位置的粗糙度是相同，以保证对周边区域内每个位置的反射光的方向进行改变，增加反射光出射的方向。
可选地，在本公开实施例提供的阵列基板中，该凹陷部在开口区域指向周边区域的方向上的宽度的取值范围为0.5μm～2.5μm；
各凹陷部之间的间距的取值范围为0.5μm～2.5μm。
具体地，在本公开实施例提供的阵列基板中，为了避免像素界定层的表面过于粗糙，增大第一电极层的电阻，影响显示质量，需要使各凹陷部之间间隔一定的距离，从而使在像素界定层上形成的第一电极层能够形成平缓的波浪结构，其中，可以将凹陷部的宽度和各凹陷部之间的间距设置为0.5μm～2.5μm，如可以设置为0.8μm或1.5μm，当然，其具体的取值可根据实际需要进行选择，在此不作具体限定。
可选地，在本公开实施例提供的阵列基板中，如图5所示，该凹陷部包括多个子凹陷部211，相邻两个子凹陷部211间隔预设距离设置；
全部子凹陷部211在衬底基板1上的正投影围成的图形的形状与开口区域a在衬底基板1上的正投影的形状相同。
具体地，在本公开实施例提供的阵列基板中，为进一步的增加周边区域内像素界定层的粗糙度，可以对凹陷部的结构进行进一步的设计，即将凹陷部设置为包括多个子凹陷部，使得相邻的子凹陷部之间间隔预设距离，通过该种设置不仅使得在开口区域指向周边区域的方向上像素界定层的表面能够形成波浪形的形貌，在沿着每个凹陷部所围成形状的走向上也能形成波浪形成形貌，从而可以进一步的增加反射光的出射方向。
可选地，在本公开实施例提供的阵列基板中，如图5和图6所示，该子凹陷部211在衬底基板1上的正投影的形状包括圆形、长方形或椭圆形。
具体地，在本公开实施例提供的阵列基板中，为便于构图可以将各子凹陷部设置为同一形状，当然可以根据需要设置为不同的形状，具体可以为圆形，长方形或任意多边形，在此不作具体限定。
其中，相邻子凹陷部之间的距离的取值范围可以为0.5μm～2.5μm，具体可以将子凹陷部的尺寸设置为与相邻子凹陷部的尺寸相同，这样可以使增加所形成图形的均匀度，有利于之后形成的第一电极的平缓过度，避免出现断路问题。
可选地，在本公开实施例提供的阵列基板中，周边区域远离开口区域一 侧的边界与开口区域的边界之间距离的取值范围为6μm～10μm。
具体地，在本公开实施例提供的阵列基板中，在开口区域指向周边区域的方向上，该周边区域的宽度的取值范围可以为6μm～10μm，该宽度是根据黑矩阵开口的边界与开口区域边界之间的间隔距离进行设定的，即黑矩阵开口的边界与开口区域边界之间的间隔距离一般为6μm～10μm，在设置周边区域时，可以将周边区域远离开口区域一侧的边界与开口区域之间的距离设置为大于或等于黑矩阵开口的边界与开口区域边界之间的间隔距离，该间隔距离的具体取值可根据实际使用情况进行选择，在此不作具体限定。
需要说明的是，在本公开实施例提供的阵列基板中，如图7所示，该像素界定层除了包括开口区域a，以及围绕该开口区域a的周边区域b外，还包括其他区域，如相邻两个周边区域b之间的间隙区域。其中，图7为了示出开口区域a、周边区域b和其他区域之间的相对位置关系，并未示出各区域内的具体结构，该周边区域b内的具体结构设计可参考图4A至图6所示的结构，在此不再赘述。
可选地，在本公开实施例提供的阵列基板中，如图2所示，该阵列基板还包括：位于衬底基板1与像素界定层2之间的第二电极层A，第二电极层A在衬底基板1上的正投影覆盖开口区域a在衬底基板1上的正投影；
位于第一电极层3与第二电极层A之间的发光层L，发光层L在衬底基板上1的正投影覆盖开口区域a在衬底基板1上的正投影。
具体地，在本公开实施例提供的阵列基板中，各开口区域对应的第二电极层是分区块设置的，连接对应的像素驱动电路，在第二电极层和第一电极层所施加电压的配合下驱动发光层发光。其中，由于本公开的阵列基板设置有滤色部，因此，本公开实施例提供的发光层可以全部发白光，或者各开口区域对应的发光层发出与滤色部对应的光。可根据实际需要进行选择，在此不作具体限定。
基于同一公开构思，本公开实施例还提供了一种阵列基板的制作方法，包括：
提供一衬底基板；
在衬底基板上形成像素界定层，并对像素界定层进行构图，以使像素界定层形成多个开口区域、围绕开口区域的周边区域以及除开口区域和周边区域之外的其他区域；
在像素界定层上形成第一电极层，且周边区域内的第一电极层远离衬底基板的表面粗糙度大于其他区域内的第一电极层远离衬底基板的表面粗糙度；
在形成有第一电极层的衬底基板上形成滤色部。
可选地，在本公开实施例提供的阵列基板的制作方法中，对像素界定层进行构图可以具体包括：
在像素界定层上形成光刻胶；
利用预设掩膜版对像素界定层进行曝光显影，形成开口区域以及像素界定层在周边区域内的图形，其中，预设掩膜版包括开口区域以及与凹陷部对应的图形。
可选的，在像素界定层上形成第一电极层之后，以及在形成有第一电极层的衬底基板上形成滤色部之前，制作方法还包括：在形成有第一电极层的衬底基板上形成黑矩阵。
其中，该阵列基板的制作方法具有上述阵列基板的实施例的全部优点，且阵列基板的各膜层的功能及相对位置关系在上述实施例中已经进行了详细的阐述，可参见上述实施例进行实施，在此不再赘述。
基于同一公开构思，本公开实施例还提供了一种显示面板，如图8所示，该显示面板包括上述任一实施例提供的阵列基板，还包括依次位于滤色部C背离衬底基板1一侧封装层4、光学胶层5和保护盖板6。
该显示面板具有上述阵列基板的实施例的全部优点，且阵列基板的各膜层的功能及相对位置关系在上述实施例中已经进行了详细的阐述，可参见上述实施例进行实施，在此不再赘述。
基于同一公开构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置可以为：手机、平板电脑、电视机、 显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
本公开实施例提供了一种阵列基板、其制作方法、显示面板及显示装置，该阵列基板包括：衬底基板，位于所述衬底基板上的像素界定层，所述像素界定层具有多个开口区域以及围绕每个所述开口区域的周边区域；还包括：位于所述像素界定层远离所述衬底基板一侧的第一电极层；还包括：位于所述第一电极层远离所述衬底基板一侧，与所述开口区域一一对应设置滤色部，以及围绕每个所述滤色部的黑矩阵；所述滤色部在所述衬底基板上的正投影覆盖所述开口区域在所述衬底基板上的正投影，所述滤色部被配置为对外界入射光进行滤光；对应于一个所述开口区域，所述周边区域在所述衬底基板上的正投影与所述黑矩阵在所述衬底基板上的正投影和所述滤色部在所述衬底基板上的正投影均存在交叠区域；所述周边区域内的所述第一电极层的粗糙度大于其他区域内的所述第一电极层的粗糙度。本公开通过使周边区域内的第一电极层的粗糙度大于其他区域内第一电极层的粗糙度，使外界照射在周边区域内第一电极层上的光以不同的方向反射出去，即通过对第一电极层在周边区域内的粗糙度进行设计，来改变原有光的反射方向，由于第一电极层的反射光是以不同的方向反射的，各不同颜色的子像素对应的反射光可以进行均匀的混光，从而缓解了显示面板出现颜色分离的现象，提高了用户对绝对黑画面的体验。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (20)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    像素界定层，所述像素界定层位于所述衬底基板的一侧，所述像素界定层具有多个开口区域、围绕所述开口区域的周边区域，以及除所述开口区域和所述周边区域之外的其他区域；
    第一电极层，所述第一电极层位于所述像素界定层远离所述衬底基板的一侧；所述周边区域内的所述第一电极层远离所述衬底基板的表面粗糙度大于所述其他区域内的所述第一电极层远离所述衬底基板的表面粗糙度；
    滤色部，所述滤色部位于所述第一电极层远离所述衬底基板的一侧，与所述开口区域一一对应设置；所述滤色部在所述衬底基板上的正投影覆盖所述开口区域在所述衬底基板上的正投影，所述滤色部被配置为对外界入射所述滤色部的光进行滤光。
  2. 如权利要求1所述的阵列基板，其中，所述周边区域包括与所述开口区域连接坡面区域，以及与所述坡面区域衔接的过渡区域。
  3. 如权利要求1所述的阵列基板，其中，所述周边区域内的所述像素界定层的远离所述衬底基板的表面粗糙度大于其他区域内的所述像素界定层远离所述衬底基板的表面粗糙度；
    在所述周边区域内所述第一电极层的粗糙度与所述像素界定层的表面粗糙度大致相同。
  4. 如权利要求3所述的阵列基板，其中，对应于一个所述开口区域，在围绕所述开口区域的周边区域内，所述像素界定层具有分别围绕所述开口区域的多个凹陷部；
    所述凹陷部在所述开口区域指向所述周边区域的方向上依次排列，且远离所述开口区域的所述凹陷部与所述衬底基板之间的距离大于靠近所述开口区域的所述凹陷部与所述衬底基板之间的距离。
  5. 如权利要求3所述的阵列基板，其中，对应于一个所述开口区域，在围绕所述开口区域的周边区域内，所述像素界定层具有围绕所述开口区域的多个凹陷部；
    所述凹陷部在所述开口区域指向所述周边区域的方向上依次排列，且远离所述开口区域的所述凹陷部与所述衬底基板之间的距离等于靠近所述开口区域的所述凹陷部与所述衬底基板之间的距离。
  6. 如权利要求4或5所述的阵列基板，其中，所述凹陷部在所述衬底基板上的正投影所围成图形的形状与所述开口区域在所述衬底基板上的正投影的形状相同。
  7. 如权利要求6所述的阵列基板，其中，各所述凹陷部在所述衬底基板上的正投影所围成图形的中心点与所述开口区域在所述衬底基板上的正投影的中心点大致重叠。
  8. 如权利要求4或5所述的阵列基板，其中，所述凹陷部在所述开口区域指向所述周边区域的方向上的宽度的取值范围为0.5μm～2.5μm；
    各所述凹陷部之间的间距的取值范围为0.5μm～2.5μm。
  9. 如权利要求4或5所述的阵列基板，其中，所述凹陷部的上表面与所述凹陷部的下表面之间的距离的取值范围为0.2μm～1.0μm。
  10. 如权利要求4或5所述的阵列基板，其中，所述凹陷部包括多个子凹陷部，相邻两个所述子凹陷部间隔预设距离设置；
    全部所述子凹陷部在所述衬底基板上的正投影围成的图形的形状与所述开口区域在所述衬底基板上的正投影的形状相同。
  11. 如权利要求10所述的阵列基板，其中，所述子凹陷部在所述衬底基板上的正投影的形状包括圆形、长方形或椭圆形。
  12. 如权利要求10所述的阵列基板，其中，所述预设距离的取值范围为0.5μm～2.5μm。
  13. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括黑矩阵，所述黑矩阵围绕至少一个所述滤色部；对应于一个所述开口区域，所述周边 区域在所述衬底基板上的正投影与所述黑矩阵在所述衬底基板上的正投影和所述滤色部在所述衬底基板上的正投影均存在交叠区域。
  14. 如权利要求1-13任一项所述的阵列基板，其中，所述周边区域远离所述开口区域一侧的边界与所述开口区域的边界之间距离的取值范围为6μm～10μm。
  15. 如权利要求1-13任一项所述的阵列基板，其中，还包括：位于所述衬底基板与所述像素界定层之间的第二电极层，所述第二电极层在所述衬底基板上的正投影覆盖所述开口区域在所述衬底基板上的正投影；
    位于所述第一电极层与所述第二电极层之间的发光层，所述发光层在所述衬底基板上的正投影覆盖所述开口区域在所述衬底基板上的正投影。
  16. 一种如权利要求1-15任一项所述的阵列基板的制作方法，其中，包括：
    提供一衬底基板；
    在所述衬底基板上形成像素界定层，并对所述像素界定层进行构图，以使所述像素界定层形成多个开口区域、围绕每个所述开口区域的周边区域，以及除所述开口区域和所述周边区域之外的其他区域；
    在所述像素界定层上形成第一电极层，且所述周边区域内的所述第一电极层远离所述衬底基板的表面粗糙度大于其他区域内的所述第一电极层远离所述衬底基板的表面粗糙度；
    在形成有所述第一电极层的衬底基板上形成滤色部。
  17. 如权利要求16所述的阵列基板的制作方法，其中，所述对所述像素界定层进行构图具体包括：
    在所述像素界定层上形成光刻胶；
    利用预设掩膜版对所述像素界定层进行曝光显影，形成所述开口区域以及所述像素界定层在周边区域内的图形，其中，所述预设掩膜版包括所述开口区域以及与所述凹陷部对应的图形。
  18. 如权利要求16所述的阵列基板的制作方法，其中，在所述像素界定 层上形成第一电极层之后，以及在形成有所述第一电极层的衬底基板上形成滤色部之前，所述制作方法还包括：
    在形成有所述第一电极层的衬底基板上形成黑矩阵。
  19. 一种显示面板，其中，包括如权利要求1-15任一项所述的阵列基板。
  20. 一种显示装置，其中，包括如权利要求19所述的显示面板。
PCT/CN2021/077437 2020-02-27 2021-02-23 阵列基板、其制作方法、显示面板及显示装置 WO2021169944A1 (zh)

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