WO2023230911A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023230911A1
WO2023230911A1 PCT/CN2022/096459 CN2022096459W WO2023230911A1 WO 2023230911 A1 WO2023230911 A1 WO 2023230911A1 CN 2022096459 W CN2022096459 W CN 2022096459W WO 2023230911 A1 WO2023230911 A1 WO 2023230911A1
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WIPO (PCT)
Prior art keywords
light
sub
pixel
substrate
display panel
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Application number
PCT/CN2022/096459
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English (en)
French (fr)
Inventor
郭丹
刘珂
方飞
徐晶晶
石领
齐璞玉
刘畅畅
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/096459 priority Critical patent/WO2023230911A1/zh
Priority to CN202280001584.7A priority patent/CN117501847A/zh
Publication of WO2023230911A1 publication Critical patent/WO2023230911A1/zh

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  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • OLEDs organic light emitting diodes
  • a display panel has a functional device setting area, and includes a substrate, a plurality of first sub-pixels and a plurality of first light shielding parts.
  • the plurality of first sub-pixels are disposed on the substrate and located in the functional device setting area.
  • At least one first sub-pixel includes a first pixel circuit and a first light-emitting device, the first light-emitting device includes a first electrode, the first electrode is electrically connected to the first pixel circuit; the first pixel circuit is The portion of the orthographic projection on the substrate is located outside the orthographic projection range of the first electrode on the substrate.
  • the plurality of first light-shielding portions are spaced apart on a side of the plurality of first light-emitting devices away from the substrate and located in the functional device setting area.
  • Each first light-shielding part is provided with a plurality of first opening areas, each first opening area corresponds to a first light-emitting device, and the light-emitting area of the first light-emitting device is located in the corresponding first opening area.
  • the orthographic projection of the first part of the first pixel circuit on the substrate is located within the orthographic projection range of the first light shielding part on the substrate; the first part is the first pixel circuit
  • the orthographic projection on the substrate is located at a portion outside the orthographic projection range of the first electrode on the substrate.
  • the display panel includes a plurality of first pixel units disposed in the functional device setting area, and each first pixel unit includes a plurality of the first sub-pixels; wherein each of the first pixel units includes a plurality of first sub-pixels.
  • the plurality of first opening areas of a light shielding part correspond to the plurality of first sub-pixels of the same first pixel unit in a one-to-one correspondence.
  • the distance between the centers of two adjacent first sub-pixels in the set direction is the first distance.
  • the distance between the centers of two adjacent first sub-pixels located within the outer boundaries of two adjacent first light-shielding portions is the second distance.
  • the first distance is smaller than the second distance.
  • the plurality of first sub-pixels includes a plurality of red sub-pixels, a plurality of first green sub-pixels, a plurality of second green sub-pixels and a plurality of blue sub-pixels.
  • the plurality of red sub-pixels and the plurality of first green sub-pixels are alternately arranged along a first oblique direction, and the plurality of second green sub-pixels are alternately arranged along a second oblique direction; the blue sub-pixels and The second green sub-pixels are alternately arranged along the first oblique direction, and the plurality of first green sub-pixels are alternately arranged along the second oblique direction; and the first green sub-pixels and the second The green sub-pixels are alternately arranged along the first direction, and the red sub-pixels and the blue sub-pixels are alternately arranged along the second direction.
  • the first direction is substantially perpendicular to the second direction, the first oblique direction and the second oblique direction intersect, and both the first oblique direction and the second oblique direction are aligned with the The first direction intersects, and both the first oblique direction and the second oblique direction intersect the second direction.
  • the set direction is at least one of the first direction, the second direction, the first oblique direction and the second oblique direction.
  • the display panel includes a plurality of first pixel units, each first pixel unit including an adjacent red sub-pixel, a first green sub-pixel, a second green sub-pixel and a blue sub-pixel.
  • each first pixel unit including an adjacent red sub-pixel, a first green sub-pixel, a second green sub-pixel and a blue sub-pixel.
  • the red sub-pixel and the blue sub-pixel are arranged along the second direction
  • the first green sub-pixel and the second green sub-pixel are arranged along the first direction. arrangement.
  • the outer boundary of the first light-shielding portion in the orthographic projection of the substrate is generally rhombus-shaped.
  • the plurality of first light-shielding parts are arranged in multiple rows and columns, each row includes a plurality of first light-shielding parts arranged along a first direction, and each column includes a plurality of first light-shielding parts arranged along a second direction. Light-shielding portion; the first direction is substantially perpendicular to the second direction.
  • the display panel further includes a second electrode layer disposed between the first electrode and the first light shielding portion.
  • the portion of the second electrode layer located in the functional device setting area is provided with a plurality of second opening areas, and the orthographic projection of the plurality of second opening areas on the substrate is located at the plurality of first light shielding areas. area between orthographic projections on the substrate.
  • the plurality of first light-shielding parts are arranged in multiple rows and columns, each row includes a plurality of first light-shielding parts arranged along a first direction, and each column includes a plurality of first light-shielding parts arranged along a second direction.
  • Light-shielding portion; the first direction is substantially perpendicular to the second direction.
  • the second opening area is provided between two first light shielding parts adjacent in the first direction; and/or the second opening area is provided between two adjacent first light shielding parts in the second direction. between a shading part.
  • a plurality of first light-shielding portions in two adjacent rows are staggered to each other, and a plurality of first light-shielding portions in two adjacent columns are staggered to each other.
  • the second opening area is generally circular or elliptical in shape.
  • the display panel further has a main display area that at least partially surrounds the functional device setting area.
  • the display panel also includes a plurality of second sub-pixels and a second light shielding portion.
  • the plurality of second sub-pixels are disposed on the substrate and located in the main display area.
  • Each second sub-pixel includes a second pixel circuit and a second light-emitting device, at least one second light-emitting device includes a third electrode, the third electrode is electrically connected to the second pixel circuit; the second pixel circuit is The portion of the orthographic projection on the substrate is located outside the orthographic projection range of the third electrode on the substrate.
  • the second light-shielding portion is disposed on a side of the plurality of second sub-pixels away from the substrate and located in the main display area.
  • the second light-shielding part includes a plurality of third opening areas, each third opening area corresponds to a second light-emitting device, and the light-emitting area of the second light-emitting device is located in the corresponding third opening area.
  • the orthographic projection of the second part of the plurality of second pixel circuits on the substrate is located within the orthographic projection range of the second light shielding part on the substrate; the second part is the The orthographic projection of the second pixel circuit on the substrate is located outside the orthographic projection range of the third electrode on the substrate.
  • the orthographic projection of the second light-shielding portion on the substrate covers a first area, and the first area is an area between the plurality of second light-emitting devices in the main display area.
  • the portion of the second electrode layer located in the main display area has a continuous film layer structure.
  • the first light-shielding part and the second light-shielding part are made of the same material and are arranged in the same layer.
  • the first sub-pixel further includes a plurality of first filter parts, each first filter part corresponds to a first opening area, and the first filter part is on the substrate.
  • the boundary of the orthographic projection is located within the range of the orthographic projection of the corresponding first light-shielding portion on the substrate.
  • the second sub-pixel further includes a plurality of second filter portions, and each second filter portion corresponds to a third opening. area, and the boundary of the orthographic projection of the second light filter portion on the substrate is located within the range of the orthographic projection of the second light shielding portion on the substrate.
  • the display panel further includes an encapsulation layer disposed between the plurality of first light-shielding portions and the first light-emitting device.
  • the display panel further includes a plurality of signal lines electrically connected to the first pixel circuit.
  • At least one signal line includes a signal line for connecting an external signal source and a transfer line connected to the first pixel circuit, and a portion of the signal line located in the functional device setting area is transparent.
  • the plurality of signal lines include scan signal lines, reset signal lines, enable signal lines and initialization signal lines.
  • the scan signal line includes a first scan line and a first transfer line.
  • the first transfer line extends generally along the first direction and is electrically connected to the first pixel circuit.
  • One end of the first scanning line extends into the functional device setting area and is electrically connected to the first transfer line; the portion of the first scanning line located in the functional device setting area is transparent.
  • the reset signal line includes a first reset line and a second transfer line.
  • the second transfer line extends generally along the first direction and is electrically connected to the first pixel circuit.
  • One end of the first reset wiring extends into the functional device setting area and is electrically connected to the second transfer line; the portion of the first reset wiring located in the functional device setting area is transparent.
  • the enable signal line includes a first enable line and a third transfer line.
  • the third transfer line extends generally along the first direction and is electrically connected to the first pixel circuit.
  • One end of the first enabling trace extends into the functional device setting area and is electrically connected to the third transfer line; the portion of the first enabling trace located in the functional device setting area is transparent.
  • the initialization signal line includes the first initialization line and the fourth transfer line.
  • the fourth transfer line extends generally along the first direction and is electrically connected to the first pixel circuit.
  • One end of the first initialization trace extends into the functional device setting area and is electrically connected to the fourth transfer line; the portion of the first initialization trace located in the functional device setting area is transparent.
  • the display panel sequentially includes a semiconductor layer, a first gate conductive layer, a second gate conductive layer, a first source-drain conductive layer and Transparent conductive layer.
  • the first transfer line, the second transfer line and the third transfer line are located on the first gate conductive layer, and the fourth transfer line is located on the second gate conductive layer; and/or, the Parts of the first scan line, the first reset line, the first enable line and the first initialization line located in the functional device setting area are located on the transparent conductive layer.
  • the plurality of signal lines further include a first voltage signal line and a data line, the first voltage signal line and the data line extend generally along the second direction, and the first voltage signal line and the data line are both electrically connected to the first pixel circuit. At least part of the first voltage signal line and the data line located in the functional device setting area is transparent.
  • the first voltage signal line includes a first voltage trace and a fifth transfer line.
  • the fifth transfer line is disposed on a side of the first pixel circuit away from the substrate and is connected to the first voltage signal line.
  • the first voltage trace is electrically connected.
  • the display substrate sequentially includes a semiconductor layer, a first gate conductive layer, a second gate conductive layer, a first source and drain conductive layer, a transparent conductive layer and a second source-drain conductive layer.
  • the portions of the first voltage trace and the data line located in the functional device setting area are located on the transparent conductive layer, and the fifth transfer line is located on the second source-drain conductive layer.
  • the display device includes a casing and a display panel as described in any of the above embodiments, and the display panel is disposed in the casing.
  • Figure 1 is a structural diagram of a display device according to some embodiments.
  • Figure 2 is an exploded view of a display device according to some embodiments.
  • Figure 3A is a cross-sectional view of a functional device setting area of a display panel according to some embodiments
  • Figure 3B is a cross-sectional view of the main display area of the display panel according to some embodiments.
  • Figure 4 is a circuit schematic diagram of a pixel driving circuit according to some embodiments.
  • Figure 5 is a timing diagram of a pixel driving circuit according to some embodiments.
  • Figure 6A is a top view of the pixel circuit arrangement in the functional device setting area of the display panel according to some embodiments.
  • 6B is a top view of the arrangement of light-emitting devices in the functional device setting area of the display panel according to some embodiments;
  • 6C is a top view of a display panel with a first light shielding portion in the functional device setting area according to some embodiments;
  • 6D is a top view of another display panel with a first light shielding portion in the functional device setting area according to some embodiments;
  • Figure 6E is a top view of the functional device setting area of the display panel according to some embodiments.
  • Figure 7 is a structural diagram of the first light shielding part of the display panel according to some embodiments.
  • Figure 8 is an enlarged view of a pixel unit in the functional device setting area of the display panel according to some embodiments.
  • Figure 9A is a top view of the pixel circuit arrangement of the main display area of the display panel according to some embodiments.
  • Figure 9B is a top view of the arrangement of light emitting devices in the main display area of the display panel according to some embodiments.
  • Figure 9C is a top view of a display panel with a second light shielding portion in the functional device setting area according to some embodiments.
  • 9D is a top view of another display panel with a second light shielding portion in the functional device setting area according to some embodiments.
  • FIG. 10A is a structural diagram of the second light shielding part of the display panel according to some embodiments.
  • Figure 10B is an enlarged view of a red sub-pixel in the main display area of the display panel according to some embodiments.
  • Figure 11 is a top view of the semiconductor layer in the functional device setting area of the display panel according to some embodiments.
  • Figure 12 is a top view of a first gate conductive layer added to the semiconductor layer in the functional device setting area shown in Figure 11;
  • Figure 13 is a top view of a second gate conductive layer added to the first gate conductive layer in the functional device setting area shown in Figure 12;
  • Figure 14 is a top view of the second gate conductive layer in the functional device setting area shown in Figure 13 after adding a first source-drain conductive layer;
  • Figure 15 is a top view of a transparent conductive layer added to the first source-drain conductive layer in the functional device setting area shown in Figure 14;
  • Figure 16 is a top view of the transparent conductive layer in the functional device setting area shown in Figure 15 after adding a second source-drain conductive layer;
  • Figure 17 is a top view of the second source-drain conductive layer in the functional device setting area shown in Figure 16 after adding a first electrode;
  • FIG. 18 is a top view of the semiconductor layer of the main display area of the display panel according to some embodiments.
  • Figure 19 is a top view of a first gate conductive layer added to the semiconductor layer of the main display area shown in Figure 18;
  • Figure 20 is a top view of a second gate conductive layer added to the first gate conductive layer of the main display area shown in Figure 19;
  • Figure 21 is a top view of the main display area shown in Figure 20 after adding a first source-drain conductive layer to the second gate conductive layer;
  • Figure 22 is a top view of a transparent conductive layer added to the first source and drain conductive layer of the main display area shown in Figure 21;
  • Figure 23 is a top view of the transparent conductive layer in the main display area shown in Figure 22 after adding a second source-drain conductive layer;
  • FIG. 24 is a top view of the second source-drain conductive layer of the main display area shown in FIG. 23 after adding a first electrode.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the transistors used in the pixel driving circuit (pixel circuit) provided by the embodiments of the present disclosure may be thin film transistors (thin film transistor, TFT for short), field effect transistors (metal oxide semiconductor, MOS for short) or other devices with the same characteristics. Switching devices, in the embodiments of the present disclosure, thin film transistors are used as examples for description.
  • the thin film transistor is a P-type transistor as an example for description. It should be noted that embodiments of the present disclosure include but are not limited to this.
  • one or more thin film transistors in the pixel driving circuit provided by embodiments of the present disclosure may also be N-type transistors. It is only necessary to refer to each pole of the selected type of thin film transistor to the corresponding thin film transistor in the embodiment of the present disclosure. Each pole is coupled accordingly, and the corresponding voltage terminal provides the corresponding high-level voltage or low-level voltage.
  • the control electrode of each thin film transistor used in the pixel driving circuit is the gate electrode of the transistor
  • the first electrode is one of the source electrode and the drain electrode of the thin film transistor
  • the second electrode is the source electrode and drain electrode of the thin film transistor.
  • the source and drain of the thin film transistor may be symmetrical in structure, the source and drain of the thin film transistor may be structurally indistinguishable. That is to say, the first electrode of the thin film transistor in the embodiment of the present disclosure There may be no difference in structure from the second pole.
  • the first electrode of the thin film transistor is a source electrode
  • the second electrode is a drain electrode
  • the first electrode of the transistor is a drain electrode
  • the drain, the second pole is the source.
  • the capacitor can be a capacitive device manufactured separately through a process.
  • the capacitive device can be realized by making special capacitive electrodes.
  • Each capacitive electrode of the capacitor can pass through a metal layer. , semiconductor layer (such as doped polysilicon) and so on.
  • the capacitor can also be the parasitic capacitance between transistors, or it can be realized by the transistor itself and other devices and circuits, or it can be realized by using the parasitic capacitance between the circuit's own circuits.
  • a display device 1000 which may be any device that displays images, whether moving (eg, video) or stationary (eg, still images), and whether text or text.
  • the display device 1000 can be a television, a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (English: personal digital assistant; referred to as: PDA), a navigator, a wearable device, a virtual reality (English: virtual reality) ; Abbreviation: VR) equipment and any other products or components with display functions.
  • PDA personal digital assistant
  • VR virtual reality
  • the display device 1000 is an electroluminescent display device or a photoluminescent display device.
  • the electroluminescent display device may be an organic electroluminescent display device (organic light-emitting diode, OLED for short) or a quantum dot electroluminescent display device (quantum dot light emitting diodes, QLED for short).
  • the photoluminescence display device may be a quantum dot photoluminescence display device.
  • the display device 1000 includes a housing 100 , a display panel 200 disposed in the housing 100 , a functional device 300 , a circuit board 400 and other electronic accessories.
  • the circuit board 400 can be bound to the display panel 200 at an end of the display panel 200 and bent to the back side of the display panel 200 to achieve a full-screen design.
  • the functional device 300 can be integrated under the display panel 200 to achieve a full-screen design.
  • the functional device 300 can be a camera, an infrared sensor, a proximity sensor, an eye tracking module, a face recognition module, etc.
  • the functional device 300 is a camera.
  • the display panel 200 includes a display substrate 10 and an encapsulation layer 20 for encapsulating the display substrate 10 .
  • the display substrate 10 has a light-emitting side and a non-light-emitting side that are oppositely arranged, and the encapsulation layer 20 is provided on the light-emitting side of the display substrate 10.
  • the packaging layer 20 may be a packaging film or a packaging substrate.
  • the display panel 200 has a display area A, and a peripheral area B disposed on at least one side of the display area A.
  • the peripheral area B is arranged around the display area A as an example.
  • the display area A is an area for displaying images and is configured to provide a plurality of pixel units P.
  • the peripheral area B is an area where no image is displayed, and the peripheral area B is configured to provide a display driving circuit, for example, a gate driving circuit and a source driving circuit.
  • the display area A also has a functional device setting area A1 and a main display area A2 that at least partially surrounds the functional device setting area A1.
  • the functional device 300 is located in the functional device setting area A1.
  • the main display area A2 surrounding the functional device setting area A1 is taken as an example for illustration.
  • the display area A of the display panel 200 is provided with a plurality of pixel units P, and each pixel unit P may include sub-pixels P' of multiple luminous colors.
  • the sub-pixels P' of multiple emission colors include red sub-pixels, green sub-pixels and blue sub-pixels.
  • each sub-pixel P' includes a substrate 11, a light-emitting device 12 and a pixel driving circuit 13 disposed on the substrate 11.
  • the pixel driving circuit 13 includes a plurality of transistors 130, and the transistor 130 includes a channel. Region S, source electrode 131, drain electrode 132 and gate electrode 133, source electrode 131 and drain electrode 132 are respectively in contact with the channel region S.
  • the light-emitting device 12 includes a first electrode 121 , a light-emitting functional layer 122 and a second electrode 123 .
  • the orthographic projection portion of the pixel driving circuit 13 on the substrate 11 is located outside the orthographic projection range of the first electrode 121 on the substrate 11 , that is, the portion of the pixel driving circuit 13 The edge is not blocked by the first electrode 121 .
  • the pixel circuit 13 mentioned below refers to the above-mentioned pixel driving circuit 13 .
  • the first electrode 121 is the anode of the light-emitting device 12
  • the second electrode 123 is the cathode of the light-emitting device 12
  • the first electrode 121 is the cathode of the light-emitting device 12
  • the second electrode 123 is the anode of the light-emitting device 12 .
  • the first electrode 121 is the anode of the light-emitting device 12
  • the second electrode 123 is the cathode of the light-emitting device 12
  • the first electrode 121 is electrically connected to the source electrode 131 or the drain electrode 132 of one transistor 130 of the pixel circuit 13 .
  • the first electrode 121 is electrically connected to the source 131 of a transistor 130 of the pixel circuit 13 as an example.
  • the light-emitting functional layer 122 only includes a light-emitting layer. In other embodiments, in addition to the light-emitting layer, the light-emitting functional layer 122 also includes an electron transporting layer (ETL), an electron injection layer (EIL), a hole transport layer ( At least one of a hole transporting layer (HTL for short) and a hole injection layer (HIL for short).
  • ETL electron transporting layer
  • EIL electron injection layer
  • HTL hole transporting layer
  • HIL hole injection layer
  • the above-mentioned pixel circuit 13 includes a variety of structures, and can be selected and arranged according to actual needs.
  • the structure of the pixel circuit 13 may include a "2T1C”, “3T1C”, “6T1C”, “7T1C”, “6T2C” or “7T2C” structure.
  • T represents the transistor
  • the number in front of “T” represents the number of transistors
  • C represents the storage capacitor
  • the number in front of "C” represents the number of storage capacitors.
  • the stability of the transistors in the pixel circuit 13 and the light-emitting device 12 may decrease (for example, the threshold voltage of the driving transistor drifts), affecting the display effect of the display panel 200, which requires pixel modification. Circuit 13 compensates.
  • a pixel compensation circuit may be provided in the pixel circuit 13 so as to use the pixel compensation circuit to perform internal compensation on the pixel circuit 13 .
  • the driving transistor or light-emitting device can be sensed through the transistor inside the pixel circuit 13, and the sensed data can be transmitted to an external sensing circuit, so that the external sensing circuit can be used to calculate the driving voltage value that needs to be compensated and provide feedback. , thereby achieving external compensation for the pixel circuit 13.
  • This disclosure uses an internal compensation method and the pixel circuit 13 adopts a "7T1C" structure as an example to schematically illustrate the structure and working process of the pixel circuit 13 .
  • the pixel circuit 13 may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a driving transistor Td and a storage transistor.
  • Capacitor C Capacitor
  • the control electrode of the first transistor T1 is electrically connected to the scanning signal terminal GATE.
  • the first electrode of the first transistor T1 is electrically connected to the second electrode of the driving transistor Td.
  • the second electrode of the first transistor T1 is electrically connected to the control electrode of the driving transistor Td. connect.
  • the control electrode of the second transistor T2 is electrically connected to the scanning signal terminal GATE, the first electrode of the second transistor T2 is electrically connected to the data signal terminal DATA, and the second electrode of the second transistor T2 is electrically connected to the first electrode of the driving transistor Td.
  • the control electrode of the third transistor T3 is electrically connected to the reset signal terminal RESET, the first electrode of the third transistor T3 is electrically connected to the initialization signal terminal VINIT, and the second electrode of the third transistor T3 is electrically connected to the control electrode of the driving transistor Td.
  • the control electrode of the fourth transistor T4 is electrically connected to the enable signal terminal EM, the first electrode of the fourth transistor T4 is electrically connected to the first voltage signal terminal VDD, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the driving transistor Td. Electrical connection.
  • the control electrode of the fifth transistor T5 is electrically connected to the enable signal terminal EM, the first electrode of the fifth transistor T5 is electrically connected to the second electrode of the driving transistor Td, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the light-emitting device 12 . Electrodes 121 (see Figure 3A) are electrically connected.
  • the control electrode of the sixth transistor T6 is electrically connected to the scanning signal terminal GATE, the first electrode of the sixth transistor T6 is electrically connected to the initialization signal terminal VINIT, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode 121 of the light-emitting device 12 (see Figure 3A) Electrical connections.
  • the first plate C1 (see FIG. 3A) of the storage capacitor C is electrically connected to the control electrode of the driving transistor Td, and the second plate C2 (see FIG. 3A) of the storage capacitor C is electrically connected to the first voltage signal terminal VDD.
  • the working process of the sub-pixel may include, for example, a reset stage S1, a data writing stage S2, and a light-emitting stage S3.
  • the sixth transistor T6 is turned on under the control of the scan signal Gate from the scan signal terminal GATE, the voltage of the first electrode of the light-emitting device 12 is reset to the initialization voltage signal Vinit, and the third transistor T3 is in It is turned on under the control of the reset signal Reset from the reset signal terminal RESET, and the voltage of the control electrode of the driving transistor Td and the first plate C1 of the storage capacitor C is reset to the initialization voltage signal Vinit.
  • the first transistor T1 and the second transistor T2 are turned on under the control of the scanning signal Gate from the scanning signal terminal GATE, and the driving transistor Td is turned on under the control of the initialization voltage signal stored in the storage capacitor C,
  • the storage capacitor C is written with the data signal Data from the data signal terminal DATA.
  • the fourth transistor T4 and the fifth transistor T5 are turned on under the control of the enable signal Em of the enable signal terminal EM to output a driving current signal to the light-emitting device 12 to drive the light-emitting device 12 to emit light.
  • the display substrate 10 further includes a pixel defining layer 14 , and the pixel defining layer 14 is disposed on a side of the first electrode 121 away from the substrate 11 .
  • the pixel defining layer 14 includes a plurality of opening areas, and one light-emitting device 12 is disposed in one opening area, that is, the light-emitting functional layer 122 of the light-emitting device 12 is in electrical contact with the first electrode 121 in the opening area.
  • the area of the first electrode 121 is larger than the area of the opening area of the pixel defining layer 14 to ensure that the entire opening area of the pixel defining layer 14 is the light-emitting area of the light-emitting device 12 .
  • the overlapping portion of the first electrode 121 , the second electrode 123 and the light-emitting functional layer 122 constitutes the light-emitting area of the light-emitting device 12 , that is, the first electrode 121 , the second electrode 123 and the light-emitting functional layer 122 are correspondingly located in the pixel defining layer 14
  • the portion of the area where the opening area is located constitutes the light-emitting area of the light-emitting device 12 .
  • the functional device 300 when the functional device 300 is integrated below the display panel 200, if the light transmittance of the display panel 200 is low, it will affect the light sensitivity of the functional device 300 below the display panel 200; if the light transmittance of the display panel 200 If the reflectivity is high, the display effect of the display panel 200 will be affected.
  • a polarizer is provided on the light exit side of the display panel to reduce the reflection intensity of external ambient light on the display panel; however, the light emitted by the display panel will lose 50% to 60% after passing through the polarizer. %, that is, the polarizer will greatly reduce the transmittance of the display device, increase the power consumption of the display device, and affect the light sensitivity of the camera below the display panel. Moreover, since part of the edge of the pixel circuit is not blocked by the first electrode, serious diffraction will occur after external ambient light is reflected by the edge of the part, resulting in a decrease in the sensitivity of the functional device.
  • a color filter layer is provided on the light exit side of the display panel instead of the polarizer.
  • the reflection intensity of external ambient light on the display panel is still greater; especially in the camera area, in order to ensure the light sensitivity of functional devices, the camera area cannot use a full light-shielding layer Covering the area between sub-pixels, the reflection intensity of the functional device setting area is too large, affecting the display effect; and, because part of the edge of the pixel circuit is not blocked by the first electrode, external ambient light will be reflected by this part of the edge. Severe diffraction phenomena lead to a decrease in the sensitivity of functional devices.
  • the display panel 200 further includes a plurality of first light shielding parts 15.
  • the pixel unit P, sub-pixel P, light-emitting device 12 and pixel circuit 13 in the functional device setting area A1 and the main display area A2, in this article, the pixel unit P, The sub-pixel P', the light-emitting device 12 and the pixel circuit 13 are respectively called the first pixel unit P1, the first sub-pixel P1', the first light-emitting device 124 and the first pixel circuit 135, and the pixel unit located in the main display area A2 P, the sub-pixel P', the light-emitting device 12 and the pixel circuit 13 are respectively called the second pixel unit P2, the second sub-pixel P2', the second light-emitting device 125 and the second pixel circuit 136.
  • Figures 6A to 6D are top views of the functional device setting area of the display panel according to some embodiments;
  • Figure 7 is a structural diagram of the first light shielding portion of the display panel according to some embodiments;
  • Figure 8 is a display panel according to some embodiments An enlarged view of a pixel unit in the functional device setting area.
  • each first light-shielding part 15 is provided with a plurality of first opening areas 151, and each first opening area 151 corresponds to a first light-emitting device 124, and the first light-emitting device 124 The light-emitting areas are located in the corresponding first opening areas 151 .
  • the orthographic projection of the first part of the first pixel circuit 135 on the substrate 11 is located within the orthographic projection range of the first light shielding portion 135 on the substrate 11 .
  • the first part is the part where the orthographic projection of the first pixel circuit 135 on the substrate 11 is outside the orthographic projection range of the first electrode 121 on the substrate 11 .
  • the orthographic projection of the first part of the first pixel circuit 135 on the substrate 11 is located within the orthographic projection range of the first light shielding portion 135 on the substrate 11. That is to say, the orthographic projection of the first pixel circuit 135 on the substrate 11 is located within the orthographic projection range of the first electrode 121 and the first light-shielding portion 135 on the substrate 11. This can prevent external ambient light from directly irradiating the first pixel.
  • the reflection intensity of the external ambient light in the functional device setting area A1 of the display panel 200 is reduced, and the diffraction phenomenon caused by the external ambient light directly shining on the edge of the first pixel circuit 135 is solved, and the sensitivity of the functional device 300 is improved.
  • the channel region S of the transistor 130 (for example, the first transistor T1) of the first pixel circuit 135 can be blocked by the first electrode 121 and the first light shielding portion 135, thereby reducing the risk of the threshold voltage of the transistor 130 drifting. , improve the accuracy of the driving current, and improve the display effect of the functional device setting area A1 of the display panel 200 .
  • each first light-shielding part 15 corresponds to a first pixel unit P1, that is, the plurality of first opening areas 151 of each first light-shielding part 15 and Multiple first sub-pixels P1' of the same first pixel unit P1 correspond one to one.
  • the first light shielding part 15 has the same shielding area for each first pixel unit P1, which can avoid the problem of uneven brightness or color shift caused by inconsistent light transmission areas of multiple first pixel units P1, thereby improving the display The display effect of the functional device setting area A1 of the panel 200.
  • the distance between the centers of two adjacent first sub-pixels P1' in the set direction is the first distance L1.
  • the distance between the centers of two adjacent first sub-pixels P1' located within the outer boundaries of two adjacent first light shielding portions 15 is the second distance L2.
  • the first distance L1 is smaller than the second distance L2.
  • the setting direction is the first direction X as an example for illustration.
  • the first pixel circuit 135 in the functional device setting area A1 is compactly designed.
  • the arrangement of the first pixel circuit 135 is similar to the arrangement of the first light-emitting devices 124 .
  • the geometric centers of the first pixel circuit 135 and the first light-emitting device 124 substantially coincide.
  • the center of the first sub-pixel P1' may refer to the center of the light-emitting area of the first light-emitting device 124 of the first sub-pixel P1'.
  • the above set direction may be the arrangement direction of any two adjacent first sub-pixels P1'.
  • the area of the first light-shielding part 15 can be reduced accordingly to improve the performance of the display panel 200.
  • the transmittance of the functional device setting area A1; in addition, the distance between adjacent first light-shielding portions 15 is relatively large, which can reduce the process difficulty of manufacturing the first light-shielding portions 15.
  • the plurality of first sub-pixels P1' includes a plurality of red sub-pixels R, a plurality of first green sub-pixels G1, a plurality of second green sub-pixels G2 and Multiple blue sub-pixels B.
  • a plurality of red sub-pixels R and a plurality of first green sub-pixels G1 are alternately arranged along the first oblique direction Z1, and are alternately arranged along the second oblique direction Z2 with a plurality of second green sub-pixels G2; the blue sub-pixel B and the first
  • the two green sub-pixels G2 are alternately arranged along the first oblique direction Z1, and are alternately arranged along the second oblique direction Z2 with the plurality of first green sub-pixels G1; and the first green sub-pixel G1 and the second green sub-pixel G2 are arranged alternately along the first oblique direction Z1.
  • the red sub-pixels R and the blue sub-pixels B are alternately arranged along the second direction Y.
  • first direction X and the second direction Y are substantially perpendicular, the first oblique direction Z1 and the second oblique direction Z2 intersect, and both the first oblique direction Z1 and the second oblique direction Z2 intersect the first direction X, and Both the first oblique direction Z1 and the second oblique direction Z2 intersect the second direction Y.
  • the angle between the first oblique direction Z1 and the first direction X may be approximately 40°-50°, and the angle between the first oblique direction Z1 and the second direction Y may be approximately 40°-50°;
  • the included angle between the second oblique direction Z2 and the first direction X may be approximately 130°-140°, and the included angle between the second oblique direction Z1 and the second direction Y may be approximately 40°-50°.
  • the set direction may be at least one of the first direction X, the second direction Y, the first oblique direction Z1 and the second oblique direction Z2.
  • the set direction includes the first direction X, the second direction Y, the first oblique direction Z1 and the second oblique direction Z2. That is to say, when each first light shielding part 15 corresponds to a first pixel unit P1, the distances between the plurality of first sub-pixels P1' located in the same first pixel unit P1 are shortened to each other.
  • each first pixel unit P1 may include an adjacent red sub-pixel R, a first green sub-pixel G1, a second green sub-pixel G2 and a blue sub-pixel.
  • Pixel B the four first sub-pixels P1' constitute a minimum repeating unit.
  • the red sub-pixels R and the blue sub-pixels B are arranged along the second direction Y
  • the first green sub-pixel G1 and the second green sub-pixel G2 are arranged along the first direction X.
  • the shape of the outer boundary of the first light shielding part 15 may be substantially rhombus, and the two diagonal lines of the rhombus are substantially parallel to the first direction X and the second direction Y respectively.
  • rhombus-shaped means that the shape is rhombus-shaped as a whole, but is not limited to a standard rhombus shape. That is, the "rhombus” here includes not only a basic rhombus shape but also a rhombus-like shape in consideration of process conditions. For example, the corners of a diamond are curved, that is, the corners are smooth.
  • the first pixel units P1 are arranged in multiple rows and columns, each row includes a plurality of first pixel units P1 arranged along the first direction X, and each column includes a plurality of first pixel units P1 arranged along the second direction Y. A plurality of first pixel units P1.
  • a plurality of first light shielding parts 15 are arranged in multiple rows and columns. Each row includes a plurality of first light shielding parts 15 arranged along the first direction X, and each column includes a plurality of first light shielding parts 15 arranged along the second direction Y. a plurality of first light shielding parts 15.
  • a plurality of first pixel units P1 in two adjacent rows can be staggered to each other, and a plurality of first pixel units P1 in two adjacent columns can be staggered to each other, so that the first pixel unit P1
  • the arrangement is more compact and the display effect is improved.
  • the plurality of first light-shielding portions 15 in two adjacent rows can be staggered to each other, and the plurality of first light-shielding portions 15 in two adjacent columns can be staggered to each other.
  • the display panel 200 further includes a second electrode layer 1230.
  • the second electrode layer 123 includes the second electrode 123 of the light emitting device 12.
  • the second electrode layer 1230 is configured between the first electrode 121 and the first light shielding part 15 .
  • the portion of the second electrode layer 1230 located in the functional device setting area A1 is provided with a plurality of second opening areas 1231.
  • the orthographic projection of the plurality of second opening areas 1231 on the substrate 11 is located at the plurality of first light shielding portions 15.
  • the area between the orthographic projections on the substrate 11 can reduce the area of the area where the second electrode layer 1230 is located between the plurality of first light shielding portions 15, and reduce the amount of light reflected by the second electrode layer 1230.
  • the external ambient light further reduces the reflection intensity of the external ambient light in the functional device setting area A1 of the display panel 200 .
  • the second opening area 1231 can be disposed between any two adjacent first light shielding portions 15 .
  • the plurality of first light shielding parts 15 are arranged in multiple rows and columns, each row includes a plurality of first light shielding parts 15 arranged along the first direction X, and each column includes a plurality of first light shielding parts 15 arranged along the second direction Y.
  • the second opening area 1231 can be disposed between two adjacent first light shielding parts 15 in the first direction X, and the second opening area 1231 can also be disposed in the second direction Y. between two adjacent first light shielding parts 15 .
  • the plurality of first light-shielding portions 15 in two adjacent rows are staggered to each other, and the plurality of first light-shielding portions 15 in two adjacent columns are staggered to each other, and the first light-shielding portions 15 are staggered to each other.
  • the second opening area 1231 is located between two adjacent first light shielding portions 15 in the first direction X, and is located between two adjacent first light shielding portions 15 in the second direction Y between a light shielding part 15.
  • the area between the two first light-shielding portions 15 adjacent in the first direction X and the two first light-shielding portions 15 adjacent in the second direction Y is relatively large, and the patterned second electrode
  • the process difficulty of layer 1230 is relatively low, that is, it is easy to open the second opening region 1231 in the second electrode layer 1230 .
  • the shape of the second opening area 1231 is generally circular or elliptical. It should be understood that the circular or elliptical shape can make the area of the second opening area 1231 larger, that is, the area of the second electrode layer 1230 between the first light shielding portions 15 can be reduced, thereby reducing the amount of external ambient light.
  • the reflection intensity of the functional device setting area A1 of the panel 200 is displayed.
  • the shape is circular or elliptical as a whole, but is not limited to a standard circular or elliptical shape. That is, the "circular or elliptical shape” here includes not only the shape of a basic rhombus, but also a shape similar to a circular or elliptical shape considering the process conditions; for example, part of the boundary of the circle or elliptical shape is a straight line.
  • the first light-emitting device 124 of the first sub-pixel P1' may be configured to emit white light or may be configured to emit colored light.
  • the first light-emitting device 124 of the first sub-pixel P1' is configured to emit colored light, and the colored light is directly emitted to the outside of the display panel 200 .
  • the plurality of first sub-pixels P1' includes a red sub-pixel R, a first green sub-pixel G1, a second green sub-pixel G2 and a blue sub-pixel B.
  • the first light emitting element of the red sub-pixel R The device 124 is configured to emit red light
  • the first light-emitting device 124 of the first green sub-pixel G1 and the second green sub-pixel G2 is configured to emit green light
  • the first light-emitting device 124 of the blue sub-pixel B is configured to emit blue light for color display.
  • the first light-emitting device 124 of the first sub-pixel P1' is configured to emit white light.
  • the first sub-pixel P1' also includes a plurality of first filter parts 21.
  • each first filter part 21 corresponds to a first opening area 151
  • the first filter part 21 corresponds to a first opening area 151.
  • the boundary S1 of the orthographic projection of a filter part 21 on the substrate 11 is located within the range of the orthographic projection of the corresponding first light-shielding part 15 on the substrate 11 (see FIG.
  • the third A light-emitting device 124 filters light and prevents the first light-shielding portion 15 from interfering with the lighting of the functional device 300 (see FIG. 2 ).
  • the plurality of first filter parts 21 can respectively transmit multiple types of monochromatic light.
  • the white light emitted by the first light-emitting device 124 of the first sub-pixel P1' is illuminated on the corresponding first filter part 21 to emit corresponding light. color monochromatic light to achieve full-color display.
  • the plurality of first sub-pixels P1' include a red sub-pixel R, a first green sub-pixel G1, a second green sub-pixel G2 and a blue sub-pixel B.
  • the red sub-pixel R The first filter part 21 can transmit red light
  • the first filter part 21 of the first green sub-pixel G1 and the second green sub-pixel G2 can transmit green light
  • the first filter part 21 of the blue sub-pixel B can transmit Blu-ray.
  • the white light emitted by the first light-emitting device 124 of the red sub-pixel R, the first green sub-pixel G1, the second green sub-pixel G2 and the blue sub-pixel B irradiates the corresponding first filter part 21 to Emit monochromatic light of the corresponding color to achieve full-color display.
  • the first filter part 21 transmits monochromatic light, the first filter part 21 can filter out most of the wavelength bands in the external ambient light, thereby further reducing the effect of the external ambient light on the display panel 200 Reflection intensity of device setting area A1.
  • FIGS. 9A to 9D are top views of the main display area of the display panel according to some embodiments;
  • FIG. 10A is a structural diagram of the second light shielding portion of the display panel according to some embodiments;
  • FIG. 10B is a view of the display panel according to some embodiments. A zoomed-in view of a red subpixel in the main display area.
  • the display panel 200 further includes a second light-shielding portion 16 located in the main display area A2 .
  • the second light-shielding portion 16 is disposed on a side of the plurality of second sub-pixels P2 ′ away from the substrate 11 .
  • first light shielding part 15 and the second light shielding part 16 may be made of the same material and be arranged in the same layer.
  • the second light-shielding part 16 includes a plurality of third opening areas 161 , each third opening area 161 corresponds to a second light-emitting device 125 , and the light-emitting area of the second light-emitting device 125 is located in the corresponding in the third opening area 161.
  • the orthographic projection of the second part of the second pixel circuit 136 on the substrate 11 is located within the orthographic projection range of the second light shielding portion 16 on the substrate 11 .
  • the second part is the orthographic projection of the second pixel circuit 136 on the substrate 11 , and is located outside the orthographic projection range of the third electrode 121 on the substrate 11 .
  • the first electrode 121 of the second light-emitting device 125 is referred to as a third light-emitting device 124 in this article.
  • the electrode 121 that is, the second light-emitting device 125 includes a third electrode 121, and the third electrode 121 is electrically connected to the second pixel circuit 136.
  • the orthographic projection of the second part of the second pixel circuit 136 on the substrate 11 is located within the orthographic projection range of the second light shielding portion 136 on the substrate 11. That is to say, the orthographic projection of the second pixel circuit 136 on the substrate 11 is located within the orthographic projection range of the third electrode 121 and the second light shielding portion 136 on the substrate 11 .
  • This can prevent external ambient light from directly irradiating the second pixel.
  • the circuit 136 reduces the reflection intensity of the external ambient light in the main display area A2 of the display panel 200 and avoids the diffraction phenomenon caused by the external ambient light directly shining on the edge of the second pixel circuit 136 to improve the display effect.
  • the channel region S of the transistor 130 (for example, the first transistor T1) of the second pixel circuit 136 can be blocked by the third electrode 121 and the second light shielding portion 136, thereby reducing the risk of the threshold voltage of the transistor 130 drifting. , improve the accuracy of the driving current, and improve the display effect of the main display area A2 of the display panel 200 .
  • the main display area A2 of the display panel 200 is only used to display images and does not need to collect external ambient light. That is, in the main display area A2 of the display panel 200, there is no need to consider the light transmission of the area between the second sub-pixels P2'. The lower the reflection intensity of external ambient light, the better the display effect.
  • the orthographic projection of the second light-shielding portion 16 on the substrate 11 covers the first area, and the first area is the area between the plurality of second light-emitting devices 125 in the main display area A2.
  • the metal layer for example, the second electrode layer 1230
  • the reflection intensity of the main display area A2 improves the display effect of the main display area A2.
  • the part of the second electrode layer 1230 located in the main display area A2 may have a continuous film layer structure, that is, the part of the second electrode layer 1230 located in the main display area A2 may not undergo a patterning process, that is, the second electrode layer
  • the area 1230 located between the plurality of second sub-pixels P2' does not need to have light-transmitting holes, and the process is simple.
  • the orthographic projection of the second light-shielding portion 16 on the substrate 11 covers the first area, that is, the area between the second light-emitting devices 125 of the second sub-pixel P2', the plurality of second light-emitting devices 125 of the same second pixel unit P2
  • the distance between the centers of the second light-emitting devices 125 of the two sub-pixels P2' does not need to be reduced, that is, the plurality of second light-emitting devices 125 are uniformly arranged.
  • a plurality of red sub-pixels R and a plurality of first green sub-pixels G1 are alternately arranged along the first oblique direction Z1, and are arranged with a plurality of second green sub-pixels G2 are alternately arranged along the second oblique direction Z2;
  • the blue sub-pixels B and the second green sub-pixels G2 are alternately arranged along the first oblique direction Z1, and are alternately arranged along the second oblique direction Z2 with the plurality of first green sub-pixels G1;
  • the first green sub-pixels G1 and the second green sub-pixels G2 are alternately arranged along the first direction X, and the red sub-pixels R and blue sub-pixels B are alternately arranged along the second direction Y.
  • the set direction may be at least one of the first direction X, the second direction Y, the first oblique direction Z1 and the second oblique direction Z2.
  • the second light-emitting device 125 of the second sub-pixel P2' may be configured to emit white light or may be configured to emit colored light.
  • the second light-emitting device 125 of the second sub-pixel P2' is configured to emit colored light, and the colored light is directly emitted to the outside of the display panel 200 .
  • the plurality of second sub-pixels P2′ include a red sub-pixel R, a first green sub-pixel G1, a second green sub-pixel G2 and a blue sub-pixel B.
  • the second luminescence of the red sub-pixel R The device 125 is configured to emit red light
  • the second light-emitting device 125 of the first green sub-pixel G1 and the second green sub-pixel G2 is configured to emit green light
  • the second light-emitting device 125 of the blue sub-pixel B is configured to emit blue light for color display.
  • the second light-emitting device 125 of the second sub-pixel P2' is configured to emit white light.
  • the second sub-pixel P2' also includes a plurality of second filter parts 22. See FIG. 9D, FIG. 10A, and FIG. 10B.
  • Each second filter part 22 corresponds to a third opening 161
  • the second filter part 22 corresponds to a third opening 161.
  • the boundary S1 of the orthographic projection of the portion 22 on the substrate 11 is located within the range of the orthographic projection of the second light-shielding portion 16 on the substrate 11 (see FIG. 9A ) to filter the light of the second light-emitting device 125 .
  • the plurality of second filter parts 22 can respectively transmit multiple types of monochromatic light.
  • the white light emitted by the second light-emitting device 125 of the second sub-pixel P2' is illuminated on the corresponding second filter part 22 to emit corresponding light. color monochromatic light to achieve full-color display.
  • the plurality of second sub-pixels P2' include a red sub-pixel R, a first green sub-pixel G1, a second green sub-pixel G2 and a blue sub-pixel B.
  • the red sub-pixel R The second filter part 22 can transmit red light
  • the second filter part 22 of the first green sub-pixel G1 and the second green sub-pixel G2 can transmit green light
  • the second filter part 22 of the blue sub-pixel B can transmit Blu-ray.
  • the white light emitted by the second light-emitting device 125 of the red sub-pixel R, the first green sub-pixel G1, the second green sub-pixel G2 and the blue sub-pixel B irradiates the corresponding second filter part 22 to Emit monochromatic light of the corresponding color to achieve full-color display.
  • the second filter part 22 transmits monochromatic light, the second filter part 22 can filter out most of the wavelength bands in the external ambient light, thereby further reducing the dominant role of the external ambient light in the display panel 200 . Displays the reflection intensity of area A2.
  • the plurality of first sub-pixels P1' and the plurality of second sub-pixels P2' each include a red sub-pixel R, a first green sub-pixel G1, a second green sub-pixel G2 and Blue sub-pixel B.
  • the boundary S2 of the light-emitting area of the red sub-pixel R, the first green sub-pixel G1, the second green sub-pixel G2 and the blue sub-pixel B and the first light shielding area are approximately equal in distance to avoid uneven brightness or color shift in the functional device setting area A1, thereby improving the display effect of the functional device setting area A1 of the display panel 200.
  • the boundary S2 of the light-emitting area of the red sub-pixel R, the first green sub-pixel G1, the second green sub-pixel G2 and the blue sub-pixel B and the inner boundary S3 of the second light shielding part 16 The distances are approximately equal to avoid uneven brightness or color shift in the main display area A2, thereby improving the display effect of the main display area A2 of the display panel 200.
  • the red sub-pixel R is taken as an example for illustration.
  • the distance between the boundary S2 of the light-emitting area of the first sub-pixel P1' in the functional device setting area A1 and the inner boundary S3 of the first light-shielding portion 15 is approximately equal to that of the second sub-pixel P2 in the main display area A2.
  • the distance between the boundary S2 of the light-emitting area and the inner boundary S3 of the second light-shielding part 16 is to avoid the problem of uneven brightness or color shift between the functional device setting area A1 and the main display area A2, thereby improving the performance of the display panel 200 display effect.
  • the boundary S2 of the light-emitting area is the boundary of the opening area of the pixel defining layer 14 .
  • the above-mentioned display panel 10 also includes a plurality of signal lines, and the plurality of signal lines are connected to the pixel circuit 13 (including the first pixel circuit 135 and the second pixel circuit 136). Electrical connection.
  • at least one signal line includes a signal line for connecting an external signal source and an adapter line connected to the first pixel circuit 135.
  • the portion of the signal line located in the functional device setting area A1 is transparent to improve the functional devices of the display panel 200. Set the transmittance of area A1.
  • the above-mentioned plurality of signal lines include the scanning signal line GL, the reset signal line RL, the enable signal line EL, the initialization signal line INL, the first voltage signal line VDL and the data line. D.L.
  • the scanning signal line GL is electrically connected to the scanning signal terminal GATE of the pixel circuit 13
  • the reset signal line RL is electrically connected to the reset signal terminal RESET of the pixel circuit 13
  • the enable signal line EL is electrically connected to the enable signal terminal EM of the pixel circuit 13.
  • the initialization signal line INL is electrically connected to the initialization signal terminal of the pixel circuit 13
  • the first voltage signal line VDL is electrically connected to the first voltage signal terminal VDD of the pixel circuit 13
  • the data line DL is electrically connected to the data signal terminal DATA of the pixel circuit 13. connect.
  • the scan signal line GL includes a first scan line GL1 and a first transfer line GL2.
  • the first transfer line GL2 extends generally along the first direction X, and is electrically connected to the first pixel circuit 135; one end of the first scanning line GL1 extends into the functional device setting area A1 and is electrically connected to the first transfer line GL2 to prevent the scanning signal line GL from interfacing with other signal lines (such as the data line DATA ) wiring arrangement causes cross interference.
  • the part of the first scanning line GL1 located in the functional device setting area A1 is transparent, so as to increase the transmittance of the functional device setting area A1 of the display panel 200.
  • the first scan line GL1 includes a first sub-scan line GL11 and a second sub-scan line GL12.
  • the first sub-scan line GL11 is located in the functional device setting area A1.
  • the second sub-scanning line GL12 is located in the main display area A2.
  • the first sub-scanning line GL11 is transparent, and the second sub-scanning line GL12 may be transparent or opaque.
  • the reset signal line RL includes a first reset line RL1 and a second transfer line RL2.
  • the second transfer line RL2 extends generally along the first direction X and is electrically connected to the first pixel circuit 135 .
  • One end of the first reset line RL1 extends into the functional device setting area A1 and is electrically connected to the second transfer line RL2 to avoid cross interference between the reset signal line RL and other signal lines (such as the data line DATA).
  • the part of the first reset trace RL1 located in the functional device setting area A1 is transparent to increase the transmittance of the functional device setting area A1 of the display panel 200.
  • the first reset line RL1 includes a first sub-reset line RL11 and a second sub-reset line RL12, and the first sub-reset line RL11 is located in the functional device setting area A1,
  • the second sub-reset trace RL12 is located in the main display area A2.
  • the first sub-reset trace RL11 is transparent, and the second sub-reset trace RL12 may be transparent or opaque.
  • the enable signal line EL includes a first enable line EL1 and a third transfer line EL2.
  • the third transfer line EL2 extends generally along the first direction X and is electrically connected to the first pixel circuit 135 .
  • One end of the first enable line EL1 extends into the functional device setting area A1 and is electrically connected to the third transfer line EL2 to avoid the intersection of the enable signal line EL and other signal lines (such as the data line DATA). interference.
  • the part of the first enable trace EL1 located in the functional device setting area A1 is transparent to increase the transmittance of the functional device setting area A1 of the display panel 200.
  • the first enable trace EL1 includes a first sub-enable trace EL11 and a second sub-enable trace EL12.
  • the first sub-enable trace EL11 is located on the functional device In the setting area A1, the second sub-enable trace EL12 is located in the main display area A2.
  • the first sub-enable trace EL11 is transparent, and the second sub-enable trace EL12 can be transparent or opaque.
  • the initialization signal line INL includes a first initialization line INL1 and a fourth transfer line INL2.
  • the fourth transfer line INL2 extends roughly along the first direction
  • the wiring arrangement of the initialization signal line INL and other signal lines causes cross interference.
  • the part of the first initialization trace INL1 located in the functional device setting area A1 is transparent to increase the transmittance of the functional device setting area A1 of the display panel 200.
  • the first initialization line INL1 includes a first sub-initialization line INL11 and a second sub-initialization line INL12.
  • the first sub-initialization line INL11 is located in the functional device setting area A1.
  • the second sub-initialization trace INL12 is located in the main display area A2.
  • the first sub-initialization trace INL11 is transparent, and the second sub-initialization trace INL12 may be transparent or opaque.
  • the first voltage signal line VDL and the data line DL extend generally along the second direction Y.
  • the first voltage signal line VDL and the data line DL are located at least partially transparent in the functional device setting area A1, so as to increase the transmittance of the functional device setting area A1 of the display panel 200.
  • the first voltage signal line VDL includes a first voltage trace VDL1 and a fifth transfer line VDL2.
  • the fifth transfer line VDL2 is disposed on a side of the first pixel circuit 135 away from the substrate 11 and is electrically connected to the first voltage line VDL1. That is to say, the fifth transfer line VDL2 spans over the first pixel circuit 135 (see FIG. 6A).
  • the distance between the first voltage signal line VDL and the first pixel circuit 135 can be further increased through the fifth transfer line VDL2 , thereby reducing electromagnetic interference.
  • the first voltage trace VDL1 can also include a first sub-voltage trace VDL11 and a second sub-voltage trace VDL12.
  • the first sub-voltage trace VDL11 is located in the functional device setting.
  • the second sub-voltage trace VDL12 is located in the main display area A2.
  • the data line DL includes a first sub-data line DL1 and a second sub-data line DL2.
  • the first sub-data line DL1 is located in the functional device setting area A1, and the second sub-data line DL2 is located in the main display area A2.
  • both the first sub-voltage line VDL11 and the first sub-data line DL1 may be transparent.
  • the signal lines included in each film layer and some other pattern film layers are exemplarily introduced below in conjunction with the film layer structure of the display substrate 10 .
  • the display substrate 10 sequentially includes a semiconductor layer ACT, a first gate conductive layer GT1 , a second gate conductive layer GT2 , and a first source and drain layer.
  • the semiconductor layer ACT the first gate conductive layer GT1, the second gate conductive layer GT2, the first source-drain conductive layer SD1, the transparent conductive layer TC and the second source-drain conductive layer SD2, each adjacent two
  • insulating film layers between the layers there are insulating film layers between the layers.
  • the semiconductor layer ACT includes the channel region S of each transistor 130 of the pixel circuit 13 as well as the source electrode 131 (not shown in FIGS. 11 and 18 ) and the drain electrode 132 (Not shown in Figures 11 and 18).
  • the material of the semiconductor layer ACT includes amorphous silicon, single crystal silicon, polycrystalline silicon, or metal oxide semiconductor materials.
  • the material of the semiconductor layer ACT includes indium gallium zinc oxide and/or zinc oxide, and embodiments of the present disclosure are not limited thereto.
  • the first gate conductive layer GT1 includes a first transfer line GL2, a second transfer line RL2, a third transfer line EL2, a second sub-scanning line GL12, a second sub-reset line RL12,
  • the second sub-enable line EL12 and the first plate C1 of the storage capacitor C that is, the first transfer line GL2, the second transfer line RL2, the third transfer line EL2, the second sub-scanning line GL12, the second sub- The reset trace RL12, the second sub-enable trace EL12 and the first plate C1 of the storage capacitor C are arranged on the same layer, and are all located on the first gate conductive layer GT1.
  • the material of the first gate conductive layer GT1 includes metal.
  • the material of the first gate conductive layer GT1 includes at least one of aluminum, copper, and molybdenum, and the embodiment of the present disclosure is not limited thereto. That is to say, the materials of the first transfer line GL2, the second transfer line RL2, the third transfer line EL2 and the first plate C1 of the storage capacitor C include metal.
  • the overlapping portion of the first transfer line GL2 and the semiconductor layer ACT forms the control electrode of the first transistor T1 , the second transistor T2 and the sixth transistor T6 .
  • the overlapping portion of the second transfer line RL2 and the semiconductor layer ACT forms the control electrode of the third transistor T3.
  • the overlapping portion of the third transfer line EL2 and the semiconductor layer forms the control electrode of the fourth transistor T4 and the fifth transistor T5.
  • the first plate C1 of the storage capacitor C located in the functional device setting area A1 is located between the first transfer line GL2 and the third transfer line EL2.
  • the overlapping portion of the second sub-reset line RL12 and the semiconductor layer ACT forms the control electrode of the third transistor T3 and the sixth transistor T6, and the overlapping portion of the second sub-scanning line GL12 and the semiconductor layer forms the first
  • the control electrodes of the transistor T1 and the second transistor T2 form the control electrodes of the fourth transistor T4 and the fifth transistor T5.
  • the first plate C1 of the storage capacitor C of the main display A2 is located between the second sub-scanning line GL12 and the second sub-enable line EL12.
  • the second gate conductive layer GT2 includes a fourth transfer line INL2 , a second sub-initialization line INL12 and a second plate C2 of the storage capacitor C.
  • the orthographic projection of the second electrode plate C2 on the substrate 11 partially overlaps with the orthographic projection of the first electrode plate on the substrate 11 .
  • the material of the second gate conductive layer GT2 includes metal.
  • the material of the second gate conductive layer GT2 includes at least one of aluminum, copper, and molybdenum, and the embodiment of the present disclosure is not limited thereto.
  • the storage capacitor C is formed by the overlapping portion of the orthographic projection of the second plate C2 on the substrate 11 and the orthographic projection of the first plate C1 on the substrate 11 .
  • the fourth transfer line INL2 is electrically connected to the third transistor T3 and the sixth transistor T6 in the first pixel circuit 135 through a connecting line; the second sub-initialization line INL12 is connected to the third transistor T3 in the second pixel circuit 136 through a connecting line. and electrically connected to the sixth transistor T6.
  • the second gate conductive layer GT2 also includes a shielding pattern 40 located in the main display area A2, and the shielding pattern 40 is located in the second sub-reset line RL12 and the second sub-scanning line GL12. between.
  • the orthographic projection of the shielding pattern 40 on the substrate 11 at least partially overlaps with the orthographic projection of the second sub-voltage trace VDL12 on the substrate 11 , and the shielding pattern 40 is electrically connected to the second sub-voltage trace VDL12 to reduce Electromagnetic interference between various traces.
  • the first source-drain conductive layer SD1 includes a first connection line 50 , a second connection line 60 , a third connection line 70 , a fourth connection line 80 and a second sub-voltage trace VDL12 .
  • the first connection line 50 and the second connection line 60 are distributed in both the functional device setting area A1 and the main display area A2, and the third connection line 70 and the fourth connection line 80 are only distributed in the functional device setting area A1.
  • the material of the first source-drain conductive layer SD1 includes metal.
  • the material of the first source-drain conductive layer SD1 includes at least one of aluminum, copper, and molybdenum, and the embodiment of the present disclosure is not limited thereto.
  • the first connection line 50 is electrically connected to the first electrode of the third transistor T3 and the first electrode of the sixth transistor T6.
  • the second connection line 60 is electrically connected to the first plate C1 of the storage capacitor C, the second electrode of the first transistor T1, and the second electrode of the third transistor T3.
  • the third connection line 70 is electrically connected to the second plate C2 of the storage capacitor C and the first electrode of the fourth transistor T4.
  • the fourth connection line 80 is electrically connected to the second electrode of the fifth transistor T5 and the second electrode of the sixth transistor T6.
  • the first connection line 50 is electrically connected to the first electrode of the third transistor T3 and the first electrode of the sixth transistor T6.
  • the second connection line 60 is electrically connected to the first plate C1 of the storage capacitor C, the second electrode of the first transistor T1, and the second electrode of the third transistor T3.
  • the first scan line GL1, the first reset line RL1, the first enable line EL1, the first initialization line INL1, the data line DL and the first voltage signal line VDL are located at the functional At least part of the device setting area A1 is transparent.
  • the transparent conductive layer TC includes a first sub-scanning line GL11, a first sub-reset line RL11, a first sub-enable line EL11, and a first sub-initialization line INL11 , the first sub-voltage line VDL11 and the first sub-data line DL1.
  • the material of the transparent conductive layer TC includes a transparent conductive material, and the transmittance of the transparent conductive layer TC made of the transparent conductive material is greater than or equal to 60%.
  • the material of the transparent conductive layer TC includes indium tin oxide, and embodiments of the present disclosure are not limited thereto.
  • both the fifth transfer line VDL2 and the second sub-data line DL2 may be located on the second source-drain conductive layer SD2.
  • the material of the second source-drain conductive layer SD2 includes metal.
  • the material of the second source-drain conductive layer SD2 includes at least one of aluminum, copper, and molybdenum, and the embodiment of the present disclosure is not limited thereto.
  • the second source-drain conductive layer SD2 may also include a support pattern 90 .
  • the support pattern 90 is located in the main display area A2 and is disposed in parallel with the second sub-data line DL2 on both sides of the second pixel circuit 136 .
  • the first electrode 121 of the light emitting device 12 plays a supporting and balancing role.
  • the support pattern 90 can be electrically connected to the second sub-voltage line VDL12, which can also reduce electromagnetic interference between signal lines.
  • the pad M of the pixel circuit 13 may be composed of one or more layers of pad patterns formed in the first source-drain conductive layer SD1, the transparent conductive layer TC, and the second source-drain conductive layer SD2.
  • the bonding pad M is formed by sequentially stacking the welding pattern of the first source-drain conductive layer SD1, the welding pattern of the transparent conductive layer TC, and the welding pattern of the second source-drain conductive layer SD2.

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Abstract

一种显示面板，包括衬底、多个第一子像素和多个第一遮光部。多个第一子像素设置于衬底上，且位于功能器件设置区。第一子像素包括第一像素电路和第一发光器件，第一发光器件包括与第一像素电路电连接的第一电极；第一像素电路在衬底上的正投影的部分，位于第一电极在衬底上的正投影范围之外。多个第一遮光部间隔设置于多个第一发光器件远离衬底的一侧，且位于功能器件设置区。每个第一遮光部设置有多个第一开口区，第一发光器件的发光区位于对应的第一开口区内。其中，第一像素电路的第一部分在衬底上的正投影，位于第一遮光部在衬底的正投影范围内；第一部分为第一像素电路在衬底上的正投影位于第一电极在衬底上的正投影范围之外的部分。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
随着显示技术的飞速发展，显示装置已经逐渐遍及在人们的生活中。其中，有机发光二极管(organic light emitting diode，简称：OLED)由于具有自发光、低功耗、宽视角、响应速度快、高对比度以及柔性显示等优点，因而被广泛的应用于手机、电视、笔记本电脑等智能产品中。
公开内容
一方面，提供一种显示面板。所述显示面板具有功能器件设置区，所述显示面板包括衬底、多个第一子像素和多个第一遮光部。所述多个第一子像素设置于所述衬底上，且位于所述功能器件设置区。至少一个第一子像素包括第一像素电路和第一发光器件，所述第一发光器件包括第一电极，所述第一电极与所述第一像素电路电连接；所述第一像素电路在所述衬底上的正投影的部分，位于所述第一电极在所述衬底上的正投影范围之外。
所述多个第一遮光部间隔设置于所述多个第一发光器件远离所述衬底的一侧，且位于所述功能器件设置区。每个第一遮光部设置有多个第一开口区，每个第一开口区对应一个第一发光器件，且所述第一发光器件的发光区位于对应的第一开口区内。其中，所述第一像素电路的第一部分在所述衬底上的正投影，位于所述第一遮光部在所述衬底的正投影范围内；所述第一部分为所述第一像素电路在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影范围之外的部分。
在一些实施例中，所述显示面板包括设置于所述功能器件设置区的多个第一像素单元，每个第一像素单元包括多个所述第一子像素；其中，每个所述第一遮光部的多个第一开口区与同一个第一像素单元的多个第一子像素一一对应。
在一些实施例中，位于同一个第一遮光部的外边界内的多个第一子像素中，在设定方向上相邻的两个第一子像素的中心之间的距离为第一距离。在所述设定方向上，位于相邻两个第一遮光部的外边界内且相邻的两个第一子像素的中心之间的距离为第二距离。其中，所述第一距离小于所述第二距离。
在一些实施例中，所述多个第一子像素包括多个红色子像素、多个第一绿色子像素、多个第二绿色子像素和多个蓝色子像素。
所述多个红色子像素和所述多个第一绿色子像素沿第一斜方向交替排列，和所述多个第二绿色子像素沿第二斜方向交替排列；所述蓝色子像素和所述第二绿色子像素沿所述第一斜方向交替排列，和所述多个第一绿色子像素沿所述第二斜方向交替排列；且所述第一绿色子像素和所述第二绿色子像素沿第一方向交替排列，所述红色子像素和所述蓝色子像素沿第二方向交替排列。其中，所述第一方向与所述第二方向大致垂直，所述第一斜方向和所述第二斜方向相交叉，且所述第一斜方向和所述第二斜方向均与所述第一方向相交叉，以及所述第一斜方向和所述第二斜方向均与所述第二方向相交叉。
在一些实施例中，所述设定方向为所述第一方向、所述第二方向、所述第一斜方向和所述第二斜方向中的至少一者。
在一些实施例中，所述显示面板包括多个第一像素单元，每个第一像素单元包括相邻的一个红色子像素、一个第一绿色子像素、一个第二绿色子像素和一个蓝色子像素。在同一个第一像素单元中，所述红色子像素和所述蓝色子像素沿所述第二方向排列，所述第一绿色子像素和所述第二绿色子像素沿所述第一方向排列。所述第一遮光部在所述衬底的正投影的外边界大致为菱形。
在一些实施例中，所述多个第一遮光部排列成多行多列，每行包括沿第一方向排列的多个第一遮光部，每列包括沿第二方向排列的多个第一遮光部；所述第一方向与所述第二方向大致垂直。
在一些实施例中，所述显示面板还包括第二电极层，所述第二电极层设置于所述第一电极和所述第一遮光部之间。所述第二电极层位于所述功能器件设置区的部分设有多个第二开口区，所述多个第二开口区在所述衬底上的正投影，位于所述多个第一遮光部在所述衬底上的正投影之间的区域。
在一些实施例中，所述多个第一遮光部排列成多行多列，每行包括沿第一方向排列的多个第一遮光部，每列包括沿第二方向排列的多个第一遮光部；所述第一方向与所述第二方向大致垂直。所述第二开口区设置于在所述第一方向上相邻的两个第一遮光部之间；和/或，所述第二开口区设置于在第二方向上相邻的两个第一遮光部之间。
在一些实施例中，相邻两行中的多个第一遮光部相互错开设置，相邻的两列中的多个第一遮光部相互错开设置。
在一些实施例中，所述第二开口区的形状大致为圆形或椭圆形。
在一些实施例中，所述显示面板还具有主显示区，所述主显示区至少部分围绕所述功能器件设置区。所述显示面板还包括多个第二子像素和第二遮 光部。所述多个第二子像素设置于所述衬底上，且位于所述主显示区。每个第二子像素包括第二像素电路和第二发光器件，至少一个第二发光器件包括第三电极，所述第三电极与所述第二像素电路电连接；所述第二像素电路在所述衬底上的正投影的部分，位于所述第三电极在所述衬底上的正投影范围之外。
所述第二遮光部设置于所述多个第二子像素远离所述衬底的一侧，且位于所述主显示区。所述第二遮光部包括多个第三开口区，每个第三开口区对应一个第二发光器件，且所述第二发光器件的发光区位于对应的第三开口区内。其中，所述多个第二像素电路的第二部分在所述衬底上的正投影，位于所述第二遮光部在所述衬底的正投影范围内；所述第二部分为所述第二像素电路在所述衬底上的正投影，位于所述第三电极在所述衬底上的正投影范围之外的部分。
在一些实施例中，所述第二遮光部在所述衬底上的正投影覆盖第一区域，所述第一区域为所述主显示区中所述多个第二发光器件之间的区域。
在一些实施例中，所述第二电极层位于所述主显示区的部分为连续的膜层结构。
在一些实施例中，所述第一遮光部与所述第二遮光部的材料相同且同层设置。
在一些实施例中，所述第一子像素还包括多个第一滤光部，每个第一滤光部对应一个第一开口区，且所述第一滤光部在所述衬底上的正投影的边界，位于对应的第一遮光部在所述衬底上的正投影的范围内。在所述显示面板还包括多个第二子像素和第二遮光部的情况下，所述第二子像素还包括多个第二滤光部，每个第二滤光部对应一个第三开口区，且所述第二滤光部在所述衬底上的正投影的边界，位于第二遮光部在所述衬底上的正投影的范围内。
在一些实施例中，所述显示面板还包括封装层，所述封装层设置于所述多个第一遮光部和所述第一发光器件之间。
在一些实施例中，所述显示面板还包括多条信号线，所述多条信号线与所述第一像素电路电连接。至少一条信号线包括用于外接信号源的信号走线以及与所述第一像素电路连接的转接线，所述信号走线中位于所述功能器件设置区的部分透明。
在一些实施例中，所述多条信号线包括扫描信号线、复位信号线、使能信号线和初始化信号线。
所述扫描信号线包括第一扫描走线和第一转接线。所述第一转接线大致 沿第一方向延伸，且与所述第一像素电路电连接。所述第一扫描走线的一端伸入所述功能器件设置区，与所述第一转接线电连接；所述第一扫描走线位于所述功能器件设置区的部分透明。
所述复位信号线包括第一复位走线和第二转接线。所述第二转接线大致沿所述第一方向延伸，且与所述第一像素电路电连接。所述第一复位走线的一端伸入所述功能器件设置区，与所述第二转接线电连接；所述第一复位走线位于所述功能器件设置区的部分透明。
所述使能信号线包括第一使能走线和第三转接线。所述第三转接线大致沿所述第一方向延伸，且与所述第一像素电路电连接。所述第一使能走线的一端伸入所述功能器件设置区，与所述第三转接线电连接；所述第一使能走线位于所述功能器件设置区的部分透明。
初始化信号线，包括第一初始化走线和第四转接线。所述第四转接线大致沿所述第一方向延伸，且与所述第一像素电路电连接。所述第一初始化走线的一端伸入所述功能器件设置区，与所述第四转接线电连接；所述第一初始化走线位于所述功能器件设置区的部分透明。
在一些实施例中，沿垂直于所述衬底且远离所述衬底的方向，所述显示面板依次包括半导体层、第一栅导电层、第二栅导电层、第一源漏导电层和透明导电层。所述第一转接线、所述第二转接线和所述第三转接线位于所述第一栅导电层，所述第四转接线位于所述第二栅导电层；和/或，所述第一扫描走线、所述第一复位走线、所述第一使能走线和所述第一初始化走线中位于所述功能器件设置区的部分位于所述透明导电层。
在一些实施例中，所述多条信号线还包括第一电压信号线和数据线，所述第一电压信号线和所述数据线大致沿第二方向延伸，且所述第一电压信号线和所述数据线均与所述第一像素电路电连接。所述第一电压信号线和所述数据线中位于所述功能器件设置区的至少部分透明。
在一些实施例中，所述第一电压信号线包括第一电压走线和第五转接线，所述第五转接线设置于所述第一像素电路远离所述衬底的一侧，且与所述第一电压走线电连接。
在一些实施例中，沿垂直于所述衬底且远离所述衬底的方向，所述显示基板依次包括半导体层、第一栅导电层、第二栅导电层、第一源漏导电层、透明导电层和第二源漏导电层。所述第一电压走线和所述数据线位于所述功能器件设置区的部分位于所述透明导电层，所述第五转接线位于所述第二源漏导电层。
另一方面，提供一种显示装置。所述显示装置包括壳体和如上述任一实施例所述的显示面板，所述显示面板设置于所述壳体内。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的结构图；
图2为根据一些实施例的显示装置的爆炸图；
图3A为根据一些实施例的显示面板的功能器件设置区的剖视图；
图3B为根据一些实施例的显示面板的主显示区的剖视图；
图4为根据一些实施例的像素驱动电路的电路原理图；
图5为根据一些实施例的像素驱动电路的时序图；
图6A为根据一些实施例的显示面板的功能器件设置区的像素电路排布的俯视图；
图6B为根据一些实施例的显示面板的功能器件设置区的发光器件的排布的俯视图；
图6C为根据一些实施例的一种显示面板的功能器件设置区设有第一遮光部的俯视图；
图6D为根据一些实施例的另一种显示面板的功能器件设置区设有第一遮光部的俯视图；
图6E为根据一些实施例的显示面板的功能器件设置区的俯视图；
图7为根据一些实施例的显示面板的第一遮光部的结构图；
图8为根据一些实施例的显示面板的功能器件设置区的一个像素单元的放大图；
图9A为根据一些实施例的显示面板的主显示区的像素电路排布的俯视图；
图9B为根据一些实施例的显示面板的主显示区的发光器件排布的俯视图；
图9C为根据一些实施例的一种显示面板的功能器件设置区设有第二遮光部的俯视图；
图9D为根据一些实施例的另一种显示面板的功能器件设置区设有第二遮光部的俯视图；
图10A为根据一些实施例的显示面板的第二遮光部的结构图；
图10B为根据一些实施例的显示面板的主显示区的一个红色子像素的放大图；
图11为根据一些实施例的显示面板的功能器件设置区的半导体层的俯视图；
图12为图11所示的功能器件设置区的半导体层上增加第一栅导电层的俯视图；
图13为图12所示的功能器件设置区的第一栅导电层上增加第二栅导电层后的俯视图；
图14为图13所示的功能器件设置区的第二栅导电层上增加第一源漏导电层后的俯视图；
图15为图14所示的功能器件设置区的第一源漏导电层上增加透明导电层后的俯视图；
图16为图15所示的功能器件设置区的透明导电层上增加第二源漏导电层后的俯视图；
图17为图16所示的功能器件设置区的第二源漏导电层上增加第一电极后的俯视图；
图18为根据一些实施例的显示面板的主显示区的半导体层的俯视图；
图19为图18所示的主显示区的半导体层上增加第一栅导电层的俯视图；
图20为图19所示的主显示区的第一栅导电层上增加第二栅导电层后的俯视图；
图21为图20所示的主显示区的第二栅导电层上增加第一源漏导电层后的俯视图；
图22为图21所示的主显示区的第一源漏导电层上增加透明导电层后的俯视图；
图23为图22所示的主显示区的透明导电层上增加第二源漏导电层后的俯视图；
图24为图23所示的主显示区的第二源漏导电层上增加第一电极后的俯视图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”、“电连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。又例如，描述一些实施例时可能使用了术语“电连接”以表明两个或两个以上部件彼此间有直接电接触或间接电连接。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所 述的值。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供的像素驱动电路(像素电路)中所采用的晶体管可以为薄膜晶体管(thin film transistor，简称：TFT)、场效应晶体管(metal oxide semiconductor，简称：MOS)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
另外，在本公开的实施例提供的像素驱动电路(像素电路)中，均以薄膜晶体管为P型晶体管为例进行说明。需要说明的是，本公开的实施例包括但不限于此。例如，本公开的实施例提供的像素驱动电路中的一个或多个薄膜晶体管也可以采用N型晶体管，只需将选定类型的薄膜晶体管的各极参照本公开的实施例中的相应薄膜晶体管的各极相应耦接，并且使相应的电压端提供对应的高电平电压或低电平电压即可。
本文中，像素驱动电路(像素电路)所采用的各薄膜晶体管的控制极为晶体管的栅极，第一极为薄膜晶体管的源极和漏极中一者，第二极为薄膜晶体管的源极和漏极中另一者。由于薄膜晶体管的源极、漏极在结构上可以是 对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的薄膜晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在薄膜晶体管为P型晶体管的情况下，薄膜晶体管的第一极为源极，第二极为漏极；示例性的，在薄膜晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
本公开的实施例提供的像素驱动电路(像素电路)中，电容器可以是通过工艺制程单独制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容器的各个电容电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现。电容器也可以是晶体管之间的寄生电容，或者通过晶体管本身与其他器件、线路来实现，又或者利用电路自身线路之间的寄生电容来实现。
参阅图1，本公开的一些实施例提供了一种显示装置1000，显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。示例性地，该显示装置1000可以为电视机、笔记本电脑、平板电脑、手机、个人数字助理(英文：personal digital assistant；简称：PDA)、导航仪、可穿戴设备、虚拟现实(英文：virtual reality；简称：VR)设备等任何具有显示功能的产品或者部件。
此处，显示装置1000为电致发光显示装置或光致发光显示装置。在显示装置1000为电致发光显示装置的情况下，电致发光显示装置可以为有机电致发光显示装置(organic light-emitting diode，简称OLED)或量子点电致发光显示装置(quantum dot light emitting diodes，简称QLED)。在显示装置1000为光致发光显示装置的情况下，光致发光显示装置可以为量子点光致发光显示装置。
在一些实施例中，参阅图1和图2，显示装置1000包括壳体100、设置于壳体100内的显示面板200、功能器件300、电路板400以及其他电子配件。
其中，电路板400可以在显示面板200的端部与显示面板200绑定，并弯折至显示面板200的背侧，以实现全面屏的设计。功能器件300可以集成于显示面板200的下方，以实现全面屏的设计。
需要说明的是，该功能器件300可以为摄像头、红外传感器、近距离传感器、眼球追踪模组和人脸识别模组等等。示例性地，如图1和图2所示，该功能器件300为摄像头。
在一些实施例中，如图2、图3A和图3B所示，显示面板200包括显示基板10和用于封装显示基板10的封装层20。
其中，显示基板10具有相对设置的出光侧和非出光侧，封装层20设置 于显示基板10的出光侧。此处，封装层20可以为封装薄膜，也可以为封装基板。
参阅图2，显示面板200具有显示区A，以及设置在显示区A的至少一侧的周边区B。图2中以周边区B围绕显示区A设置为例。
其中，显示区A为显示图像的区域，被配置为设置多个像素单元P。周边区B为不显示图像的区域，周边区B被配置为设置显示驱动电路，例如，栅极驱动电路和源极驱动电路。
需要说明的是，在功能器件300集成于显示面板200的下方的情况下，显示区A还具有功能器件设置区A1和至少部分环绕功能器件设置区A1的主显示区A2，功能器件300位于功能器件设置区A1。图1和图2中以主显示区A2环绕功能器件设置区A1为例进行示意。
示例性地，参阅图2和图6B，显示面板200的显示区A设置有多个像素单元P，每个像素单元P可以包括多种发光颜色的子像素P＇。例如，多种发光颜色的子像素P＇包括红色子像素、绿色子像素和蓝色子像素。
参见图3A和图3B，每个子像素P＇均包括衬底11、以及设置于衬底11上的发光器件12和像素驱动电路13，像素驱动电路13包括多个晶体管130，晶体管130包括沟道区S、源极131、漏极132和栅极133，源极131和漏极132分别与沟道区S接触。沿垂直于衬底11且远离衬底11的方向，发光器件12包括第一电极121、发光功能层122和第二电极123。
此处，参阅图6A和图6B，像素驱动电路13在衬底11上的正投影的部分，位于第一电极121在衬底11上的正投影范围之外，也即像素驱动电路13的部分边缘未被第一电极121遮挡。
需要说明的是，为了便于说明，以下所提到的像素电路13均指的是上述像素驱动电路13。
此处，第一电极121为发光器件12的阳极，第二电极123为发光器件12的阴极。或者，第一电极121为发光器件12的阴极，第二电极123为发光器件12的阳极。
示例性地，如图3A和图3B所示，第一电极121为发光器件12的阳极，第二电极123为发光器件12的阴极。第一电极121和像素电路13的一个晶体管130的源极131或漏极132电连接。图3A和图3B中以第一电极121与像素电路13的一个晶体管130的源极131电连接为例进行示意。
在一些实施例中，发光功能层122仅包括发光层。在另一些实施例中，发光功能层122除包括发光层外，还包括电子传输层(election transporting layer， 简称：ETL)、电子注入层(election injection layer，简称：EIL)、空穴传输层(hole transporting layer，简称：HTL)和空穴注入层(hole injection layer，简称：HIL)中的至少一个。
此外，上述像素电路13的结构包括多种，可以根据实际需要选择设置。例如，像素电路13的结构可以包括“2T1C”、“3T1C”、“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构。其中，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字表示为存储电容器的数量。
其中，在显示面板200使用的过程中，像素电路13中的晶体管及发光器件12的稳定性可能会下降(例如驱动晶体管的阈值电压漂移)，影响显示面板200的显示效果，这样便需要对像素电路13进行补偿。
对像素电路13进行补偿的方式可以包括多种，可以根据实际需要选择设置。例如，可以在像素电路13中设置像素补偿电路，以利用该像素补偿电路对像素电路13进行内部补偿。又如，可以通过像素电路13内部的晶体管对驱动晶体管或发光器件进行感测，并将感测到的数据传输到外部感应电路，以利用该外部感应电路计算需要补偿的驱动电压值并进行反馈，从而实现对像素电路13的外部补偿。
本公开以采用内部补偿的方式，且像素电路13采用“7T1C”的结构为例，对像素电路13的结构及工作过程进行示意性说明。
示例性地，如图4所示，像素电路13可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、驱动晶体管Td和存储电容器C。
第一晶体管T1的控制极与扫描信号端GATE电连接，第一晶体管T1的第一极与驱动晶体管Td的第二极电连接，第一晶体管T1的第二极与驱动晶体管Td的控制极电连接。
第二晶体管T2的控制极与扫描信号端GATE电连接，第二晶体管T2的第一极与数据信号端DATA电连接，第二晶体管T2的第二极与驱动晶体管Td的第一极电连接。
第三晶体管T3的控制极与复位信号端RESET电连接，第三晶体管T3的第一极与初始化信号端VINIT电连接，第三晶体管T3的第二极与驱动晶体管Td的控制极电连接。
第四晶体管T4的控制极与使能信号端EM电连接，第四晶体管T4的第一极与第一电压信号端VDD电连接，第四晶体管T4的第二极与驱动晶体管 Td的第一极电连接。
第五晶体管T5的控制极与使能信号端EM电连接，第五晶体管T5的第一极与驱动晶体管Td的第二极电连接，第五晶体管T5的第二极与发光器件12的第一电极121(参见图3A)电连接。
第六晶体管T6的控制极与扫描信号端GATE电连接，第六晶体管T6的第一极与初始化信号端VINIT电连接，第六晶体管T6的第二极与发光器件12的第一电极121(参见图3A)电连接。
存储电容器C的第一极板C1(参见图3A)与驱动晶体管Td的控制极电连接，存储电容器C的第二极板C2(参见图3A)与第一电压信号端VDD电连接。
基于上述像素电路13的结构，如图4和图5所示，在一帧显示阶段中，子像素的工作过程例如可以包括复位阶段S1、数据写入阶段S2和发光阶段S3。
在复位阶段S1，第六晶体管T6在来自扫描信号端GATE的扫描信号Gate的控制下导通，发光器件12的第一电极的电压被重置为初始化电压信号Vinit，以及，第三晶体管T3在来自复位信号端RESET的复位信号Reset的控制下导通，驱动晶体管Td的控制极和存储电容器C的第一极板C1的电压被重置为初始化电压信号Vinit。
在数据写入阶段S2，第一晶体管T1和第二晶体管T2在来自扫描信号端GATE的扫描信号Gate的控制下导通，驱动晶体管Td在存储电容器C存储的初始化电压信号的控制下导通，存储电容器C被写入来自数据信号端DATA的数据信号Data。
在发光阶段S3，第四晶体管T4和第五晶体管T5在使能信号端EM的使能信号Em的控制下导通，以向发光器件12输出驱动电流信号，驱动发光器件12发光。
在一些实施例中，如图3A和图3B所示，显示基板10还包括像素界定层14，像素界定层14设置于第一电极121远离衬底11的一侧。其中，像素界定层14包括多个开口区，一个发光器件12设置于一个开口区中，即发光器件12的发光功能层122在开口区与第一电极121电接触。
需要说明的是，为了降低工艺难度，第一电极121的面积大于像素界定层14的开口区的面积，以保证像素界定层14的整个开口区均为发光器件12的发光区。即，第一电极121、第二电极123以及发光功能层122重叠的部分构成发光器件12的发光区，也即，第一电极121、第二电极123和发光功能 层122对应位于像素界定层14的开口区所在的区域的部分构成发光器件12的发光区。
可以理解的是，在功能器件300集成于显示面板200的下方的情况下，若显示面板200的透光率较低，则会影响显示面板200下方的功能器件300的感光；若显示面板200的反射率较高，则会影响显示面板200的显示效果。
基于此，在一些相关技术中，显示面板的出光侧设有偏光片，以降低外界环境光在显示面板上的反射强度；但是，显示面板所发出的光经过偏光片之后会损失50％～60％，即该偏光片会大大降低显示装置的透过率，导致显示装置的功耗增大，且影响显示面板下方的摄像头的感光。并且，由于像素电路的部分边缘未被第一电极遮挡，外界环境光在被该部分边缘反射后，会产生严重的衍射现象，导致功能器件的感光度下降。
在另一些相关技术中，显示面板的出光侧设有彩色滤光层取代偏光片。但是，相较于在的显示面板的出光侧设置偏光片，外界环境光在显示面板上的反射强度仍然较大；特别是在摄像头区域，为保证功能器件的感光，摄像头区域无法采用遮光层全面覆盖子像素之间的区域，功能器件设置区的反射强度过大，影响显示效果；并且，由于像素电路的部分边缘未被第一电极遮挡，外界环境光在被该部分边缘反射后，会产生严重的衍射现象，导致功能器件的感光度下降。
基于此，本公开的一些实施例提供的显示面板200，参阅图6C和图6D，显示面板200还包括多个第一遮光部15。
需要说明的是，为了区分功能器件设置区A1和主显示区A2的像素单元P、子像素P、发光器件12和像素电路13，在本文中，将位于功能器件设置区A1的像素单元P、子像素P＇、发光器件12和像素电路13分别称为第一像素单元P1、第一子像素P1＇、第一发光器件124和第一像素电路135，以及将位于主显示区A2的像素单元P、子像素P＇、发光器件12和像素电路13分别称为第二像素单元P2、第二子像素P2＇、第二发光器件125和第二像素电路136。
图6A～图6D为根据一些实施例的显示面板的功能器件设置区的俯视图；图7为根据一些实施例的显示面板的第一遮光部的结构图；图8为根据一些实施例的显示面板的功能器件设置区的一个像素单元的放大图。
如图6A～图6D所示，多个第一遮光部15间隔设置于多个第一发光器件124远离衬底11的一侧，且位于功能器件设置区A1。如图6B、图6C和图7所示，每个第一遮光部15设置有多个第一开口区151，每个第一开口区151 对应一个第一发光器件124，且第一发光器件124的发光区位于对应的第一开口区151内。
其中，参见图6A～图6D，第一像素电路135的第一部分在衬底11上的正投影，位于第一遮光部135在衬底11的正投影范围内。第一部分为第一像素电路135在衬底11上的正投影位于第一电极121在衬底11上的正投影范围之外的部分。
在这种情况下，在功能器件设置区A1，第一像素电路135的第一部分在衬底11上的正投影，位于第一遮光部135在衬底11的正投影范围内。也就是说，第一像素电路135在衬底11的正投影，位于第一电极121和第一遮光部135在衬底11的正投影范围内，这样可以避免外界环境光直接照射在第一像素电路135上，降低外界环境光在显示面板200的功能器件设置区A1的反射强度，以及解决外界环境光直接照射在第一像素电路135的边缘而产生的衍射现象，提高功能器件300的感光度。并且，第一像素电路135的晶体管130(例如第一晶体管T1)的沟道区S，均可以被第一电极121和第一遮光部135遮挡，进而降低该晶体管130的阈值电压产生漂移的风险，提高驱动电流的准确度，提升显示面板200的功能器件设置区A1的显示效果。
在一些实施例中，如图6B、图6C和图7所示，每个第一遮光部15对应一个第一像素单元P1，即每个第一遮光部15的多个第一开口区151与同一个第一像素单元P1的多个第一子像素P1＇一一对应。这样的话，第一遮光部15对每个第一像素单元P1的遮挡面积一致，可以避免多个第一像素单元P1的透光的面积不一致而导致亮度不均一或色偏的问题，从而提高显示面板200的功能器件设置区A1的显示效果。
可以理解的是，为了缩减第一遮光部15的面积，降低第一遮光部15对显示面板200的功能器件设置区A1的透过率的影响，如图6B和图6C所示，位于同一个第一遮光部15的外边界内的多个第一子像素P1＇中，在设定方向上相邻的两个第一子像素P1＇的中心之间的距离为第一距离L1。在设定方向上，位于相邻两个第一遮光部15的外边界内且相邻的两个第一子像素P1＇的中心之间的距离为第二距离L2。其中，第一距离L1小于第二距离L2。图6C中以设定方向为第一方向X为例进行示意。
需要说明的是，为了提高显示面板200的功能器件设置区A1的透过率，在功能器件设置区A1的第一像素电路135进行紧缩设计。如图6A和图6B所示，在功能器件设置区A1，第一像素电路135的排列方式与第一发光器件124的排列方式相似。这样的话，第一像素电路135与第一发光器件124几何 中心大致重合。基于此，上述第一子像素P1＇的中心，可以指的是第一子像素P1＇的第一发光器件124的发光区的中心。
上述设定方向可以为任意相邻的两个第一子像素P1＇的排列方向。
在这种情况下，由于第一遮光部15所需要遮挡的多个第一子像素P1＇之间的距离缩减，因此，第一遮光部15的面积可以相应的缩减，以提高显示面板200的功能器件设置区A1的透过率；此外，相邻的第一遮光部15之间的间距较大，可以降低制作第一遮光部15的工艺难度。
在一些实施例中，参阅图6B、图6C和图6D，多个第一子像素P1＇包括多个红色子像素R、多个第一绿色子像素G1、多个第二绿色子像素G2和多个蓝色子像素B。多个红色子像素R和多个第一绿色子像素G1沿第一斜方向Z1交替排列，并和多个第二绿色子像素G2沿第二斜方向Z2交替排列；蓝色子像素B和第二绿色子像素G2沿第一斜方向Z1交替排列，并和多个第一绿色子像素G1沿第二斜方向Z2交替排列；且第一绿色子像素G1和第二绿色子像素G2沿第一方向X交替排列，红色子像素R和蓝色子像素B沿第二方向Y交替排列。
其中，第一方向X与第二方向Y大致垂直，第一斜方向Z1和第二斜方向Z2相交叉，且第一斜方向Z1和第二斜方向Z2均与第一方向X相交叉，以及第一斜方向Z1和第二斜方向Z2均与第二方向Y相交叉。
需要说明的是，第一斜方向Z1与第一方向X的夹角可以大致为40°～50°，且第一斜方向Z1和第二方向Y的夹角可以大致为40°～50°；第二斜方向Z2与第一方向X的夹角可以大致为130°～140°，且第二斜方向Z1和第二方向Y的夹角可以大致为40°～50°。
此时，上述设定方向可以为第一方向X、第二方向Y、第一斜方向Z1和第二斜方向Z2中的至少一者。例如，设定方向包括第一方向X、第二方向Y、第一斜方向Z1和第二斜方向Z2。也就是说，在每个第一遮光部15对应一个第一像素单元P1的情况下，位于同一个第一像素单元P1内的多个第一子像素P1＇之间的距离相互拉近。
在此基础上，参阅图6B和图6D，每个第一像素单元P1可以包括相邻的一个红色子像素R、一个第一绿色子像素G1、一个第二绿色子像素G2和一个蓝色子像素B。即4个第一子像素P1＇构成一个最小重复单元。其中，在同一个第一像素单元P1中，红色子像素R和蓝色子像素B沿第二方向Y排列，第一绿色子像素G1和第二绿色子像素G2沿第一方向X排列。
此时，第一遮光部15的外边界的形状可以大致为菱形，菱形的两条对角 线分别与第一方向X和第二方向Y大致平行。
需要说明的是，在本文中，“大致为菱形”是指，形状整体上呈菱形，但是并不局限为标准的菱形。即，这里的“菱形”不但包括基本菱形的形状，而且考虑到工艺条件，还包括类似于菱形的形状。例如，菱形的拐角处为弯曲状，即拐角处平滑。
在一些实施例中，参阅图6B，第一像素单元P1排列成多行多列，每行包括沿第一方向X排列的多个第一像素单元P1，每列包括沿第二方向Y排列的多个第一像素单元P1。在此基础上，参阅图6C，多个第一遮光部15排列成多行多列，每行包括沿第一方向X排列的多个第一遮光部15，每列包括沿第二方向Y排列的多个第一遮光部15。
此外，参阅图6B，相邻两行中的多个第一像素单元P1可以相互错开设置，相邻的两列中的多个第一像素单元P1可以相互错开设置，以使得第一像素单元P1的排列更加紧凑，提升显示效果好。在此基础上，参阅图6C，相邻两行中的多个第一遮光部15可以相互错开设置，相邻的两列中的多个第一遮光部15可以相互错开设置。
在一些实施例中，如图3A、图3B和图6B所示，显示面板200还包括第二电极层1230，第二电极层123包括发光器件12的第二电极123，第二电极层1230设置于第一电极121和第一遮光部15之间。
其中，第二电极层1230位于功能器件设置区A1的部分设有多个第二开口区1231，多个第二开口区1231在衬底11上的正投影，位于多个第一遮光部15在衬底11(参见图6A)上的正投影之间的区域，这样可以减小第二电极层1230位于多个第一遮光部15之间的区域的面积，减少被第二电极层1230反射的外界环境光，进一步地降低外界环境光在显示面板200的功能器件设置区A1的反射强度。
可以理解的是，第二开口区1231可以设置在任意相邻的两个第一遮光部15之间。示例性地，在多个第一遮光部15排列成多行多列，每行包括沿第一方向X排列的多个第一遮光部15，每列包括沿第二方向Y排列的多个第一遮光部15的情况下，第二开口区1231可以设置于在第一方向X上相邻的两个第一遮光部15之间，第二开口区1231还可以设置于在第二方向Y上相邻的两个第一遮光部15之间。
其中，如图6C所示，在相邻两行中的多个第一遮光部15相互错开设置，相邻的两列中的多个第一遮光部15相互错开设置，且第一遮光部15的外边界的形状大致为菱形的情况下，第二开口区1231位于在第一方向X上相邻的 两个第一遮光部15之间，且位于第二方向Y上相邻的两个第一遮光部15之间。此时，在第一方向X上相邻的两个第一遮光部15，以及在第二方向Y上相邻的两个第一遮光部15之间的区域面积较大，图案化第二电极层1230的工艺难度较低，即便于在第二电极层1230开设第二开口区1231。
这里，第二开口区1231的形状大致为圆形或椭圆形。应理解，圆形或椭圆形的形状，可以使第二开口区1231的面积设置的比较大，即可以减小第一遮光部15之间第二电极层1230的面积，从而降低外界环境光在显示面板200的功能器件设置区A1的反射强度。
需要说明的是，在本文中，“大致为圆形或椭圆形”是指，形状整体上呈圆形或椭圆形，但是并不局限为标准的圆形或椭圆形。即，这里的“圆形或椭圆形”不但包括基本菱形的形状，而且考虑到工艺条件，还包括类似于圆形或椭圆形的形状；例如，圆形或椭圆形的部分边界为直线。
可以理解的是，参阅图6B，第一子像素P1＇的第一发光器件124可以被配置为发射白色光线，也可以被配置为发射彩色光线。
示例性地，参阅图6C，第一子像素P1＇的第一发光器件124被配置为发射彩色光线，彩色光线直接射向显示面板200的外侧。
例如，如图6C所示，多个第一子像素P1＇包括红色子像素R、第一绿色子像素G1、第二绿色子像素G2和蓝色子像素B，红色子像素R的第一发光器件124被配置为发射红色光线，第一绿色子像素G1和第二绿色子像素G2的第一发光器件124被配置为发射绿色光线，蓝色子像素B的第一发光器件124被配置为发射蓝色光线，以实现彩色显示。
示例性地，如图6C和图6D所示，第一子像素P1＇的第一发光器件124被配置为发射白色光线。此时，第一子像素P1＇还包括多个第一滤光部21，如图6D、图7和图8所示，每个第一滤光部21对应一个第一开口区151，且第一滤光部21在衬底11(参见图6A)上的正投影的边界S1，位于对应的第一遮光部15在衬底11(参见图6A)上的正投影的范围内，以对第一发光器件124光进行过滤，以及避免第一遮光部15对功能器件300(参见图2)的采光造成干扰。其中，多个第一滤光部21可以分别透射多种单色光，第一子像素P1＇的第一发光器件124发射的白色光线，照射在对应的第一滤光部21上以出射对应颜色的单色光，以实现全彩化显示。
例如，如图6C和图6D所示，多个第一子像素P1＇包括红色子像素R、第一绿色子像素G1、第二绿色子像素G2和蓝色子像素B，红色子像素R的第一滤光部21可以透射红光，第一绿色子像素G1和第二绿色子像素G2的 第一滤光部21可以透射绿光，蓝色子像素B的第一滤光部21可以透射蓝光。此时，红色子像素R、第一绿色子像素G1、第二绿色子像素G2和蓝色子像素B的第一发光器件124发射的白色光线，照射在对应的第一滤光部21上以出射对应颜色的单色光，从而实现全彩化显示。
此外，由于第一滤光部21透射单色光，因此，第一滤光部21可以滤去外界环境光中的大部分波段的光，从而可以进一步地降低外界环境光在显示面板200的功能器件设置区A1的反射强度。
图9A～图9D为根据一些实施例的显示面板的主显示区的俯视图；图10A为根据一些实施例的显示面板的第二遮光部的结构图；图10B为根据一些实施例的显示面板的主显示区的一个红色子像素的放大图。
如图9A～图9D所示，显示面板200还包括位于主显示区A2的第二遮光部16，第二遮光部16设置于多个第二子像素P2＇远离衬底11的一侧。
需要说明的是，第一遮光部15与第二遮光部16的材料可以相同且同层设置。
参阅图9B、图9C和图10A，第二遮光部16包括多个第三开口区161，每个第三开口区161对应一个第二发光器件125，且第二发光器件125的发光区位于对应的第三开口区161内。
其中，参阅图9A～图9D，第二像素电路136的第二部分在衬底11上的正投影，位于第二遮光部16在衬底11的正投影范围内。第二部分为第二像素电路136在衬底11上的正投影，位于第三电极121在衬底11上的正投影范围之外的部分。
需要说明的是，为了将第二发光器件125的第一电极121与第一发光器件124的第一电极121进行区分，在本文中，将第二发光器件125的第一电极121称为第三电极121，即第二发光器件125包括第三电极121，第三电极121与第二像素电路136电连接。
在这种情况下，在主显示区A2，第二像素电路136的第二部分在衬底11上的正投影，位于第二遮光部136在衬底11的正投影范围内。也就是说，第二像素电路136在衬底11的正投影，位于第三电极121和第二遮光部136在衬底11的正投影范围内，这样可以避免外界环境光直接照射在第二像素电路136上，降低外界环境光在显示面板200的主显示区A2的反射强度，以及避免外界环境光直接照射在第二像素电路136的边缘而产生的衍射现象，提高显示效果。并且，第二像素电路136的晶体管130(例如第一晶体管T1)的沟道区S，均可以被第三电极121和第二遮光部136遮挡，进而降低该晶体管 130的阈值电压产生漂移的风险，提高驱动电流的准确度，提升显示面板200的主显示区A2的显示效果。
应理解，显示面板200的主显示区A2仅用于显示图像，无需采集外界环境光，也即在显示面板200的主显示区A2，无需考虑第二子像素P2＇之间的区域的透光率，外界环境光的反射强度越低，显示效果越好。
基于此，参阅图9A～图9D，第二遮光部16在衬底11上的正投影覆盖第一区域，第一区域为主显示区A2中多个第二发光器件125之间的区域。在这种情况下，多个第二发光器件125之间的区域的金属层(例如，第二电极层1230)均可被第二遮光部16遮挡，从而可以降低外界环境光在显示面板200的主显示区A2的反射强度，提升主显示区A2的显示效果。
在此基础上，第二电极层1230位于主显示区A2的部分可以为连续的膜层结构，即第二电极层1230位于主显示区A2的部分可以不进行图案化工艺，即第二电极层1230位于多个第二子像素P2＇之间的区域可以不开设透光孔，工艺简单。
此外，由于第二遮光部16在衬底11上的正投影覆盖第一区域，即覆盖第二子像素P2＇的第二发光器件125之间的区域，同一第二像素单元P2的多个第二子像素P2＇的第二发光器件125的中心的距离无需进行缩减，即多个第二发光器件125的均匀排列。
示例性地，参阅图9A～图9D，在主显示区A2,多个红色子像素R和多个第一绿色子像素G1沿第一斜方向Z1交替排列，并和多个第二绿色子像素G2沿第二斜方向Z2交替排列；蓝色子像素B和第二绿色子像素G2沿第一斜方向Z1交替排列，并和多个第一绿色子像素G1沿第二斜方向Z2交替排列；且第一绿色子像素G1和第二绿色子像素G2沿第一方向X交替排列，红色子像素R和蓝色子像素B沿第二方向Y交替排列。
在此基础上，在设定方向上任意相邻的两个第二子像素P2＇的第二发光器件125的中心之间的距离大致相等。其中，设定方向可以为第一方向X、第二方向Y、第一斜方向Z1和第二斜方向Z2中的至少一者。
可以理解的是，参阅图9B，第二子像素P2＇的第二发光器件125可以被配置为发射白色光线，也可以被配置为发射彩色光线。
示例性地，参阅图9C，第二子像素P2＇的第二发光器件125被配置为发射彩色光线，彩色光线直接射向显示面板200的外侧。
例如，如图9C所示，多个第二子像素P2＇包括红色子像素R、第一绿色子像素G1、第二绿色子像素G2和蓝色子像素B，红色子像素R的第二发光 器件125被配置为发射红色光线，第一绿色子像素G1和第二绿色子像素G2的第二发光器件125被配置为发射绿色光线，蓝色子像素B的第二发光器件125被配置为发射蓝色光线，以实现彩色显示。
示例性地，如图9C和图9D所示，第二子像素P2＇的第二发光器件125被配置为发射白色光线。此时，第二子像素P2＇还包括多个第二滤光部22，参见图9D、图10A和图10B，每个第二滤光部22对应一个第三开口161，且第二滤光部22在衬底11上的正投影的边界S1，位于第二遮光部16在衬底11(参见图9A)上的正投影的范围内，以对第二发光器件125光进行过滤。其中，多个第二滤光部22可以分别透射多种单色光，第二子像素P2＇的第二发光器件125发射的白色光线，照射在对应的第二滤光部22上以出射对应颜色的单色光，以实现全彩化显示。
例如，如图9C和图9D所示，多个第二子像素P2＇包括红色子像素R、第一绿色子像素G1、第二绿色子像素G2和蓝色子像素B，红色子像素R的第二滤光部22可以透射红光，第一绿色子像素G1和第二绿色子像素G2的第二滤光部22可以透射绿光，蓝色子像素B的第二滤光部22可以透射蓝光。此时，红色子像素R、第一绿色子像素G1、第二绿色子像素G2和蓝色子像素B的第二发光器件125发射的白色光线，照射在对应的第二滤光部22上以出射对应颜色的单色光，从而实现全彩化显示。
此外，由于第二滤光部22透射单色光，因此，第二滤光部22可以滤去外界环境光中的大部分波段的光，从而可以进一步地降低外界环境光在显示面板200的主显示区A2的反射强度。
参阅图6B、6C、9B和图9C，上述多个第一子像素P1＇和多个第二子像素P2＇均包括红色子像素R、第一绿色子像素G1、第二绿色子像素G2和蓝色子像素B。
在此基础上，结合图8，在功能器件设置区A1，红色子像素R、第一绿色子像素G1、第二绿色子像素G2和蓝色子像素B的发光区的边界S2与第一遮光部15的内边界S3的距离大致相等，以避免功能器件设置区A1产生亮度不均一或色偏的问题，从而提高显示面板200的功能器件设置区A1的显示效果。
结合图10B，在主显示区A2，红色子像素R、第一绿色子像素G1、第二绿色子像素G2和蓝色子像素B的发光区的边界S2与第二遮光部16的内边界S3的距离大致相等，以避免主显示区A2产生亮度不均一或色偏的问题，从而提高显示面板200的主显示区A2的显示效果。图10B中以红色子像素R 为例进行示意。
在此基础上，在功能器件设置区A1的第一子像素P1＇的发光区的边界S2与第一遮光部15的内边界S3的距离大致等于，在主显示区A2的第二子像素P2＇的发光区的边界S2与第二遮光部16的内边界S3的距离，以避免功能器件设置区A1与主显示区A2之间产生亮度不均一或色偏的问题，从而提高显示面板200的显示效果。
需要说明的是，在本文中，发光区的边界S2即像素界定层14的开口区的边界。
应理解，参阅图3A、图6A、图6E和图24，上述显示面板10还包括多条信号线，多条信号线均与像素电路13(包括第一像素电路135和第二像素电路136)电连接。其中，至少一条信号线包括用于外接信号源的信号走线以及与第一像素电路135连接的转接线，信号走线中位于功能器件设置区A1的部分透明，以提高显示面板200的功能器件设置区A1的透过率。
示例性地，参阅图3A、图12和图16，上述多条信号线包括扫描信号线GL、复位信号线RL、使能信号线EL、初始化信号线INL、第一电压信号线VDL和数据线DL。
其中，扫描信号线GL与像素电路13的扫描信号端GATE电连接，复位信号线RL与像素电路13的复位信号端RESET电连接，使能信号线EL与像素电路13的使能信号端EM电连接，初始化信号线INL与像素电路13的初始化信号端电连接，第一电压信号线VDL与像素电路13的第一电压信号端VDD电连接，数据线DL与像素电路13的数据信号端DATA电连接。
在一些实施例中，参阅图6E、图12、图17和图19，扫描信号线GL包括第一扫描走线GL1和第一转接线GL2，第一转接线GL2大致沿第一方向X延伸，且与第一像素电路135电连接；第一扫描走线GL1的一端伸入功能器件设置区A1且与第一转接线GL2电连接，以避免扫描信号线GL与其他信号线(例如数据线DATA)的走线排布产生交叉干扰。
在此基础上，在功能器件设置区A1，第一扫描走线GL1位于功能器件设置区A1的部分透明，以提高显示面板200的功能器件设置区A1的透过率。
示例性地，如图15和图19所示，第一扫描走线GL1包括第一子扫描走线GL11和第二子扫描走线GL12，第一子扫描走线GL11位于功能器件设置区A1，第二子扫描走线GL12位于主显示区A2。其中，第一子扫描走线GL11透明，第二子扫描走线GL12可以透明也可以不透明。
在一些实施例中，参阅图6E、图12、图15和图19，复位信号线RL包 括第一复位走线RL1和第二转接线RL2。第二转接线RL2大致沿第一方向X延伸，且与第一像素电路135电连接。第一复位走线RL1的一端伸入功能器件设置区A1，与第二转接线RL2电连接，以避免复位信号线RL与其他信号线(例如数据线DATA)的走线排布产生交叉干扰。
在此基础上，在功能器件设置区A1，第一复位走线RL1位于功能器件设置区A1的部分透明，以提高显示面板200的功能器件设置区A1的透过率。
示例性地，如图15和图19所示，第一复位走线RL1包括第一子复位走线RL11和第二子复位走线RL12，第一子复位走线RL11位于功能器件设置区A1，第二子复位走线RL12位于主显示区A2。其中，第一子复位走线RL11透明，第二子复位走线RL12可以透明也可以不透明。
在一些实施例中，参阅图6E、图12、图15和图19，使能信号线EL包括第一使能走线EL1和第三转接线EL2。第三转接线EL2大致沿第一方向X延伸，且与第一像素电路135电连接。第一使能走线EL1的一端伸入功能器件设置区A1，与第三转接线EL2电连接，以避免使能信号线EL与其他信号线(例如数据线DATA)的走线排布产生交叉干扰。
在此基础上，在功能器件设置区A1，第一使能走线EL1位于功能器件设置区A1的部分透明，以提高显示面板200的功能器件设置区A1的透过率。
示例性地，如图15和图19所示，第一使能走线EL1包括第一子使能走线EL11和第二子使能走线EL12，第一子使能走线EL11位于功能器件设置区A1，第二子使能走线EL12位于主显示区A2。其中，第一子使能走线EL11透明，第二子使能走线EL12可以透明也可以不透明。
在一些实施例中，参阅图6E、图13、图15和图20，初始化信号线INL包括第一初始化走线INL1和第四转接线INL2。第四转接线INL2大致沿第一方向X延伸，且与第一像素电路电135连接，第一初始化走线INL1的一端伸入功能器件设置区A1，与第四转接线INL2电连接,以避免初始化信号线INL与其他信号线(例如数据线DATA)的走线排布产生交叉干扰。
在此基础上，在功能器件设置区A1，第一初始化走线INL1位于功能器件设置区A1的部分透明，以提高显示面板200的功能器件设置区A1的透过率。
示例性地，如图15和图20所示，第一初始化走线INL1包括第一子初始化走线INL11和第二子初始化走线INL12，第一子初始化走线INL11位于功能器件设置区A1，第二子初始化走线INL12位于主显示区A2。其中，第一子初始化走线INL11透明，第二子初始化走线INL12可以透明也可以不透明。
在一些实施例中，参阅图6E、图16和图23，第一电压信号线VDL和数据线DL大致沿第二方向Y延伸。其中，在功能器件设置区A1，第一电压信号线VDL和数据线DL位于功能器件设置区A1的至少部分透明，以提高显示面板200的功能器件设置区A1的透过率。
示例性地，如图6E、图16和图23所示，第一电压信号线VDL包括第一电压走线VDL1和第五转接线VDL2。第五转接线VDL2设置于第一像素电路135远离衬底11的一侧，且与第一电压走线VDL1电连接。也就是说，第五转接线VDL2跨过第一像素电路135(参见图6A)的上方。在这种情况下，第一电压信号线VDL在经过第一像素电路135(参见图6A)的上方时，可以通过第五转接线VDL2拉远与第一像素电路135(参见图6A)的距离，从而降低电磁干扰。
在此基础上，如图16和图23所示，第一电压走线VDL1还可以包括第一子电压走线VDL11和第二子电压走线VDL12，第一子电压走线VDL11位于功能器件设置区A1，第二子电压走线VDL12位于主显示区A2。数据线DL包括第一子数据线DL1和第二子数据线DL2，第一子数据线DL1位于功能器件设置区A1，第二子数据线DL2位于主显示区A2。其中，第一子电压走线VDL11和第一子数据线DL1均可以为透明的。
以下结合显示基板10的膜层结构，对各个膜层所包括的信号线以及部分其他图案膜层进行示例性地介绍。
如图17和图24所示，沿垂直于衬底11且远离衬底11的方向，显示基板10依次包括半导体层ACT、第一栅导电层GT1、第二栅导电层GT2、第一源漏导电层SD1、透明导电层TC和第二源漏导电层SD2。
需要说明的是，半导体层ACT、第一栅导电层GT1、第二栅导电层GT2、第一源漏导电层SD1、透明导电层TC和第二源漏导电层SD2中，每相邻的两层之间均设有绝缘膜层，例如，参阅图3A和图3B，第一栅绝缘层GI1、第二栅绝缘层GI2、层间绝缘层ILD、第一平坦层PLN1、第二平坦层PLN2和第三平坦层PLN3等，本公开实施例在此不做具体限定。
如图3A、图3B、图11和图18所示，半导体层ACT包括像素电路13的各个晶体管130的沟道区S以及源极131(图11和图18中未示意出)和漏极132(图11和图18中未示意出)。
需要说明的是，半导体层ACT的材料包括非晶硅、单晶硅、多晶硅、或金属氧化物半导体材料。例如，半导体层ACT的材料包括铟镓锌氧化物和/或氧化锌，本公开实施例不限于此。
如图12和图19所示，第一栅导电层GT1包括第一转接线GL2、第二转接线RL2、第三转接线EL2、第二子扫描走线GL12、第二子复位走线RL12、第二子使能走线EL12和存储电容器C的第一极板C1，也即第一转接线GL2、第二转接线RL2、第三转接线EL2、第二子扫描走线GL12、第二子复位走线RL12、第二子使能走线EL12和存储电容器C的第一极板C1同层设置，均位于第一栅导电层GT1。
需要说明的是，第一栅导电层GT1的材料包括金属。例如，第一栅导电层GT1的材料包括铝、铜、钼中的至少一种，本公开实施例不限于此。也就是说，第一转接线GL2、第二转接线RL2、第三转接线EL2和存储电容器C的第一极板C1的材料包括金属。
其中，参阅图12，第一转接线GL2与半导体层ACT的交叠部分形成第一晶体管T1、第二晶体管T2和第六晶体管T6的控制极。第二转接线RL2与半导体层ACT的交叠部分形成第三晶体管T3的控制极。第三转接线EL2与半导体层的交叠部分形成第四晶体管T4和第五晶体管T5的控制极。位于功能器件设置区A1的存储电容器C的第一极板C1位于第一转接线GL2和第三转接线EL2之间。
此外，参阅图19，第二子复位走线RL12与半导体层ACT交叠部分形成第三晶体管T3和第六晶体管T6的控制极，第二子扫描走线GL12与半导体层交叠部分形成第一晶体管T1和第二晶体管T2的控制极，第二子使能走线EL12与半导体层ACT交叠部分形成第四晶体管T4和第五晶体管T5的控制极。位于主显示A2的存储电容器C的第一极板C1，位于第二子扫描走线GL12和第二子使能走线EL12之间。
如图13和图20所示，第二栅导电层GT2包括第四转接线INL2、第二子初始化走线INL12和存储电容器C的第二极板C2。第二极板C2在衬底11上的正投影，与第一极板在衬底11上的正投影部分交叠。
需要说明的是，第二栅导电层GT2的材料包括金属。例如，第二栅导电层GT2的材料包括铝、铜、钼中的至少一种，本公开实施例不限于此。
其中，参阅图13和图20，第二极板C2在衬底11上的正投影，与第一极板C1在衬底11上的正投影交叠的部分形成存储电容器C。第四转接线INL2通过连接线与第一像素电路135中的第三晶体管T3和第六晶体管T6电连接；第二子初始化走线INL12通过连接线与第二像素电路136中的第三晶体管T3和第六晶体管T6电连接。
在一些实施例中，参阅图20和图21，第二栅导电层GT2还包括位于主 显示区A2的屏蔽图案40，屏蔽图案40位于第二子复位走线RL12和第二子扫描走线GL12之间。其中，屏蔽图案40在衬底11的正投影，与第二子电压走线VDL12在衬底11的正投影至少部分交叠，且屏蔽图案40与第二子电压走线VDL12电连接，以降低各个走线之间的电磁干扰。
如图14和图21所示，第一源漏导电层SD1包括第一连接线50、第二连接线60、第三连接线70、第四连接线80和第二子电压走线VDL12。其中，第一连接线50、第二连接线60在功能器件设置区A1和主显示区A2均有分布，第三连接线70和第四连接线80仅分布于功能器件设置区A1。
需要说明的是，第一源漏导电层SD1的材料包括金属。例如，第一源漏导电层SD1的材料包括铝、铜、钼中的至少一种，本公开实施例不限于此。
在功能器件设置区A1，如图13和图14所示，第一连接线50与第三晶体管T3的第一极、以及第六晶体管T6的第一极电连接。第二连接线60与存储电容器C的第一极板C1、第一晶体管T1的第二极、以及第三晶体管T3的第二极电连接。第三连接线70与存储电容器C的第二极板C2、以及第四晶体管T4的第一极电连接。第四连接线80与第五晶体管T5的第二极、以及第六晶体管T6的第二极电连接。
在主显示区A2，如图20和图21所示，第一连接线50与第三晶体管T3的第一极、以及第六晶体管T6的第一极电连接。第二连接线60与存储电容器C的第一极板C1、第一晶体管T1的第二极、以及第三晶体管T3的第二极电连接。
如图15和图22所示，第一扫描走线GL1、第一复位走线RL1、第一使能走线EL1、第一初始化走线INL1、数据线DL以及第一电压信号线VDL位于功能器件设置区A1的至少部分透明。
示例性地，如图15和图22所示，透明导电层TC包括第一子扫描走线GL11、第一子复位走线RL11、第一子使能走线EL11、第一子初始化走线INL11、第一子电压走线VDL11以及第一子数据线DL1。
需要说明的是，透明导电层TC的材料包括透明导电材料，透明导电材料制备的透明导电层TC的透过率大于或等于60％。例如，透明导电层TC的材料包括氧化铟锡，本公开实施例不限于此。
如图16和图23所示，第五转接线VDL2、第二子数据线DL2均可以位于第二源漏导电层SD2。
需要说明的是，第二源漏导电层SD2的材料包括金属。例如，第二源漏导电层SD2的材料包括铝、铜、钼中的至少一种，本公开实施例不限于此。
此外，参阅图23，第二源漏导电层SD2还可以包括支撑图案90，支撑图案90位于主显示区A2，且与第二子数据线DL2并行设置于第二像素电路136的两侧，以对发光器件12的第一电极121起到支撑平衡的作用。并且，该支撑图案90可以与第二子电压走线VDL12电连接，这样还可以起到降低信号线之间的电磁干扰的作用。
基于上述，像素电路13的焊盘M可以由第一源漏导电层SD1、透明导电层TC和第二源漏导电层SD2中形成的焊盘图案的一层或多层组成。示例性地，焊盘M由第一源漏导电层SD1的焊接图案、透明导电层TC的焊接图案和第二源漏导电层SD2的焊接图案依次叠置形成。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种显示面板，具有功能器件设置区，所述显示面板包括：
    衬底；
    多个第一子像素，设置于所述衬底上，且位于所述功能器件设置区；至少一个第一子像素包括第一像素电路和第一发光器件，所述第一发光器件包括第一电极，所述第一电极与所述第一像素电路电连接；所述第一像素电路在所述衬底上的正投影的部分，位于所述第一电极在所述衬底上的正投影范围之外；
    多个第一遮光部，间隔设置于所述多个第一发光器件远离所述衬底的一侧，且位于所述功能器件设置区；每个第一遮光部设置有多个第一开口区，每个第一开口区对应一个第一发光器件，且所述第一发光器件的发光区位于对应的第一开口区内；其中，所述第一像素电路的第一部分在所述衬底上的正投影，位于所述第一遮光部在所述衬底的正投影范围内；所述第一部分为所述第一像素电路在所述衬底上的正投影位于所述第一电极在所述衬底上的正投影范围之外的部分。
  2. 根据权利要求1所述的显示面板，包括设置于所述功能器件设置区的多个第一像素单元，每个第一像素单元包括多个所述第一子像素；其中，每个所述第一遮光部的多个第一开口区与同一个第一像素单元的多个第一子像素一一对应。
  3. 根据权利要求1或2所述的显示面板，其中，位于同一个第一遮光部的外边界内的多个第一子像素中，在设定方向上相邻的两个第一子像素的中心之间的距离为第一距离；
    在所述设定方向上，位于相邻两个第一遮光部的外边界内且相邻的两个第一子像素的中心之间的距离为第二距离；
    其中，所述第一距离小于所述第二距离。
  4. 根据权利要求3所述的显示面板，其中，所述多个第一子像素包括多个红色子像素、多个第一绿色子像素、多个第二绿色子像素和多个蓝色子像素；
    所述多个红色子像素和所述多个第一绿色子像素沿第一斜方向交替排列，和所述多个第二绿色子像素沿第二斜方向交替排列；所述蓝色子像素和所述第二绿色子像素沿所述第一斜方向交替排列，和所述多个第一绿色子像素沿所述第二斜方向交替排列；且所述第一绿色子像素和所述第二绿色子像素沿第一方向交替排列，所述红色子像素和所述蓝色子像素沿第二方向交替排列；
    其中，所述第一方向与所述第二方向大致垂直，所述第一斜方向和所述 第二斜方向相交叉，且所述第一斜方向和所述第二斜方向均与所述第一方向相交叉，以及所述第一斜方向和所述第二斜方向均与所述第二方向相交叉。
  5. 根据权利要求4所述的显示面板，其中，所述设定方向为所述第一方向、所述第二方向、所述第一斜方向和所述第二斜方向中的至少一者。
  6. 根据权利要求4或5所述的显示面板，包括多个第一像素单元，每个第一像素单元包括相邻的一个红色子像素、一个第一绿色子像素、一个第二绿色子像素和一个蓝色子像素；
    在同一个第一像素单元中，所述红色子像素和所述蓝色子像素沿所述第二方向排列，所述第一绿色子像素和所述第二绿色子像素沿所述第一方向排列；
    所述第一遮光部在所述衬底的正投影的外边界大致为菱形。
  7. 根据权利要求1～6中任一项所述的显示面板，其中，所述多个第一遮光部排列成多行多列，每行包括沿第一方向排列的多个第一遮光部，每列包括沿第二方向排列的多个第一遮光部；所述第一方向与所述第二方向大致垂直。
  8. 根据权利要求1～7中任一项所述的显示面板，还包括：
    第二电极层，设置于所述第一电极和所述第一遮光部之间；所述第二电极层位于所述功能器件设置区的部分设有多个第二开口区，所述多个第二开口区在所述衬底上的正投影，至少部分位于所述多个第一遮光部在所述衬底上的正投影之间的区域。
  9. 根据权利要求8所述的显示面板，其中，所述多个第一遮光部排列成多行多列，每行包括沿第一方向排列的多个第一遮光部，每列包括沿第二方向排列的多个第一遮光部；所述第一方向与所述第二方向大致垂直；
    所述第二开口区设置于在所述第一方向上相邻的两个第一遮光部之间；和/或，所述第二开口区设置于在第二方向上相邻的两个第一遮光部之间。
  10. 根据权利要求9所述的显示面板，其中，相邻两行中的多个第一遮光部相互错开设置，相邻的两列中的多个第一遮光部相互错开设置。
  11. 根据权利要求8～10中任一项所述的显示面板，其中，所述第二开口区的形状大致为圆形或椭圆形。
  12. 根据权利要求1～11中任一项所述的显示面板，还具有主显示区，所述主显示区至少部分围绕所述功能器件设置区；所述显示面板还包括：
    多个第二子像素，设置于所述衬底上，且位于所述主显示区；每个第二子像素包括第二像素电路和第二发光器件，至少一个第二发光器件包括第三 电极，所述第三电极与所述第二像素电路电连接；所述第二像素电路在所述衬底上的正投影的部分，位于所述第三电极在所述衬底上的正投影范围之外；
    第二遮光部，设置于所述多个第二子像素远离所述衬底的一侧，且位于所述主显示区；所述第二遮光部包括多个第三开口区，每个第三开口区对应一个第二发光器件，且所述第二发光器件的发光区位于对应的第三开口区内；其中，所述多个第二像素电路的第二部分在所述衬底上的正投影，位于所述第二遮光部在所述衬底的正投影范围内；所述第二部分为所述第二像素电路在所述衬底上的正投影，位于所述第三电极在所述衬底上的正投影范围之外的部分。
  13. 根据权利要求12所述的显示面板，其中，所述第二遮光部在所述衬底上的正投影覆盖第一区域，所述第一区域为所述主显示区中所述多个第二发光器件之间的区域。
  14. 根据权利要求12或13所述的显示面板，其中，所述第二电极层位于所述主显示区的部分为连续的膜层结构。
  15. 根据权利要求12～14中任一项所述的显示面板，其中，所述第一遮光部与所述第二遮光部的材料相同且同层设置。
  16. 根据权利要求1～15中任一项所述的显示面板，其中，所述第一子像素还包括：
    多个第一滤光部，每个第一滤光部对应一个第一开口区，且所述第一滤光部在所述衬底上的正投影的边界，位于对应的第一遮光部在所述衬底上的正投影的范围内；
    在所述显示面板还包括多个第二子像素和第二遮光部的情况下，所述第二子像素还包括：
    多个第二滤光部，每个第二滤光部对应一个第三开口区，且所述第二滤光部在所述衬底上的正投影的边界，位于第二遮光部在所述衬底上的正投影的范围内。
  17. 根据权利要求1～16中任一项所述的显示面板，还包括：
    封装层，设置于所述多个第一遮光部和所述第一发光器件之间。
  18. 根据权利要求1～17中任一项所述的显示面板，还包括：
    多条信号线，与所述第一像素电路电连接；至少一条信号线包括用于外接信号源的信号走线以及与所述第一像素电路连接的转接线，所述信号走线中位于所述功能器件设置区的部分透明。
  19. 根据权利要求18所述的显示面板，所述多条信号线包括：
    扫描信号线，包括第一扫描走线和第一转接线，所述第一转接线大致沿第一方向延伸，且与所述第一像素电路电连接；所述第一扫描走线的一端伸入所述功能器件设置区，与所述第一转接线电连接；所述第一扫描走线位于所述功能器件设置区的部分透明；
    复位信号线，包括第一复位走线和第二转接线；所述第二转接线大致沿所述第一方向延伸，且与所述第一像素电路电连接；所述第一复位走线的一端伸入所述功能器件设置区，与所述第二转接线电连接；所述第一复位走线位于所述功能器件设置区的部分透明；
    使能信号线，包括第一使能走线和第三转接线；所述第三转接线大致沿所述第一方向延伸，且与所述第一像素电路电连接；所述第一使能走线的一端伸入所述功能器件设置区，与所述第三转接线电连接；所述第一使能走线位于所述功能器件设置区的部分透明；
    初始化信号线，包括第一初始化走线和第四转接线；所述第四转接线大致沿所述第一方向延伸，且与所述第一像素电路电连接；所述第一初始化走线的一端伸入所述功能器件设置区，与所述第四转接线电连接；所述第一初始化走线位于所述功能器件设置区的部分透明。
  20. 根据权利要求19所述的显示面板，其中，沿垂直于所述衬底且远离所述衬底的方向，所述显示面板依次包括半导体层、第一栅导电层、第二栅导电层、第一源漏导电层和透明导电层；
    所述第一转接线、所述第二转接线和所述第三转接线位于所述第一栅导电层，所述第四转接线位于所述第二栅导电层；和/或，所述第一扫描走线、所述第一复位走线、所述第一使能走线和所述第一初始化走线中位于所述功能器件设置区的部分位于所述透明导电层。
  21. 根据权利要求18～20中任一项所述的显示面板，所述多条信号线还包括第一电压信号线和数据线，所述第一电压信号线和所述数据线大致沿第二方向延伸，且所述第一电压信号线和所述数据线均与所述第一像素电路电连接；
    所述第一电压信号线和所述数据线中位于所述功能器件设置区的至少部分透明。
  22. 根据权利要求20所述的显示面板，其中，所述第一电压信号线包括第一电压走线和第五转接线，所述第五转接线设置于所述第一像素电路远离所述衬底的一侧，且与所述第一电压走线电连接。
  23. 根据权利要求21所述的显示面板，其中，沿垂直于所述衬底且远离 所述衬底的方向，所述显示基板依次包括半导体层、第一栅导电层、第二栅导电层、第一源漏导电层、透明导电层和第二源漏导电层；
    所述第一电压走线和所述数据线位于所述功能器件设置区的部分位于所述透明导电层，所述第五转接线位于所述第二源漏导电层。
  24. 一种显示装置，包括：
    壳体；
    如权利要求1～23中任一项所述的显示面板，所述显示面板设置于所述壳体内。
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CN114420876A (zh) * 2022-01-28 2022-04-29 武汉天马微电子有限公司 显示面板及显示装置

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