WO2023207291A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023207291A1
WO2023207291A1 PCT/CN2023/077861 CN2023077861W WO2023207291A1 WO 2023207291 A1 WO2023207291 A1 WO 2023207291A1 CN 2023077861 W CN2023077861 W CN 2023077861W WO 2023207291 A1 WO2023207291 A1 WO 2023207291A1
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WO
WIPO (PCT)
Prior art keywords
fan
line
area
lines
display
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PCT/CN2023/077861
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English (en)
French (fr)
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WO2023207291A9 (zh
Inventor
王梦奇
于子阳
蒋志亮
胡明
陈飞
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2023207291A1 publication Critical patent/WO2023207291A1/zh
Publication of WO2023207291A9 publication Critical patent/WO2023207291A9/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • organic light-emitting diode (English full name: Organic Light-Emitting Diode, English abbreviation: OLED) display devices are widely used because of their characteristics of self-illumination, fast response, high contrast, wide viewing angle and can be produced on flexible substrates. application.
  • the OLED display device includes a plurality of sub-pixels.
  • Each sub-pixel includes a pixel driving circuit and a light-emitting device.
  • the pixel driving circuit drives the light-emitting device to emit light, thereby achieving display.
  • a display substrate has a display area and a fan-out area, and the fan-out area is adjacent to one edge of the display area.
  • the display substrate includes: a substrate and a multi-layer conductive layer.
  • the multiple conductive layers are located on the same side of the substrate.
  • the multiple conductive layers are stacked.
  • the multi-layer conductive layer includes: multiple data lines, multiple connection lines and multiple fan-out lines.
  • the plurality of data lines are arranged at intervals along a first direction, and the plurality of data lines all extend along a second direction, and the second direction intersects the first direction; the plurality of data lines include a plurality of first data lines and a plurality of second data lines.
  • the first data lines are located at two edge areas of the display area along the first direction.
  • the second data lines are located at the display area. area along the central area of the first direction.
  • the first end of a connecting line is located in the edge area and is electrically connected to a first data line, and the second end of the connecting line extends to the junction between the central area and the fan-out area; at least One of the connecting lines spans at least one data line and is insulated from the data line it spans; the second end of at least one of the connecting lines is located between two adjacent second data lines.
  • the plurality of fan-out lines are located in the fan-out area; the plurality of fan-out lines include a plurality of first fan-out lines and a plurality of second fan-out lines; wherein the first fan-out lines are electrically connected to the second end of the connecting line.
  • the second fan-out line is electrically connected to an end of the data line that is not electrically connected to the connection line and is close to the fan-out area.
  • the display substrate also has a bending area and a chip mounting area that are sequentially away from the display area;
  • the fan-out area includes a first fan-out area and a second fan-out area, and the first fan-out area is located at the Between the display area and the bending area, the second fan-out area is located between the bending area and the chip mounting area.
  • the first fan-out line includes a transfer line, and the transfer line is located in the second fan-out area; the transfer line spans at least one of the second fan-out lines,
  • the arrangement order of the ends of the plurality of fan-out lines away from the display area along the first direction is the same as the arrangement order of the plurality of data lines along the first direction.
  • the adapter cable includes a main body part and two connecting end parts, and the main body part is located on a side of the two connecting end parts close to the display area.
  • the display substrate further has a circuit testing area located between the bending area and the chip mounting area; the second fan-out area is located between the circuit testing area and the chip mounting area. between.
  • the patch cord is U-shaped or approximately U-shaped.
  • the central axis of the display substrate extending along the second direction is defined as the first central axis; the area of the second fan-out area on one side of the first central axis is a sub-fan-out area; In the sub-fan-out area: a plurality of the transfer lines are arranged in a radial manner; among the two adjacent transfer lines, the outer transfer line is arranged around the inner transfer line.
  • two adjacent transfer lines are located in different conductive layers.
  • the central axis of the display substrate extending along the second direction is defined as the first central axis; the area of the second fan-out area on one side of the first central axis is a sub-fan-out area;
  • the first fan-out line also includes a first wiring segment and a second wiring segment that are sequentially away from the display area and electrically connected to each other; the first wiring segment approaches the display area from from one end to the end far away from the display area, gradually approaching the first central axis; the second wiring segment is parallel to the first central axis; the second fan-out lines include components that are sequentially away from the display area and each other
  • the third wiring segment and the fourth wiring segment are electrically connected; the third wiring segment gradually approaches the first central axis from an end close to the display area to an end far away from the display area; the fourth wiring segment gradually approaches the first central axis;
  • the line segment is parallel to the first central axis; wherein the connection end of the adapter line close to the first central axis
  • a plurality of first wiring segments and a plurality of third wiring segments are alternately arranged; an end of the first wiring segment away from the display area and The fitting straight line defined by the end of the third wiring segment away from the display area gradually approaches the display area from an end away from the first central axis to an end close to the first central axis.
  • the directly adjacent second wiring segments are in the same group, and the second wiring segments in the same group are far away from each other. Ends of the display area are staggered along the first direction.
  • the length of the second wiring segment close to the first central axis is smaller than the length of the second wiring segment far away from the first central axis.
  • the length of the second wiring section of a central axis; among the two adjacent transfer wires, the one close to the first central axis The connection end of the adapter line for connecting to the second wiring segment is opposite to the connection end of the adapter line for connecting to the second wiring segment that is away from the first central axis. part, closer to the display area.
  • the main body part includes a first transfer section; the first transfer section is connected to the connection end of the transfer line that connects to the second wiring section; the first transfer section
  • the orthographic projection of the connection segment on the substrate overlaps or substantially overlaps the orthographic projection of the corresponding connected second trace segment on the substrate.
  • the main body part further includes a second adapter section connected to the first adapter section, and a third adapter section connected to the second adapter section.
  • the multi-layer conductive layer also includes: an isolation block located on a side of the first wiring segment and the third wiring segment away from the substrate, and the isolation block covers the first wiring segment and the The third wiring section; wherein, the transfer line is located on the side of the isolation block away from the substrate; the orthographic projection of the second transfer section on the substrate is located on the side of the isolation block. Within the orthographic projection on the substrate; the orthographic projections of both the first transfer section and the third transfer section on the substrate are located outside the orthographic projection of the isolation block on the substrate .
  • the multi-layer conductive layer includes: at least two gate metal layers and at least two source and drain metal layers.
  • the at least two layers of source and drain metal layers are located on the side of the at least two layers of gate metal layers away from the substrate.
  • the first wiring segment, the second wiring segment, the third wiring segment and the fourth wiring segment are located in the at least two layers of gate metal layers, and the isolation block is located in the at least two layers of source and drain layers.
  • the source and drain metal layers in the metal layer are relatively close to the source and drain metal layers of the substrate, and the transfer lines are located in the at least two source and drain metal layers and are relatively far away from the source and drain metal layers of the substrate.
  • the display device includes: the display panel as described in any of the above embodiments.
  • Figure 1 is a structural diagram of a display device according to some embodiments.
  • Figure 2 is a structural diagram of a display panel according to some embodiments.
  • Figure 3 is a structural diagram of a display substrate according to some embodiments.
  • Figure 4 is a structural diagram of the connection structure between the light-emitting device and the pixel driving circuit in the sub-pixel;
  • Figure 5 is a structural diagram of a display substrate according to other embodiments.
  • Figure 6 is a structural diagram of a display substrate according to still other embodiments.
  • Figure 7 is a structural diagram of a display substrate according to still other embodiments.
  • Figure 8 is a partial structural view of a display substrate according to some embodiments.
  • Figure 9 is a structural diagram of the first gate metal layer, the second gate metal layer and the first source and drain metal layer in Figure 8;
  • Figure 10 is a structural diagram of the second source-drain metal layer and the third source-drain metal layer in Figure 8;
  • Figure 11 is a partial structural diagram of area 001 in Figure 8.
  • Figures 12 to 17 are structural diagrams of each film layer in Figure 11.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • Figure 1 is a structural diagram of a display device according to some embodiments.
  • some embodiments of the present disclosure provide a display device 200 .
  • the display device 200 is a product with an image display function.
  • the display device 200 may be used to display static images, such as pictures or photos.
  • the display device 200 may also be used to display dynamic images, such as videos or game screens.
  • display device 200 may be a laptop computer, mobile phone, wireless device, personal data assistant (PDA), handheld or portable computer, GPS receiver/navigator, camera, MP4 video player, video camera, game control Desks, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and/or displays, camera view displays (e.g., vehicle Displays for rear-view cameras), electronic photos, electronic billboards or signs, projectors, packaging and aesthetic structures (for example, displays for images of a piece of jewelry), etc.
  • PDA personal data assistant
  • GPS receiver/navigator GPS receiver/navigator
  • camera MP4 video player
  • video camera game control Desks
  • watches clocks
  • calculators television monitors
  • flat panel displays flat panel displays
  • computer monitors computer monitors
  • automotive displays e.g., odometer displays, etc.
  • navigators e.g., odometer displays, etc.
  • the display device 200 includes a display panel 210 .
  • the display panel 210 is an organic light-emitting diode display (full English name: Organic Light-Emitting Diode, English abbreviation: OLED) or a quantum dot electroluminescent display (Quantum Dot Light-Emitting Diodes, abbreviated as QLED).
  • the display device 200 may also include an under-screen camera, an under-screen fingerprint recognition sensor, etc., so that the display device can implement multiple different functions such as taking pictures, video recording, fingerprint recognition, or face recognition.
  • Figure 2 is a structural diagram of a display panel according to some embodiments.
  • the display panel 210 includes the display substrate 100 .
  • the display panel 210 may also include other functional film layers 211 located on the display side of the display substrate 100, such as a touch functional layer, an anti-reflective layer, an anti-fingerprint layer, a hardening layer, and a packaging cover, etc.
  • the display panel 210 is enabled to implement different functions.
  • the embodiments of the present disclosure do not further limit other functional film layers 211 of the display panel 210 .
  • An example of the display substrate 100 will be described below.
  • Figure 3 is a structural diagram of a display substrate according to some embodiments.
  • the display substrate 100 includes a plurality of sub-pixels 101 .
  • the plurality of sub-pixels 101 are arranged in multiple columns along the first direction X and in multiple rows along the second direction Y.
  • the first direction X and the second direction Y intersect.
  • the first direction X is perpendicular to the second direction Y.
  • the first direction X is a horizontal direction and the second direction Y is a vertical direction.
  • the sub-pixel 101 is the smallest unit of the display substrate 100 for image display.
  • Each sub-pixel 101 can display a single color, such as red, green or blue.
  • the display substrate 100 may include a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels.
  • red light, green light and blue light of different intensities can be obtained, and at least two of the red light, green light and blue light of different intensities can be superimposed to obtain More colors of light are displayed, thereby realizing full-color display of the display substrate 100 .
  • the display substrate 100 has a display area AA and a fan-out area (English full name: Fanout) BB, and the fan-out area BB is adjacent to one edge of the display area AA.
  • the display area AA is used to display image information, and the plurality of sub-pixels 101 are located in the display area AA of the display substrate 100 .
  • the fan-out area BB is adjacent to one edge of the display area AA, that is, the one edge of the fan-out area BB close to the display area AA coincides with the one edge of the display area AA close to the fan-out area BB.
  • the edges of the fan-out area BB and the edges of the display area AA are separated from each other. This is only for the convenience of showing the display area AA and the fan-out area BB, and does not affect the display area AA and the fan-out area AA. Exit zone BB is further restricted.
  • the fan-out area BB is located on one side of the display area AA along the second direction Y.
  • the fan-out area BB is adjacent to the lower edge of the display area AA. That is, the fan-out area BB is located below the display area AA along the second direction Y. For example, when the display device 200 is used in a state that is perpendicular or approximately perpendicular to the ground, the fan-out area BB is closer to the ground than the display area AA.
  • each sub-pixel 101 includes a light-emitting device 300 and a pixel driving circuit.
  • the pixel driving circuit is electrically connected to the light-emitting device 300 and is used to drive the light-emitting device 300 to emit light.
  • Figure 4 is a schematic diagram of the connection structure between the light-emitting device and the pixel driving circuit in the sub-pixel.
  • the display substrate 100 includes a substrate 102 and a multi-layer conductive layer 103 .
  • Multiple conductive layers 103 are located on the same side of substrate 102 .
  • Multiple conductive layers 103 are stacked.
  • substrate 102 is a flexible material such that display substrate 100 can bend, As a result, the display panel 210 can realize functions such as curved display, folding display, or sliding display. In other examples, substrate 102 is a rigid material.
  • the material of the substrate 102 may be polyimide (English full name: Polyimide, English abbreviation: PI), polycarbonate (English full name: polycarbonate, English abbreviation: PC) or polyvinyl chloride (English full name: polyvinyl chloride). , English abbreviation: PVC) any one.
  • an insulating layer (such as a gate insulating layer and a buffer layer, a passivation layer, an organic layer, etc.) may be disposed between the multi-layer conductive layers 103 to electrically isolate the two adjacent conductive layers 103 . effect.
  • the pixel driving circuit is disposed in the multi-layer conductive layer 103 .
  • the multi-layer conductive layer 103 includes an active film layer 1031 in sequence away from the substrate 102, at least one gate metal layer Gate (such as a first gate metal layer Gate1, a second gate metal layer Gate2 and the third gate metal layer (not shown in the figure, which can be located between the second gate metal layer Gate2 and the first source-drain metal layer SD1)), at least one source-drain metal layer (such as the first source-drain metal layer SD1, the second source-drain metal layer SD2 and the third source-drain metal layer (not shown in the figure, which may be located between the second source-drain metal layer SD2 and the anode layer AND)), etc.
  • gate metal layer Gate such as a first gate metal layer Gate1, a second gate metal layer Gate2 and the third gate metal layer (not shown in the figure, which can be located between the second gate metal layer Gate2 and the first source-drain metal layer SD1
  • source-drain metal layer such as
  • any gate metal layer Gate may include molybdenum material.
  • Any source-drain metal layer may include a titanium/aluminum/titanium composite laminate structure.
  • the pixel driving circuit includes multiple thin film transistors (English full name: Thin Film Transistor, English abbreviation: TFT) and at least one capacitor.
  • the active film layer 1031 and the first gate metal layer Gate1 can be used to form a part of the plurality of thin film transistors (one, two or more).
  • the active film layer 1031 and the second gate metal layer Gate2 may be used to form another portion of the plurality of thin film transistors (one, two, or more).
  • the first gate metal layer Gate1 and the second gate metal layer Gate2 may be used to form at least one capacitor.
  • the number of active film layers 1031 is not limited here.
  • some embodiments of the present disclosure may include only one active film layer 1031 , and the material of the active film layer 1031 may include metal. Oxides may also include low temperature polysilicon.
  • some embodiments of the present disclosure may further include two active film layers 1031 , wherein the material of one active film layer 1031 includes metal oxide, and the material of the other active film layer includes low-temperature polysilicon.
  • the display substrate 100 further includes a light-emitting device 300, and the pixel driving circuit is electrically connected to the light-emitting device 300.
  • the pixel driving circuit is electrically connected to the light-emitting device 300.
  • the light emitting device 300 is located on a side of the multi-layer conductive layer 103 away from the substrate 102 .
  • the light-emitting device 300 includes an anode layer AND, a light-emitting layer EML, and a cathode layer CTD that are sequentially arranged in a direction away from the substrate 102 .
  • the light-emitting layer EML includes a plurality of effective light-emitting parts arranged at intervals. It can be understood that the effective light-emitting parts are used to emit light.
  • the effective light-emitting part includes electroluminescent material. Understandably, electroluminescence refers to the phenomenon in which organic semiconductor materials, driven by an electric field, form excitons through carrier injection, transport, combination of electrons and holes, and then radiative recombination leads to luminescence.
  • one part of the multiple effective light-emitting parts is used to emit red light, another part is used to emit green light, and another part is used to emit blue light.
  • different electroluminescent materials can be selected so that the effective light-emitting part can emit light of different colors. It can be understood that the number of the effective light-emitting parts that emit red light, the effective light-emitting parts that emit green light, and the effective light-emitting parts that emit blue light may be the same or different.
  • the effective light-emitting parts that emit red light, the effective light-emitting parts that emit green light, and the effective light-emitting parts that emit blue light can be arranged in a mixed array.
  • the luminous intensity of the effective light-emitting parts that emit different colors we can obtain Different intensities of red, green and blue light.
  • the display substrate 100 can display a color image.
  • the pixel driving circuit can drive the light-emitting layer EML to emit light.
  • a pixel driving circuit is electrically connected to an effective light-emitting part through the anode layer AND, so that each pixel driving circuit can provide driving current to each effective light-emitting part through the anode layer AND, that is, multiple effective light-emitting parts can be provided.
  • Each part emits light independently, thereby reducing mutual interference between multiple effective light-emitting parts and improving the display effect of the display substrate 100 .
  • the size of the driving current provided by the pixel driving circuit to the effective light-emitting part the light-emitting brightness of the effective light-emitting part can be adjusted.
  • the anode layer AND is a metal material, such as copper or silver.
  • the cathode layer CTD is a transparent material, such as transparent indium tin oxide (English full name: Indium Tin Oxide, English abbreviation: ITO) or transparent indium zinc oxide (English full name: Indium Zinc Oxide, English abbreviation: IZO), etc., so that the effective light-emitting part emits The light can be emitted through the cathode layer CTD, that is, the display substrate 100 is a top-emitting display substrate at this time.
  • the anode layer AND is a transparent material, such as ITO or IZO
  • the cathode layer CTD is a metal material, such as copper or silver, so that the light emitted by the effective light-emitting part can be emitted through the anode layer AND, that is, the display is
  • the substrate 100 is a bottom emission display substrate.
  • both the anode layer AND and the cathode layer CTD are made of transparent materials, such as ITO or IZO, so that the light emitted by the effective light-emitting part can be emitted through the anode layer AND and the cathode layer CTD. That is, at this time, the display substrate 100 is double Surface emitting display substrate.
  • the material of the anode layer AND includes ITO, or a stack of ITO-Ag-ITO, so that the anode layer AND can provide more holes.
  • the material of the cathode layer CTD includes MgAg, so that the cathode layer CTD can provide more electrons.
  • the thickness of the cathode layer CTD is very thin and can transmit light, so that the display substrate 100 can achieve top emission.
  • a hole injection layer (English full name: Hole Inject Layer, English abbreviation: HIL) and a hole transport layer are provided between the anode layer AND and the effective light-emitting part.
  • HIL Hole Inject Layer
  • HTL Hole Transport Layer
  • EBL Electron Blocking Layer
  • an electron injection layer (English full name: Electron Inject Layer, English abbreviation: EIL) and an electron transport layer (English full name: Electron Transport Layer) are provided between the cathode layer CTD and the effective light-emitting part.
  • EIL Electron Inject Layer
  • E transport layer English full name: Electron Transport Layer
  • ETL ETL
  • HBL Hole Blocking Layer
  • FIG. 5 is a structural diagram of a display substrate according to other embodiments.
  • the display substrate 100 further includes an encapsulation layer 104 .
  • the encapsulation layer 104 is located on the side of the light-emitting device 300 away from the substrate 102 and can cover the light-emitting device 300 to prevent water vapor and oxygen in the external environment from entering the light-emitting device 300 and protect the light-emitting device 300 role.
  • FIG. 6 is a structural diagram of a display substrate according to further embodiments.
  • the multi-layer conductive layer 103 also includes a plurality of data lines 110 and a plurality of fan-out lines 130 in addition to the pixel driving circuit.
  • the plurality of data lines 110 are located in the display area AA and are electrically connected to multiple pixel driving circuits for transmitting driving signals to the pixel driving circuit, so that the pixel driving circuit can drive the light-emitting device 300 to emit light to achieve different gray levels. display.
  • the plurality of fan-out lines 130 are located in the fan-out area BB and are electrically connected to the plurality of data lines 110 in one-to-one correspondence.
  • the plurality of data lines 110 are arranged at intervals along the first direction X, and the plurality of data lines 110 all extend along the second direction Y.
  • the second direction Y intersects the first direction X, and , the first direction X and the second direction Y may both be parallel to the substrate 102 .
  • first direction X and the second direction Y are perpendicular or approximately perpendicular.
  • first direction X is the horizontal direction
  • second direction Y is the vertical direction.
  • the plurality of sub-pixels 101 are arranged in multiple columns along the first direction X and in multiple rows along the second direction Y. That is, the pixel driving circuits in the multiple sub-pixels 101 can be arranged along the The first direction X and the second direction Y are arranged in a multi-row and multi-column array. As shown in FIG. 6 , a plurality of data lines 110 extend along the second direction Y, so that one data line 110 can be electrically connected to the pixel driving circuit in a column of sub-pixels 101 arranged along the second direction Y, so as to A data voltage is supplied to the pixel driving circuit in a column of sub-pixels 101 .
  • the plurality of data lines 110 are spaced at the same or approximately the same distance along the first direction X. same.
  • the fan-out area BB is adjacent to one edge of the display area AA along the second direction Y. Therefore, multiple data lines 110 are provided to extend along the second direction Y, so that the multiple data lines 110 are arranged to extend along the second direction Y. 110 can be electrically connected to a plurality of fan-out lines 130 located in the fan-out area BB in a one-to-one correspondence.
  • the multiple fan-out lines 130 located in the fan-out area BB gradually approach and converge, and extend to the side of the fan-out area BB away from the display area AA to facilitate the connection between the multiple fan-out lines 130 and the display substrate.
  • the external driver chip (English full name: Integrated Circuit, English abbreviation: IC) is electrically connected. It can be understood that the driving IC can input signals to each pixel driving circuit through a plurality of fan-out lines 130 and a plurality of data lines 110 .
  • the plurality of fan-out lines 130 extend to a side edge of the fan-out area BB away from the display area AA, so that the plurality of fan-out lines 130 can be electrically connected to the driving IC.
  • the above implementation will increase the space occupied by the multiple fan-out lines 130 along the second direction Y, thereby causing the width of the fan-out area BB to increase, that is, causing the width of the side frame (such as the bottom frame) of the display panel 210 to increase.
  • Large size is not conducive to achieving a narrow frame for the display panel 210 and affects the visual effect of the display panel 210 .
  • the plurality of fan-out lines 130 are located at at least one gate metal layer gate (such as a first gate metal layer gate1, a second gate metal layer gate2, and a third gate metal layer).
  • the gate metal layer gate includes molybdenum material, and molybdenum material has a large resistance.
  • FIG. 7 is a structural diagram of a display substrate according to further embodiments.
  • the display substrate 100 includes a display area AA and a fan-out area BB.
  • the fan-out area BB is adjacent to one edge of the display area AA.
  • the display substrate 100 includes a substrate 102 and a multi-layer conductive layer 103 (as shown in FIG. 4 ).
  • the multi-layer conductive layer 103 is located on the same side of the substrate 102 and is stacked.
  • the multi-layer conductive layer 103 includes a plurality of data lines 110 .
  • the plurality of data lines 110 are arranged at intervals along the first direction X, and the plurality of data lines 110 all extend along the second direction Y.
  • the second direction Y intersects the first direction X.
  • the display substrate 100 may also include a plurality of scan control signal lines 105 , the plurality of scan control signal lines 105 are arranged at intervals along the second direction Y, and all extend along the first direction X, so that A scan control signal line 105 can be electrically connected to a pixel driving circuit in a row of sub-pixels 101 arranged along the first direction X to control the working state of the pixel driving circuit in a row of sub-pixels 101 .
  • FIG. 7 illustrate the display substrate 100 provided by some embodiments of the present disclosure.
  • the plurality of data lines 110 includes a plurality of first data lines 111 and a plurality of second data lines 112 .
  • the plurality of first data lines 111 are located in two edge areas AA1 of the display area AA along the first direction X
  • the plurality of second data lines 112 are located in the central area AA2 of the display area AA along the first direction X.
  • the number of edge areas AA1 is two.
  • the two edge areas AA1 are located on both sides of the display substrate 100 along the first direction X.
  • the central area AA2 is located on both edges along the first direction X. Between area AA1.
  • the number of the first data lines 111 and the second data lines 112 may be the same or different.
  • the number of first data lines 111 located in the two edge areas AA1 may be the same or different.
  • first data line 111 and the second data line 112 are only used to distinguish the data line 110 located in the edge area AA1 and the center area AA2, and no other aspects of the data line 110 are made. Further qualification.
  • the widths of the two edge areas AA1 of the display area AA are the same or approximately the same.
  • the display area AA includes rounded corners, that is, two adjacent edges of the display area AA are connected in an arc shape or approximately an arc shape. The rounded corners are located in the edge area AA1 of the display area AA.
  • the width dimension of the edge area AA1 in the first direction X may be greater than or equal to the width dimension of the fillet in the first direction X.
  • the plurality of first data lines 111 and the plurality of second data lines 112 are located in the same conductive layer 103 .
  • the plurality of first data lines 111 and the plurality of second data lines 112 are located on the first source-drain metal layer SD1.
  • the plurality of first data lines 111 and the plurality of second data lines 112 are located on the second source-drain metal layer SD2.
  • the plurality of first data lines 111 and the plurality of second data lines 112 may also be located in other conductive layers 103 (for example, the third source-drain metal layer SD1 ) other than the first source-drain metal layer SD1 and the second source-drain metal layer SD2 . layer).
  • the multi-layer conductive layer 103 also includes a plurality of connecting lines 120 .
  • a connecting line The first end of 120 (ie, the arrow end in FIG. 7 ) is located in the edge area AA1 of the display area AA, and is electrically connected to a first data line 111 .
  • the second end of the connecting line 120 (ie, the opposite end of the arrow end in FIG. 7 ) extends to the junction between the central area AA2 of the display area AA and the fan-out area BB.
  • the second end of any one of the plurality of connection lines 120 extends to the central area AA2 of the display area AA.
  • the second end of the connection line 120 extends to the junction of the central area AA2 and the fan-out area BB. It can be understood that the second end of the connecting line 120 may be located on the dividing line between the central area AA2 and the fan-out area BB; or, there may be a small gap between the connecting line 120 and the dividing line, such as a gap of several microns. , at this time, the second end of the connecting line 120 may be located on the side of the dividing line close to the display area AA, or may be located on the side of the dividing line close to the fan-out area BB.
  • connection line 120 spans at least one data line 110 (for example, the first data line 111 and/or the second data line 112 ), and is insulated from the crossed data line 110 .
  • connection lines 120 may cross the first data line 111 and the second data line 112 at the same time.
  • at least one connection line 120 may only cross the first data line 111 (not shown).
  • at least one connection line 120 may only cross the second data line 112 (not shown).
  • the display substrate 100 may also include connection lines 120 that do not cross any data lines 110 , for example, the first connection line 120 and the last connection line 120 arranged from left to right along the first direction X in FIG. 7 1 connecting cable 120.
  • connection line 120 crosses at least one data line 110 , that is, the orthographic projection of the connection line 120 on the substrate 102 intersects the orthographic projection of the at least one data line 110 on the substrate 102 .
  • connection line 120 and the data line 110 are located on different conductive layers 103 so that the connection line 120 can be insulated from the data line 110 that spans it.
  • the data line 110 is located on the first source-drain metal layer SD1, and the connection line 120 is located on the second source-drain metal layer SD2.
  • the data line 110 is located on the second source-drain metal layer SD2, and the connection line 120 is located on the third source-drain metal layer.
  • connection line 120 and the data line 110 are located on different conductive layers 103
  • the first end of the connection line 120 can be electrically connected to the first data line 111 through the transfer hole.
  • the transfer hole penetrates the insulating film layer between two adjacent conductive layers 103 in a direction perpendicular or approximately perpendicular to the substrate 102, so that the different conductive layers 103 can be electrically connected, that is, so that Conductive traces (eg, connection lines 120 and data lines 110) located on different conductive layers 103 can be electrically connected.
  • Conductive traces eg, connection lines 120 and data lines 110
  • the transfer hole that electrically connects the conductive traces on the first source-drain metal layer SD1 and the second source-drain metal layer SD2 can be called a PLN1 hole
  • the transfer hole that electrically connects the second source-drain metal layer SD2 can be called a PLN1 hole.
  • the transfer hole between the conductive traces on the source-drain metal layer SD2 and the conductive traces on the third source-drain metal layer is called a PLN2 hole.
  • the first end of the connection line 120 passes through the PLN1 hole and is electrically connected to the first data line 111. connect.
  • the first end of the connection line 120 is electrically connected to the first data line 111 through the PLN2 hole.
  • connection line 120 and the data line 110 are located on different conductive layers 103 so that the connection line 120 can be insulated from the data line 110 that it spans.
  • the connection cable 120 includes a body portion and a jumper portion.
  • the main part and the jumper part can be electrically connected through the transfer hole.
  • the main body portion may be located on the same conductive layer 103 as the data line 110, and the jumper portion may be located on a different conductive layer 103 than the data line 110, so that the jumper portion can span at least one data line 110 and be connected to the crossed data line 110.
  • Wire 110 insulated.
  • the second end of at least one connection line 120 is located between two adjacent second data lines 110 . That is to say, the second end of one connecting line 120 can be disposed between two adjacent second data lines 112 , or the second end of two or more connecting lines 120 can be disposed between two adjacent second data lines 112 . between the second data lines 112.
  • the second end of a connecting line 120 may be provided, or two or more connections may be provided.
  • the second end of the line 120 may not be provided with the second end of the connecting line 120 .
  • the number of second ends of the connection lines 120 provided between two adjacent second data lines 112 may be the same or different.
  • the second end of the connecting line 120 is disposed between two adjacent second data lines 112 so that the second end of the connecting line 120 can pass between the two adjacent second data lines 112 .
  • the interval extends to the junction between the central area AA2 and the fan-out area BB.
  • the number of connecting lines 120 and the number of first data lines 110 may be the same or different.
  • the number of connection lines 120 is the same as the number of first data lines 110 .
  • the plurality of connection lines 120 and the plurality of first data lines 111 are connected in one-to-one correspondence.
  • the number of connection lines 120 is less than the number of first data lines 111. In this case, all connection lines 120 can be connected to a part of the first data lines 111 in a one-to-one correspondence, and another part of the first data lines 111 can be connected in a one-to-one correspondence. Not connected to the connection line 120.
  • the connection line 120 includes a first sub-connection line 121 and a second sub-connection line 122 .
  • One end of the first sub-connection line 121 is located in the edge area AA1 and is electrically connected to the first data line 111 .
  • the other end of the first sub-connection line 121 extends to the central area AA2.
  • One end of the second sub-connection line 122 is electrically connected to an end of the first sub-connection line 121 away from the first data line 111 , and the other end of the second sub-connection line 122 extends to the junction between the central area AA2 and the fan-out area BB. .
  • first sub-connection line 121 extends along the first direction X
  • second sub-connection line 122 extends along the second direction Y
  • first sub-connection line 121 and the second sub-connection line 122 are perpendicular or approximately perpendicular.
  • the connection line 120 includes a main body part and a jumper part.
  • the connection line 120 when the connection line 120 includes a first sub-connection line 121 and a second sub-connection line 122 , the second sub-connection line 122 can be set as the main part, and the main part is located with the plurality of data lines 110 In the same conductive layer 103, the first sub-connection line 121 is a jumper part, and the jumper part and the plurality of data lines 110 are located in different conductive layers 103.
  • the first sub-connection line 121 can span at least one data line 110 and is insulated from the data line 110 it spans.
  • the second sub-connection line 122 can also be set as a main body part, and the first sub-connection line 121 includes both a main body part and a jumper part, where the jumper part is used to cross the data line 110 .
  • the jumper portion is further away from the substrate 102 relative to the plurality of data lines 110, which can reduce the distance between the jumper portion and the gate metal layer Gate (for example, the first gate metal layer Gate1, the second gate metal layer Gate2 and the third gate metal layer Gate2).
  • the gate metal layer Gate for example, the first gate metal layer Gate1, the second gate metal layer Gate2 and the third gate metal layer Gate2.
  • the parasitic capacitance generated between the three gate metal layers, etc. improves the reliability of signal transmission.
  • the multi-layer conductive layer 103 also includes a plurality of fan-out lines 130 .
  • the plurality of fan-out lines 130 are located in the fan-out area BB.
  • the plurality of fan-out lines 130 include a plurality of first fan-out lines 131 and a plurality of second fan-out lines 132 .
  • the first fan-out line 131 is electrically connected to the second end of the connection line 120
  • the second fan-out line 132 is electrically connected to an end of the second data line 112 close to the fan-out area BB.
  • both the data line 110 and the connection line 120 can be located in the display area AA, when the fan-out line 130 and the data line 110 (or the connection line 120) are arranged in different layers and are electrically connected to each other, the two The switching position may be located in the display area AA. At this time, the fan-out line 130 can still be considered to meet the condition of being located in the fan-out area BB.
  • the number of the first fan-out lines 131 is the same as the number of the connecting lines 120 , so that the plurality of first fan-out lines 131 can be electrically connected to the plurality of connecting lines 120 in a one-to-one correspondence.
  • the number of the second fan-out lines 132 is the same as or different from the number of the second data lines 112 .
  • the number of the second fan-out lines 132 is the same as the number of the second data lines 112, and the plurality of second fan-out lines are 132 is electrically connected to a plurality of second data lines 112 in one-to-one correspondence.
  • the number of second fan-out lines 132 and the number of second data lines 112 are different.
  • a part of the second fan-out lines 132 (two or more) among the plurality of second fan-out lines 132 are electrically connected to the second data lines 112 in a one-to-one correspondence, while the other part of the second fan-out lines 132 (two or more or more) can be electrically connected to the first data lines 111 that are not electrically connected to the connection line 120 in a one-to-one correspondence.
  • the number of the above-mentioned fan-out lines 130 may be the same as the number of the data lines 110 (including the first data lines 111 and the second data lines 112).
  • the signal output by the driving IC can be transmitted to a data line 110 electrically connected to the fan-out line 130 through a fan-out line 130, thereby achieving driving of a column of sub-pixels 101.
  • the central axis extending along the second direction Y of the display substrate 100 is defined as the first central axis Q, that is, the first central axis Q is located at the center of the display substrate 100 along the first direction X and is parallel to on the substrate 102. It can be understood that the first central axis Q is a virtual reference line, and the first central axis Q is located in the central area AA2 of the display substrate 100 .
  • Such an arrangement can reduce the space occupied by the multiple fan-out lines 130 along the second direction Y when the fan-out area BB is gathered and extends away from the display area AA. Therefore, the width of the fan-out area BB in the second direction Y can be reduced. For example, the width of the first fan-out area BB1 in the second direction Y can be significantly reduced. Therefore, the width of the side frame (for example, the bottom frame) of the display panel 210 can be reduced, so that the display panel 210 can achieve an ultra-narrow bottom frame and improve the visual effect of the display panel 210 .
  • the rounded corners are located in the edge area AA1 of the display area AA. Therefore, by adopting the above arrangement, the first data line 111 at the rounded corner position can be electrically connected to the first fan-out line 131 through the connecting wire 120, thereby preventing the first fan-out line 131 from occupying the fan-out area close to the rounded corner position. BB space, thereby reducing the width of the frame at the rounded corners, so that the display area AA of the display panel 210 can achieve ultra-large rounded corners.
  • the visual effect of the display panel 210 can be improved, on the other hand, it can also improve the convenience of installation between the outer frame of the display panel 210 and the display panel 210 and reduce the stress on the frame during installation.
  • the risk of frame wrinkles or even cracking caused by installation stress is reduced, the processing convenience of the display device 200 is improved, and the yield rate of the display device 200 is improved.
  • first data line 111 located in the edge area AA1 can be electrically connected to the first fan-out line 131 through the connecting line 120, it is also beneficial to reduce the length of the first fan-out line 131 electrically connected to the first data line 111.
  • the first fan-out line 131 includes the first sub-fan-out line 133, and the first to third first sub-fan-out lines 133 arranged from left to right along the first direction
  • the shortening amount of the third first sub-fanout line 133 is greater than the shortening amount of the second first sub-fanout line 133
  • the shortening amount of the second first sub-fanout line 133 is is greater than the shortening amount of the first sub-fanout line 133)
  • the second fan-out line 132 includes a third sub-fan-out line 136. Taking the above-mentioned third first sub-fan-out line 133 as an example, the shortened length of the third first sub-fan-out line 133 is shorter than the length on its left side (as shown in the figure).
  • the resistance of the third first sub-fanout line 133 is smaller than the resistance of the adjacent third sub-fanout line 136 on its left.
  • the third first sub-fanout line 133 is also connected to the connection line 120, and the connection line 120 is located in the source-drain metal layer SD (which may include a titanium/aluminum/titanium stacked structure) with very low resistance, Therefore, the total resistance on the third first sub-fanout line 133 and the connecting line 120 can be slightly less than or equal to the resistance of the third sub-fanout line 136 adjacent to the left side of the third first sub-fanout line 133, That is to say: the resistance on the first data line 111 to which the third first sub-fanout line 133 is electrically connected is slightly less than or equal to the resistance on the left side of the third first sub-fanout line 133 (as shown in the figure). Therefore, it is also beneficial to the resistance difference between the first data line 111 and the
  • connection line 120 is added between the first fan-out line 131 and the first data line 111, since the connection line 120 is located in at least one source-drain metal layer SD, and the source-drain metal layer SD includes titanium /Aluminum/titanium composite laminate structure, compared with the gate metal layer Gate (including molybdenum material), the resistance will be much smaller, for example, it can be one-tenth. Therefore, although adding the connection line 120 will cause the resistance on the first data line 111 to increase slightly, the increased resistance is much smaller than the resistance reduced by shortening the first fan-out line 131 . Therefore, in some of the above embodiments, it is still beneficial to reduce the resistance on the first data line 111 and balance the resistance difference between the first data line 111 and the second data line 112, thereby improving the brightness uniformity of the display screen.
  • the above-mentioned fan-out method of adding connecting lines 120 can be called FIAA (full English name: Fanout In AA, Chinese name: fan-out in display area) or FIP (full English name: Fanout In Panel, Chinese name: fan-out in panel) ).
  • FIAA full English name: Fanout In AA, Chinese name: fan-out in display area
  • FIP full English name: Fanout In Panel, Chinese name: fan-out in panel
  • the number of connection lines 120 can be set to be the same as the number of first data lines 110 .
  • the first data lines 111 and the connection lines 120 are connected in a one-to-one correspondence.
  • this setting can be called full FIAA.
  • first data line 111 and the connecting line 120 may also be provided.
  • the other part of the first data line 111 may not be connected to the connection line 120 , for example, it may be directly led out through the second fan-out line 132 like the second data line 112 .
  • Such an arrangement is beneficial to reducing the spacing between the multiple data lines 110 and increasing the pixel density of the display area AA, so that the display panel 210 can achieve high PPI (English full name: Pixels Per Inch, Chinese name: Pixels Per Inch). For example, this setting can be called partial FIAA.
  • the display panel 210 may be a QHD (English full name: Quad High Definition, Chinese name: Quad High Definition) display panel.
  • QHD English full name: Quad High Definition, Chinese name: Quad High Definition
  • any two adjacent connection lines 120 may be defined as a first connection line 120 a and a second connection line 120 b. It can be understood that in this embodiment, the first connection line 120a and the second connection line 120b are only used to distinguish two adjacent connection lines 120, and the connection lines 120 are not further limited.
  • the first data line 111 electrically connected to the first end of the first connection line 120a is different from the first data line 111 electrically connected to the first end of the second connection line 120b. further away from the first central axis Q of the display substrate 100 .
  • the second end of the first connection line 120a is closer to the first central axis Q of the display substrate than the second end of the second connection line 120b.
  • the above connection method can be called reverse FIAA.
  • the first data line 111 electrically connected to the first end of the first connection line 120a is closer to the display substrate than the first data line 111 electrically connected to the first end of the second connection line 120b.
  • the second end of the first connection line 120a is closer to the first central axis Q of the display substrate 100 than the second end of the second connection line 120b.
  • the above connection method can be called positive sequence FIAA.
  • first data line 111 when the first data line 111 is electrically connected to the first fan-out line 131 through the connecting line 120 (for example, using the above-mentioned reverse sequence FIAA or positive sequence FIAA), it will result in multiple fan-out lines 130 (including the first fan-out line 131 and The end of the second fan-out line 132) away from the display area AA (for example, the end electrically connected to the driving IC) is arranged along the first direction ) are arranged in different orders along the first direction X.
  • an edge of the display substrate 100 in the first direction X may be defined as the first edge. It can be understood that the first edge is any one of the two edges of the display substrate 100 in the first direction X.
  • a plurality of data lines 110 (including the first data line 111 and the second data line 112 ) arranged at intervals along the first edge of the display substrate 100 to the first central axis Q direction of the display substrate 100 can be defined as Data line 1 ⁇ data line n.
  • data line 1 to data line m (m ⁇ n) are located in the edge area AA1
  • data lines m+1 to data line n are located in the central area AA2. That is to say, data line 1 to data line m are the first number
  • the data line 111, the data line m+1 to the data line n are the second data lines 112.
  • the first end of the connection line 120 is electrically connected to the first data line 111, and the second end of at least one connection line 120 is located between two adjacent second data lines 112.
  • the second end of the connection line 120 electrically connected to the data line 1 can be located between the data line m+1 and the data line m+2 (positive sequence FIAA), or the connection line electrically connected to the data line 1
  • the second end of 120 can be located between data line n-1 and data line n (reverse FIAA). That is, the second end of the connection line 120 will be inserted between two adjacent second data lines 112 (for example, the data line m+1 and the data line m+2).
  • first fan-out line 131 is electrically connected to the second end of the connecting line 120, and the second fan-out line 132 is electrically connected to an end of the second data line 112 close to the fan-out area BB, at least one first fan-out line 131 will be electrically connected to the second end of the second data line 112.
  • the outlet wire 131 is inserted between two adjacent second fan-out wires 132 .
  • a plurality of fan-out lines 130 (including the first fan-out line 131 and the second fan-out line 132) electrically connected to the data lines 1 to n can be defined as fan-out lines 1 to n.
  • Fanout line 1 is electrically connected to data line 1
  • fanout line 2 is electrically connected to data line 2, and so on.
  • the fan-out lines 1 to n are far away from one end of the display area AA (that is, multiple fan-out lines 130 One end electrically connected to the driving IC) cannot be arranged in sequence along the direction from the first edge to the first central axis Q.
  • the data lines 1 to n are arranged at intervals. That is to say, using all or part of FIAA for wiring will result in the arrangement of multiple fan-out lines 130 (including the first fan-out line 131 and the second fan-out line 132) away from the end of the display area AA along the first direction X. It is different from the arrangement order of the plurality of data lines 110 (including the first data line 111 and the second data line 112) along the first direction X.
  • the driving IC has an output terminal, and the arrangement order of the output terminals of the driving IC along the first direction X is the same as the arrangement order of the plurality of data lines 110 along the first direction X. It can be understood that due to the arrangement sequence of the plurality of fan-out lines 130 (including the first fan-out line 131 and the second fan-out line 132) along the first direction Lines 111 and second data lines 112) are arranged in different orders along the first direction Column sub-pixels 101 emit light. The cost of re-developing the driver IC is high, which leads to an increase in the cost of the display panel 210 .
  • the display substrate 100 also has a bending area (English full name: Bending) CC.
  • the fan-out area BB includes a first fan-out area BB1 and a second fan-out area BB2.
  • the first fan-out area BB1 is closer to the display area AA than the second fan-out area BB2.
  • the bending area CC is located in the first fan-out area BB1. and the second fan-out area BB2.
  • the substrate 102 is a flexible substrate.
  • a substrate 102 and multiple conductive layers are provided in the bending area CC.
  • At least one layer of the substrate 102 and the multi-layer conductive layer 103 can be bent in the bending region CC.
  • the substrate 102 and the second source-drain metal layer SD2 are disposed in the bending region CC.
  • the bending area CC is located between the first fan-out area BB1 and the second fan-out area BB2, so that the second fan-out area BB2 can be bent to the back of the display substrate 100 located in the display area AA, avoiding the second fan-out.
  • the area BB2 occupies the space on the display side of the display substrate 100 , thereby further reducing the width of the side frame (for example, the lower frame) of the display panel 210 and improving the visual effect of the display panel 210 .
  • the display substrate 100 also includes a chip mounting (English full name: Chip On Panel, English abbreviation: COP) area.
  • the COP area is used to install the driver IC.
  • the second fan-out area BB2 is located between the bending area CC and the COP area.
  • the display substrate 100 also includes a circuit test (English full name: Cell Test, English abbreviation: CT) area.
  • the CT area is used to test the display substrate 100 .
  • the second fan-out area BB2 may be located between the CT area and the COP area. It should be noted that at this time, the distance between the CT area and the bending area CC may be 0 (that is, there may not be the intermediate fan-out area BB0 shown in Figure 7), or it may not be 0 (that is, there may be The middle fan-out area BB0 shown in Figure 7).
  • the middle fan-out area BB0 when the middle fan-out area BB0 is included, the middle fan-out area BB0 may be part of the second fan-out area BB2 (not shown), or may not be part of the second fan-out area BB2 (as shown in FIG. 7 Show).
  • the display substrate 100 also includes an ILB (English full name: Inner Lead Bonding, Chinese name: inner lead bonding) area (not shown) and FOP (English full name: Flexible Printed Circuit On Panel, Chinese name: on panel Flexible circuit board) area (not shown).
  • the ILB area and the FOP area are located in sequence on the side of the COP area away from the second fan-out area BB2.
  • some pins of the driver IC can be electrically connected to pins in the FOP area through traces in the ILB area, and the pins in the FOP area can be used to connect to an external flexible circuit board.
  • all the first data lines 111 in the edge area AA1 can be drawn out through the connecting line 120), or it can be a partial FIAA (that is, part of the first data line 111 in the edge area AA1 is drawn out through the connecting line 120); and it can be a positive sequence FIAA or a reverse sequence FIAA.
  • some embodiments of the present disclosure will be introduced, taking all FIAA and reverse FIAA shown in FIG. 7 as examples.
  • the first fan-out line 131 includes a patch cord 134 .
  • the adapter line 134 is located in the second fan-out area BB2.
  • the transfer line 134 and the plurality of second fan-out lines 132 are located on different conductive layers 103, and the transfer line 134 spans at least one second fan-out line 132, so that the plurality of fan-out lines 130 are far away from each other.
  • the arrangement order along the first direction X from one end of the display area AA is the same as the arrangement order along the first direction X of the plurality of data lines 110 .
  • one trace "crosses" another trace, that is, at least part of one trace is located on a different conductive layer 103 than another trace, and at least part of the trace
  • the orthographic projection on the substrate 102 intersects the orthographic projection of another trace on the substrate 102, thereby "crossing" the other trace.
  • the transfer line 134 crosses at least one second fan-out line 132 , that is, the orthographic projection of the transfer line 134 on the substrate 102 intersects the orthographic projection of the at least one second fan-out line 132 on the substrate 102 .
  • the adapter wire 134 and the plurality of second fan-out lines 132 are located on different conductive layers 103 so that the adapter wire 134 can be insulated from the plurality of second fan-out lines 132 .
  • the plurality of transfer lines 134 may be located on one conductive layer 103 or on multiple conductive layers 103 .
  • any one of the transfer lines 134 and the plurality of second fan-out lines 132 are located in different conductive layers 103.
  • any two adjacent transfer wires 134 may be located in different conductive layers 103.
  • the transfer line 134 may be located on the second source-drain metal layer SD2 and/or the third source-drain metal layer.
  • any two adjacent transfer lines 134 are located on different source-drain metal layers SD (including the second source-drain metal layer SD2 or the third source and drain metal layer).
  • the end of the first fan-out line 131 away from the display area AA (that is, the end of the first fan-out line 131 electrically connected to the driving IC) can be The arrangement order is adjusted, so that the arrangement order of the end of the multiple fan-out lines 130 away from the display area AA (that is, the end of the multiple fan-out lines 130 electrically connected to the driving IC) can be adjusted, so that the fan-out lines 1 to fan-out lines n
  • the end far away from the display area AA can be arranged at intervals along the direction from the first edge to the first central axis Q, so that the plurality of fan-out lines 130 at the end far away from the display area AA can be arranged in sequence along the first direction
  • the first data lines 110 can be arranged in the same order along the first direction X.
  • the output terminals of the driving IC are arranged in the first direction X, the ends of the multiple fan-out lines 130 away from the display area AA are arranged in the first direction X, and the data lines 110 are arranged in the first direction X.
  • the order of the three can be the same, and the output end of the driving IC can provide driving signals to multiple data lines 110 in sequence, that is, the driving IC can drive multiple columns of sub-pixels 101 to emit light in sequence, without Redevelopment of the driver IC reduces the cost of the display substrate 100 on the basis that the display substrate 100 can achieve a narrow frame.
  • arranging the adapter line 134 in the second fan-out area BB2 prevents the adapter line 134 from occupying the space of the first fan-out area BB1 and reduces the width of the first fan-out area BB1. Since the first fan-out area BB1 is located on the side of the bending area CC close to the display area AA, reducing the width of the first fan-out area BB1 can further reduce the width of the lower frame of the display substrate 100, thereby increasing the height of the display panel 210. visual effects.
  • the first fan-out line 131 is directly electrically connected to the output terminal of the driving IC through the adapter line 134 .
  • the first fan-out line 131 also includes other portions of wiring, and the first fan-out line 131 is electrically connected to the output end of the driver IC through other portions of wiring.
  • the adapter cable 134 includes a main body part 1340 and two connection end parts (G1, G2).
  • the main body part 1340 is located near the two connection end parts (G1, G2) near the display area AA. side.
  • the connecting end close to the first central axis Q is defined as the first connecting end G1
  • the connecting end far away from the first central axis Q is defined as the second connecting end G2. .
  • first connection end G1 may be used to connect the part of the first fan-out line 131 close to the display area AA
  • second connection end G2 may be used to connect the part of the first fan-out line 131 close to the COP area.
  • the first fan-out line 131 also includes a first sub-fan-out line 133 and a second sub-fan-out line 135 .
  • the first connection end G1 is electrically connected to the first sub-fanout line 133 and is electrically connected to the connection line 120 through the first sub-fanout line 133 .
  • the second connection end G2 is electrically connected to the second sub-fanout line 135 and is electrically connected to the driving IC through the second sub-fanout line 135 .
  • the second fan-out line 132 includes a third sub-fan-out line 136 and a fourth sub-fan-out line 137 .
  • One end of the third sub-fanout line 136 is electrically connected to the second data line 112
  • the other end of the third sub-fanout line 136 is electrically connected to the fourth sub-fanout line 137
  • one end of the fourth sub-fanout line 137 is away from the third sub-fanout line. Electrically connected to the driver IC.
  • adjacent sub-fanout lines may be located in different gate metal layers Gate, for example, one of them is located in the first gate metal layer Gate1 and the other is located in the second gate metal layer Gate2. Such an arrangement is beneficial to reducing signal crosstalk between adjacent sub-fanout lines.
  • the third sub-fanout line 136 and the first sub-fanout The line 133 is located in the first fan-out area BB1 and has a smaller intersection angle with the first central axis Q, that is, it is closer to being parallel to the first central axis Q. Therefore, in the first fan-out area BB1, between the third sub-fanout line 136 and the first sub-fanout line 133, between the two third sub-fanout lines 136, and between the two first sub-fanout lines 133, Both can have more distances.
  • the third sub-fanout line 136 and the first sub-fanout line 133 can be set to be located in the first fan-out area BB1 in the same source-drain metal layer SD, or along the first direction X Alternately located in different source-drain metal layers SD, this allows the third sub-fanout line 136 and the first sub-fanout line 133 to have smaller resistance respectively, that is, the first data line 111 and the second data line 112 can Having smaller resistance is beneficial to improving the display brightness of the display substrate 100 .
  • any one of the third sub-fanout line 136 and the first sub-fanout line 133 located in the bending area CC can be provided with a film layer outside the gate metal layer (for example, any layer of source-drain metal layer). layer), the embodiment of the present disclosure does not limit this.
  • part of the wiring of the first sub-fanout line 133 and the third sub-fanout line 136 located in the second fan-out area BB2 needs to be arranged at an angle to achieve further shrinkage and facilitate subsequent transfer lines 134
  • the second sub-fanout line 135 and the fourth sub-fanout line 137 are electrically connected to the driving IC.
  • the width of the second fan-out area BB2 occupied by this part of the inclined wiring is larger than the second fan-out area occupied by both the second sub-fan-out line 135 and the fourth sub-fan-out line 137 BB2 width.
  • the main body 1340 is located on the side of the two connecting ends (G1, G2) close to the COP area, it is necessary to further increase the width of the second fan-out area BB2 along the second direction Y. In this case, As a result, the lengths of the second sub-fanout line 135 and the fourth sub-fanout line 137 are increased. Therefore, the resistance of the plurality of data lines 110 is increased, thereby affecting the display brightness of the display substrate 100 and affecting the display effect of low-grayscale images.
  • the main body part 1340 since the main body part 1340 is located on the side of the two connecting ends (G1, G2) close to the display area AA, the main body part 1340 can be in contact with the first part in the thickness direction of the substrate 102.
  • the areas where the sub-fanout line 133 and the third sub-fanout line 136 are located overlap.
  • the width of the second fan-out area BB2 occupied by the oblique wiring in the first sub-fanout line 133 and the third sub-fanout line 136 is larger, there is no need to extend the first sub-fanout area BB2.
  • the fan-out line 133 and the third sub-fan-out line 136 are conducive to reducing the occupation of the space of the second fan-out area BB2 along the second direction Y by the fan-out line 130, thereby being conducive to reducing the space occupied by the second fan-out area BB2 along the second direction Y.
  • the width of Y is conducive to reducing the occupation of the space of the second fan-out area BB2 along the second direction Y by the fan-out line 130, thereby being conducive to reducing the space occupied by the second fan-out area BB2 along the second direction Y.
  • the solution is beneficial to reducing the resistance of the plurality of data lines 110, thereby being beneficial to increasing the display brightness of the display substrate 100 and improving the display effect of low-grayscale images.
  • the display substrate 100 further includes an isolation block 140 .
  • isolation block 140 The transfer line 134 is separated from the first sub-fanout line 133 , and the transfer line 134 is separated from the third sub-fanout line 136 .
  • the first sub-fanout line 133 and the third sub-fanout line 136 are located on at least one gate metal layer Gate.
  • the transfer line 134 is located in the second source-drain metal layer SD2 and/or the third source-drain metal layer.
  • the isolation block may be located in the first source-drain metal layer SD1.
  • such an arrangement is beneficial to reducing the signal crosstalk between the adapter line 134 and the first sub-fanout line 133, and reducing the signal crosstalk between the adapter line 134 and the third sub-fanout line 136, thus facilitating Improving the brightness uniformity of the display area AA makes the multiple sub-pixels of the display substrate 100 less prone to problems such as flickering or poor dark lines.
  • the isolation block 140 is connected to the voltage signal line 141 , that is, the isolation block 140 can be configured to transmit the voltage signal.
  • the voltage signal line 141 may be, but is not limited to, any of the Vdd signal line that provides voltage to the anode of the light-emitting device 300 , the Vss signal line that provides voltage to the cathode of the light-emitting device 300 , and other signal lines.
  • the adapter line 134 and the first sub-fanout line 133, as well as the adapter line 134 and the third sub-fanout line 136 are isolated by the isolation block 140 configured to transmit voltage signals, so that no additional settings are required.
  • Other components simplify the preparation process and reduce the cost of the display substrate 100.
  • FIG. 8 is a partial structural diagram of a display substrate according to some embodiments.
  • FIG. 9 is a structural diagram of the first gate metal layer, the second gate metal layer and the first source and drain metal layer in FIG. 8 .
  • FIG. 10 is a structural diagram of the second source-drain metal layer and the third source-drain metal layer in FIG. 8 .
  • the area of the second fan-out area BB2 located on one side of the first central axis Q is a sub-fan-out area BBZ.
  • the wiring method in a sub-fanout zone BBZ is mainly introduced. It can be understood that the wiring methods in the two sub-fan-out zones BBZ may be the same or different.
  • the display substrate 100 includes a first gate metal layer Gate1, a second gate metal layer Gate2, a first source-drain metal layer SD1, and a the second source-drain metal layer SD2 and the third source-drain metal layer SD3. Moreover, the display substrate 100 has a first fan-out area BB1, a bending area CC, a middle fan-out area BB0 (optional), a CT area, a second fan-out area BB2, a COP area, and an ILB area that are far away from the display area AA in order. and FOP area.
  • the part of the display substrate 100 located on the side of the bending area CC away from the display area AA can be bent to the back of the part of the display substrate 100 located on the display area AA, thereby preventing the part of the display substrate 100 located on the side of the bending area CC away from the display area.
  • the area AA occupies the space on the display side of the display substrate 100 , thereby reducing the width of the side frame (for example, the bottom frame) of the display panel 210 and improving the visual effect of the display panel 210 .
  • the patch cord 134 is U-shaped or approximately U-shaped. transfer The opening of line 134 faces the COP area.
  • the U-shaped or approximately U-shaped adapter line 134 can cross at least one second fan-out line 132, so that the adapter line 134 can adjust one end of the plurality of first fan-out lines 131 away from the display area AA along the first direction X.
  • the arrangement order is such that the end of the fan-out lines 1 to n away from the display area AA can be arranged at intervals along the direction from the edge to the first central axis Q, that is, the multiple fan-out lines 130 are far away from the display area.
  • the arrangement order of one end of AA along the first direction X can be the same as the arrangement order of the plurality of first data lines 110 along the first direction X.
  • the isolation block 140 is located on a side of the second gate metal layer Gate2 away from the first gate metal layer Gate1.
  • the isolation block 140 may be located on the first source-drain metal layer SD1.
  • either one of the first sub-fanout line 133 and the third sub-fanout line 136 is located in the first gate metal layer Gate1 and/or the second gate metal layer Gate2, and the transfer line 134 is located in the second source-drain layer.
  • Figure 11 is a partial structural diagram of area 001 in Figure 8.
  • Figures 12 to 17 are structural diagrams of each film layer in Figure 11.
  • multiple transfer lines 134 are arranged in a radial manner.
  • the "radial arrangement" means that for any two adjacent transfer lines 134 , the outer transfer lines 134 are partially arranged around the inner transfer lines 134 , that is, for example, the arrangement shown in FIG. 11 .
  • each adapter line 134 is U-shaped, and the inner adapter line 134 is generally located within the outer adapter line 134 .
  • the outer transfer line 134 is arranged around the inner transfer line 134 , which helps to save wiring space, thereby increasing the distance between the transfer lines 134 and the transfer lines 134 . spacing between the display substrate 100 and the display substrate 100 to reduce signal crosstalk, and also help reduce the size of the second fan-out area BB2 of the display substrate 100 along the second direction Y, so that the lower frame of the display substrate 100 can be set narrower.
  • adjacent transfer lines 134 may also be substantially parallel to each other. In this way, the spacing between adjacent transfer lines 134 can be kept substantially consistent, which is beneficial to reducing signal interference between adjacent transfer lines 134 and thus is beneficial to improving the brightness uniformity of the display screen of the display substrate.
  • two adjacent patch lines are located on different conductive layer. This arrangement is helpful to further improve the signal interference problem between adjacent transfer lines 134, thereby being helpful to further improve the brightness uniformity of the display screen of the display substrate.
  • the first fan-out line 131 also includes a first wiring segment 1311 and a second wiring segment 1312 that are sequentially away from the display area AA and electrically connected to each other, that is, in the first fan-out line 131
  • the first sub-fanout line 133 may include a first trace segment 1311 and a second trace segment 1312 that are sequentially away from the display area AA and electrically connected to each other.
  • the first wiring segment 1311 gradually approaches the first central axis Q from an end close to the display area AA to an end far away from the display area AA.
  • the second wiring segment 1312 is parallel to the first central axis Q.
  • the second fan-out line 132 includes a third wiring segment 1321 and a fourth wiring segment 1322 that are sequentially away from the display area AA and are electrically connected to each other. That is, the third sub-fanout line 136 in the second fan-out line 132 may include a sequence that is away from the display area AA. and the third wiring segment 1321 and the fourth wiring segment 1322 are electrically connected to each other.
  • the third wiring segment 1321 gradually approaches the first central axis Q from an end close to the display area AA to an end far away from the display area AA.
  • the fourth wiring segment 1322 is parallel to the first central axis Q.
  • the adapter line 134 includes: a connection end close to the first central axis Q (ie, the first connection end G1 ), and a connection end far away from the first central axis Q (ie, the second connection end). Connect end G2). Among them, the connection end of the adapter wire 134 close to the first central axis Q (ie, the first connection end G1) can be electrically connected to the end a1 of the second wiring segment 1312 away from the first wiring segment 1311 in FIGS. 12 and 13 .
  • the interlayer dielectric layer ILD shown in FIG. 14 includes a first connection hole 161 and a second connection hole 162.
  • the first source-drain metal layer SD1 shown in FIG. 15 includes a first transfer part M1 and a second transfer part M2.
  • the two adjacent second wiring segments 1312 are respectively located in the first gate metal layer Gate1 and the second gate metal layer Gate2.
  • ends a1 of the two adjacent second wiring segments 1312 located in the first gate metal layer
  • the end a1 of the second wiring segment 1312 of Gate1 can be electrically connected to the first transition portion M1 located on the first source-drain metal layer SD1 through the first connection hole 161, and the end a1 located on the second gate metal layer Gate2 It can be directly electrically connected to the second transfer portion M2 located on the first source-drain metal layer SD1 through the second connection hole 162 .
  • the transfer hole that electrically connects the conductive traces on the first source-drain metal layer SD1 and the second source-drain metal layer SD2 can be called a PLN1 hole, and the transfer hole that electrically connects the second source-drain metal layer SD2
  • the transfer hole between the conductive traces on the source-drain metal layer SD2 and the conductive traces on the third source-drain metal layer is called a PLN2 hole. Therefore, the first connection end G1 of the transfer line 134 in the second source-drain metal layer SD2 shown in FIG.
  • the first connection end G1 of the transfer line 134 in the second source-drain metal layer SD2 shown in FIG. 16 can be connected to the end of one second trace segment 1312. a1 electrical connection.
  • the second source-drain metal layer SD2 shown in FIG. 16 may also include a third transfer part M3.
  • the first connection end G1 of the transfer line 134 in the third source-drain metal layer SD3 shown in FIG. 17 can be electrically connected to the third transfer portion M3 through the PLN2 hole, and the third transfer portion M3 can pass through the PLN1 hole. Electrically connected to the first transfer part M1. Since the first transfer part M1 is electrically connected to the end a1 of the other second wiring segment 1312, therefore, the transfer line in the third source-drain metal layer SD3 shown in Figure 17 The first connection end G1 of 134 may be electrically connected to the end a1 of another second wiring segment 1312.
  • the second source-drain metal layer SD2 further includes a fourth transfer portion M4.
  • the third source-drain metal layer SD3 also includes a fifth transfer portion M5.
  • the second connection end G2 of the transfer line 134 in the second source-drain metal layer SD2 can be electrically connected to the fifth transfer portion M5 in the third source-drain metal layer SD3 through the PLN2 hole, and the third source-drain metal layer SD3
  • the second connection end G2 of the transfer line 134 in may be electrically connected to the fourth transfer part M4 in the second source-drain metal layer SD2 through the PLN2 hole. This arrangement is beneficial to balancing the parasitic capacitance differences between adjacent transfer lines 134 located on different layers.
  • the first source-drain metal layer SD1 includes a first extension line N1 and a second extension line N2.
  • the second connection end portion G2 and the fourth transfer portion M4 of the transfer line 134 in the second source-drain metal layer SD2 can be electrically connected to different first extension traces N1 through different PLN1 holes respectively.
  • the first gate metal layer Gate1 includes a seventh transition portion M7 and a second dummy transition portion M02.
  • the second gate metal layer Gate2 includes a sixth transition portion M6 and a first dummy transition portion M01.
  • the interlayer dielectric layer ILD also includes a third connection hole 163 .
  • the plurality of first extension traces N1 are connected to the first virtual switching part M01 and the second virtual switching part M02 through a part of the third connection hole 163 , and the plurality of second extension traces N2 pass through another part of the third connection hole 163 Transfer to the sixth transfer part M6 and the seventh transfer part M7.
  • both the first fan-out line 131 and the second fan-out line 132 can be connected to the first source-drain metal layer SD1. Moreover, by arranging the first virtual switching part M01 and the second virtual switching part M02, the difference in parasitic capacitance between the multiple fan-out lines 130 caused by the cross-layer switching can be balanced.
  • the interlayer dielectric layer ILD also includes a fourth connection hole 164 .
  • the first extension trace N1 and the second extension trace N2 can be connected to the pin 150 located in the first gate metal layer Gate1 through the fourth connection hole 164.
  • the pin 150 in the first gate metal layer Gate1 can be used to connect to the driver IC.
  • the first gate metal layer Gate1 also includes a third dummy transition portion M03.
  • the interlayer dielectric layer ILD also includes a fifth connection hole 165 .
  • the first extension trace N1 can be transferred to the first gate metal layer through the fifth connection hole 165 On the third virtual switching unit M03 in Gate1. This arrangement is beneficial to balancing the parasitic capacitance differences between the multiple fanout lines 130 caused by cross-layer switching.
  • the insulating layer between the first source-drain metal layer SD1 and the second source-drain metal layer SD1 may not be provided.
  • the first extension wire N1 and the second extension wire N2 provided here may be a stacked structure located on the first source-drain metal layer SD1 and the second source-drain metal layer SD1 at the same time.
  • Such an arrangement is beneficial to reducing the resistance on the first extension wire N1 and the second extension wire N2, thereby helping to improve the display effect of the display substrate 100.
  • a plurality of first wiring segments 1311 and a plurality of third wiring segments 1321 are alternately arranged.
  • four adjacent third sub-fanout lines 136 can be divided into a first wiring group, and two adjacent first sub-line groups can be divided into a second wiring group. , and set the first wiring group and the second wiring group to be arranged alternately, that is, the "4 plug in 2" method is used for wiring. It should be noted that in some other examples, "3 plug 1", "4 plug 3" and other methods can be used for wiring, which can be flexibly set according to factors such as wiring space.
  • the fitting straight line L defined by the end of the first wiring segment 1311 away from the display area AA and the end of the third wiring segment 1321 away from the display area AA extends from one end far away from the first central axis Q to One end close to the first central axis Q gradually approaches the display area AA.
  • the arrangement range of the end a1 of the second wiring segment 1312 away from the display area AA along the second direction Y can be increased. Therefore, the position of the end a1 of the different second wiring segments 1312 can be adjusted to achieve multiple balances.
  • the difference in resistance between the first fan-out lines 131 is also beneficial to balancing the resistance differences between the plurality of first fan-out lines 131 and the plurality of second fan-out lines 132 . In this way, the resistance difference between the plurality of first data lines 111 and the plurality of second data lines 112 is reduced, and the brightness uniformity of the display substrate 100 is improved.
  • the sub-fan-out zone BBZ among the plurality of second wiring segments 1312, at least two (for example, two) directly adjacent second wiring segments 1312 are in the same group, and the same The second trace segments 1312 in the group are staggered along the first direction X away from the end a1 of the display area AA.
  • the length of the second trace segment 1312 close to the first central axis Q is smaller than the length of the second trace segment 1312 away from the first central axis Q.
  • the length of the wiring segment 1312; among the two adjacent transfer lines 134, the transfer line 134 close to the first central axis Q is The connection end (i.e., the first connection end G1 ) connecting to the second wiring segment 1312 is opposite to the connection end (i.e., the connection end (i.e., the first connection end G1 ) of the patch cord 134 used to connect the second wiring segment 1312 away from the first central axis Q
  • the second connection end G2) is closer to the display area AA.
  • the length of the second wiring segment 1312 close to the first central axis Q is smaller than the length of the second wiring segment 1312 far away from the first central axis Q.
  • the length of the second wiring segment 1312 of the central axis Q; among the two adjacent transfer lines 134, the connecting end of the transfer line 134 close to the first central axis Q is used to connect the second wiring segment 1312 (i.e., the third One connection end G1) is closer to the display area AA than the connection end (ie, the second connection end G2) of the adapter line 134 away from the first central axis Q for connecting the second wiring segment 1312.
  • the length of the first sub-fanout line 133 close to the first central axis Q is reduced compared with the length of the first sub-fanout line 133 far away from the first central axis Q.
  • the length decreases more. Therefore, the resistance decrease of the first sub-fanout line 133 close to the first central axis Q is also smaller than the resistance decrease of the first sub-fanout line 133 far away from the first central axis Q.
  • the resistance differences between the plurality of first sub-fanout lines 133 can be better balanced, that is, the resistance differences between the plurality of first data lines 111 can be balanced, and the brightness uniformity of the display substrate 100 can be improved.
  • the body portion 1340 includes a first adapter section 1341 .
  • the first transfer section 1341 is connected to the connection end (ie, the first connection end G1 ) of the transfer line 134 that is connected to the second wiring section 1312 .
  • the orthographic projection of the first transfer section 1341 on the substrate overlaps or substantially overlaps the orthographic projection of the corresponding connected second wiring section 1312 on the substrate.
  • first transfer section 1341 and the second wiring section 1312 are used to transmit the same signal, there is no signal crosstalk problem between the two.
  • Overlapping settings help save wiring space.
  • the main body portion 1340 further includes a second adapter section 1342 connected to the first adapter section 1341, and a third adapter section connected to the second adapter section 1342. 1343.
  • the isolation block 140 is located on the side of the first trace segment 1311 and the third trace segment 1321 away from the substrate, and the isolation block 140 covers the first trace segment 1311 and the third trace segment 1321 . 1321.
  • the transfer line 134 is located on the side of the isolation block 140 away from the substrate.
  • the orthographic projection of the second transition section 1342 on the substrate is located within the orthographic projection of the isolation block 140 on the substrate.
  • the orthographic projections of both the first transfer section 1341 and the third transfer section 1343 on the substrate are located outside the orthographic projection of the isolation block 140 on the substrate.
  • This arrangement not only facilitates adjusting the transfer position between the end a1 of the second wiring segment 1312 away from the display area AA and the transfer line 134 to balance the resistance difference between the multiple data lines 110, but also facilitates the use of the isolation block 140 to separate the transfer lines.
  • the second transfer section 1342 of 134 and the first wiring section 1311 of the first sub-fanout line 133, and the isolation block 140 is used to separate the second transfer section 1342 of the transfer line 134 from the third wiring section of the third sub-fanout line 136.
  • a dotted line extending generally along the first direction X is a partial boundary of the isolation block 140 .
  • the transfer line 134 can be divided into a first transfer section 1341, a second transfer section 1342, and a third transfer section 1343 based on the location of the partial boundary.
  • the first transfer section 1341 and the third transfer section 1343 are both parallel to the first central axis Q, and the second transfer section 1342 is U-shaped or approximately U-shaped. It can be understood that in other examples, because the boundary positions of the isolation block 140 are different, the boundary positions of the first transfer section 1341, the second transfer section 1342, and the third transfer section 1343 are also not fixed.
  • At least one of the second trace segment 1312 and the fourth trace segment 1322 may be configured to include serpentine traces or other irregular traces. Such a design is conducive to further balancing the relationship between the multiple fan-out lines. resistance, thereby balancing the resistance between multiple data lines.
  • the isolation block 140 includes a first boundary E1 and a second boundary E2.
  • the first boundary E1 gradually moves away from the display area AA along the direction approaching the first central axis Q; the second boundary E2 gradually approaches the display area AA along the direction approaching the first central axis Q.
  • first boundary E1 and the second boundary E2 may be at least a straight line (for example, in the example of FIG. 15 , the first boundary E1 is a straight line, and the second boundary E2 is a connected straight line. Two straight lines), or it can be at least one curve, or it can be at least one connected straight line and at least one curve.
  • Figure 11, Figure 15, Figure 16, and Figure 17 only show parts of the first boundary E1 and the second boundary E2.
  • Figure 9 Block 140 for a more complete first boundary E1 and the second boundary E2 may be directly connected or indirectly connected.
  • the first boundary E1 is a fit defined by the end of the first trace segment 1311 away from the display area AA and the end of the third trace segment 1321 away from the display area AA.
  • the straight lines L coincide or approximately coincide.
  • substantially coincident means that there may be a small distance between the first boundary E1 and the fitting straight line L, for example, a distance of several microns.
  • the area of the isolation block 140 can be set relatively small to reduce the impact on the second fan-out area.
  • the occupation of the BB space simultaneously achieves signal shielding for the first wiring segment 1311 and the adapter cable 134, as well as signal shielding for the third wiring segment 1321 and the adapter cable 134, thereby preventing the first wiring segment 1311 and the adapter cable 134 from interfering with each other. signal crosstalk between the third wiring section 1321 and the adapter line 134, thereby improving the brightness uniformity of the display substrate 100.
  • the second boundary E2 is connected to the trace segment farthest from the first central axis Q among all the first trace segments 1311 and all the third trace segments 1321 (for example, in FIG. 13 A third trace segment 1321 is shown in the lower left corner.
  • the trace segment may also be the first trace segment 1311), which overlaps or substantially overlaps.
  • substantially coincident means that there may be a small distance between the second boundary E2 and the trace segment farthest from the first central axis Q, for example, a distance of several microns.
  • the area of the isolation block 140 can be set relatively small, reducing the space occupation of the second fan-out area BB, while achieving signal shielding for the first wiring segment 1311 and the transfer line 134, and for the third
  • the signal shielding between the wiring section 1321 and the adapter wire 134 can prevent signal crosstalk between the first wiring section 1311 and the adapter wire 134, and prevent the signal crosstalk between the third wiring section 1321 and the adapter wire 134, thereby improving the display substrate 100 brightness uniformity.
  • the angle between the first boundary E1 and the second boundary E2 is an obtuse angle.
  • Such an arrangement is conducive to making the isolation block 140 more comprehensively cover the obliquely arranged first wiring section 1311 and the third wiring section 1321 , thereby conducive to preventing the transition between the transition line 134 and the first wiring section 1311 , and the transition line 134 Signal crosstalk occurs between the third trace segment 1321 and the third trace segment 1321 .
  • the orthographic projection of isolation block 140 on the substrate is triangular or approximately triangular.
  • the orthographic projection shape can be considered to be an approximate triangle.
  • the orthographic projection of the isolation block 140 on the substrate can also be set to be a triangle, or other approximate triangle.
  • other approximate triangles may include, for example, a case where the sides of the triangle are jagged or wavy.
  • the isolation block 140 by arranging the orthographic projection of the isolation block 140 on the substrate to be a triangle or an approximate triangle, it is advantageous to make the isolation block 140 more comprehensively cover the obliquely arranged first trace segment 1311 and the third trace segment 1321 to prevent rotation.
  • Signal crosstalk occurs between the wiring 134 and the first wiring segment 1311, and between the adapter line 134 and the third wiring segment 1321.
  • the area of the isolation block 140 can be set relatively small, thereby reducing the space occupation of the second fan-out area BB.
  • the first trace segment 1311, the second trace segment 1312, the third trace segment 1321 and the fourth trace segment 1322 are located in the at least two gate metal layers Gate (for example, the first gate metal layer Gate1 and the second gate metal layer Gate1). Metal layer Gate2).
  • the isolation block 140 is located relatively close to each other in the at least two source and drain metal layers SD.
  • the source-drain metal layer close to the substrate 102 for example, the first source-drain metal layer SD1
  • the transfer line 134 is located in the at least two source-drain metal layers relatively far from the source-drain metal layer of the substrate (for example, the second source-drain metal layer layer SD2 and the third source-drain metal layer SD3).
  • any two adjacent wiring segments (such as the first wiring segment 1311 and the third wiring segment 1321, Either the two first wiring segments 1311 or the two second wiring segments 1321) are located on different gate metal layers (for example, the first gate metal layer Gate1 and the second gate metal layer Gate2).
  • This arrangement is beneficial to reducing the number of adjacent gate metal layers.
  • the signal interference between the wiring segments (such as the first wiring segment 1311 and the third wiring segment 1321, or the two first wiring segments 1311, or the two second wiring segments 1321) is beneficial to improving the brightness uniformity of the display substrate. sex.
  • any two adjacent transfer lines 134 are located on different source-drain metal layers SD (for example, the second source-drain metal layer SD2 and the third source-drain metal layer SD3). As such, It is beneficial to reduce signal interference between two adjacent transfer lines 134, thereby improving the brightness uniformity of the display substrate.

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Abstract

公开一种显示基板，包括多层导电层，多层导电层包括多条数据线、多条连接线和多条扇出线。连接线跨过至少一条数据线，且与所跨过的数据线绝缘。第一扇出线与连接线电连接，第二扇出线与第二数据线靠近扇出区的一端电连接。第一扇出线包括转接线。扇出区包括第一扇出区和第二扇出区，转接线位于第二扇出区。转接线与多条第二扇出线位于不同的导电层，且跨过至少一条第二扇出线，以使多条扇出线远离显示区的一端沿第一方向的排列顺序，与多条数据线沿第一方向的排列顺序相同。其中，转接线包括主体部和两个连接端部，主体部位于两个连接端部靠近显示区的一侧。

Description

显示基板及显示装置
本申请要求于2022年7月25日提交的、申请号为202210880462.1的中国专利申请、以及于2022年4月25日提交的、申请号为PCT/CN2022/089120的PCT国际申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
目前，有机发光二极管(英文全称：Organic Light-Emitting Diode，英文简称：OLED)显示装置，因其具有自发光、快速响应、高对比度、宽视角和可制作在柔性衬底上等特点，受到广泛应用。
OLED显示装置包括多个子像素，各子像素包括像素驱动电路和发光器件，通过像素驱动电路驱动发光器件发光，从而实现显示。
发明内容
一方面，提供一种显示基板。所述显示基板，具有显示区和扇出区，所述扇出区与所述显示区的一侧边缘邻接。所述显示基板包括：衬底和多层导电层。所述多层导电层位于所述衬底的同一侧。所述多层导电层层叠设置。所述多层导电层中包括：多条数据线、多条连接线和多条扇出线。所述多条数据线沿第一方向间隔排布、且所述多条数据线均沿第二方向延伸，所述第二方向与所述第一方向相交叉；所述多条数据线包括多条第一数据线和多条第二数据线，所述多条第一数据线位于所述显示区沿所述第一方向的两个边缘区域，所述多条第二数据线位于所述显示区沿所述第一方向的中心区域。一条连接线的第一端位于所述边缘区域，且与一条第一数据线电连接，该条连接线的第二端延伸至所述中心区域与所述扇出区之间的交界处；至少一条所述连接线跨过至少一条数据线，且与所跨过的数据线绝缘；至少一条所述连接线的第二端位于相邻的两条第二数据线之间。所述多条扇出线位于所述扇出区；所述多条扇出线包括多条第一扇出线和多条第二扇出线；其中，第一扇出线与所述连接线的第二端电连接，第二扇出线和未与所述连接线电连接的数据线的靠近所述扇出区的一端电连接。其中，所述显示基板还具有依次远离所述显示区的弯折区和芯片安装区；所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区位于所述显示区与所述弯折区之间，所述第二扇出区位于所述弯折区与所述芯片安装区之间。所述第一扇出线包括转接线，所述转接线位于所述第二扇出区；所述转接线跨过至少一条所述第二扇出线， 以使所述多条扇出线远离所述显示区的一端沿所述第一方向的排列顺序，与所述多条数据线沿所述第一方向的排列顺序相同。其中，所述转接线包括主体部和两个连接端部，所述主体部位于所述两个连接端部靠近所述显示区的一侧。
在一些实施例中，所述显示基板还具有位于所述弯折区和所述芯片安装区之间的电路测试区；所述第二扇出区位于所述电路测试区与所述芯片安装区之间。
在一些实施例中，所述转接线呈U形或近似U形。
在一些实施例中，所述显示基板沿所述第二方向延伸的中轴线定义为第一中轴线；所述第二扇出区位于第一中轴线一侧的区域为一个子扇出区；在所述子扇出区中：多条所述转接线呈辐射状排布；其中，相邻的两条所述转接线中，位于外侧的转接线围绕位于内侧的转接线设置。
在一些实施例中，相邻的两条所述转接线位于不同的导电层中。
在一些实施例中，所述显示基板沿所述第二方向延伸的中轴线定义为第一中轴线；所述第二扇出区位于第一中轴线一侧的区域为一个子扇出区；在所述子扇出区中：所述第一扇出线还包括依次远离所述显示区且彼此电连接的第一走线段和第二走线段；所述第一走线段自靠近所述显示区的一端至远离所述显示区的一端，逐渐靠近所述第一中轴线；所述第二走线段与所述第一中轴线平行；所述第二扇出线包括依次远离所述显示区且彼此电连接的第三走线段和第四走线段；所述第三走线段自靠近所述显示区的一端至远离所述显示区的一端，逐渐靠近所述第一中轴线；所述第四走线段与所述第一中轴线平行；其中，所述转接线靠近所述第一中轴线的所述连接端部与所述第二走线段远离所述第一走线段的端部电连接。
在一些实施例中，在所述子扇出区中：多条所述第一走线段与多条所述第三走线段交替布置；所述第一走线段远离所述显示区的端部和所述第三走线段远离所述显示区的端部所限定的拟合直线，自远离所述第一中轴线的一端至靠近所述第一中轴线的一端，逐渐靠近所述显示区。
在一些实施例中，在所述子扇出区中：多条所述第二走线段中，直接相邻的所述第二走线段为同一组，同一组中的所述第二走线段远离所述显示区的端部沿所述第一方向错开设置。
在一些实施例中，在所述子扇出区中：相邻的两条所述第二走线段中，靠近所述第一中轴线的所述第二走线段的长度，小于远离所述第一中轴线的所述第二走线段的长度；相邻的两条所述转接线中，靠近所述第一中轴线的 所述转接线中用于连接所述第二走线段的所述连接端部，相对于远离所述第一中轴线的所述转接线中用于连接所述第二走线段的所述连接端部，更靠近所述显示区。
在一些实施例中，所述主体部包括第一转接段；所述第一转接段与所述转接线中连接所述第二走线段的所述连接端部相连；所述第一转接段在所述衬底上的正投影与对应连接的所述第二走线段在所述衬底上的正投影重叠或大致重叠。
在一些实施例中，所述主体部还包括与所述第一转接段连接的第二转接段，以及与所述第二转接段连接的第三转接段。所述多层导电层中还包括：隔离块，位于所述第一走线段和所述第三走线段远离所述衬底的一侧，且所述隔离块覆盖所述第一走线段和所述第三走线段；其中，所述转接线位于所述隔离块远离所述衬底的一侧；所述第二转接段在所述衬底上的正投影位于所述隔离块在所述衬底上的正投影内；所述第一转接段和所述第三转接段两者在所述衬底上的正投影均位于所述隔离块在所述衬底上的正投影外。
在一些实施例中，所述多层导电层中包括：至少两层栅金属层和至少两层源漏金属层。所述至少两层源漏金属层均位于所述至少两层栅金属层远离所述衬底的一侧。所述第一走线段、所述第二走线段、所述第三走线段和所述第四走线段位于所述至少两层栅金属层中，所述隔离块位于所述至少两层源漏金属层中相对靠近所述衬底的源漏金属层，所述转接线位于所述至少两层源漏金属层中相对远离所述衬底的源漏金属层。
另一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的结构图；
图2为根据一些实施例的显示面板的结构图；
图3为根据一些实施例的显示基板的结构图；
图4为子像素中发光器件与像素驱动电路连接结构的结构图；
图5为根据另一些实施例的显示基板的结构图；
图6为根据又一些实施例的显示基板的结构图；
图7为根据又一些实施例的显示基板的结构图；
图8为根据一些实施例的显示基板的局部结构图；
图9为图8中第一栅金属层、第二栅金属层和第一源漏金属层的结构图；
图10为图8中第二源漏金属层和第三源漏金属层的结构图；
图11为图8中区域001的局部结构图；
图12～图17为图11中各个膜层的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或 元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
图1为根据一些实施例的显示装置的结构图。
如图1所示，本公开的一些实施例提供了一种显示装置200。可以理解地，显示装置200为具有图像显示功能的产品。示例的，显示装置200可以用于显示静态图像，例如图片或者照片。显示装置200也可以用于显示动态图像，例如视频或者游戏画面。
在一些示例中，显示装置200可以为笔记本电脑、移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
显示装置200包括显示面板210。在一些示例中，显示面板210为有机发光二极管显示器(英文全称：Organic Light-Emitting Diode，英文简称：OLED)或量子点电致发光显示器(Quantum Dot Light-Emitting Diodes，简称QLED)。
除此之外，显示装置200还可以包括屏下摄像头以及屏下指纹识别传感器等，使得显示装置能够实现拍照、录像、指纹识别或者人脸识别等多种不同功能。
图2为根据一些实施例的显示面板的结构图。
显示面板210包括显示基板100。示例的，如图2所示，显示面板210还可以包括位于显示基板100显示侧的其他功能膜层211，例如触控功能层、减反射层、抗指纹层、硬化层以及封装盖板等，使得显示面板210能够实现不同的功能。
本公开的实施例对显示面板210的其他功能膜层211不做进一步限定。下面对显示基板100进行举例说明。
图3为根据一些实施例的显示基板的结构图。
在一些示例中，如图3所示，显示基板100包括多个子像素101。多个子像素101沿第一方向X排列成多列，且沿第二方向Y排列成多行。在一些示例中，第一方向X和第二方向Y相交叉。示例的，第一方向X与第二方向Y垂直。在一些示例中，第一方向X为水平方向，第二方向Y为竖直方向。
可以理解地，子像素101是显示基板100进行画面显示的最小单元。每个子像素101可显示一种单一的颜色，例如红色、绿色或蓝色。显示基板100可以包括多个红色子像素、多个绿色子像素和多个蓝色子像素。通过调节不同颜色的子像素101的亮度(灰阶)，即可得到不同强度的红光、绿光和蓝光，而不同强度的红光、绿光和蓝光中的至少两者进行叠加，又可以显示出更多颜色的光，从而实现了显示基板100的全彩化显示。
可以理解地，如图3所示，显示基板100具有显示区AA和扇出区(英文全称：Fanout)BB，扇出区BB与显示区AA的一侧边缘邻接。其中，显示区AA用于显示图像信息，多个子像素101位于显示基板100的显示区AA。
需要说明的是，扇出区BB与显示区AA的一侧边缘邻接，也即是扇出区BB靠近显示区AA的一侧边缘，与显示区AA靠近扇出区BB的一侧边缘相重合。本公开的说明书附图中，以图3为例，扇出区BB的边缘与显示区AA的边缘相互分离，仅仅是为了便于示出显示区AA和扇出区BB，不对显示区AA和扇出区BB做进一步限定。
在一些示例中，如图3所示，扇出区BB沿第二方向Y位于显示区AA的一侧。
在一些示例中，如图3所示，扇出区BB与显示区AA的下边缘邻接。也即是，扇出区BB沿第二方向Y位于显示区AA的下方。示例性的，当显示装置200在垂直于或者近似垂直于地面的状态下使用时，扇出区BB相对于显示区AA更靠近地面。
在一些示例中，每个子像素101包括发光器件300和像素驱动电路，像素驱动电路与发光器件300电连接，用于驱动发光器件300发光。
图4为子像素中发光器件与像素驱动电路连接结构的示意图。
在一些示例中，如图4所示，显示基板100包括衬底102和多层导电层103。多层导电层103位于衬底102的同一侧。多层导电层103层叠设置。
在一些示例中，衬底102为柔性材料，使得显示基板100能够弯曲， 从而使得显示面板210能够实现曲面显示、折叠显示或滑卷显示等功能。在另一些示例中，衬底102为硬性材料。
示例的，衬底102的材料可以为聚酰亚胺(英文全称：Polyimide，英文简称：PI)、聚碳酸酯(英文全称：polycarbonate，英文简称：PC)或者聚氯乙烯(英文全称：polyvinyl chloride，英文简称：PVC)中的任一个。
在一些示例中，多层导电层103之间可以设置有绝缘层(例如栅绝缘层和缓冲层、钝化层、有机层等)，起到对于相邻的两层导电层103进行电隔离的作用。
示例的，像素驱动电路设置在多层导电层103中。在一些示例中，如图4所示，多层导电层103包括依次远离衬底102的有源膜层1031、至少一层栅金属层Gate(如第一栅金属层Gate1、第二栅金属层Gate2和第三栅金属层(图中未示出，可位于第二栅金属层Gate2与第一源漏金属层SD1之间))、至少一层源漏金属层(如第一源漏金属层SD1、第二源漏金属层SD2和第三源漏金属层(图中未示出，可位于第二源漏金属层SD2与阳极层AND之间))等。
示例的，任一层栅金属层Gate可以包括钼材料。任一层源漏金属层可以包括钛/铝/钛复合叠层结构。
像素驱动电路包括多个薄膜晶体管(英文全称：Thin Film Transistor，英文简称：TFT)和至少一个电容。示例的，有源膜层1031和第一栅金属层Gate1可以用于形成多个薄膜晶体管中的一部分薄膜晶体管(一个、两个或者更多个)，有源膜层1031和第二栅金属层Gate2可以用于形成多个薄膜晶体管中的另一部分薄膜晶体管(一个、两个或者更多个)。第一栅金属层Gate1和第二栅金属层Gate2可以用于形成至少一个电容。
需要说明的是，此处并不对有源膜层1031的数量进行限定，例如，本公开的一些实施例中可以仅包括一层有源膜层1031，该有源膜层1031的材料可以包括金属氧化物、也可以包括低温多晶硅。或者，本公开的一些实施例中还可以包括两层有源膜层1031，其中，一层有源膜层1031的材料包括金属氧化物，另一层有源膜层的材料包括低温多晶硅。
由上述一些实施例可知，显示基板100还包括发光器件300，像素驱动电路与发光器件300电连接。下面继续参照图4，对发光器件300进行举例说明。
在一些示例中，发光器件300位于所述多层导电层103远离衬底102的一侧。示例的，发光器件300包括沿远离衬底102的方向依次设置的阳极层AND、发光层EML和阴极层CTD。
在一些示例中，发光层EML包括多个间隔设置的有效发光部，可以理解地，有效发光部用于发光。示例的，有效发光部包括电致发光材料。可以理解地，电致发光指的是有机半导体材料在电场驱动下，通过载流子注入、传输、电子和空穴结合形成激子，进而辐射复合导致发光的现象。
可以理解地，多个有效发光部中的一部分用于发红光，另一部分用于发绿光，又一部分用于发蓝光。示例的，可以选择不同的电致发光材料，使得有效发光部能够发不同颜色的光。可以理解地，发红光的有效发光部、发绿光的有效发光部和发蓝光的有效发光部三者的数量可以相同，也可以不同。
示例的，发红光的有效发光部、发绿光的有效发光部和发蓝光的有效发光部可以混合阵列排布，这样一来，通过控制发不同的有效发光部的发光强度，就能够得到不同强度的红光、绿光和蓝光。将不同强度的红光、绿光和蓝光混合，即可使得显示基板100显示彩色图像。
可以理解地，像素驱动电路能够驱动发光层EML发光。在一些示例中，一个像素驱动电路通过阳极层AND与一个有效发光部电连接，使得各个像素驱动电路能够通过阳极层AND，分别向各个有效发光部提供驱动电流，也即是使得多个有效发光部进行独立发光，减小多个有效发光部之间的相互干扰，提高显示基板100的显示效果。可以理解地，通过调节像素驱动电路向有效发光部提供的驱动电流的大小，能够对有效发光部的发光亮度起到调节作用。
在一些示例中，阳极层AND为金属材料，例如铜或者银等。阴极层CTD为透明材料，例如透明氧化铟锡(英文全称：Indium Tin Oxide，英文简称：ITO)或者透明氧化铟锌(英文全称：Indium Zinc Oxide，英文简称：IZO)等，使得有效发光部发射的光线能够经由阴极层CTD射出，即此时显示基板100为顶发光显示基板。
在另一些示例中，阳极层AND为透明材料，例如ITO或者IZO等，阴极层CTD为金属材料，例如铜或者银等，使得有效发光部发射的光线能够经由阳极层AND射出，即此时显示基板100为底发光显示基板。
在又一些示例中，阳极层AND和阴极层CTD均为透明材料，例如ITO或者IZO等，使得有效发光部发射的光线可以经由阳极层AND和阴极层CTD射出，即此时显示基板100为双面发光显示基板。
在一些示例中，基于功函数考虑，阳极层AND的材料包括ITO、或者ITO-Ag-ITO的叠层，使得阳极层AND能够提供更多的空穴。阴极层CTD的材料包括MgAg，使得阴极层CTD能够提供更多的电子。阴极层CTD的厚度很薄，可透光，使得显示基板100能够实现顶发射。
在一些示例中，沿阳极层AND至有效发光部的方向，在阳极层AND和有效发光部之间设置有空穴注入层(英文全称：Hole Inject Layer，英文简称：HIL)、空穴传输层(英文全称：Hole Transport Layer，英文简称：HTL)和电子阻挡层(英文全称：Electron Blocking Layer，英文简称：EBL)中的至少一个。沿阴极层CTD至有效发光部的方向，在阴极层CTD和有效发光部之间设置有电子注入层(英文全称：Electron Inject Layer，英文简称：EIL)、电子传输层(英文全称：Electron Transport Layer，英文简称：ETL)和空穴阻挡层(英文全称：Hole Blocking Layer，英文简称：HBL)中的至少一个。上述设置方式，提高了有效发光部的发光可靠性。
图5为根据另一些实施例的显示基板的结构图。
在一些示例中，如图5所示，显示基板100还包括封装层104。封装层104位于发光器件300远离衬底102的一侧，并且能够覆盖发光器件300，将发光器件300包覆起来，以避免外界环境中的水汽和氧气进入发光器件300，起到保护发光器件300的作用。
图6为根据又一些实施例的显示基板的结构图。
在一些实施例中，在一些示例中，如图6所示，多层导电层103除了包括像素驱动电路之外，还包括多条数据线110和多条扇出线130。可以理解地，多条数据线110位于显示区AA，且与多个像素驱动电路电连接，用于将驱动信号传输至像素驱动电路，使得像素驱动电路能够驱动发光器件300发光，实现不同灰阶的显示。多条扇出线130位于扇出区BB，且与多条数据线110一一对应地电连接。
示例的，如图6所示，多条数据线110沿第一方向X间隔排布、且多条数据线110均沿第二方向Y延伸，第二方向Y与第一方向X相交叉，并且，第一方向X和第二方向Y可以均平行于衬底102。
在一些示例中，第一方向X和第二方向Y相垂直或者近似相垂直。示例的，如图6所示，第一方向X为水平方向，第二方向Y为竖直方向。
由上述可知，如图3所示，多个子像素101沿第一方向X排列成多列，且沿第二方向Y排列成多行，也即是，多个子像素101中的像素驱动电路能够沿第一方向X和第二方向Y，呈多行和多列阵列排布。如图6所示，多条数据线110沿第二方向Y延伸，这样一来，使得一条数据线110能够与沿第二方向Y排布的一列子像素101中的像素驱动电路电连接，以向一列子像素101中的像素驱动电路提供数据电压。
在一些示例中，多条数据线110沿第一方向X的间隔距离相同或者近似相 同。
可以理解地，如图6所示，扇出区BB沿第二方向Y，与显示区AA的一侧边缘邻接，因此，设置多条数据线110沿第二方向Y延伸，使得多条数据线110能够与位于扇出区BB内的多条扇出线130一一对应地电连接。
示例的，如图6所示，位于扇出区BB内的多条扇出线130逐渐靠近并收拢，并延伸至扇出区BB远离显示区AA的一侧，便于多条扇出线130与显示基板100外部的驱动芯片(英文全称：Integrated Circuit，英文简称：IC)电连接。可以理解地，驱动IC能够通过多条扇出线130和多条数据线110，向各个像素驱动电路输入信号。
在一些示例中，多条扇出线130远离显示区AA的一侧，延伸至扇出区BB远离显示区AA的一侧边缘，使得多条扇出线130能够与驱动IC电连接。
但是，上述实现方式，会增大多条扇出线130沿第二方向Y的占用空间，从而导致扇出区BB的宽度增大，也即是导致显示面板210的侧边框(例如下边框)宽度增大，不利于显示面板210实现窄边框，影响显示面板210的视觉效果。
在一些示例中，多条扇出线130位于至少一层栅金属层gate(如第一栅金属层gate1、第二栅金属层gate2和第三栅金属层)。栅金属层gate包括钼材料，钼材料的电阻较大。在此基础上，如图6所示，位于沿第一方向X两端区域的扇出线130的长度较长，导致位于沿第一方向X两端区域的数据线110上的电阻比较大，容易降低显示基板100沿第一方向X两端区域的显示亮度。并且，如图6所示，由于位于沿第一方向X两端区域的扇出线130的长度明显大于位于第一方向X中间区域的扇出线130的长度，还会导致位于沿第一方向X两端区域的数据线110与位于第一方向X中间区域的数据线110之间的电阻差异增大，因此，容易导致显示基板100沿第一方向X中间区域的显示亮度，高于显示基板100沿第一方向X两端区域的显示亮度，从而影响显示基板100的显示画面亮度均匀性。
图7为根据又一些实施例的显示基板的结构图。
本公开的一些实施例提供的一种显示基板100，如图7所示，显示基板100包括显示区AA和扇出区BB。扇出区BB与显示区AA的一侧边缘邻接。显示基板100包括衬底102和多层导电层103(如图4所示)，多层导电层103位于衬底102的同一侧，且多层导电层103层叠设置。多层导电层103中包括多条数据线110。多条数据线110沿第一方向X间隔排布、且多条数据线110均沿第二方向Y延伸，第二方向Y与第一方向X相交叉。
需要说明的是，本公开的上述实施例已经对显示区AA、扇出区BB、衬底102、多层导电层103以及多条数据线110等进行了举例说明，在此不再赘述。此外，参阅图7，显示基板100还可以包括多条扫描控制信号线105，多条扫描控制信号线105沿第二方向Y间隔排布，且均沿第一方向X延伸，这样一来，使得一条扫描控制信号线105能够与沿第一方向X排布的一行子像素101中的像素驱动电路电连接，以控制一行子像素101中的像素驱动电路的工作状态。
下面继续参照图7，对本公开的一些实施例提供的显示基板100进行举例说明。
在一些示例中，如图7所示，多条数据线110包括多条第一数据线111和多条第二数据线112。多条第一数据线111位于显示区AA沿第一方向X的两个边缘区域AA1，多条第二数据线112位于显示区AA沿第一方向X的中心区域AA2。
示例的，如图7所示，边缘区域AA1的数量为两个，两个边缘区域AA1沿第一方向X位于显示基板100的两侧区域，中心区域AA2沿第一方向X，位于两个边缘区域AA1之间。
示例的，第一数据线111和第二数据线112的数量可以相同，也可以不同。并且，位于两个边缘区域AA1内的第一数据线111的数量可以相同，也可以不同。
需要说明的是，本公开的各个实施例中，第一数据线111和第二数据线112仅用于区分位于边缘区域AA1和中心区域AA2内的数据线110，不对数据线110的其他方面做进一步限定。
示例的，沿第一方向X，显示区AA的两个边缘区域AA1的宽度相同或者近似相同。在一些示例中，如图7所示，显示区AA包括圆角，也即是显示区AA相邻的两条边缘之间呈圆弧状或者近似圆弧状相连接。圆角位于显示区AA的边缘区域AA1内。示例的，边缘区域AA1在第一方向X上的宽度尺寸可以大于或等于圆角在第一方向X上的宽度尺寸。
示例的，多条第一数据线111和多条第二数据线112位于同一层导电层103中。例如，多条第一数据线111和多条第二数据线112均位于第一源漏金属层SD1上。又例如，多条第一数据线111和多条第二数据线112均位于第二源漏金属层SD2上。再例如，多条第一数据线111和多条第二数据线112也可以位于除了第一源漏金属层SD1和第二源漏金属层SD2以外的其他导电层103(例如第三源漏金属层)上。
如图7所示，所述多层导电层103还包括多条连接线120。一条连接线 120的第一端(即图7中的箭头端)位于显示区AA的边缘区域AA1，且与一条第一数据线111电连接。连接线120的第二端(即图7中箭头端的对端)延伸至显示区AA的中心区域AA2与扇出区BB之间的交界处。
示例的，如图7所示，多条连接线120中的任一条连接线120的第二端，均延伸至显示区AA的中心区域AA2。
由上述可知，显示区AA靠近扇出区BB的一侧边缘，可以与扇出区BB靠近显示区AA的一侧边缘相重合。连接线120的第二端延伸至中心区域AA2和扇出区BB交界处。可以理解为，连接线120的第二端，可以位于中心区域AA2和扇出区BB之间的分界线上；或者，也可以与该分界线之间具有较小的间隙，例如几微米的间隙，此时，连接线120的第二端可以位于分界线靠近显示区AA一侧，也可以位于分界线靠近扇出区BB一侧。
如图7所示，至少一条连接线120跨过至少一条数据线110(例如第一数据线111和/或第二数据线112)，且与所跨过的数据线110绝缘。
可以理解地，由于多条数据线110沿第一方向X间隔排布，使得一些连接线120的第二端在延伸至中心区域AA2与扇出区BB之间的交界处时，需要跨过至少一条数据线110。例如，至少一条连接线120可以同时跨过第一数据线111和第二数据线112。又例如，至少一条连接线120可以仅跨过第一数据线111(未图示)。又例如，至少一条连接线120可以仅跨过第二数据线112(未图示)。
此外，结合图7所示，显示基板100中还可以包括不跨过任何数据线110的连接线120，例如图7中沿第一方向X由左至右排列的第1根连接线120和最后1根连接线120。
可以理解地，连接线120跨过至少一条数据线110，也即是，连接线120在衬底102上的正投影，与至少一条数据线110在衬底102上的正投影相交。
在一些示例中，连接线120和数据线110位于不同的导电层103，使得连接线120能够与跨过的数据线110绝缘。
示例的，数据线110位于第一源漏金属层SD1，连接线120位于第二源漏金属层SD2。或者，数据线110位于第二源漏金属层SD2，连接线120位于第三源漏金属层。
示例的，当连接线120和数据线110位于不同的导电层103时，连接线120的第一端可以通过转接孔，与第一数据线111电连接。可以理解地，转接孔沿垂直于或者近似垂直于衬底102的方向，贯穿相邻的两层导电层103之间的绝缘膜层，使得不同的导电层103能够电连接，也即是使得位于不同的导电层103上的导电走线(例如连接线120和数据线110)能够电连接。示例的，当两层 导电层103不相邻时，可以通过多个转接孔，使得位于不同的导电层103上的导电走线能够电连接。
示例的，为了便于说明，可以将电连接第一源漏金属层SD1上的导电走线和第二源漏金属层SD2上的导电走线的转接孔称为PLN1孔，将电连接第二源漏金属层SD2上的导电走线和第三源漏金属层上的导电走线的转接孔称为PLN2孔。
也即是，当第一数据线111位于第一源漏金属层SD1，连接线120位于第二源漏金属层SD2时，连接线120的第一端通过PLN1孔，与第一数据线111电连接。当第一数据线111位于第二源漏金属层SD2，连接线120位于第三源漏金属层时，连接线120的第一端通过PLN2孔，与第一数据线111电连接。
由上述可知，在一些示例中，连接线120和数据线110位于不同的导电层103，使得连接线120能够与所跨过的数据线110绝缘。在另一些示例中，连接线120包括主体部分和跳线部分。其中，主体部分和跳线部分可以通过转接孔电连接。主体部分可以与数据线110位于同一导电层103，而跳线部分可以与数据线110位于不同的导电层103，以使得跳线部分能够跨过至少一条数据线110，并且与所跨过的数据线110绝缘。
如图7所示，至少一条连接线120的第二端位于相邻的两条第二数据线110之间。也即是，可以将一条连接线120的第二端设置于相邻的两条第二数据线112之间，也可以两条或者更多条连接线120的第二端设置于相邻的两条第二数据线112之间。
可以理解地，如图7所示，对于任意一组相邻的两条第二数据线112之间，可以设置有一条连接线120的第二端，也可以设置有两条或者更多条连接线120的第二端，还可以不设置有连接线120的第二端。不同的相邻两条第二数据线112之间设置的连接线120的第二端的数量可以相同，也可以不同。
如图7所示，将连接线120的第二端设置在相邻的两条第二数据线112之间，使得连接线120的第二端能够通过相邻的两条第二数据线112之间的间隔，延伸至中心区域AA2与扇出区BB之间的交界处。
可以理解地，连接线120的数量与第一数据线110的数量，可以相同，也可以不同。在一些示例中，连接线120的数量与第一数据线110的数量相同。多条连接线120与多条第一数据线111，两者一一对应地连接。在另一些示例中，连接线120的数量小于第一数据线111的数量，此时，所有连接线120可以与一部分第一数据线111一一对应地连接，而另一部分第一数据线111可以不与连接线120连接。
在一些示例中，如图7所示，连接线120包括第一子连接线121和第二子连接线122。第一子连接线121的一端位于边缘区域AA1，且与第一数据线111电连接。第一子连接线121的另一端延伸至中心区域AA2。第二子连接线122的一端与第一子连接线121远离第一数据线111的一端电连接，第二子连接线122的另一端延伸至中心区域AA2与扇出区BB之间的交界处。示例的，第一子连接线121沿第一方向X延伸，第二子连接线122沿第二方向Y延伸，第一子连接线121和第二子连接线122垂直或者近似垂直。
由上述可知，在一些示例中，连接线120包括主体部分和跳线部分。示例的，如图7所示，当连接线120包括第一子连接线121和第二子连接线122时，可以设置第二子连接线122为主体部分，主体部分与多条数据线110位于同一导电层103，第一子连接线121为跳线部分，跳线部分与多条数据线110位于不同的导电层103。第一子连接线121能够跨过至少一条数据线110，且与所跨过的数据线110绝缘。此外，在另一些示例中，还可以设置第二子连接线122为主体部分，第一子连接线121中同时包括主体部分和跳线部分，其中，跳线部分用于跨过数据线110。
在一些示例中，跳线部分相对于多条数据线110更远离衬底102，这样可以减小跳线部分与栅金属层Gate(例如第一栅金属层Gate1、第二栅金属层Gate2和第三栅金属层等)之间产生的寄生电容，提高信号的传输可靠性。
如图7所示，多层导电层103还包括多条扇出线130。多条扇出线130位于扇出区BB。多条扇出线130包括多条第一扇出线131和多条第二扇出线132。第一扇出线131与连接线120的第二端电连接，第二扇出线132与第二数据线112靠近扇出区BB的一端电连接。
需要说明的是，由于数据线110和连接线120，均可以位于显示区AA，因此，在扇出线130与数据线110(或连接线120)不同层设置，且相互电连接时，两者的转接位置可能会位于显示区AA内，此时，仍可以认为扇出线130是满足位于扇出区BB这一条件的。
第一扇出线131的数量和连接线120的数量相同，使得多条第一扇出线131能够与多条连接线120，一一对应地电连接。第二扇出线132的数量和第二数据线112的数量相同或不同。
示例的，在所有的第一数据线111与多条连接线120一一对应地电连接的情况下，第二扇出线132的数量和第二数据线112的数量相同，多条第二扇出线132与多条第二数据线112，一一对应地电连接。
而在所有的第一数据线111中的一部分第一数据线111与多条连接线120 一一对应地电连接的情况下(也即是当第一数据线111的数量大于连接线120的数量时)，第二扇出线132的数量和第二数据线112的数量不同。此时，多条第二扇出线132中的一部分第二扇出线132(两条或者更多条)与第二数据线112一一对应地电连接，而另一部分第二扇出线132(两条或者更多条)则可以与没有和连接线120电连接的第一数据线111一一对应地电连接。
可以理解地，上述扇出线130(包括第一扇出线131和第二扇出线132)的数量可以与数据线110(包括第一数据线111和第二数据线112)的数量相同。驱动IC输出的信号能够通过一条扇出线130传输至与该扇出线130电连接的一条数据线110，从而实现对于一列子像素101的驱动。
示例的，如图7所示，显示基板100沿第二方向Y延伸的中轴线定义为第一中轴线Q，也即第一中轴线Q位于显示基板100沿第一方向X的中心，且平行于衬底102。可以理解地，第一中轴线Q为虚拟参考线，第一中轴线Q位于显示基板100的中心区域AA2内。
可以理解地，如图7所示，由于连接线120的第二端延伸至所述中心区域AA2与扇出区BB之间的交界处，这样一来，多条第一扇出线131能够在更靠近显示基板100的第一中轴线Q的位置，与连接线120的第二端电连接。
如此设置，能够减小多条扇出线130在扇出区BB聚拢、并向远离显示区AA的方向延伸时，沿第二方向Y的占用空间。从而，能够减小扇出区BB在第二方向Y的宽度，例如，可以明显减小第一扇出区BB1在第二方向Y的宽度。因此能够减小显示面板210的侧边框(例如下边框)的宽度，使得显示面板210能够实现超窄下边框，提高显示面板210的视觉效果。
此外，由上述可知，圆角位于显示区AA的边缘区域AA1内。故而，采用上述设置方式，使得圆角位置处的第一数据线111，能够通过连接线120与第一扇出线131电连接，避免了第一扇出线131占用靠近圆角位置处的扇出区BB的空间，从而能够减小圆角处的边框宽度，使得显示面板210的显示区AA能够实现超大圆角。这样一来，一方面，能够提高显示面板210的视觉效果，另一方面，还能够提高显示面板210外部的边框与显示面板210之间的安装便捷性，减小在安装时边框受到的应力，降低安装应力导致边框褶皱甚至碎裂的风险，提高显示装置200的加工便捷性，提高显示装置200的良品率。
此外，由于位于边缘区域AA1内的第一数据线111，能够通过连接线120与第一扇出线131电连接，还有利于减小与第一数据线111电连接的第一扇出线131的长度(例如图7所示的方案中，第一扇出线131包括第一子扇出线133，沿第一方向X由左至右排列的第1～3根第一子扇出线133，在通过连 接线130与第一数据线111连接时，第3根第一子扇出线133的缩短量大于第2根第一子扇出线133的缩短量，而第2根第一子扇出线133的缩短量大于第1根第一子扇出线133的缩短量)，从而有利于减小第一扇出线131的电阻，也即可以减小第一数据线111上的电阻，提高与第一数据线111电连接的子像素的亮度。与此同时，由于第二扇出线132的长度不变，也即电阻基本不变，而第一扇出线131的长度减小后，可以更接近第二扇出线132的长度，继续参阅图7，第二扇出线132包括第三子扇出线136，以上述第3根第一子扇出线133为例，由于该第3根第一子扇出线133缩短后的长度，小于其左侧(图示方位)相邻的第三子扇出线136的长度，因此该第3根第一子扇出线133的电阻小于其左侧相邻的第三子扇出线136的电阻。在此基础上，由于该第3根第一子扇出线133还连接有连接线120，而连接线120位于电阻很小的源漏金属层SD(可以包括钛/铝/钛叠层结构)，因此，该第3根第一子扇出线133和连接线120上的总电阻，可以略小于或等于该第3根第一子扇出线133左侧相邻的第三子扇出线136的电阻，也即是：该第3根第一子扇出线133所电连接的第一数据线111上的电阻，略小于或等于该第3根第一子扇出线133左侧(图示方位)相邻的第三子扇出线136所电连接的第二数据线112上的电阻，因此，还有利于第一数据线111与第二数据线112之间的电阻差异，提高显示画面的亮度均一性。
值得说明的是，虽然第一扇出线131与第一数据线111之间还增加了连接线120，但由于连接线120位于至少一层源漏金属层SD中，而源漏金属层SD包括钛/铝/钛复合叠层结构，相较于栅金属层Gate(包括钼材料)而言，电阻会小很多，例如可以为十分之一。因此，增加连接线120，虽然会导致第一数据线111上的电阻略微增加，但所增加的电阻远小于通过缩短第一扇出线131所减小的电阻。因此，上述一些实施例中，还是有利于减小第一数据线111上的电阻，平衡第一数据线111与第二数据线112之间的电阻差异，从而提高显示画面的亮度均匀性。
示例的，可以将上述增加连接线120的扇出方式称为FIAA(英文全称：Fanout In AA，中文名称：显示区扇出)或者FIP(英文全称：Fanout In Panel，中文名称：面板中扇出)。
由上述可知，在一些示例中，如图7所示，可以设置连接线120的数量与第一数据线110的数量相同，此时，第一数据线111与连接线120一一对应地连接。示例的，可以将该设置方式称为全部FIAA。
在另一些示例中，还可以设置一部分第一数据线111与连接线120与一一 对应地连接，而另一部分第一数据线111可以不与连接线120连接，例如可以与第二数据线112一样，直接通过第二扇出线132引出。如此设置，有利于减小多条数据线110之间的间隔，提高显示区AA的像素密度，使得显示面板210能够实现高PPI(英文全称：Pixels Per Inch，中文名称：每英寸像素数)。示例的，可以将该设置方式称为部分FIAA。
综上所述，采用全部FIAA或者部分FIAA的方式，使得显示面板210能够在高分辨率的基础上实现窄边框。在一些示例中，显示面板可以是QHD(英文全称：Quad High Definition，中文名称：四倍高清)显示面板。
继续参阅图7，在一些实施例中，任意两条相邻的连接线120可以定义为第一连接线120a和第二连接线120b。可以理解地，本实施例中，第一连接线120a和第二连接线120b仅用于区分相邻的两条连接线120，不对连接线120做进一步限定。
在一些示例中，如图7所示，与第一连接线120a的第一端电连接的第一数据线111，相对于与第二连接线120b的第一端电连接的第一数据线111更远离显示基板100的第一中轴线Q。并且，第一连接线120a的第二端相对于第二连接线120b的第二端更靠近显示基板的第一中轴线Q。示例的，可以将上述连接方式称为逆序FIAA。
而在另一些示例中，与第一连接线120a的第一端电连接的第一数据线111，相对于与第二连接线120b的第一端电连接的第一数据线111更靠近显示基板100的第一中轴线Q。并且，第一连接线120a的第二端相对于第二连接线120b的第二端更靠近显示基板100的第一中轴线Q。示例的，可以将上述连接方式称为正序FIAA。
可以理解地，第一数据线111通过连接线120，与第一扇出线131电连接(例如采用上述逆序FIAA或正序FIAA)时，会导致多条扇出线130(包括第一扇出线131和第二扇出线132)远离显示区AA的一端(例如与驱动IC电连接的一端)沿第一方向X的排列顺序，与多条数据线110(包括第一数据线111和第二数据线112)沿第一方向X的排列顺序不同。
示例的，可以将显示基板100在第一方向X上一个边缘定义为第一边缘。可以理解地，第一边缘为显示基板100在第一方向X上两个边缘中的任一个。
示例的，可以将沿显示基板100的第一边缘至显示基板100的第一中轴线Q方向，间隔排布的多条数据线110(包括第一数据线111和第二数据线112)定义为数据线1～数据线n。其中，数据线1～数据线m(m＜n)位于边缘区域AA1，数据线m+1～数据线n位于中心区域AA2。也即是，数据线1～数据线m为第一数 据线111，数据线m+1～数据线n为第二数据线112。
由上述可知，连接线120的第一端与第一数据线111电连接，并且至少一条连接线120的第二端位于相邻的两条第二数据线112之间。示例的，与数据线1电连接的连接线120的第二端，能够位于数据线m+1和数据线m+2之间(正序FIAA)，或者，与数据线1电连接的连接线120的第二端，能够位于数据线n-1和数据线n之间(逆序FIAA)。也即是，连接线120的第二端会插入在相邻的两条第二数据线112(例如数据线m+1和数据线m+2)之间。
这样一来，当第一扇出线131与连接线120的第二端电连接，第二扇出线132与第二数据线112靠近扇出区BB的一端电连接时，会导致至少一条第一扇出线131插入在相邻的两条第二扇出线132之间。
示例的，可以将与数据线1～数据线n一一对应地电连接的多条扇出线130(包括第一扇出线131和第二扇出线132)，定义为扇出线1～扇出线n。扇出线1与数据线1电连接，扇出线2与数据线2电连接，以此类推。
由于至少一条第一扇出线131插入在相邻的两条第二扇出线132之间，这样一来，导致扇出线1～扇出线n远离显示区AA的一端(也即是多条扇出线130与驱动IC电连接的一端)，沿第一边缘至第一中轴线Q方向不能够按顺序排布。
由上述可知，沿第一边缘至第一中轴线Q方向，数据线1～数据线n间隔排布。也即是，采用全部FIAA或者部分FIAA的方式布线，会导致多条扇出线130(包括第一扇出线131和第二扇出线132)远离显示区AA的一端沿第一方向X的排列顺序，与多条数据线110(包括第一数据线111和第二数据线112)沿第一方向X的排列顺序不同。
示例的，驱动IC具有输出端，驱动IC的输出端沿第一方向X的排列顺序，与多条数据线110沿第一方向X的排列顺序相同。可以理解地，由于多条扇出线130(包括第一扇出线131和第二扇出线132)远离显示区AA的一端沿第一方向X的排列顺序，与多条数据线110(包括第一数据线111和第二数据线112)沿第一方向X的排列顺序不同，会导致驱动IC的输出端无法按顺序向多条数据线110输出驱动信号，也即是使得驱动IC无法按顺序驱动多列子像素101发光。而重新开发驱动IC成本较高，导致显示面板210的成本增大。
在一些实施例中，如图7所示，显示基板100还具有弯折区(英文全称：Bending)CC。扇出区BB包括第一扇出区BB1和第二扇出区BB2，第一扇出区BB1相对于第二扇出区BB2更靠近显示区AA，弯折区CC位于第一扇出区BB1和第二扇出区BB2之间。
示例的，衬底102为柔性衬底。弯折区CC内设置有衬底102和多层导电层 103中的至少一层。衬底102和多层导电层103中的至少一层能够在弯折区CC进行弯折。
在一些示例中，弯折区CC内设置有衬底102和第二源漏金属层SD2。弯折区CC位于第一扇出区BB1和第二扇出区BB2之间，使得第二扇出区BB2可以弯折至显示基板100位于显示区AA的部位的背面，避免了第二扇出区BB2占用显示基板100的显示侧的空间，从而能够进一步减小显示面板210的侧边框(例如下边框)的宽度，提高显示面板210的视觉效果。
在一些实施例中，如图7所示，显示基板100还包括芯片安装(英文全称：Chip On Panel，英文简称：COP)区。COP区用于安装驱动IC。第二扇出区BB2位于弯折区CC与COP区之间。
在一些示例中，如图7所示，显示基板100还包括电路测试(英文全称：Cell Test，英文简称：CT)区。CT区用于测试显示基板100。此时，第二扇出区BB2可以位于CT区与COP区之间。需要说明的是，此时，CT区与弯折区CC之间的间距，可以为0(即，可以没有图7所示的中间扇出区BB0)，也可以不为0(即，可以有图7所示的中间扇出区BB0)。
此外，在包含中间扇出区BB0时，中间扇出区BB0可以作为第二扇出区BB2内的一部分(未图示)，也可以不作为第二扇出区BB2的一部分(如图7所示)。
在一些示例中，显示基板100还包括ILB(英文全称：Inner Lead Bonding，中文名称：内引脚接合)区(未图示)和FOP(英文全称：Flexible Printed Circuit On Panel，中文名称：面板上柔性电路板)区(未图示)。ILB区和FOP区依次位于COP区远离第二扇出区BB2的一侧。在一些示例中，驱动IC的部分引脚可以通过ILB区的走线电连接至FOP区的引脚，FOP区的引脚可以用于连接外部的柔性电路板。
由前文中的描述可知，本公开的上述一些实施例中，在采用FIAA的方式，将一些数据线110连接至驱动IC时：可以为全部FIAA(即边缘区域AA1的全部第一数据线111都通过连接线120引出)，也可以为部分FIAA(即边缘区域AA1的部分第一数据线111通过连接线120引出)；而且可以为正序FIAA，也可以为逆序FIAA。下文中，以图7中示出的全部FIAA以及逆序FIAA的方式为例，对本公开的一些实施例进行介绍。
本公开的一些实施例中，如图7所示，第一扇出线131包括转接线134。转接线134位于第二扇出区BB2。转接线134与多条第二扇出线132位于不同的导电层103，且转接线134跨过至少一条第二扇出线132，以使多条扇出线130远 离显示区AA的一端沿第一方向X的排列顺序，与多条数据线110沿第一方向X的排列顺序相同。
可以理解地，本公开的实施例中，一条走线“跨过”另一条走线，也即是一条走线的至少部分与另一条走线位于不同的导电层103，并且该至少部分走线在衬底102上的正投影，与另一条走线在衬底102上的正投影相交叉，从而实现“跨过”该另一条走线。
可以理解地，转接线134跨过至少一条第二扇出线132，也即是转接线134在衬底102上的正投影，与至少一条第二扇出线132在衬底102上的正投影相交。转接线134与多条第二扇出线132位于不同的导电层103，使得转接线134能够与多条第二扇出线132绝缘。
在一些示例中，多条转接线134可以位于一层导电层103或者多层导电层103。示例的，当多条转接线134位于多层导电层103时，任一条转接线134与多条第二扇出线132位于不同的导电层103。
在一些示例中，当转接线134位于多层导电层103时，任意相邻的两条转接线134可以位于不同的导电层103。在一些示例中，转接线134可以位于第二源漏金属层SD2和/或第三源漏金属层。示例的，当转接线134位于第二源漏金属层SD2和第三源漏金属层时，任意相邻的两条转接线134位于不同的源漏金属层SD(包括第二源漏金属层SD2或第三源漏金属层)。
可以理解地，如图7所示，通过设置转接线134跨过至少一条第二扇出线132，并且转接线134与多条第二扇出线132绝缘，这样一来，通过调节转接线134的延伸方向或者延伸长度等，就能能够调整多条第一扇出线131远离显示区AA的一端沿第一方向X的排列顺序。
也即是，通过设置转接线134跨过至少一条第二扇出线132，能够对第一扇出线131远离显示区AA的一端(也即是第一扇出线131与驱动IC电连接的一端)的排列顺序进行调整，从而能够对多条扇出线130远离显示区AA的一端(也即是多条扇出线130与驱动IC电连接的一端)的排列顺序进行调整，使得扇出线1～扇出线n远离显示区AA的一端，能够沿第一边缘至第一中轴线Q方向按顺序间隔排布，从而使得多条扇出线130远离显示区AA的一端沿第一方向X的排列顺序，与多条第一数据线110沿第一方向X的排列顺序能够相同。
从而，使得驱动IC的输出端沿第一方向X的排列顺序、多条扇出线130远离显示区AA的一端沿第一方向X的排列顺序、以及多条数据线110沿第一方向X的排列顺序三者能够相同，驱动IC的输出端能够按顺序向多条数据线110提供驱动信号，也即是使得驱动IC能够按照顺序驱动多列子像素101发光，无需 重新开发驱动IC，在显示基板100能够实现窄边框的基础上，降低了显示基板100的成本。
此外，将转接线134设置在第二扇出区BB2，避免了转接线134占用第一扇出区BB1的空间，减小第一扇出区BB1的宽度。由于第一扇出区BB1位于弯折区CC靠近显示区AA的一侧，故而，减小第一扇出区BB1的宽度，能够进一步减小显示基板100的下边框宽度，从而提高显示面板210的视觉效果。
在一些示例中，第一扇出线131通过转接线134，直接与驱动IC的输出端电连接。在另一些示例中，第一扇出线131还包括其他部分走线，第一扇出线131通过其他部分走线，与驱动IC的输出端电连接。
本公开的一些实施例中，继续参阅图7，转接线134包括主体部1340和两个连接端部(G1，G2)，主体部1340位于两个连接端部(G1，G2)靠近显示区AA的一侧。下文中，为了便于描述，定义两个连接端部中，靠近第一中轴线Q的连接端部为第一连接端部G1，远离第一中轴线Q的连接端部为第二连接端部G2。
示例的，第一连接端部G1可以用于连接第一扇出线131中靠近显示区AA的部分，第二连接端部G2可以用于连接第一扇出线131中靠近COP区的部分。
在一些示例中，如图7所示，第一扇出线131还包括第一子扇出线133和第二子扇出线135。第一连接端部G1与第一子扇出线133电连接，并通过该第一子扇出线133电连接至连接线120。第二连接端部G2与第二子扇出线135电连接，并通过该第二子扇出线135电连接至驱动IC。
在一些示例中，如图7所示，第二扇出线132包括第三子扇出线136和第四子扇出线137。第三子扇出线136的一端与第二数据线112电连接，第三子扇出线136的另一端与第四子扇出线137电连接，第四子扇出线137远离第三子扇出线的一端电连接至驱动IC。
示例的，沿第一方向X，多条第三子扇出线136与多条第一子扇出线133交替设置，例如可以四条第三子扇出线136为一组，两条第一子扇出线133为一组，然后组与组之间交替设置(也即4插2方式)。当然，本公开实施例对此不作限制，例如，也可以采用3插1、4插3等方式。在此基础上，相邻的子扇出线(如相邻的第三子扇出线136与第一子扇出线133、或相邻的两条第三子扇出线136、或相邻的两条第一子扇出线133)可以位于不同的栅金属层Gate中，例如，其中一条位于第一栅金属层Gate1，另一条位于第二栅金属层Gate2。如此设置，有利于减小相邻的子扇出线之间的信号串扰。
在一些示例中，由于采用FIAA方案，使得第三子扇出线136和第一子扇出 线133位于第一扇出区BB1的部位，与第一中轴线Q之间的交角更小，也即更趋近于与第一中轴线Q平行。因此，在第一扇出区BB1中，第三子扇出线136和第一子扇出线133之间、两条第三子扇出线136之间、以及两条第一子扇出线133之间，均可以有更多的距离，因此，可以设置第三子扇出线136和第一子扇出线133位于第一扇出区BB1的部位位于同一层源漏金属层SD中，或者沿第一方向X交替位于不同的源漏金属层SD中，这样可以使第三子扇出线136和第一子扇出线133分别具有更小的电阻，也即可以使第一数据线111和第二数据线112可以具有更小的电阻，有利于提高显示基板100的显示亮度。
此外，为了降低电阻，还可以设置第三子扇出线136和第一子扇出线133中的任一者位于弯折区CC的部位位于栅金属层以外的膜层(例如任一层源漏金属层)，本公开实施例对此不作限制。
可以理解地，参阅图7可知，第一子扇出线133和第三子扇出线136两者位于第二扇出区BB2的部分走线需要倾斜布置，以实现进一步收拢，方便后续通过转接线134以及第二子扇出线135和第四子扇出线137与驱动IC电连接。其中，在第二方向Y上，这部分倾斜走线所占用的第二扇出区BB2的宽度，大于第二子扇出线135和第四子扇出线137两者所占用的第二扇出区BB2的宽度。
在此基础上，若设置主体部1340位于两个连接端部(G1，G2)靠近COP区的一侧，则需要进一步增大第二扇出区BB2沿第二方向Y的宽度，此时会导致第二子扇出线135的长度和第四子扇出线137的长度增加，因此，会增大多条数据线110的电阻，进而影响显示基板100的显示亮度，影响低灰阶画面的显示效果。
而本公开的上述一些实施例中，由于主体部1340位于两个连接端部(G1，G2)靠近显示区AA的一侧，使得主体部1340可以在衬底102的厚度方向上，与第一子扇出线133和第三子扇出线136两者所在的区域存在交叠。这样设计，由于在第二方向Y上，第一子扇出线133和第三子扇出线136中的倾斜走线所占用的第二扇出区BB2的宽度较大，因此不需要延长第一子扇出线133和第三子扇出线136，有利于减小扇出线130对第二扇出区BB2沿第二方向Y的空间的占用，从而有利于减小第二扇出区BB2沿第二方向Y的宽度。而且，还有利于减小第二子扇出线135的长度和第四子扇出线137的长度，也即，相较于上述主体部1340位于两个连接端部(G1，G2)靠近COP区的一侧的方案而言，有利于降低多条数据线110的电阻，从而有利于提高显示基板100的显示亮度，改善低灰阶画面的显示效果。
在一些实施例中，如图7所示，显示基板100还包括隔离块140。隔离块140 将转接线134与第一子扇出线133分隔开，并将转接线134与第三子扇出线136分隔开。
示例的，第一子扇出线133和第三子扇出线136位于至少一层栅金属层Gate。转接线134位于第二源漏金属层SD2和/或第三源漏金属层中。而上述隔离块可以位于第一源漏金属层SD1中。
本实施例中，如此设置，有利于减小转接线134与第一子扇出线133之间的信号串扰，以及减小转接线134与第三子扇出线136之间的信号串扰，从而有利于提高显示区AA的亮度均匀性，使显示基板100的多个子像素不容易出现闪烁或暗线不良等问题。
在一些示例中，如图7所示，隔离块140与电压信号线141相连，也即隔离块140可以被配置为传输电压信号。示例的，电压信号线141可以是但不限于，为发光器件300的阳极提供电压的Vdd信号线、为发光器件300的阴极提供电压的Vss信号线等信号线中的任一种。
可以理解地，通过被配置为传输电压信号的隔离块140，对转接线134和第一子扇出线133，以及转接线134和第三子扇出线136进行隔离，这样一来，就无需额外设置其他部件，简化了制备工艺，降低了显示基板100的成本。
图8为根据一些实施例的显示基板的局部结构图。图9为图8中第一栅金属层、第二栅金属层和第一源漏金属层的结构图。图10为图8中第二源漏金属层和第三源漏金属层的结构图。
示例的，如图8～图10所示，第二扇出区BB2位于第一中轴线Q一侧的区域为一个子扇出区BBZ。下文中，主要对一个子扇出区BBZ内的布线方式进行介绍。可以理解地，对于两个子扇出区BBZ内的布线方式，可以相同，也可以不同。
本公开的一些实施例中，如图8～图10所示，显示基板100包括依次远离衬底102的第一栅金属层Gate1、第二栅金属层Gate2、第一源漏金属层SD1、第二源漏金属层SD2和第三源漏金属层SD3。并且，显示基板100具有依次远离显示区AA的第一扇出区BB1、弯折区CC、中间扇出区BB0(可选的)、CT区、第二扇出区BB2、COP区、ILB区和FOP区。其中，显示基板100的位于弯折区CC远离显示区AA一侧的部位，可以弯折至显示基板100的位于显示区AA的部位的背面，避免了显示基板100的位于弯折区CC远离显示区AA一侧的部位占用显示基板100的显示侧的空间，从而能够减小显示面板210的侧边框(例如下边框)的宽度，提高显示面板210的视觉效果。
在一些实施例中，如图8和图10所示，转接线134呈U形或近似U形。转接 线134的开口朝向COP区。
可以理解地，呈U形或近似U形的转接线134能够跨过至少一条第二扇出线132，使得转接线134能够调整多条第一扇出线131远离显示区AA的一端沿第一方向X的排列顺序，从而使得扇出线1～扇出线n远离显示区AA的一端，能够沿由边缘至第一中轴线Q的方向按顺序间隔排布，也即是使得多条扇出线130远离显示区AA的一端沿第一方向X的排列顺序，与多条第一数据线110沿第一方向X的排列顺序能够相同。
示例的，如图9所示，隔离块140位于第二栅金属层Gate2远离第一栅金属层Gate1的一侧。例如，隔离块140可以位于第一源漏金属层SD1。
在此基础上，示例的，第一子扇出线133和第三子扇出线136中的任一个位于第一栅金属层Gate1和/或第二栅金属层Gate2，转接线134位于第二源漏金属层SD2和/或第三源漏金属层。因此，可以利用隔离块140，将转接线134与第一子扇出线133分隔开，并将转接线134与第三子扇出线136分隔开。从而有利于减小转接线134与第一子扇出线133之间的信号串扰，以及减小转接线134与第三子扇出线136之间的信号串扰，从而有利于提高显示基板100的亮度均匀性，使显示基板100不容易出现闪烁或暗线不良等问题。
图11为图8中区域001的局部结构图。图12～图17为图11中各个膜层的结构图。
在一些实施例中，如图11所示，在一个子扇出区中：多条转接线134呈辐射状排布。其中，“辐射状排布”是指：对于任意相邻的两条转接线134，位于外侧的转接线134部分围绕位于内侧的转接线134设置，也即例如图11所示的排布方式。
示例的，各转接线134呈U形，处于内侧的转接线134大致位于处于外侧的转接线134内。
本实施例中，通过设置相邻的两条转接线134中，位于外侧的转接线134围绕位于内侧的转接线134设置有利于节省布线空间，从而有利于增大转接线134与转接线134之间的间距，降低信号串扰，同时还有利于减小显示基板100的第二扇出区BB2沿第二方向Y的尺寸，使显示基板100的下边框可以设置的更窄。
示例的，相邻的转接线134还可以彼此大致平行。这样，可以使得相邻转接线134之间的间距基本保持一致，从而有利于减小相邻转接线134之间的信号干扰，从而有利于提高显示基板的显示画面的亮度均匀性。
在一些实施例中，如图11所示，相邻的两条所述转接线位于不同的导电 层中。这样设置，有利于进一步改善相邻转接线134之间的信号干扰问题，从而有利于进一步提高显示基板的显示画面的亮度均匀性。
参阅图12和图13，在一些实施例中，第一扇出线131还包括依次远离显示区AA且彼此电连接的第一走线段1311和第二走线段1312，也即第一扇出线131中的第一子扇出线133可以包括依次远离显示区AA且彼此电连接的第一走线段1311和第二走线段1312。第一走线段1311自靠近显示区AA的一端至远离显示区AA的一端，逐渐靠近第一中轴线Q。第二走线段1312与第一中轴线Q平行。
第二扇出线132包括依次远离显示区AA且彼此电连接的第三走线段1321和第四走线段1322，也即第二扇出线132中的第三子扇出线136可以包括依次远离显示区AA且彼此电连接的第三走线段1321和第四走线段1322。第三走线段1321自靠近显示区AA的一端至远离显示区AA的一端，逐渐靠近第一中轴线Q。第四走线段1322与第一中轴线Q平行。
如图16和图17所示，转接线134包括：靠近第一中轴线Q的连接端部(即第一连接端部G1)，以及，远离第一中轴线Q的连接端部(即第二连接端部G2)。其中，转接线134靠近第一中轴线Q的连接端部(即第一连接端部G1)可以与图12和图13中的第二走线段1312远离第一走线段1311的端部a1电连接。
图14示出的层间介质层ILD中包括第一连接孔161和第二连接孔162。图15示出的第一源漏金属层SD1中包括第一转接部M1和第二转接部M2。
相邻的两个第二走线段1312分别位于第一栅金属层Gate1和第二栅金属层Gate2，对于相邻的两个第二走线段1312的端部a1：其中，位于第一栅金属层Gate1的第二走线段1312的端部a1，可以通过第一连接孔161电连接至位于第一源漏金属层SD1上的第一转接部M1，位于第二栅金属层Gate2的端部a1可以直接通过第二连接孔162电连接至位于第一源漏金属层SD1上的第二转接部M2。
由前文中的描述可知，可以将电连接第一源漏金属层SD1上的导电走线和第二源漏金属层SD2上的导电走线的转接孔称为PLN1孔，将电连接第二源漏金属层SD2上的导电走线和第三源漏金属层上的导电走线的转接孔称为PLN2孔。因此，图16示出的第二源漏金属层SD2中的转接线134的第一连接端部G1，可以通过PLN1孔电连接至第二转接部M2，由于第二转接部M2与一个第二走线段1312的端部a1电连接，因此，图16示出的第二源漏金属层SD2中的转接线134的第一连接端部G1，可以与一个第二走线段1312的端部a1电连接。
在此基础上，图16示出的第二源漏金属层SD2还可以包括第三转接部M3。 图17示出的第三源漏金属层SD3中的转接线134的第一连接端部G1，可以通过PLN2孔电连接至第三转接部M3，而第三转接部M3可以通过PLN1孔电连接至第一转接部M1，由于第一转接部M1与另一个第二走线段1312的端部a1电连接，因此，图17示出的第三源漏金属层SD3中的转接线134的第一连接端部G1，可以与另一个第二走线段1312的端部a1电连接。
在一些实施例中，如图16所示，第二源漏金属层SD2还包括第四转接部M4。如图17所示，第三源漏金属层SD3还包括第五转接部M5。
第二源漏金属层SD2中的转接线134的第二连接端部G2可以通过PLN2孔电连接至第三源漏金属层SD3中的第五转接部M5，而第三源漏金属层SD3中的转接线134的第二连接端部G2可以通过PLN2孔电连接至第二源漏金属层SD2中的第四转接部M4。如此设置，有利于平衡位于不同层的相邻转接线134之间的寄生电容差异。
在此基础上，如图15所示，第一源漏金属层SD1中包括第一延伸走线N1和第二延伸走线N2。
第二源漏金属层SD2中的转接线134的第二连接端部G2和第四转接部M4，可以分别通过不同的PLN1孔，电连接至不同的第一延伸走线N1上。
如图12所示，第一栅金属层Gate1包括第七转接部M7和第二虚拟转接部M02。如图13所示，第二栅金属层Gate2包括第六转接部M6和第一虚拟转接部M01。如图14所示，层间介质层ILD中还包括第三连接孔163。多条第一延伸走线N1通过一部分第三连接孔163转接至第一虚拟转接部M01和第二虚拟转接部M02，多条第二延伸走线N2通过另一部分第三连接孔163转接至第六转接部M6和第七转接部M7。
通过上述方式，可以将第一扇出线131和第二扇出线132均转接至第一源漏金属层SD1。而且，通过设置第一虚拟转接部M01和第二虚拟转接部M02，可平衡由跨层转接带来的多条扇出线130之间的寄生电容差异。
如图14所示，层间介质层ILD中还包括第四连接孔164。第一延伸走线N1和第二延伸走线N2，可以通过第四连接孔164，转接至位于第一栅金属层Gate1中的引脚150上。第一栅金属层Gate1中的引脚150可以用于连接驱动IC。通过将用于连接驱动IC的引脚全部设置在第一栅金属层Gate1上，有利于提高驱动IC焊接后的稳固性。
此外，如图12所示，第一栅金属层Gate1还包括第三虚拟转接部M03。如图14所示，层间介质层ILD中还包括第五连接孔165。
通过第五连接孔165可以将第一延伸走线N1转接至位于第一栅金属层 Gate1中的第三虚拟转接部M03上。这样设置，有利于平衡由跨层转接带来的多条扇出线130之间的寄生电容差异。
在一些示例中，参阅图11，在区域002(即图11中呈网格状的矩形区域)内，可以不设置第一源漏金属层SD1与第二源漏金属层SD1之间的绝缘层，也即，在此处设置的第一延伸走线N1和第二延伸走线N2，可以为同时位于第一源漏金属层SD1与第二源漏金属层SD1的叠层结构。这样设置，有利于减小第一延伸走线N1和第二延伸走线N2上的电阻，从而有利于改善显示基板100的显示效果。
在一些实施例中，如图11、图12和图13所示，在子扇出区BBZ中：多条第一走线段1311与多条第三走线段1321交替布置。
示例的，结合图12和图13所示，可以将四条相邻的第三子扇出线136划分为第一走线组，将两条相邻的第一子走线划分为第二走线组，并设置第一走线组与第二走线组交替排布，也即采“4插2”的方式进行布线。需要说明的是，在其他的一些示例中，也可以采用“3插1”、“4插3”等方式进行布线，可以根据布线空间等因素灵活设置。
参阅图12和图13，第一走线段1311远离显示区AA的端部和第三走线段1321远离显示区AA的端部所限定的拟合直线L，自远离第一中轴线Q的一端至靠近第一中轴线Q的一端，逐渐靠近显示区AA。
这样设置，可以增大第二走线段1312远离显示区AA的端部a1沿第二方向Y的布置范围，因此，可以通过调节不同的第二走线段1312的端部a1的位置，实现平衡多条第一扇出线131之间的电阻差异，从而还有利于平衡多条第一扇出线131与多条第二扇出线132之间的电阻差异。如此，使得多条第一数据线111与多条第二数据线112之间的电阻差异减小，提高了显示基板100的亮度均匀性。
在一些示例中，如图11所示，在子扇出区BBZ中：多条第二走线段1312中，直接相邻的至少两条(例如两条)第二走线段1312为同一组，同一组中的第二走线段1312远离显示区AA的端部a1沿第一方向X错开设置。
本示例中，通过设置同一组中的第二走线段1312远离显示区AA的端部沿第一方向X错开设置，有利于节省布线空间，而且有利与降低相邻的第二走线段之间的信号串扰，提高显示基板100的亮度均匀性。
在一些示例中，在子扇出区BBZ中：相邻的两条第二走线段1312中，靠近第一中轴线Q的第二走线段1312的长度，小于远离第一中轴线Q的第二走线段1312的长度；相邻的两条转接线134中，靠近第一中轴线Q的转接线134中用 于连接所述第二走线段1312的连接端部(即第一连接端部G1)，相对于远离第一中轴线Q的转接线134中用于连接第二走线段1312的连接端部(即第二连接端部G2)，更靠近显示区AA。
需要说明的是，对于图7所示的逆序FIAA，由于越靠近第一中轴线Q的第一子扇出线133，所连接第一数据线越靠近显示区沿第一方向X的边缘，所以，越靠近第一中轴线Q的第一子扇出线133所连接的连接线120越长，越靠近第一中轴线Q的第一子扇出线133和其所连接的连接线120的总电阻越大。因此，本公开上述一些示例中，通过在子扇出区BBZ中：设置相邻的两条第二走线段1312中，靠近第一中轴线Q的第二走线段1312的长度，小于远离第一中轴线Q的第二走线段1312的长度；相邻的两条转接线134中，靠近第一中轴线Q的转接线134中用于连接所述第二走线段1312的连接端部(即第一连接端部G1)，相对于远离第一中轴线Q的转接线134中用于连接第二走线段1312的连接端部(即第二连接端部G2)，更靠近显示区AA。使得相邻的两个第一子扇出线133中，靠近第一中轴线Q的第一子扇出线133的长度减小量，相较于远离第一中轴线Q的第一子扇出线133的长度减小量更多，因此，靠近第一中轴线Q的第一子扇出线133的电阻减小量，相较于远离第一中轴线Q的第一子扇出线133的电阻减小量也就更多，从而可以更好的平衡多条第一子扇出线133之间的电阻差异，也即可以平衡多条第一数据线111之间的电阻差异，提高显示基板100的亮度均匀性。
在一些示例中，如图16和图17所示，主体部1340包括第一转接段1341。
第一转接段1341与转接线134中连接第二走线段1312的连接端部(即第一连接端部G1)相连。第一转接段1341在衬底上的正投影与对应连接的第二走线段1312在衬底上的正投影重叠或大致重叠。
需要说明的是，由于第一转接段1341与第二走线段1312用于传输相同的信号，因此两者之间不存在信号串扰的问题，此外，通过将这两者沿衬底的厚度方向交叠设置，有利于节省布线空间。
在一些示例中，如图16和图17所示，主体部1340还包括与第一转接段1341连接的第二转接段1342，以及与第二转接段1342连接的第三转接段1343。
示例的，参阅图11和图12～图17，隔离块140位于第一走线段1311和第三走线段1321远离衬底的一侧，且隔离块140覆盖第一走线段1311和第三走线段1321。转接线134位于隔离块140远离衬底的一侧。第二转接段1342在衬底上的正投影位于隔离块140在衬底上的正投影内。第一转接段1341和第三转接段1343两者在衬底上的正投影均位于隔离块140在衬底上的正投影外。
这样设置，既便于调节第二走线段1312远离显示区AA的端部a1与转接线134的转接位置，以平衡多条数据线110之间的电阻差异，又便于利用隔离块140分隔转接线134的第二转接段1342与第一子扇出线133的第一走线段1311，以及利用隔离块140分隔转接线134的第二转接段1342与第三子扇出线136的第三走线段1321，从而可以防止转接线134的第二转接段1342与第一子扇出线133的第一走线段1311发生串扰，以及防止转接线134的第二转接段1342与第三子扇出线136的第三走线段1321之间发生串扰，提高了显示基板100的亮度均匀性。
在图16和图17中，大致沿第一方向X延伸的虚线为隔离块140的部分边界。示例的，可以通过该部分边界所在的位置，将转接线134划分为第一转接段1341、第二转接段1342和第三转接段1343。
示例的，如图16和图17所示，第一转接段1341与第三转接段1343均平行于第一中轴线Q，第二转接段1342呈U形或近似U形。可以理解地，在其他的示例中，由于隔离块140的边界位置不同，第一转接段1341、第二转接段1342和第三转接段1343的分界位置也不固定。
示例的，第二走线段1312和第四走线段1322中的至少一者，可以被配置为包括蛇形走线或其他不规则走线，这样设计，有利于进一步平衡多条扇出线之间的电阻，进而平衡多条数据线之间的电阻。
在一些实施例中，参阅图11和图15、图16、图17，隔离块140包括第一边界E1和第二边界E2。其中，第一边界E1沿靠近第一中轴线Q的方向，逐渐远离显示区AA；第二边界E2沿靠近第一中轴线Q的方向，逐渐靠近显示区AA。
需要说明的是，第一边界E1和第二边界E2中的任一者，可以为至少一段直线(例如在图15的示例中，第一边界E1为一段直线，第二边界E2为相连接的两段直线)，或者也可以为至少一段曲线，或者还可以为相连接的至少一段直线和至少一段曲线。此外，图11和图15、图16、图17只示出了第一边界E1和第二边界E2的部分，更完整的第一边界E1和第二边界E2，可以参阅图9所示的隔离块140。示例的，第一边界E1与第二边界E2可以直接相连，也可以间接相连。
在一些示例中，如图11～图13所示，第一边界E1，与第一走线段1311远离显示区AA的端部和第三走线段1321远离显示区AA的端部所限定的拟合直线L，重合或大致重合。此处，“大致重合”是指，第一边界E1与拟合直线L之间可以具有较小的间距，例如几微米的间距。
本示例中，使得隔离块140的面积可以设置的比较小，减小对第二扇出区 BB的空间的占用，同时实现对第一走线段1311与转接线134的信号屏蔽，以及对第三走线段1321与转接线134的信号屏蔽，从而可以防止第一走线段1311与转接线134之间发生信号串扰，以及防止第三走线段1321与转接线134之间发生信号串扰，提高显示基板100的亮度均一性。
在一些示例中，如图11和图13所示，第二边界E2，与所有第一走线段1311和所有第三走线段1321中，最远离第一中轴线Q的走线段(例如图13中左下角示出的一条第三走线段1321，可以理解地，本公开实施例对此不作限制，在其他的一些实施例中，该走线段也可以为第一走线段1311)，重合或大致重合。此处，“大致重合”是指，第二边界E2与所述的最远离第一中轴线Q的走线段之间可以具有较小的间距，例如几微米的间距。
本示例中，使得隔离块140的面积可以设置的比较小，减小对第二扇出区BB的空间的占用，同时实现对第一走线段1311与转接线134的信号屏蔽，以及对第三走线段1321与转接线134的信号屏蔽，从而可以防止第一走线段1311与转接线134之间发生信号串扰，以及防止第三走线段1321与转接线134之间发生信号串扰，提高显示基板100的亮度均一性。
在一些示例中，第一边界E1与第二边界E2之间的夹角为钝角。这样设置，有利于使隔离块140更全面的覆盖到倾斜设置的第一走线段1311和第三走线段1321，从而，有利于防止转接线134与第一走线段1311之间，以及转接线134与第三走线段1321之间，发生信号串扰。
在一些示例中，隔离块140在衬底上的正投影为三角形或近似三角形。例如，参阅图9，图9所示出的隔离块140在衬底上的正投影，相对于正常三角形而言，左端缺少了一个较大的角，右端缺少了一个较小的角。此时，可以认为该正投影形状为近似三角形。可以理解地，在其他的示例中，也可以设置隔离块140在衬底上的正投影为三角形，或者其他的近似三角形。这里，其他的近似三角形，例如可以包括三角形的边为锯齿状或波浪状的情况。
本示例中，通过设置隔离块140在衬底上的正投影为三角形或近似三角形，有利于使隔离块140更全面的覆盖到倾斜设置的第一走线段1311和第三走线段1321，防止转接线134与第一走线段1311之间，以及转接线134与第三走线段1321之间，发生信号串扰。而且，使得隔离块140的面积可以设置的比较小，减小对第二扇出区BB的空间的占用。
在一些示例中，第一走线段1311、第二走线段1312、第三走线段1321和第四走线段1322位于所述至少两层栅金属层Gate(例如第一栅金属层Gate1和第二栅金属层Gate2)。隔离块140位于所述至少两层源漏金属层SD中相对靠 近衬底102的源漏金属层(例如第一源漏金属层SD1)，转接线134位于所述至少两层源漏金属层中相对远离衬底的源漏金属层(例如第二源漏金属层SD2和第三源漏金属层SD3)。
示例的，在一个子扇出区中，多条第一走线段1311和多条第三走线段1321中，任意相邻的两条走线段(如第一走线段1311和第三走线段1321、或者两个第一走线段1311、或者两个第二走线段1321)位于不同的栅金属层(例如第一栅金属层Gate1和第二栅金属层Gate2)，如此设置，有利于减小相邻的走线段(如第一走线段1311和第三走线段1321、或者两个第一走线段1311、或者两个第二走线段1321)之间的信号干扰，从而有利于提高显示基板的亮度均匀性。
示例的，在一个子扇出区中，任意相邻的两条转接线134位于不同的源漏金属层SD(例如第二源漏金属层SD2和第三源漏金属层SD3)，如此设置，有利于减小相邻的两条转接线134之间的信号干扰，从而有利于提高显示基板的亮度均匀性。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种显示基板，具有显示区和扇出区，所述扇出区与所述显示区的一侧边缘邻接；所述显示基板包括：
    衬底；
    多层导电层，位于所述衬底的同一侧；所述多层导电层层叠设置；
    所述多层导电层中包括：
    多条数据线，所述多条数据线沿第一方向间隔排布、且所述多条数据线均沿第二方向延伸，所述第二方向与所述第一方向相交叉；所述多条数据线包括多条第一数据线和多条第二数据线，所述多条第一数据线位于所述显示区沿所述第一方向的两个边缘区域，所述多条第二数据线位于所述显示区沿所述第一方向的中心区域；
    多条连接线，一条连接线的第一端位于所述边缘区域，且与一条第一数据线电连接，该条连接线的第二端延伸至所述中心区域与所述扇出区之间的交界处；至少一条所述连接线跨过至少一条数据线，且与所跨过的数据线绝缘；至少一条所述连接线的第二端位于相邻的两条第二数据线之间；
    多条扇出线，位于所述扇出区；所述多条扇出线包括多条第一扇出线和多条第二扇出线；其中，第一扇出线与所述连接线的第二端电连接，第二扇出线和未与所述连接线电连接的数据线的靠近所述扇出区的一端电连接；
    其中，所述显示基板还具有依次远离所述显示区的弯折区和芯片安装区；所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区位于所述显示区与所述弯折区之间，所述第二扇出区位于所述弯折区与所述芯片安装区之间；
    所述第一扇出线包括转接线，所述转接线位于所述第二扇出区；所述转接线跨过至少一条所述第二扇出线，以使所述多条扇出线远离所述显示区的一端沿所述第一方向的排列顺序，与所述多条数据线沿所述第一方向的排列顺序相同；
    其中，所述转接线包括主体部和两个连接端部，所述主体部位于所述两个连接端部靠近所述显示区的一侧。
  2. 根据权利要求1所述的显示基板，其中，所述显示基板还具有位于所述弯折区和所述芯片安装区之间的电路测试区；所述第二扇出区位于所述电路测试区与所述芯片安装区之间。
  3. 根据权利要求1或2所述的显示基板，其中，
    所述转接线呈U形或近似U形。
  4. 根据权利要求1～3中任一项所述的显示基板，其中，所述显示基板沿所述第二方向延伸的中轴线定义为第一中轴线；所述第二扇出区位于第一中 轴线一侧的区域为一个子扇出区；在所述子扇出区中：
    多条所述转接线呈辐射状排布；其中，相邻的两条所述转接线中，位于外侧的转接线围绕位于内侧的转接线设置。
  5. 根据权利要求4所述的显示基板，其中，
    相邻的两条所述转接线位于不同的导电层中。
  6. 根据权利要求1～5中任一项所述的显示基板，其中，
    所述显示基板沿所述第二方向延伸的中轴线定义为第一中轴线；所述第二扇出区位于第一中轴线一侧的区域为一个子扇出区；在所述子扇出区中：
    所述第一扇出线还包括依次远离所述显示区且彼此电连接的第一走线段和第二走线段；所述第一走线段自靠近所述显示区的一端至远离所述显示区的一端，逐渐靠近所述第一中轴线；所述第二走线段与所述第一中轴线平行；
    所述第二扇出线包括依次远离所述显示区且彼此电连接的第三走线段和第四走线段；所述第三走线段自靠近所述显示区的一端至远离所述显示区的一端，逐渐靠近所述第一中轴线；所述第四走线段与所述第一中轴线平行；
    其中，所述转接线靠近所述第一中轴线的所述连接端部与所述第二走线段远离所述第一走线段的端部电连接。
  7. 根据权利要求6所述的显示基板，其中，
    在所述子扇出区中：
    多条所述第一走线段与多条所述第三走线段交替布置；所述第一走线段远离所述显示区的端部和所述第三走线段远离所述显示区的端部所限定的拟合直线，自远离所述第一中轴线的一端至靠近所述第一中轴线的一端，逐渐靠近所述显示区。
  8. 根据权利要求6或7所述的显示基板，其中，
    在所述子扇出区中：
    多条所述第二走线段中，直接相邻的所述第二走线段为同一组，同一组中的所述第二走线段远离所述显示区的端部沿所述第一方向错开设置。
  9. 根据权利要求6～8中任一项所述的显示基板，其中，
    在所述子扇出区中：
    相邻的两条所述第二走线段中，靠近所述第一中轴线的所述第二走线段的长度，小于远离所述第一中轴线的所述第二走线段的长度；
    相邻的两条所述转接线中，靠近所述第一中轴线的所述转接线中用于连接所述第二走线段的所述连接端部，相对于远离所述第一中轴线的所述转接线中用于连接所述第二走线段的所述连接端部，更靠近所述显示区。
  10. 根据权利要求6～9中任一项所述的显示基板，其中，
    所述主体部包括第一转接段；
    所述第一转接段与所述转接线中连接所述第二走线段的所述连接端部相连；所述第一转接段在所述衬底上的正投影与对应连接的所述第二走线段在所述衬底上的正投影重叠或大致重叠。
  11. 根据权利要求10所述的显示基板，其中，
    所述主体部还包括与所述第一转接段连接的第二转接段，以及与所述第二转接段连接的第三转接段；
    所述多层导电层中还包括：
    隔离块，位于所述第一走线段和所述第三走线段远离所述衬底的一侧，且所述隔离块覆盖所述第一走线段和所述第三走线段；
    其中，所述转接线位于所述隔离块远离所述衬底的一侧；所述第二转接段在所述衬底上的正投影位于所述隔离块在所述衬底上的正投影内；
    所述第一转接段和所述第三转接段两者在所述衬底上的正投影均位于所述隔离块在所述衬底上的正投影外。
  12. 根据权利要求11所述的显示基板，其中，所述隔离块按照以下至少一种方式设置：
    所述隔离块与电压信号线电连接；
    或者，所述隔离块包括第一边界，所述第一边界，与所述第一走线段远离所述显示区的端部和所述第三走线段远离所述显示区的端部所限定的拟合直线，重合或大致重合；
    或者，所述隔离块包括第二边界；所述第二边界，与所有所述第一走线段和所有所述第三走线段中，最远离所述第一中轴线的走线段，重合或大致重合；
    或者，所述隔离块包括第一边界和第二边界，所述第一边界与所述第二边界之间的夹角为钝角；
    或者，所述隔离块在所述衬底上的正投影为三角形或近似三角形。
  13. 根据权利要求11或12所述的显示基板，其中，
    所述多层导电层中包括：
    至少两层栅金属层；
    至少两层源漏金属层，均位于所述至少两层栅金属层远离所述衬底的一侧；
    所述第一走线段、所述第二走线段、所述第三走线段和所述第四走线段 位于所述至少两层栅金属层中，所述隔离块位于所述至少两层源漏金属层中相对靠近所述衬底的源漏金属层，所述转接线位于所述至少两层源漏金属层中相对远离所述衬底的源漏金属层。
  14. 一种显示装置，其特征在于，包括如权利要求1～13中任一项所述的显示基板。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
CN115207073B (zh) * 2022-04-25 2023-10-24 京东方科技集团股份有限公司 显示基板及显示装置
CN115862475A (zh) * 2022-12-15 2023-03-28 云谷（固安）科技有限公司 显示面板和显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110286532A (zh) * 2019-07-19 2019-09-27 昆山国显光电有限公司 阵列基板和显示面板
CN110297370A (zh) * 2018-12-11 2019-10-01 友达光电股份有限公司 元件基板
US20210028261A1 (en) * 2019-07-22 2021-01-28 Samsung Display Co., Ltd. Display device having a sensor area
CN112599058A (zh) * 2020-12-22 2021-04-02 湖北长江新型显示产业创新中心有限公司 一种显示面板、显示装置和显示面板的修护方法
CN113964142A (zh) * 2021-11-19 2022-01-21 昆山国显光电有限公司 显示面板和显示装置
CN115207073A (zh) * 2022-04-25 2022-10-18 京东方科技集团股份有限公司 显示基板及显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105427787B (zh) * 2015-12-30 2019-02-26 上海中航光电子有限公司 阵列基板和显示面板
CN108598142B (zh) * 2018-06-28 2020-11-17 上海天马微电子有限公司 柔性显示基板、柔性显示面板和柔性显示装置
US11258675B2 (en) * 2019-10-29 2022-02-22 Dell Products L.P. Message oriented middleware topology explorer
CN111584475B (zh) * 2020-05-15 2021-11-23 深圳市华星光电半导体显示技术有限公司 拼接显示面板及其制备方法
CN111933674B (zh) * 2020-08-18 2024-06-11 京东方科技集团股份有限公司 显示基板和显示装置
CN112310125B (zh) * 2020-10-30 2022-08-09 合肥京东方卓印科技有限公司 显示基板及显示装置
CN113161401B (zh) * 2021-04-22 2022-08-05 武汉天马微电子有限公司 显示面板和显示装置
CN216286614U (zh) * 2021-09-14 2022-04-12 京东方科技集团股份有限公司 显示基板及显示装置
CN114003143B (zh) * 2021-10-28 2024-06-18 成都京东方光电科技有限公司 触控显示面板和触控显示装置
CN115064108A (zh) * 2022-06-30 2022-09-16 武汉天马微电子有限公司 显示面板及显示装置
CN115188792A (zh) * 2022-07-15 2022-10-14 京东方科技集团股份有限公司 显示基板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110297370A (zh) * 2018-12-11 2019-10-01 友达光电股份有限公司 元件基板
CN110286532A (zh) * 2019-07-19 2019-09-27 昆山国显光电有限公司 阵列基板和显示面板
US20210028261A1 (en) * 2019-07-22 2021-01-28 Samsung Display Co., Ltd. Display device having a sensor area
CN112599058A (zh) * 2020-12-22 2021-04-02 湖北长江新型显示产业创新中心有限公司 一种显示面板、显示装置和显示面板的修护方法
CN113964142A (zh) * 2021-11-19 2022-01-21 昆山国显光电有限公司 显示面板和显示装置
CN115207073A (zh) * 2022-04-25 2022-10-18 京东方科技集团股份有限公司 显示基板及显示装置

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