WO2021168839A1 - Mémoire et dispositif électronique - Google Patents

Mémoire et dispositif électronique Download PDF

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Publication number
WO2021168839A1
WO2021168839A1 PCT/CN2020/077293 CN2020077293W WO2021168839A1 WO 2021168839 A1 WO2021168839 A1 WO 2021168839A1 CN 2020077293 W CN2020077293 W CN 2020077293W WO 2021168839 A1 WO2021168839 A1 WO 2021168839A1
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WO
WIPO (PCT)
Prior art keywords
memory
chip
differential amplifier
word line
differential
Prior art date
Application number
PCT/CN2020/077293
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English (en)
Chinese (zh)
Inventor
焦慧芳
赫然
范鲁明
刘燕翔
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202080096121.4A priority Critical patent/CN115151972A/zh
Priority to PCT/CN2020/077293 priority patent/WO2021168839A1/fr
Publication of WO2021168839A1 publication Critical patent/WO2021168839A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency

Definitions

  • This application relates to the field of information technology, and in particular to a memory and electronic equipment.
  • DRAM dynamic random access memory
  • CPU central processing unit
  • IOPS reads and writes per second
  • the memory chip includes a memory cell array and a logic circuit.
  • the memory cell array is designed to have a larger size, which can generally reach 512 Row X 1024 Column, which includes 512 word lines and 1024 bit lines, that is, both word lines and bit lines are longer, and more transistors are connected.
  • the word line activates multiple transistors, the data transmission path through the bit line is longer, and the parasitic capacitance of the bit line is large, which will cause high latency of the memory.
  • the present application provides a memory and an electronic device to expand the storage capacity of the memory, shorten the delay of the memory, simplify the memory structure, and reduce the cost.
  • the present application provides a memory that includes a first memory chip and a logic chip that are stacked and electrically connected, wherein the first memory chip includes a plurality of first memory cell arrays.
  • the memory cell array includes a plurality of transistors, and a plurality of bit lines and a plurality of word lines, and each transistor is connected with a bit line and a word line.
  • a plurality of transistor arrays are arranged, and one of the above-mentioned transistors is connected between any word line and any bit line.
  • the logic chip includes a differential amplifier and an interface control circuit, wherein both the differential amplifier and the interface control circuit are electrically connected to the first memory cell array.
  • the differential amplifier includes a first differential input terminal, a second differential input terminal, and an output terminal.
  • the first differential input terminal and the second differential input terminal are a set of differential input terminals, that is, the differential amplifier pair is from the first differential input terminal.
  • the input signal and the signal input from the second differential input terminal are differentially amplified.
  • the interface control circuit also includes a reference voltage source.
  • the first differential input terminal of the differential amplifier is electrically connected to the first memory cell array, specifically to the bit line of the first memory cell array, and the second differential input terminal is electrically connected to the logic chip.
  • the reference voltage source is electrically connected, and the differential amplifier performs differential amplification on the reference voltage of the reference voltage source and the signal of the bit line.
  • the differential amplifier is located in the logic chip, which does not occupy the area of the first memory chip and can expand the capacity of the memory.
  • the length of the connection line when the first memory cell array is connected to the differential amplifier can be shortened, which is beneficial to shorten the delay.
  • the peripheral control circuit part is located in the logic chip, and the storage part is located in the first storage chip.
  • the logic chip and the first storage chip can be processed separately by using more advanced technology to improve the transistor density and speed of the memory.
  • This solution also uses a reference voltage source to input a reference voltage to the differential amplifier to simplify the structure of the memory, reduce the area occupied by the connection line between the differential amplifier and the first memory chip, and reduce the cost.
  • the memory in this application may also include a bit line multiplexer.
  • the bit line multiplexer has multiple input ports and one output port.
  • the bit line multiplexer One end of the input port of the gate is connected to the bit line of the first memory cell array, and one end of the output port is connected to the differential amplifier. Then the bit line multiplexer can be connected to multiple bit lines.
  • the bit line multiplexer selects one of the multiple bit lines to output from the output port to the differential amplifier according to requirements. This solution can reduce the number of differential amplifiers in the memory, reduce the area occupied by the differential amplifiers, and can also reduce costs.
  • the bit line multiplexer When the bit line multiplexer is specifically set, the bit line multiplexer can be located in the first memory chip. Since the number of connections between the multiplexer and the bit line located in the first memory chip is large, and the number of connections to the differential amplifier located in the logic chip is small, this solution can reduce the number of connections from the first memory chip to the logic chip. In order to reduce the area occupied by the connection line, simplify the process, and improve the reliability of the connection between the first memory chip and the logic chip.
  • the logic chip further includes a word line driver, and the word line driver is connected to the word line of the first memory chip.
  • the word line driver can provide the gate voltage for the transistor on the word line, and control the opening and closing of the memory cell on the word line.
  • the word line driver of the memory is located on the logic chip and does not occupy the area of the first memory chip, which is beneficial to increase the number of first memory cell arrays of the first memory chip and expand the storage capacity of the memory.
  • the memory in this application may also include a word line multiplexer.
  • the word line multiplexer has multiple output ports and one input port.
  • the word line multiplexer One end of the output port of the gate is connected to the word line of the first memory cell array, and the input end is connected to the word line driver. Then the word line multiplexer can be connected to multiple word lines.
  • the word line multiplexer selects one of the multiple word lines to be connected to the word line driver according to requirements. This solution can reduce the number of word line drivers in the memory, reduce the area occupied by the word line drivers, and can also reduce costs.
  • the word line multiplexer When the word line multiplexer is specifically set, the word line multiplexer can be located in the first memory chip. Since the number of connections between the multiplexer and the word line located in the first memory chip is large, and the number of connections with the word line driver located in the logic chip is small, this solution can reduce the number of connections from the first memory chip to the logic chip.
  • the number of wires is used to reduce the area occupied by the connection wires, simplify the process, and improve the reliability of the connection between the first memory chip and the logic chip.
  • the memory may further include a second memory chip, the second memory chip is overlapped with the first memory chip, the second memory chip has a plurality of second memory cell arrays, and the second memory cell is also connected to the second memory chip.
  • the differential amplifier of the logic chip is electrically connected. Both the first storage chip and the second storage chip are connected to the logic chip.
  • the number of memory chips included in the memory is not limited, and can be selected according to actual needs.
  • the above-mentioned second memory chip further includes a local differential amplifier, the bit line of the second memory cell array is connected to the input end of the local differential amplifier, and the output end of the local differential amplifier is connected to the differential amplifier on the logic chip.
  • the signal can be first amplified by a local differential amplifier, and then amplified by a differential amplifier located on the logic chip.
  • an appropriate connection method can be selected according to requirements, specifically, hybrid bonding can be used to connect the wiring layer of the first memory chip to the wiring layer of the logic chip.
  • hybrid bonding connection process the preparation of the first storage chip and the logic chip can be separately completed in batches, and then the first storage chip and the logic chip are connected.
  • the technical solution of the present application also provides an electronic device, which includes the memory in any of the foregoing technical solutions.
  • the storage data reading delay time of the electronic device is relatively short, and the storage capacity is relatively high and the cost is relatively low under the condition of a certain memory volume.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a memory in an embodiment of the application
  • FIG. 2 is a schematic diagram of a layout of a memory in an embodiment of the application
  • FIG. 3 is a schematic structural diagram of a first memory cell array in an embodiment of the application.
  • FIG. 4 is a schematic diagram of another layout of the memory in an embodiment of the application.
  • FIG. 5 is a schematic diagram of another cross-sectional structure of the memory in an embodiment of the application.
  • FIG. 6 is a schematic diagram of another cross-sectional structure of the memory in an embodiment of the application.
  • 25-reference voltage source 26-word line driver
  • 3-interconnect layer 4-bit line multiplexer
  • references described in this specification to "one embodiment” or “some embodiments”, etc. mean that one or more embodiments of the present application include a specific feature, structure, or characteristic described in combination with the embodiment. Therefore, the sentences “in one embodiment”, “in some embodiments”, “in some other embodiments”, “in some other embodiments”, etc. appearing in different places in this specification are not necessarily All refer to the same embodiment, but mean “one or more but not all embodiments” unless it is specifically emphasized otherwise.
  • the terms “including”, “including”, “having” and their variations all mean “including but not limited to”, unless otherwise specifically emphasized.
  • the memory provided in the embodiments of this application can be applied to electronic devices.
  • the above-mentioned electronic devices can be computer systems, such as servers, desktop computers, and notebook computers.
  • the above-mentioned electronic device may also be a mobile terminal product such as a mobile phone, and this application does not specifically limit the type of electronic device.
  • the memory in this application may specifically be a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the memory of this application can be specifically used to store data, and can write and read data.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a memory in an embodiment of this application
  • FIG. 2 is a schematic diagram of a layout of a memory in an embodiment of this application.
  • the first storage chip 1 and the logic chip 2 and the above-mentioned first storage chip 1 and the logic chip 2 are stacked and fixedly connected, and are electrically connected.
  • the aforementioned first memory chip 1 includes a plurality of first memory cell arrays 11 (subarray), and the logic chip 2 includes a plurality of differential amplifiers 21 and an interface control circuit 22.
  • FIG. 3 is a schematic structural diagram of the first memory cell array 11 in an embodiment of the application. Please refer to FIG. 3.
  • the first memory cell array 11 may include a plurality of memory cells arranged in an array, and each memory cell includes a transistor 111 and an AND This transistor 111 is connected to the bit line 113 and the word line 112.
  • the transistors 111 in each row are connected to the same word line 112, and the transistors 111 in each column are connected to the same bit line 113.
  • a transistor 111 is connected between any bit line 113.
  • the differential amplifier 21 of the logic chip 2 is electrically connected to the bit line 113 of the first memory cell array 11. Specifically, each differential amplifier 21 is connected to at least one bit line 113 of the first memory cell array 11. Each time it works, it is connected to a bit line 113 to amplify the signal corresponding to the connected bit line 113, so as to realize data transmission.
  • the differential amplifier 21 is located in the logic chip 2, and the first memory chip 1 can have a larger area for the first memory cell array 11 to expand the capacity of the memory.
  • the differential amplifier 21 and the first memory array unit 11 are both located on the first memory chip 1. That is, the differential amplifier 21 and the first memory array unit 11 are both located on the plane where the first memory chip 1 is located.
  • the connection line with the bit line 113 needs to cross a long distance in the first logic chip 1.
  • the first memory chip 1 and the logic chip 2 are overlapped, so that the differential amplifier 21 and the connected bit line 113 can be arranged oppositely, and the connection line when the first memory cell array 11 and the differential amplifier 21 are connected starts from the
  • the memory chip 1 spans to the logic chip 2, and the length of the above-mentioned connection line can be shortened, which is beneficial to shorten the delay.
  • the differential amplifier 21 and the interface control circuit 22 are both located in the logic chip 2, and the storage part is located in the first memory chip 1. Different processes can be used to prepare the first memory chip 1 and the logic chip 2.
  • the first memory chip 1 mainly includes a memory structure, which can increase the transistor density of the memory.
  • the logic chip 1 only includes the circuit structure, which facilitates the use of more advanced technology for processing, and can improve the density of the circuit structure and the calculation speed.
  • the above-mentioned differential amplifier 21 includes at least one set of differential input terminals, and each set of differential input terminals includes a first differential input terminal 211 and a second differential input terminal 212.
  • the differential amplifier 21 can perform data input from the first differential input terminal 211, and The data input by the two differential input terminals 212 is subjected to differential calculation.
  • the interface control circuit 22 further includes a reference voltage source 25.
  • the first differential input terminal 211 of the differential amplifier 21 is electrically connected to the first memory cell array 11, and specifically to the bit line 113 of the first memory cell array 11.
  • the second differential input terminal 212 is electrically connected to the above-mentioned reference voltage source 25.
  • the reference voltage source 25 inputs a reference voltage to the above-mentioned differential amplifier 21.
  • the differential amplifier 21 uses the reference voltage and the bit line 113 voltage input from the first input terminal to perform Differential calculation to obtain the data information of the storage unit.
  • the differential amplifier 21 is located in the memory chip.
  • the first differential input terminal 211 and the second differential input terminal 212 are both connected to the bit line 113, and the differential amplifier 21 is connected to the bit line 113.
  • the first memory chip 1 and the logic chip 2 are overlapped and electrically connected.
  • the connection lines between the first memory chip 1 and the logic chip 2 for connecting the bit line 113 and the differential amplifier 21 are greatly reduced, almost by half.
  • This solution can simplify the structure of the memory and reduce the area occupied by the connecting line between the differential amplifier 21 and the first memory chip 1.
  • the cost can also be reduced, and the calculation procedure can be simplified.
  • first memory chip 1 and the logic chip 2 are overlapped in the embodiment of the present application, and only the positional relationship between the first memory chip and the logic chip is described. Specifically, as shown in FIG. 2, the first memory chip 1 and the logic chip 2 are not located on the same plane. Both the first memory chip 1 and the logic chip 2 can be considered as a sheet structure, and the two sheet structures are stacked on top of each other. The first memory chip 1 and the logic chip 2 may be arranged in contact with each other, and other structures may also be arranged between the first memory chip 1 and the logic chip 2.
  • the differential amplifier 21 is a single-channel differential amplifier 21 and includes only a set of differential input terminals and output terminals 213, that is, the input terminal only includes a first differential input terminal 211 and a second differential input terminal 212.
  • each group of differential amplifiers 21 includes a first differential input terminal 211 and a second differential input terminal 212 in the embodiment of the present application.
  • Each differential amplifier 21 only performs a differential operation on the data obtained by the two corresponding differential input terminals of the road, and outputs the operation result from the output terminal 213 of the differential amplifier 21 of the road.
  • the aforementioned interface control circuit 22 may include a data bus, an address bus, a command enable terminal, a command register, a data/address latch, a global differential amplifier, a refresh counter and refresh control logic, a data buffer, a power supply circuit, a reference power supply, and so on.
  • the specific manner in which the first memory chip 1 and the logic chip 2 are stacked and electrically connected is not limited. It can be considered that there is an interconnection layer 3 between the first memory chip 1 and the logic chip 2.
  • the interconnection layer 3 realizes the fixed connection and electrical connection between the first memory chip 1 and the logic chip 2.
  • the first memory chip 1 includes a first semiconductor substrate 12, a plurality of first memory cell arrays 11 formed on the above-mentioned first semiconductor substrate 12, and a first wiring connected to the first memory cell array 11 Layer 13
  • the logic chip 2 includes a second semiconductor substrate 23, a differential amplifier 21 and an interface control circuit 22 formed on the second semiconductor substrate 23, and a second wiring layer connected to the differential amplifier 21 and the interface control circuit 22 twenty four.
  • the first memory chip 1 and the logic chip 2 are connected face-to-face. Specifically, it may be the first wiring layer 13 (first wiring layer) of the first memory chip 1.
  • the top wiring layer of the memory chip) and the second wiring layer 24 of the logic chip 2 are hybrid bonding, as shown in FIG. 1.
  • the hybrid bonding connection process is adopted, the preparation of the first storage chip 1 and the logic chip 2 can be completed in batches, and then the first storage chip 1 and the logic chip 2 can be connected.
  • the first chip top wiring layer 13 is opposite to the second chip top wiring layer 24 and is located inside the memory, it is necessary to provide through holes in the first semiconductor substrate 12 or the second semiconductor substrate 23 231, so that the memory can be connected to an external circuit.
  • the number of bit lines 113 included in the first memory cell array 11 may be less than 1024, and the number of word lines 112 included is less than 512, that is, the memory is fine-grained.
  • the number of bit lines 113 of the first memory cell array 11 may be 8 to 512; in another embodiment, the number of word lines 112 of the first memory cell array 11 is 8 to 256; in an embodiment, the number of bit lines 113 of the first memory cell array 11 can be 8 to 256, and the number of word lines 112 can be 8 to 512.
  • the memory cell array of the memory is fine-grained, and the number of memory cell arrays in each memory chip increases, and the number of differential amplifiers 21 connected to the bit line 113 also increases, resulting in differential The amplifier 21 occupies more area of the memory chip. In a memory chip of the same area, the area occupied by the memory cell array is reduced, the storage capacity is reduced, and the average cost per byte of storage is increased.
  • the differential amplifier 21 is disposed on the logic chip 2, and the first memory chip 1 can have a larger area for disposing the first memory cell array 11, which can increase the storage capacity of the memory.
  • FIG. 4 is a schematic diagram of another layout of the memory in an embodiment of the application.
  • the memory further includes a bit line multiplexer 4, one end of the bit line multiplexer 4 has multiple input ports, and the other end has an output The output port can be connected to any one of the multiple input ports.
  • Each input port of the bit line multiplexer 4 can be connected to a bit line 113 of the first memory cell array 11.
  • bit line multiplexer 4 Part of the input port of the bit line is connected to the bit line 113, which is not limited in this application; the output port of the bit line multiplexer 4 is connected to the differential amplifier 21, and the bit line multiplexer 4 can select a bit connected to the input port.
  • the line 113 communicates with the output port.
  • multiple bit lines 113 can share a differential amplifier 21 connection, and the bit line multiplexer 4 is used to make one bit line of the multiple bit lines 113 connected to the bit line multiplexer 4 113 is connected to the differential amplifier 21.
  • each bit line 113 is connected to a differential amplifier 21.
  • the number of bit lines 113 of each first memory cell array 11 of the memory decreases, that is, after the first memory cell array 11 is fine-grained, the number of first memory cell arrays 11 increases, and the bit lines 113 of the first memory chip 1
  • the total number also increases, and the number of differential amplifiers 21 that need to be connected is also larger, which occupies a larger area, and the cost of the first memory chip 1 also increases.
  • the number of differential amplifiers 21 used can be reduced, the area of the logic chip 2 occupied by the differential amplifiers 21 can be reduced, and the cost can be reduced.
  • the bit line multiplexer 4 when the bit line multiplexer 4 is specifically provided, the bit line multiplexer 4 can be provided on the first memory chip 1, thereby reducing the gap between the first memory chip 1 and the logic chip 2.
  • the number of connecting wires to simplify the process.
  • the reliability of the connection between the first storage chip 1 and the logic chip 2 is also high, and it is not easy to be damaged.
  • the bit line multiplexer 4 is located on the logic chip 2, the bit lines 113 of the first memory chip 1 need to be connected from the first memory chip 1 to the bit line multiplexer located on the logic chip 2. 4 input ports, more in number.
  • bit line multiplexer 4 While the bit line multiplexer 4 is located in the first memory chip 1, the bit line 113 is directly connected to the bit line multiplexer 4 in the first memory chip 1.
  • the logic chip 2 further includes a word line driver 26, and the word line driver 26 is connected to the word line 112 of the first memory chip 1.
  • the word line driver 26 is electrically connected to the word line 112 of the above-mentioned first memory cell array 11 to realize the opening and closing of the memory cells on the word line 112.
  • the word line driver 26 of the memory is located in the logic chip 2. Therefore, it does not occupy the area of the first memory chip 1, which is beneficial to increase the number of the first memory cell array 11 of the first memory chip 1 and increase the storage capacity of the memory. capacity.
  • the memory also includes a word line multiplexer 5, one end of the word line multiplexer 5 has multiple output ports, the other end has an input port, the input port can be connected with multiple output Any one of the mouth is connected.
  • Each output port of the word line multiplexer 5 can be connected to a word line 112 of the first memory cell array 11.
  • the input port of the word line multiplexer 5 is connected to the word line driver 26, and the word line multiplexer 5 can choose the one connected to the output port
  • the word line 112 communicates with the input port.
  • a word line driver 26 can be shared by multiple word lines 112, and the word line multiplexer 5 is used to make one word of the multiple word lines 112 connected by the word line multiplexer 5
  • the line 112 is connected to the word line driver 26.
  • each word line 112 is usually connected to a word line driver 26.
  • the number of word lines 112 of each first memory cell array 11 of the memory decreases, that is, after the first memory cell array 11 is fine-grained, the number of first memory cell arrays 11 increases, and the word lines 112 of the first memory chip 1
  • the total number also increases, the number of word line drivers 26 that need to be connected is also larger, the word line driver 26 occupies a larger area, and the cost of the first memory chip 1 also increases.
  • the number of word line drivers 26 used can be reduced, the area of the logic chip 2 occupied by the word line drivers 26 can be reduced, and the cost can be reduced.
  • the word line multiplexer 5 can be provided on the first memory chip 1, thereby reducing the number of connecting lines between the first memory chip 1 and the logic chip 2 to Simplify the process. In addition, if the number of connection lines between the first storage chip 1 and the logic chip 2 is small, the reliability of the connection between the first storage chip 1 and the logic chip 2 is also high, and it is not easy to be damaged. Specifically, if the word line multiplexer 5 is located in the logic chip 2, the word lines 112 of the first memory chip 1 need to be connected from the first memory chip to the word line multiplexer 5 located in the logic chip 2. More output ports.
  • the word line multiplexer 5 is located in the first memory chip 1, and the word line 112 is directly connected to the word line multiplexer 5 in the first memory chip 1.
  • the input port of the word line multiplexer 5 Connected to the logic chip 2, and the multiple output ports of the word line multiplexer 5 correspond to one input port, so the number of input ports is less than the number of output ports, then the first memory chip 1 and the logic chip 2 The number of connecting lines is small.
  • FIG. 5 is a schematic diagram of another cross-sectional structure of the memory in an embodiment of this application. Please refer to FIG. 1 is stacked, and the second memory chip 6 shares a logic chip 2 with the first memory chip 1.
  • the second memory chip 6 includes a plurality of second memory cell arrays 61, and the second memory cell array 61 is electrically connected to the differential amplifier 21.
  • the second memory chip 6 may have the structural features of the first memory chip 1, the connection relationship between the second memory chip 6 and the logic chip 2, or the connection relationship between the first memory chip 1 and the logic chip 2 .
  • the memory may include one second storage chip 6, or may include two or more second storage chips 6, which is not limited in this application.
  • the second memory chip 6 is a schematic diagram of another cross-sectional structure of the memory in an embodiment of the application.
  • the second memory chip 6 further includes a local differential amplifier 62, and the second memory cell array 61
  • the bit line is connected to the input terminal of the local differential amplifier 62, and the output terminal of the local differential amplifier 62 is connected to the differential amplifier 21 on the logic chip 2.
  • the signal can be first amplified by the local differential amplifier 62, and then amplified by the differential amplifier 21 located in the logic chip 2 for the second stage.

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

Mémoire et dispositif électronique. La mémoire comprend une première puce de stockage (1) et une puce logique (2) qui sont empilées et connectées électriquement. La première puce de stockage (1) comprend un premier réseau d'unités de stockage. Le réseau d'unités de stockage comprend une pluralité de transistors (111), et une pluralité de lignes de bits (113) et une pluralité de lignes de mots (112), les lignes de mots (112) et les lignes de bits (113) étant couplées aux transistors (111). La puce logique (2) comprend un amplificateur différentiel (21), un pilote de ligne de mots et une source de tension de référence (25), l'amplificateur différentiel (21), le pilote de ligne de mots et la source de tension de référence (25) étant tous connectés électriquement au premier réseau d'unités de stockage. L'amplificateur différentiel (21) comprend une première extrémité d'entrée différentielle (211), une seconde extrémité d'entrée différentielle (212) et une extrémité de sortie (213). La première extrémité d'entrée différentielle (211) est connectée électriquement aux lignes de bits (113) du premier réseau d'unités de stockage, et la seconde extrémité d'entrée différentielle (212) est connectée électriquement à la source de tension de référence (25), de sorte que l'amplificateur différentiel (21) réalise un traitement différentiel sur une tension de référence de la source de tension de référence (25) et des signaux des lignes de bits (113).
PCT/CN2020/077293 2020-02-28 2020-02-28 Mémoire et dispositif électronique WO2021168839A1 (fr)

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CN202080096121.4A CN115151972A (zh) 2020-02-28 2020-02-28 一种存储器和电子设备
PCT/CN2020/077293 WO2021168839A1 (fr) 2020-02-28 2020-02-28 Mémoire et dispositif électronique

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Cited By (1)

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CN116367540A (zh) * 2023-05-10 2023-06-30 长鑫存储技术有限公司 半导体结构及其形成方法

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