WO2021166067A1 - Substrat de transistor à couches minces et dispositif d'affichage - Google Patents

Substrat de transistor à couches minces et dispositif d'affichage Download PDF

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WO2021166067A1
WO2021166067A1 PCT/JP2020/006233 JP2020006233W WO2021166067A1 WO 2021166067 A1 WO2021166067 A1 WO 2021166067A1 JP 2020006233 W JP2020006233 W JP 2020006233W WO 2021166067 A1 WO2021166067 A1 WO 2021166067A1
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electrode
tft
gate
wiring
film
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PCT/JP2020/006233
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English (en)
Japanese (ja)
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井上　和式
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三菱電機株式会社
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Priority to JP2020536705A priority Critical patent/JP6806956B1/ja
Priority to PCT/JP2020/006233 priority patent/WO2021166067A1/fr
Publication of WO2021166067A1 publication Critical patent/WO2021166067A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/14—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • the present disclosure relates to a thin film transistor substrate having a thin film transistor (TFT) and a display device provided with the thin film transistor.
  • TFT thin film transistor
  • An active matrix substrate using a TFT as a switching element (hereinafter referred to as a TFT substrate) is known to be used in such an electro-optical display device.
  • An electro-optical display device using a TFT substrate is required not only to have high performance and high reliability of TFT characteristics necessary for improving display performance, but also to simplify the manufacturing process and efficiently perform manufacturing. There is also a demand for cost reduction.
  • the organic EL element has a basic structure in which an electric field light emitting layer containing an organic EL element is sandwiched between an anode electrode and a cathode electrode, and an anode is formed by applying a voltage between the anode electrode and the cathode electrode.
  • the organic EL element emits light by controlling the current in which holes are injected from the side and electrons are injected from the cathode side.
  • the basic pixel drive circuit for driving the organic EL elements is composed of two TFTs and one holding capacitance. ing.
  • the two TFTs one is a switching (selection) TFT for selecting display pixels, and the other is a pixel-driven TFT that supplies a current for causing the organic EL element to emit light.
  • the holding capacitance is configured such that, for example, the gate electrode of the pixel-driven TFT is used as one electrode and the source electrode or drain electrode of the pixel-driven TFT is used as the other electrode so as to face each other with an insulating layer interposed therebetween.
  • the scanning line (gate line) connected to the gate electrode of the selected TFT is selected, the selected TFT is turned on, and the signal voltage from the signal line (source line) connected to the selected TFT is accumulated in the holding capacitance.
  • the pixel-driven TFT is turned on by the signal voltage stored in the holding capacitance, the set current is output from the drain electrode of the pixel-driven TFT, and the anode electrode (pixel electrode) connected to the drain electrode of the pixel-driven TFT is organic. It is supplied to the EL element and becomes a light emitting state. This light emitting state is maintained until the next writing is performed.
  • Patent Document 1 A specific basic configuration of such a pixel drive circuit is disclosed in, for example, Patent Document 1.
  • Amorphous silicon has generally been used for the semiconductor channel layer of the TFT of the conventional TFT substrate for an electro-optical display device.
  • the main reasons for this are that a film with good uniformity of characteristics can be formed even on a large-area substrate because it is amorphous, and that it can be manufactured on an inexpensive glass substrate that is inferior in heat resistance because it can be formed at a relatively low temperature. It is possible to reduce the manufacturing cost of a display for a display device, and it is possible to manufacture a display for a display device that can be bent because it can be manufactured on a resin substrate having inferior heat resistance.
  • TFTs oxide semiconductor TFTs
  • oxide semiconductors examples include zinc oxide (ZnO) type and InGaZnO type in which gallium oxide (Ga 2 O 3 ) and indium oxide (In 2 O 3) are added to zinc oxide (ZnO).
  • oxide semiconductors generally have poor chemical resistance and have the property of being easily dissolved even in weak acid chemicals such as oxalic acid. Therefore, when an oxide semiconductor is used for the BCE (back channel etching) type TFT that is the mainstream in a-Si, the source electrode and drain electrode directly above the channel layer are formed by performing wet etching using an acid chemical solution. When formed, the oxide semiconductor of the channel layer is also etched, and there is a problem that a highly reliable channel region cannot be formed.
  • BCE back channel etching
  • Fig. 2. Fig. 3 and Fig. No. 5 discloses a TFT substrate for an organic EL display in which a selection TFT is arranged on the substrate and a pixel-driven TFT is arranged on the selection TFT.
  • the TFT substrate includes a part of BCE type TFT. Therefore, when an oxide semiconductor having high mobility is used for the channel layer of these TFT substrates, all TFTs are composed of ES type TFTs in order to secure chemical resistance and environmental resistance and obtain high reliability. There is a need to. Therefore, in order to complete the TFT substrate before the formation of the organic EL element, it is considered that at least 10 photoplate-making steps (1) to (10) shown below are required.
  • Forming step of gate electrode of selective TFT (2) Forming step of channel layer of selective TFT (3) Forming step of etching stopper (ES) layer on channel layer of selective TFT (4) Source electrode of selective TFT, Drain electrode, gate electrode of drive TFT forming step (5) Channel layer forming step of pixel-driven TFT (6) ES layer forming step on channel layer of pixel-driven TFT (7) Source electrode of pixel-driven TFT (7) Drive current supply electrode), drain electrode forming process (8) Contact hole forming process of protective insulating layer (9) Pixel electrode forming process (10) Pixel opening forming process of pixel separating layer (bank layer)
  • both the selective TFT and the pixel-driven TFT are composed of the ES type TFT, and the TFT substrate before the formation of the organic EL layer is formed by eight photoplate making steps.
  • the present disclosure has been made in order to solve the above problems, and an object of the present disclosure is to provide a technique for obtaining a TFT substrate having a TFT by simplifying a manufacturing process with high productivity and low cost.
  • the thin film semiconductor substrate includes at least a substrate, a bottom gate type first thin film film provided on the substrate, and a top gate type second thin film thin film.
  • a first gate electrode provided on the substrate, a first gate insulating layer provided on the first gate electrode, and a first semiconductor layer provided on the first gate insulating layer.
  • a second protective insulating layer provided on the source electrode and the second drain electrode of the above, and a third opening provided on the second protective insulating layer and penetrating the second protective insulating layer, respectively.
  • a second semiconductor layer in contact with the second source electrode and the second drain electrode through the portion and the fourth opening, and a second gate insulating layer provided on the second semiconductor layer. It has a second gate electrode provided on the second gate insulating layer, and the first gate electrode, the second source electrode, and the second drain electrode are the same in the same layer.
  • the first gate insulating layer and the second protective insulating layer are formed of the same conductive film of 1, and the same first insulating film is formed of the same layer, and the first semiconductor layer and the second semiconductor are formed.
  • the layer is formed of the same semiconductor film in the same layer, and the first protective insulating layer and the second gate insulating layer are formed of the same second insulating film in the same layer, and the first source electrode, The first drain electrode and the second gate electrode are formed of the same second conductive film in the same layer.
  • the manufacturing process can be simplified and the production can be carried out with high productivity, so that the manufacturing cost can be reduced. Can be reduced.
  • FIG. 1 shows schematic the structure of the TFT substrate which concerns on Embodiment 1.
  • FIG. 2 is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 1.
  • FIG. 2 is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 1.
  • FIG. is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 1.
  • FIG. is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 1.
  • FIG. is a top view which shows typically the whole structure of the TFT substrate which concerns on Embodiment 2.
  • It is a top view which shows schematic the plane structure of the TFT substrate which concerns on Embodiment 2.
  • FIG. 1 shows typically the whole structure of the TFT substrate which concerns on Embodiment 2.
  • FIG. 2 It is sectional drawing which shows schematic the structure of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. 2 It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the
  • FIG. 2 It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a perspective view which shows typically the display device provided with the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a figure which shows typically the structure of the pixel part drive circuit of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view which shows the plan structure of the TFT substrate which concerns on Embodiment 3 schematically.
  • FIG. drawing which shows schematic the structure of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which
  • FIG. 1 shows typically the structure of the pixel part drive circuit of the TFT substrate which concerns on the modification 1 of Embodiment 3.
  • FIG. 2 shows typically the structure of the pixel part drive circuit of the TFT substrate which concerns on the modification 2 of Embodiment 3.
  • FIG. 2 shows roughly the structure of the TFT substrate which concerns on the modification 2 of Embodiment 3.
  • FIG. 2 shows roughly the structure of the signal generation circuit.
  • the TFT substrate according to the embodiment described below can be used as an active matrix substrate for a self-luminous display device using a light emitting body such as an organic EL element or an LED element as a display element. It can also be applied to a TFT substrate having a signal drive circuit including a display device (Liquid Crystal display; LCD).
  • a display device Liquid Crystal display; LCD
  • FIG. 1 is a cross-sectional view schematically showing the configuration of the TFT substrate 100 according to the first embodiment.
  • the TFT substrate 100 includes a TFT 101 (first thin film transistor) and a TFT 102 (second thin film transistor).
  • the first TFT portion on which the TFT 101 is formed is shown on the right side of the figure, and the first TFT portion on which the TFT 102 is formed is shown on the left side of the figure.
  • the TFT 101 and the TFT 102 are arranged on the same substrate 1 having transparent insulation, for example, a glass substrate.
  • the TFT 101 has a structure in which a bottom gate reverse stagger structure is used to protect the channel, and a gate electrode 2 (first gate electrode) composed of a first conductive film is provided on the substrate 1 to cover the gate electrode 2.
  • the gate insulating layer 5 first gate insulating layer
  • a semiconductor layer 9 first semiconductor layer
  • a protective insulating layer 11 first protective insulating layer
  • a second insulating film is provided on the gate insulating layer 5 and the semiconductor layer 9.
  • the protective insulating layer 11 in the region overlapping the semiconductor layer 9 has an opening 13 (first opening) and an opening 14 (second opening), respectively, so that the surface of the lower semiconductor layer 9 is exposed. It is provided.
  • the opening 13 is a source region contact hole that exposes the surface of the semiconductor layer 9 that is the source region
  • the opening 14 is a drain region contact hole that exposes the surface of the semiconductor layer 9 that is the drain region.
  • a source electrode 15 (first source electrode) composed of a second conductive film is provided on the protective insulating layer 11 so as to come into contact with the semiconductor layer 9 through the opening 13, and the semiconductor is provided through the opening 14.
  • a drain electrode 16 (first drain electrode) composed of a second conductive film is provided so as to be in contact with the layer 9.
  • the source electrode 15 and the drain electrode 16 are provided separately from each other in the region overlapping the semiconductor layer 9, and the separated region sandwiched between the source electrode 15 and the drain electrode 16 in the semiconductor layer 9 is the channel region CL1 of the TFT 101. It is defined as (first channel region).
  • the protective insulating layer 11 on the channel region CL1 functions as a channel protection layer (first channel protection layer) that protects the channel region CL1 of the semiconductor layer 9 from process damage and the like. Therefore, the TFT 101 is a TFT having excellent characteristics and reliability.
  • the TFT 102 has a structure in which channels are protected by a top gate forward staggered structure, and a source electrode 3 (second source electrode) and a drain electrode 4 (second source electrode) composed of a first conductive film are formed on a glass substrate 1. Drain electrodes) are provided separately from each other, and a protective insulating layer 6 (second protective insulating layer) composed of a first insulating film is provided on the drain electrodes).
  • the protective insulating layer 6 has an opening 7 (third opening) that exposes a part of the surface of the source electrode 3 and an opening 8 (fourth opening) that exposes a part of the surface of the drain electrode 4. ) Is provided.
  • the semiconductor layer 10 (second semiconductor layer) formed of a semiconductor film is in contact with the source electrode 3 of the lower layer through the opening 7 and is in contact with the drain electrode 4 of the lower layer through the opening 8. ) Is provided.
  • the lower source electrode 3 and the drain electrode 4 are provided separately from each other in the region overlapping the semiconductor layer 10, and the separated region sandwiched between the source electrode 3 and the drain electrode 4 in the semiconductor layer 10 is the channel of the TFT 102. It is defined as region CL2 (second channel region).
  • a gate insulating layer 12 (second gate insulating layer) composed of a second insulating film is provided on the protective insulating layer 6 and the semiconductor layer 10, and further overlaps with the channel region CL2 of the semiconductor layer 10.
  • a gate electrode 17 (second gate electrode) composed of a second conductive film is provided on the gate insulating layer 12 of the above.
  • the protective insulating layer 6 of the channel region CL2 functions as a channel protection layer (second channel protection layer) that protects the channel region CL2 of the semiconductor layer 10 from process damage and the like. Therefore, the TFT 102 is a TFT having excellent characteristics and reliability.
  • the gate electrode 17 so as not to overlap the source electrode 3 and the drain electrode 4 in the lower layer, it is possible to eliminate the parasitic capacitance formed between the gate electrode and the source electrode and the drain electrode. It is possible to obtain characteristics having excellent responsiveness.
  • the TFT 101 having a bottom gate reverse stagger structure and the channel protection type TFT 102 having a top gate forward stagger structure have different structures and characteristics. Can be arranged on the same substrate.
  • Fig. 2 First, the substrate 1 having transparent insulation such as glass is washed with a cleaning liquid or pure water. In the first embodiment, a glass substrate having a thickness of 0.5 mm was used as the substrate 1. Then, the first conductive film is formed on one main surface of the washed substrate 1.
  • the first conductive film examples include metals such as chromium (Cr), molybdenum (Mo), titanium (Ti), copper (Cu), tantalum (Ta), tungsten (W), and aluminum (Al), or these.
  • An alloy or the like to which a small amount of other elements is added can be used.
  • a laminated structure containing two or more layers of these metals or alloys may be used. By using these metals and alloys, a low resistance conductive film having a specific resistance value of 50 ⁇ cm or less can be obtained.
  • Mo was used as the first conductive film, and the Mo film was formed to a thickness of 200 nm by a sputtering method using Ar (argon) gas. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the first photoplate-making step, and the Mo film is patterned by etching using the photoresist pattern as a mask.
  • wet etching with a solution (PAN chemical solution) containing phosphoric acid (Phosphoric Acid), acetic acid (Acetic Acid) and nitric acid (Nitric Acid) was used. After that, by removing the photoresist pattern, as shown in FIG. 2, the gate electrode 2 of the TFT 101, the source electrode 3 of the TFT 102, and the drain electrode 4 are simultaneously formed on the substrate 1.
  • the first insulating film is formed on the entire main surface of the substrate 1.
  • a silicon oxide film SiO film
  • CVD chemical vapor deposition
  • a SiO film having a thickness of 300 nm was formed under substrate heating conditions of about 300 ° C.
  • the first insulating film is not limited to the SiO film, and for example, a silicon nitride film (SiN film) can be used.
  • the SiN film can also be formed by the CVD method in the same manner as the SiO film. Further, it may be a laminated film of a SiO film and a SiN film.
  • a photoresist pattern is formed on the SiO film which is the first insulating film, and the SiO film is etched using this as a mask.
  • a dry etching method using a gas containing fluorine (F), for example, sulfur hexafluoride (SF 6 ) gas or carbon tetrafluoride (CF 4) gas can be used.
  • an opening 7 that exposes a part of the surface of the source electrode 3 and an opening that exposes a part of the surface of the drain electrode 4 8 are formed respectively.
  • the first insulating film of the first TFT portion functions as the gate insulating layer 5, and the first insulating film of the second TFT portion is used when the second semiconductor layer formed in a later step is formed. 2
  • the semiconductor layer functions as a protective insulating layer 6 (second channel protective layer) that protects the semiconductor layer from damage received from the source electrode 3 and the drain electrode 4.
  • a semiconductor film is formed on the first insulating film.
  • an oxide semiconductor film is formed as the semiconductor film.
  • an oxide (InGaZnO) containing indium (In), gallium (Ga), zinc (Zn) and oxygen (O) is used.
  • an oxide semiconductor film (InGaZnO film) was formed by a sputtering method using Ar gas using an InGaZnO target having an atomic composition ratio of In: Ga: Zn: O of 1: 1: 1: 4.
  • the atomic composition ratio of O is usually smaller than that of the stoichiometric composition, resulting in an oxide film in an O ion-deficient state (in the above example, the composition ratio of O is less than 4). Therefore, it is preferable to mix Ar gas with oxygen (O 2 ) gas and perform sputtering.
  • Ar gas oxygen
  • an InGaZnO film having a thickness of 50 nm was formed by sputtering using a mixed gas in which O 2 gas having a partial pressure ratio of 10% was added to Ar gas.
  • the InGaZnO film is formed with an amorphous structure.
  • the InGaZnO film having an amorphous structure generally has a crystallization temperature of more than 500 ° C., and at room temperature, most of the film remains stable with an amorphous structure.
  • the amorphous structure can have higher structural uniformity than a partially crystallized microcrystal structure or a polycrystalline structure. Therefore, even when the size of the substrate is increased, there is an advantage that a semiconductor film having a small variation in characteristics can be formed on the entire substrate.
  • a photoresist pattern is formed on the InGaZnO film in the third photoengraving process, and the InGaZnO film is etched using this as a mask.
  • wet etching with an oxalic acid chemical solution can be used.
  • the semiconductor layer 10 is formed on the protective insulating layer 6.
  • the semiconductor layer 10 is formed so as to be in contact with the source electrode 3 of the lower layer through the opening 7 of the protective insulating layer 6 and to be in contact with the drain electrode 4 of the lower layer through the opening 8 of the protective insulating layer 6.
  • the source electrode 3 and the drain electrode 4 are formed so as to have a separated region separated from each other in a region overlapping the semiconductor layer 10, and in the semiconductor layer 10, this separated region is a channel region (second channel) of the TFT 102. Region) CL2.
  • the oxide semiconductor film which is the material of the semiconductor layer 10
  • the metal films such as the source electrode 3 and the drain electrode 4 are exposed in the lower layer
  • the oxide semiconductor reacts with the metal during sputtering.
  • an oxide semiconductor film having deteriorated characteristics in the reduced (O ion deficient) state may be formed.
  • the protective insulating layer 6 of the channel region CL2 functions as the channel protective layer 6 (second channel protective layer) of the semiconductor layer 10.
  • the glass substrate 1 is heat-treated at a temperature of 400 ° C. in an air atmosphere.
  • the amorphous InGaZnO film of the semiconductor layer 9 and the semiconductor layer 10 causes structural relaxation, and the semiconductor characteristics can be further stabilized.
  • Structural relaxation is a phenomenon in which lattice defects of constituent atoms due to process damage such as film formation and wet etching are reduced, and the amorphous structure is more stabilized.
  • the temperature of the heat treatment for causing the above-mentioned structural relaxation of the amorphous InGaZnO film is preferably at least 300 ° C. or higher.
  • the temperature exceeds 500 ° C. crystallization starts in the entire film and the semiconductor characteristics change significantly, and for example, it becomes a conductor due to an increase in carrier density. Therefore, here, it is preferable to heat-treat at least the glass substrate 1 at a temperature of 300 ° C. or higher and 500 ° C. or lower.
  • such a heat treatment may be carried out at the end of the manufacturing process.
  • a second insulating film is formed on the entire main surface of the substrate 1.
  • a SiO film having a thickness of 300 nm was formed by a CVD method under a substrate heating condition of about 200 ° C.
  • the second insulating film is not limited to the SiO film, and for example, a SiN film can be used. Further, it may be a laminated film of a SiO film and a SiN film.
  • a photoresist pattern is formed on the SiO film which is the second insulating film, and the SiO film is etched using this as a mask.
  • a dry etching method using SF 6 gas or CF 4 gas can be used.
  • the second insulating film of the first TFT portion functions as a protective insulating layer 11 (first channel protective layer) for preventing processing process damage from the source electrode 15 and the drain electrode 16 formed in a later step. .. Further, the second insulating film of the second TFT portion functions as the gate insulating layer 12.
  • a second conductive film is formed on the second insulating film.
  • a metal such as Cr, Mo, Ti, Cu, Ta, W, Al, or an alloy obtained by adding a small amount of other elements to these, or the like. Can be used. Further, a laminated structure containing two or more layers of these metals or alloys may be used. By using these metals or alloys, a low resistance conductive film having a specific resistance value of 50 ⁇ cm or less can be obtained.
  • a Mo film was used as the second conductive film, and the Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the fifth photoplate-making step, and the Mo film is patterned by etching using the photoresist pattern as a mask. Here, wet etching with a PAN chemical solution was used. After that, by removing the photoresist pattern, as shown in FIG. 1, the source electrode 15 and the drain electrode 16 of the TFT 101 are formed on the substrate 1, and at the same time, the gate electrode 17 of the TFT 102 is formed.
  • the source electrode 15 of the TFT 101 is formed so as to be in contact with the semiconductor layer 9 through the opening 13. Further, the drain electrode 16 is formed so as to be in contact with the semiconductor layer 9 through the opening 14.
  • the source electrode 15 and the drain electrode 16 are provided separately from each other in the region overlapping the semiconductor layer 9, and the separated region sandwiched between the source electrode 15 and the drain electrode 16 in the semiconductor layer 9 is the channel region CL1 of the TFT 101. Is specified as.
  • the oxide semiconductor film has poor chemical resistance, and the InGaZnO film, which is the material of the semiconductor layer 9, is easily dissolved in the PAN chemical solution used for wet etching of the second conductive film.
  • the entire surface of the glass substrate 1 excluding the opening 13 and the opening 14 is covered with the protective insulating layer 11 formed of an insulating film, and the protective insulating layer 11 is particularly provided on the channel region CL1 of the semiconductor layer 9. Functions as a channel protection layer (etching stopper; ES). Therefore, a highly reliable TFT without process damage can be obtained.
  • the gate electrode 17 of the TFT 102 is formed so as to overlap the channel region CL2 of the lower second semiconductor layer. Further, by forming the source electrode 3 and the drain electrode 4 in the lower layer so as not to overlap with each other, it is possible to eliminate the parasitic capacitance formed between the gate electrode 17 and the source electrode 3 and the drain electrode 4, and the response is excellent. A high-speed response TFT can be obtained. Further, since the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained as in the case of the TFT 101.
  • the first TFT and the second TFT have different positional (upper and lower layers) relationships between the gate electrode, the source electrode, and the drain electrode. Both semiconductor layers are composed of the same semiconductor layer, and the structure of each layer including the respective electrodes can be made common. Therefore, the channel is a channel-protected first TFT with a bottom gate reverse staggered structure that is excellent in operation stability and reliability, and a top gate forward staggered structure that is excellent in reliability and has a small parasitic capacitance between electrodes and is excellent in responsiveness.
  • a TFT having a structure and characteristics different from that of the protective type second TFT can be manufactured with high productivity and low cost by using five photoplate-making steps.
  • each layer is standardized, for example, a TFT circuit in which the TFT 101 and the TFT 102 are combined is formed so as to connect the gate electrode 2 of the TFT 101 and either the source electrode 3 or the drain electrode 4 of the TFT 102.
  • a TFT circuit in which the TFT 101 and the TFT 102 are combined is formed so as to connect the gate electrode 2 of the TFT 101 and either the source electrode 3 or the drain electrode 4 of the TFT 102.
  • the gate electrode 2 and the source electrode 3 or the drain electrode 4 into a continuous integrated pattern, for example, as compared with a configuration in which both are formed separately and electrically connected via a contact hole.
  • the occurrence rate of defects due to poor signal transmission from the TFT 102 to the TFT 101 can be suppressed to a low level.
  • the same effect can be obtained by forming them in a continuous integrated pattern. ..
  • FIG. 6 is a plan view schematically showing the overall configuration of the TFT substrate 110 according to the second embodiment.
  • the TFT substrate 110 has a display region 150 in which pixels including at least the TFT 101, the TFT 102, and the pixel region PX are arranged in a matrix on the substrate 1, and a frame region 160 adjacent to the display region 150. It can be roughly divided.
  • An EL element 44 electroluminescence element
  • An organic material is arranged in the pixel region PX, and can be suitably used as a TFT substrate for a self-luminous display device provided with an organic EL display. can.
  • the contour shape of the TFT substrate 110 is shown as a quadrangle in FIG. 6, the contour shape is not limited to this, and may be a shape including a curved line such as a circular shape or an elliptical shape. Further, the TFT substrate 110 is not limited to being flat and may be curved.
  • a plurality of gate wirings 32 and a plurality of source wirings 34 are arranged so as to intersect each other so as to be orthogonal to each other, and are defined by the gate wirings 32 and the source wirings 34.
  • Is provided with a pixel and a pixel unit drive circuit ELC1 for driving the pixel is provided in the pixel.
  • a plurality of drive current wirings 36 are arranged adjacent to and parallel to the plurality of source wirings 34.
  • the pixel unit drive circuit ELC1 has a TFT 102 provided at the intersection of the gate wiring 32 and the source wiring 34, and a TFT 101 provided at the intersection of the gate wiring 32 and the drive current wiring 36.
  • the gate electrode 17 of the TFT 102 is electrically connected to the gate wiring 32
  • the source electrode 3 of the TFT 102 is electrically connected to the source wiring 34.
  • the TFT 102 functions as a selection TFT for selecting display pixels corresponding to the signals of the gate wiring and the source wiring.
  • the gate electrode 2 of the TFT 101 is electrically connected to the drain electrode 4 of the TFT 102. Further, the source electrode 15 of the TFT 101 is electrically connected to the drive current wiring 36, and the drain electrode 16 is electrically connected to the anode electrode 41 for driving the EL element 44. The cathode electrode 45 of the EL element 44 is connected to the ground potential.
  • the TFT 101 is provided with a holding capacity CsA connected between the gate electrode 2 and the drain electrode 16.
  • the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is used as the drive current from the TFT 101 through the anode electrode 41. It is supplied to the EL element 44, and the EL element 44 emits light.
  • a scanning signal drive circuit 170 that applies a signal voltage to the gate wiring 32 is connected to a gate terminal 33 provided at the end of the gate wiring 32, and is also driven by the source wiring 34 and the drive current wiring 36.
  • the display signal drive circuit 180 that gives a signal is provided at the end of the source wiring 34 and the end of the drive current wiring 36, respectively, at the source terminal 35 (second source terminal) and the source terminal 37 (first source terminal). It is connected to and arranged in. Further, alignment marks AM for alignment are provided at the four corners of the substrate 1.
  • the scanning signal drive circuit 170 and the display signal drive circuit 180 are arranged in the frame region 160 on the TFT substrate 110, but these are not arranged on the TFT substrate 110.
  • An external drive IC Integrated Circuit
  • TAB Tape Automated Bonding
  • COG Chip On Glass
  • FIG. 7 is a partial plan view showing a planar configuration of pixels including the TFT 101, TFT 102, holding capacity CsA, and pixel region PX provided in the display region 150 (FIG. 6) of the TFT substrate 110
  • FIG. 8 is a partial plan view of the pixels. It is a partial cross-sectional view which shows the cross-sectional structure.
  • the X1-X2 line in FIG. 7 is provided so as to extend over the TFT 101, the TFT 102 and the holding capacitance CsA, and the Y1-Y2 line extends from the drain electrode 16 of the TFT 101 to the pixel region PX.
  • the cross-sectional view in the direction shown and the cross-sectional view taken along the line Y1-Y2 are shown on the left side and the right side of FIG. 8, respectively.
  • the TFT 101 and the TFT 102 of the second embodiment have basically the same configuration as the TFT 101 and the TFT 102 of the first embodiment, the same components are designated by the same reference numerals, and redundant description will be omitted. ..
  • the TFT substrate 110 has various elements arranged on one main surface of the transparent insulating substrate 1.
  • the substrate 1 is made of a transparent and insulating material such as glass, plastic or resin.
  • the planar shape of the substrate 1 is not limited to the quadrangle illustrated in FIG.
  • the first TFT portion on the substrate 1 includes a gate electrode 2 (first gate electrode) composed of a first conductive film and a drive.
  • a current wiring 36 (first wiring) is provided, and a gate insulating layer 5 (first gate insulating layer) composed of a first insulating film is provided so as to cover the current wiring 36 (first wiring).
  • the second TFT portion is provided with a source electrode 3 (second source electrode) and a drain electrode 4 (second drain electrode), and is protected by a first insulating film so as to cover them.
  • An insulating layer 6 (second protective insulating layer) is provided.
  • the protective insulating layer 6 has an opening 7 (third opening) that exposes a part of the surface of the source electrode 3 and an opening 8 (fourth opening) that exposes a part of the surface of the drain electrode 4. ) Is provided.
  • the gate electrode 2 of the TFT 101 and the drain electrode 4 of the TFT 102 are provided in a continuous integrated pattern.
  • the drive current wiring 36 is arranged so as to extend in the vertical direction (Y direction), and the source wiring 34 is arranged so as to extend in parallel in the vertical direction so as to be adjacent to the drive current wiring 36. ..
  • the source electrode 3 of the TFT 102 is a part of the source wiring 34. That is, the source wiring 34 is composed of the first conductive film, and the portion of the source wiring 34 extending toward the TFT 102 is the source electrode 3. The portion provided with the source electrode 3 is wider than the other portion of the source wiring 34.
  • a semiconductor layer 9 (first semiconductor layer) composed of a semiconductor film is provided on the gate insulating layer 5 of the first TFT portion.
  • a semiconductor layer 10 (second semiconductor layer) composed of a semiconductor film is provided on the protective insulating layer 6 of the second TFT portion.
  • the semiconductor layer 10 is in contact with the source electrode 3 of the lower layer through the opening 7, and is in contact with the drain electrode 4 of the lower layer through the opening 8.
  • the semiconductor layer 9 of the TFT 101 is arranged in an island-like pattern in a region overlapping the gate electrode 2. Further, the source electrode 3 and the drain electrode 4 of the TFT 102 are separated and arranged so as to face each other, and the semiconductor layer 10 has an island shape so as to straddle the source electrode 3 and the drain electrode 4 separated from each other. It is arranged in the pattern of.
  • a second insulating film is provided so as to cover the first insulating film and the semiconductor film described above, and as shown in the cross-sectional view taken along the line X1-X2 of FIG. 8, the second TFT portion of the first TFT portion is provided.
  • the insulating film is provided with an opening 13 (first opening) and an opening 14 (second opening), respectively, so that a part of the surface of the lower semiconductor layer 9 is exposed.
  • the opening 13 is a contact hole that exposes a surface serving as a source region (first source region) of the semiconductor layer 9
  • the opening 14 is a surface serving as a drain region (first drain region) of the semiconductor layer 9. It is a contact hole that exposes.
  • the region between the opening 13 and the opening 14 of the second insulating film functions as a protective insulating layer 11 for protecting the semiconductor layer 9 from process damage.
  • the second insulating film on the semiconductor layer 10 of the second TFT portion functions as the gate insulating layer 12 of the TFT 102.
  • the source electrode 15 composed of the second conductive film so as to be in contact with the semiconductor layer 9 through the opening 13.
  • a drain electrode 16 (first drain electrode) composed of a second conductive film is provided so as to come into contact with the semiconductor layer 9 through the opening 14).
  • the source electrode 15 extends to a region overlapping the drive current wiring 36, and is provided so as to penetrate the first insulating film and the second insulating film so as to expose a part of the surface of the drive current wiring 36. It is connected to the drive current wiring 36 through the opening 30. Further, the drain electrode 16 is arranged so as to extend to a region overlapping the gate electrode 2 of the TFT 101 provided in an integral pattern continuous with the drain electrode 4 of the TFT 102. A gate electrode 17 (second gate electrode) composed of a second conductive film is provided on the gate insulating layer 12 in a region overlapping the semiconductor layer 10 of the TFT 102.
  • the drain electrode 16 of the TFT 101 overlaps the pattern of the gate electrode 2 and the drain electrode 4 of the TFT 102 in a region that does not overlap with the semiconductor layer 10, and is in the Y direction from these. It is arranged so that the width of the is wide. Then, the holding capacity CsA is formed by the region where the drain electrode 16 and the gate electrode 2 overlap.
  • the gate electrode 17 of the TFT 102 is arranged so as to overlap the semiconductor layer 10 in a region where the source electrode 3 and the drain electrode 4 are separated so as to face each other. Has been done. Further, the gate electrode 17 is arranged so as not to overlap the source electrode 3 and the drain electrode 4, and is configured so that a parasitic capacitance due to the overlap thereof is not formed.
  • the gate wiring 32 extending from the gate electrode 17 is provided so as to extend in the lateral direction (X direction) so as to be orthogonal to the source wiring 34 and the drive current wiring 36.
  • a protective insulating layer 18 (third protective insulating layer) composed of a third insulating film is provided on the entire surface of the substrate 1 so as to cover the 17 and the gate wiring 32.
  • the protective insulating layer 18 is provided with an opening 40 (fifth opening) so as to expose a part of the surface of the drain electrode 16 of the first TFT portion.
  • An anode electrode 41 composed of a fourth conductive film is provided on the protective insulating layer 18 so as to be connected to the drain electrode 16 through the opening 40 and extend to the pixel region PX.
  • a bank layer 42 composed of a fourth insulating film is provided on the anode electrode 41 and the protective insulating layer 18.
  • a bank opening 43 is provided in the bank layer 42 so that the surface of the anode electrode 41 is exposed, and an EL element 44 that functions as a pixel emitter is provided on the anode electrode 41 of the bank opening 43. ing.
  • the pixel region PX is defined by a region surrounded by the gate wiring 32, the source wiring 34, and the drive current wiring 36 in a plan view.
  • the anode electrode 41 is provided so as to extend from the region overlapping the opening 40 provided in the region overlapping the drain electrode 16 to the pixel region PX.
  • the anode electrode 41 is arranged so as not to overlap with the source wiring 34 or the drive current wiring 36, but may be arranged so as to partially overlap with each other.
  • the bank opening 43 provided in the bank layer 42 is arranged so as not to protrude from the anode electrode 41 in a region overlapping the anode electrode 41, and the adjacent bank openings 43 are separated (separated) by the bank layer 42. ), And are arranged in an manner independent of each other.
  • the EL element 44 is arranged on the entire region of the bank opening 43 so as not to protrude from the anode electrode 41.
  • the EL element 44 for example, an organic EL element composed of an organic material is used.
  • the organic EL element may have a three-layer structure in which a hole transport layer, an organic EL layer, and an electron transport layer are laminated in this order directly above the anode electrode 41. Further directly above it, a cathode electrode (not shown), which is the opposite electrode of the anode electrode 41, is provided. A current is supplied to the EL element 44 due to the potential difference between the anode electrode 41 and the cathode electrode, and the EL element 44 emits light. The emitted light is radiated downward through, for example, a substrate 1 made of glass, and an image is displayed.
  • the TFT substrate 110 according to the second embodiment is configured as described above, and the TFT substrate 110 including the EL element 44 is further provided with a sealing layer for blocking the EL element 44 from moisture and impurities. Further, a facing substrate is provided so as to face the TFT substrate 110, and the TFT substrate can be suitably used as a TFT substrate for a self-luminous display device using an organic EL element.
  • FIGS. 9 to 24 alternately show a plan view with FIG. 7 as the final process diagram and a cross-sectional view with FIG. 8 as the final process diagram.
  • a cross-sectional view along the line and a cross-sectional view along the Y1-Y2 line are shown on the left and right sides of the figure, respectively.
  • a Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the first photoplate-making step, and the Mo film is patterned by wet etching using a PAN chemical solution using the photoresist pattern as a mask. Then, by removing the photoresist pattern, as shown in FIGS. 9 and 10, the gate electrode 2 of the TFT 101, the source electrode 3 of the TFT 102, the drain electrode 4, the source wiring 34, and the drive current wiring 36 are placed on the substrate 1. Are formed at the same time.
  • the gate electrode 2 and the drain electrode 4 are formed in a continuous integrated pattern. Further, the source wiring 34 and the drive current wiring 36 are formed so as to extend in parallel in the vertical direction (Y direction) so as to be adjacent to each other.
  • the source electrode 3 is a part of the source wiring 34, and a portion having a width wider than the other parts of the source wiring 34 is formed as the source electrode 3.
  • the first insulating film is formed on the entire main surface of the substrate 1.
  • a SiO film having a thickness of 300 nm was formed by a CVD method under the substrate heating condition of about 300 ° C.
  • the first insulating film is not limited to the SiO film, and for example, a SiN film can be used.
  • the SiN film can also be formed by the CVD method in the same manner as the SiO film. Further, it may be a laminated film of a SiO film and a SiN film.
  • a photoresist pattern is formed on the SiO film which is the first insulating film, and the SiO film is etched using this as a mask.
  • a dry etching method using SF 6 gas or CF 4 gas can be used.
  • the opening 7 that exposes a part of the surface of the source electrode 3 and the surface of the drain electrode 4 Each of the openings 8 that exposes a part is formed.
  • the first insulating film of the first TFT portion functions as the gate insulating layer 5
  • the first insulating film of the second TFT portion is the second insulating film formed in a later step.
  • the semiconductor layer When the semiconductor layer is formed, it functions as a protective insulating layer 6 that protects the second semiconductor layer from damage received from the source electrode 3 and the drain electrode 4.
  • a semiconductor film is formed on the first insulating film.
  • an oxide semiconductor film is formed as the semiconductor film. Specifically, sputtering using an InGaZnO target having an atomic composition ratio of In: Ga: Zn: O of 1: 1: 1: 4 and a mixed gas in which O 2 gas having a partial pressure ratio of 10% is added to Ar gas. By the method, an InGaZnO film, which is an oxide semiconductor film, was formed with a thickness of 50 nm.
  • the InGaZnO film is formed with an amorphous structure.
  • the InGaZnO film having an amorphous structure generally has a crystallization temperature of more than 500 ° C., and at room temperature, most of the film remains stable with an amorphous structure.
  • the amorphous structure can have higher structural uniformity than the partially crystallized microcrystal structure and polycrystalline structure. Therefore, even when the size of the substrate is increased, there is an advantage that a semiconductor film having a small variation in characteristics can be formed on the entire substrate. That is, even when the TFT substrate used for a large display device is used for a large display device, the in-plane variation of the TFT characteristics can be reduced, so that display unevenness can be prevented.
  • a photoresist pattern is formed on the InGaZnO film in the third photoengraving process, and the InGaZnO film is etched using this as a mask.
  • wet etching with an oxalic acid chemical solution can be used.
  • the semiconductor layer 10 is formed on the protective insulating layer 6.
  • the semiconductor layer 10 is formed so as to be in contact with the source electrode 3 of the lower layer through the opening 7 of the protective insulating layer 6 and to be in contact with the drain electrode 4 of the lower layer through the opening 8 of the protective insulating layer 6.
  • the source electrode 3 and the drain electrode 4 are formed so as to be separated from each other in a region overlapping the semiconductor layer 10 and have a separated region, and in the semiconductor layer 10, this is formed.
  • the separation region is defined as the channel region CL2 (FIG. 14) of the TFT 102.
  • the oxide semiconductor film which is the material of the semiconductor layer 10
  • the metal films such as the source electrode 3 and the drain electrode 4 are exposed in the lower layer
  • the oxide semiconductor reacts with the metal during sputtering.
  • an oxide semiconductor film having deteriorated characteristics in the reduced (O ion deficient) state may be formed.
  • the protective insulating layer 6 of the channel region CL2 functions as the channel protective layer 6 of the semiconductor layer 10.
  • the substrate 1 is heat-treated at a temperature of 400 ° C. in an air atmosphere.
  • the amorphous InGaZnO film of the semiconductor layer 9 and the semiconductor layer 10 causes structural relaxation, and the semiconductor characteristics can be further stabilized.
  • the temperature of the heat treatment for causing the above-mentioned structural relaxation of the amorphous InGaZnO film is preferably at least 300 ° C. or higher.
  • the temperature exceeds 500 ° C. crystallization starts in the entire film and the semiconductor characteristics change significantly, and for example, it becomes a conductor due to an increase in carrier density. Therefore, here, it is preferable to heat-treat at least the substrate 1 at a temperature of 300 ° C. or higher and 500 ° C. or lower.
  • such a heat treatment may be carried out at the end of the manufacturing process.
  • a second insulating film is formed on the entire main surface of the substrate 1.
  • a SiO film having a thickness of 300 nm was formed by a CVD method under a substrate heating condition of about 200 ° C.
  • the second insulating film is not limited to the SiO film, and for example, a SiN film can be used. Further, it may be a laminated film of a SiO film and a SiN film.
  • a photoresist pattern is formed on the SiO film which is the second insulating film, and the SiO film is etched using this as a mask.
  • a dry etching method using SF 6 gas or CF 4 gas can be used.
  • the portion 14 is formed.
  • the second insulating film of the first TFT portion functions as a protective insulating layer 11 for preventing processing process damage from the source electrode 15 and the drain electrode 16 formed in a later step.
  • the second insulating film of the second TFT portion functions as the gate insulating layer 12 of the TFT 102. Further, an opening 30 penetrating the first insulating film and the second insulating film is formed so as to expose a part of the surface of the drive current wiring 36.
  • a second conductive film is formed on the second insulating film.
  • the Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas as the second conductive film.
  • a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the fifth photoplate-making step, and the Mo film is patterned by wet etching using a PAN chemical solution using the photoresist pattern as a mask.
  • the source electrode 15 and the drain electrode 16 of the TFT 101 are formed, and at the same time, the gate electrode 17 of the TFT 102 is formed.
  • the source electrode 15 of the TFT 101 is formed so as to be in contact with the semiconductor layer 9 through the opening 13. Further, the drain electrode 16 is formed so as to be in contact with the semiconductor layer 9 through the opening 14.
  • the source electrode 15 and the drain electrode 16 are formed separately from each other in a region overlapping the semiconductor layer 9, and the separated region sandwiched between the source electrode 15 and the drain electrode 16 in the semiconductor layer 9 is the channel region CL1 of the TFT 101. Is defined as.
  • the oxide semiconductor film has poor chemical resistance, and the InGaZnO film, which is the material of the semiconductor layer 9, is easily dissolved in the PAN chemical solution used for wet etching of the second conductive film.
  • the protective insulating layer 11 formed of the second insulating film since the entire surface of the substrate 1 excluding the opening 13 and the opening 14 is covered with the protective insulating layer 11 formed of the second insulating film, the channel is particularly on the channel region CL1 of the semiconductor layer 9. It functions as a protective layer (etching stopper; ES layer). Therefore, a highly reliable TFT without process damage can be obtained.
  • the source electrode 15 extends to a region overlapping the drive current wiring 36, and is connected to the drive current wiring 36 through the opening 30. Further, the drain electrode 16 is formed so as to extend to a region overlapping the gate electrode 2 of the TFT 101 provided in an integral pattern continuous with the drain electrode 4 of the TFT 102.
  • the drain electrode 16 of the TFT 101 overlaps the pattern of the gate electrode 2 and the drain electrode 4 of the TFT 102 in a region that does not overlap with the semiconductor layer 10, and is wider in the Y direction than these. Is formed to be wide.
  • the holding capacity CsA is formed by the region where the drain electrode 16 and the gate electrode 2 overlap.
  • the gate wiring 32 extending from the gate electrode 17 is formed so as to extend in the lateral direction (X direction) so as to be orthogonal to the source wiring 34 and the drive current wiring 36.
  • the gate electrode 17 of the second TFT portion is separated from the channel region CL2 of the lower semiconductor layer 10 in the region where the source electrode 3 and the drain electrode 4 are separated from each other. It is formed so as to overlap. Further, the gate electrode 17 is formed so as not to overlap the source electrode 3 and the drain electrode, and is configured so that a parasitic capacitance due to the overlap thereof is not formed. Thereby, a TFT having excellent responsiveness can be obtained. Further, since the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained as in the case of the TFT 101.
  • a third insulating film is formed on the entire main surface of the substrate 1.
  • a resin-based coating film is used as the third insulating film.
  • a photosensitive transparent acrylic resin film was applied and formed by using a spin coating method.
  • the transparent acrylic resin film was coated and formed so that the thickness was 1.5 ⁇ m at the portion where the film thickness was the thinnest.
  • a SiO film or a SiN film may be formed by, for example, a CVD method before the transparent acrylic resin film is applied and formed as the third insulating film.
  • an SOG (Spin-On Glass) -based, epoxy-based, polyimide-based, or polyolefin-based resin film can be used in addition to the acrylic-based coating film.
  • the protective insulating layer 18 in the region where the holding capacity CsA was formed was first covered with the first protective insulating layer 18.
  • the opening 40 is formed so that a part of the surface of the drain electrode 16 of the TFT portion is exposed.
  • dry etching using SF 6 gas or CF 4 gas is performed using the protective insulating layer 18 (transparent acrylic resin) on which the opening 40 is formed as a mask.
  • a fourth conductive film is formed on the protective insulating layer 18 including the opening 40.
  • a transparent ITO film an oxide conductive film containing indium oxide In 2 O 3 and tin oxide Sn O 2
  • the ITO film generally has a stable crystalline (polycrystalline) structure at room temperature, but here, a gas containing hydrogen (H) in Ar gas, for example, hydrogen (H 2 ) gas or water vapor (H 2 O).
  • H hydrogen
  • H 2 O water vapor
  • a photoresist pattern is formed on the amorphous ITO film in the 7th photoplate making process, and the amorphous ITO film is etched using this as a mask.
  • wet etching with an oxalic acid chemical solution can be used.
  • the anode electrode 41 made of a transparent ITO film is formed.
  • the anode electrode 41 is formed so as to be connected to the drain electrode 16 of the lower layer through the opening 40 of the protective insulating layer 18 and extend to the pixel region PX in the holding capacity CsA.
  • the pixel area PX is defined by the area surrounded by the gate wiring 32, the source wiring 34, and the drive current wiring 36.
  • the anode electrode 41 is formed so as to extend from a region overlapping the opening 40 provided in the region overlapping the drain electrode 16 to the pixel region PX.
  • the anode electrode 41 is formed so as not to overlap with the source wiring 34 or the drive current wiring 36, but may be formed so as to partially overlap. Since the amorphous ITO film formed as the fourth conductive film in the second embodiment has no crystal grain boundaries, the flatness of the film surface can be made extremely high.
  • a current signal having high in-plane uniformity can be supplied from the anode electrode 41 to the EL element 44 (FIG. 7), so that uniform light emission with little unevenness can be generated from the entire in-plane of the EL element 44. ..
  • a fourth insulating film to be the bank layer 42 is formed on the entire main surface of the substrate 1.
  • a resin-based coating film is used as the fourth insulating film.
  • a photosensitive transparent acrylic resin film was applied and formed so as to have a thickness of 1.5 ⁇ m by a spin coating method.
  • the acrylic type, SOG type, epoxy type, polyimide type, or polyolefin type resin films can be used.
  • the polyimide resin film is preferable because it has a small amount of adsorbed water and does not affect the characteristics and reliability of the EL element formed in the subsequent steps.
  • the bank opening 43 in which the surface of the anode electrode 41 is exposed in the pixel region PX is formed.
  • the bank layer 42 having the bank layer 42 is formed.
  • the bank openings 43 are formed only in the pixel display region on the anode electrode 41, that is, the region where the EL element 44 is formed in the subsequent step, and the bank openings 43 adjacent to each other are formed by the bank layer 42. It is an isolated aspect.
  • the EL element 44 is formed in the region of the bank opening 43 so as to be in contact with the anode electrode 41, thereby obtaining the configurations shown in FIGS. 7 and 8.
  • an organic organic EL material is used as the EL layer of the EL element 44.
  • an EL layer was formed by laminating a hole transport layer, an organic EL layer, and an electron transport layer in this order using an inkjet printing method. According to the inkjet printing method, the EL layer can be selectively formed only in the concave region of the bank opening 43, so that the EL element 44 can be formed without using the photoengraving process.
  • the whole transport layer can be widely selected from known organic materials such as triarylamines, aromatic hydrazones, aromatic-substituted pyrazolines, and stillbens, and can be selected from, for example, N, N'-diphenyl-N, N-. It is formed to an arbitrary thickness of 1 nm to 200 nm using a triphenylamine system (TPD) such as bis (3-methylphenyl) -1,1'-diphenyl-4,4'-diamine.
  • TPD triphenylamine system
  • Known organic EL layers include dicyanomethylenepyrane derivative (R color emission), coumarin type (G color emission), quinacridone type (G color emission), tetraphenylbutadiene type (B color emission), and distyrylbenzene type (B color emission).
  • a material such as (emission) is formed with an arbitrary thickness of 1 nm to 200 nm.
  • the electron transport layer is formed with an arbitrary thickness of 0.1 nm to 200 nm using a material selected from known oxadiazole derivatives, triazole derivatives, coumarin derivatives and the like.
  • the EL layer can be formed by using a vapor deposition method in addition to the printing method.
  • the EL element 44 is formed without using the photoengraving process by using a mask vapor deposition method in which, for example, a metal mask having the same opening pattern as the bank opening 43 is attached to the surface of the substrate 1. Can be done.
  • the TFT substrate 110 according to the second embodiment is completed through the steps described above. As shown in FIG. 25, a cathode electrode 45, which is a counter electrode of the anode electrode 41, is formed on the completed TFT substrate 110. Further, if necessary, a sealing layer 46 for further blocking the TFT substrate 110 including the EL element 44 from moisture and impurities is formed, and the opposing substrate 47 is further bonded so as to face the TFT substrate 110, so that the organic EL element is formed. A self-luminous display device 300 equipped with an organic EL display using the above is completed.
  • the self-luminous display device 300 can realize a display device with a high aperture ratio and bright display quality at low cost with few display defects.
  • the self-luminous display device 300 including the TFT substrate 110 according to the second embodiment emits the emitted light ELL of the EL element downward (opposite to the opposing substrate 47) through the TFT substrate 110 for display.
  • It will be a bottom emission type self-luminous display device.
  • it is not limited to the bottom emission type, and it is also possible to use a top emission type self-luminous display device that emits light from the emission light ELL of the EL element above the TFT substrate 110 (opposite substrate 47 side) for display. ..
  • the fourth conductive film which is the material of the anode electrode 41, is made of silver (Ag) -based or Al having high reflectance instead of the transparent ITO film.
  • the ITO film may be formed on the metal film.
  • the emitted light ELL from the organic EL element can be reflected by the anode electrode 41 to emit light upward, so that a top-emission type self-luminous display device can be obtained.
  • the TFT 102 is electrically connected to the gate wiring 32 and the source wiring 34, and is used to select display pixels according to the signals of the gate wiring 32 and the source wiring 34. Functions as a selective TFT.
  • the gate electrode 17 of the TFT 102, the source electrode 3 and the drain electrode 4 are configured so that parasitic capacitances are not formed on each other, a TFT having excellent responsiveness can be obtained.
  • the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained. Therefore, high performance can be exhibited as a selective TFT.
  • the TFT 101 is electrically connected to the drain electrode 4, the drive current wiring 36, and the EL element 44 of the TFT 102, and functions as a pixel drive TFT of the EL element 44.
  • the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is supplied to the EL element 44 as a drive current.
  • EL element 44 emits light.
  • the channel region CL1 of the TFT 101 is protected by the protective insulating layer 11, the reliability is high and the signal current can be stably supplied to the EL element 44, so that the EL element 44 is made to emit light stably. High quality image display is possible.
  • the drain electrode 4 of the TFT 102 and the gate electrode 2 of the TFT 101 are formed in the same continuous pattern of the first conductive film and integrated. Is formed as a separate body and electrically connected via a contact hole, and the occurrence rate of display defects due to poor signal transmission from the TFT 102 to the TFT 101 can be suppressed to a low level.
  • the continuously integrated gate electrode 2 and drain electrode 4 can be used as a capacitance electrode having a holding capacitance of CsA, Fig. 9721973 of US Pat. No.
  • the holding capacity CsA can be formed much more efficiently in the area, so that the formation region of the TFT circuit can be reduced and the pixel region can be reduced.
  • the aperture ratio of the PX can be improved. As a result, even in the case of a bottom-emission type self-luminous display device in which the EL element 44 emits light downward through the substrate 1 for display, bright and high-quality image display can be performed.
  • Section 3 shows a configuration example of a TFT substrate for a self-luminous display device (LED display) in which an LED element (LED chip) is mounted on the TFT substrate to display an image.
  • the configuration of the TFT substrate 120 according to the third embodiment will be described with reference to FIGS. 26 to 28.
  • the same components as those in the first and second embodiments are designated by the same reference numerals, and duplicate description will be omitted.
  • FIG. 26 is a diagram showing the configuration of the pixel portion drive circuit LEDC1 of the pixels of the TFT substrate 120 according to the third embodiment.
  • FIG. 27 is a partial plan view showing the planar configuration of the pixels including the TFT 101, TFT 102, the holding capacity CsA, and the pixel region PX provided on the TFT substrate 120
  • FIG. 28 is a partial cross-sectional view showing the cross-sectional configuration of the pixels. be.
  • the X1-X2 wire in FIG. 27 extends over the pixel region PX including the TFT 101, the TFT 102, the holding capacity CsA, and the LED element mounting portion, and the Y1-Y2 wire is provided so as to extend from the source electrode 15 of the TFT 101 to the drive current wiring portion.
  • the cross-sectional view taken along the line X1-X2 and the cross-sectional view taken along the line Y1-Y2 are shown on the left and right sides of FIG. 28, respectively.
  • an LED element is mounted on each pixel of the TFT substrate 120 to form a self-luminous display device. Therefore, unlike the pixel unit drive circuit ELC1 of the second embodiment shown in FIG. 6, as shown in FIG. 26, the anode electrode 61 (first electrode) and the cathode electrode 63 (second electrode) are on the TFT substrate 120. The electrode) is provided, and the LED element 200 (light emitting diode element) is arranged so as to be connected to the anode electrode 61 and the cathode electrode 63.
  • the TFT substrate 120 is arranged on the substrate so that a plurality of gate wirings 32 and a plurality of source wirings 34 intersect each other so as to be orthogonal to each other, and the gate wirings 32 are arranged.
  • a TFT 102 is provided at the intersection of the source wiring 34 and the source wiring 34.
  • the gate electrode 17 of the TFT 102 is electrically connected to the gate wiring 32, and the source electrode 3 of the TFT 102 is electrically connected to the source wiring 34.
  • the TFT 102 functions as a selection TFT for selecting display pixels corresponding to the signals of the gate wiring 32 and the source wiring 34.
  • a plurality of drive current wirings 36 are arranged in parallel adjacent to the plurality of source wirings 34, and a TFT 101 is provided at the intersection of the gate wiring 32 and the drive current wiring 36.
  • the gate electrode 2 of the TFT 101 is electrically connected to the drain electrode 4 of the TFT 102.
  • the source electrode 15 of the TFT 101 is electrically connected to the drive current wiring 36, and the drain electrode 16 is electrically connected to the anode electrode 61 for driving the LED element 200.
  • a plurality of cathode electrode wirings 62 (second wirings) are arranged adjacent to and parallel to the plurality of gate wirings 32, and the cathode electrodes 63 electrically connected to the cathode electrode wirings 62 are connected to the LED element 200. It is connected.
  • the TFT 101 is provided with a holding capacity CsA connected between the gate electrode 2 and the drain electrode 16.
  • the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is transferred to the anode electrode 61 and the cathode electrode 63. It is supplied to the LED element 200 by the potential difference, and the LED element 200 emits light.
  • the TFT 101 on the substrate 1 has a gate electrode 2 composed of a first conductive film and a driving current.
  • Wiring 36 is provided, and a gate insulating layer 5 composed of a first insulating film is provided so as to cover the wiring 36.
  • the TFT 102 is provided with a source electrode 3 and a drain electrode 4, and is provided with a protective insulating layer 6 formed of a first insulating film so as to cover them.
  • the protective insulating layer 6 is provided with an opening 7 for exposing a part of the surface of the source electrode 3 and an opening 8 for exposing a part of the surface of the drain electrode 4.
  • the gate electrode 2 of the TFT 101 and the drain electrode 4 of the TFT 102 are provided as a continuous integrated pattern.
  • the drive current wiring 36 is arranged so as to extend in the vertical direction (Y direction), and the source wiring 34 is arranged so as to extend parallel to the vertical direction (Y direction) so as to be adjacent to the drive current wiring 36. It is installed.
  • the source electrode 3 of the TFT 102 is a part of the source wiring 34. That is, the source wiring 34 is composed of the first conductive film, and the portion of the source wiring 34 extending toward the TFT 102 is the source electrode 3. The portion provided with the source electrode 3 is wider than the other portion of the source wiring 34.
  • a semiconductor layer 9 composed of a semiconductor film is provided on the gate insulating layer 5 of the TFT 101. ing. Further, a semiconductor layer 10 made of a semiconductor film is provided on the protective insulating layer 6 of the TFT 102. The semiconductor layer 10 is in contact with the source electrode 3 of the lower layer through the opening 7, and is in contact with the drain electrode 4 of the lower layer through the opening 8.
  • the semiconductor layer 9 of the TFT 101 is arranged in an island-like pattern in a region overlapping the gate electrode 2. Further, the source electrode 3 and the drain electrode 4 of the TFT 102 of the TFT 102 are separated and arranged so as to face each other, and the semiconductor layer 10 is an island so as to straddle the source electrode 3 and the drain electrode 4 separated from each other. It is arranged in a similar pattern.
  • a second insulating film is provided so as to cover the first insulating film and the semiconductor film described above, and as shown in the cross-sectional view taken along the line X1-X2 and the cross-sectional view taken along the line Y1-Y2 in FIG. 28.
  • the second insulating film of the TFT 101 is provided with an opening 13 and an opening 14, respectively, so that a part of the surface of the lower semiconductor layer 9 is exposed.
  • the region between the opening 13 and the opening 14 of the second insulating film functions as a protective insulating layer 11 for protecting the semiconductor layer 9 from process damage.
  • the second insulating film on the semiconductor layer 10 of the TFT 102 functions as the gate insulating layer 12 of the TFT 102.
  • a source electrode 15 composed of a second conductive film is provided so as to be in contact with the semiconductor layer 9 through the opening 13, and the opening is further provided.
  • a drain electrode 16 composed of a second conductive film is provided so as to come into contact with the semiconductor layer 9 through 14.
  • a cathode electrode wiring 62 composed of a second conductive film is provided on the second insulating film of the pixel region PX.
  • the source electrode 15 extends to a region overlapping the drive current wiring 36, and is provided so as to penetrate the first insulating film and the second insulating film so as to expose a part of the surface of the drive current wiring 36. It is connected to the drive current wiring 36 through the opening 30. Further, the drain electrode 16 is arranged so as to extend to a region overlapping the gate electrode 2 of the TFT 101 provided in an integral pattern continuous with the drain electrode 4 of the TFT 102 portion. A gate electrode 17 composed of a second conductive film is provided on the gate insulating layer 12 in a region overlapping the semiconductor layer 10 of the TFT 102.
  • the drain electrode 16 of the TFT 101 is arranged so as to be a region protruding from the region overlapping the semiconductor layer 9 and widely overlapping the pattern of the gate electrode 2 and the drain electrode 4 of the TFT 102. It is installed. Then, the holding capacity CsA is formed by the region where the drain electrode 16 and the gate electrode 2 overlap.
  • the gate electrode 17 of the TFT 102 is arranged so as to overlap the semiconductor layer 10 in a region where the source electrode 3 and the drain electrode 4 are separated from each other so as to face each other. ing. Further, the gate electrode 17 is arranged so as not to overlap the source electrode 3 and the drain electrode 4, and is configured so that a parasitic capacitance due to the overlap thereof is not formed.
  • the gate wiring 32 extending from the gate electrode 17 is provided so as to extend in the lateral direction (X direction) so as to be orthogonal to the source wiring 34 and the drive current wiring 36. Further, the cathode electrode wiring 62 is arranged so as to extend in parallel in the lateral direction so as to be adjacent to the gate wiring 32 in the pixel region PX on the side opposite to the TFT 101 and the TFT 102.
  • the source electrode 15 and the drain electrode 16 of the TFT 101, and the gate electrode 17 and the gate wiring 32 of the TFT 102 are provided.
  • a protective insulating layer 18 composed of a third insulating film is provided on the entire surface of the substrate 1 so as to cover it.
  • the protective insulating layer 18 is provided with an opening 48 (fifth opening) so as to expose a part of the surface of the drain electrode 16 of the FT101 portion so as to expose a part of the surface of the cathode electrode wiring 62.
  • anode electrode 61 (first electrode) composed of a fifth conductive film is arranged on the protective insulating layer 18 of the pixel region PX so as to be connected to the drain electrode 16 through the opening 48. .. Further, a cathode electrode 63 (second electrode) composed of a fifth conductive film is arranged so as to be connected to the cathode electrode wiring 62 through the opening 49.
  • a protective insulating layer 50 composed of a fifth insulating film is provided on the protective insulating layer 18 including the anode electrode 61 and the cathode electrode 63.
  • an anode electrode opening 51 is provided so that the surface of the lower anode electrode 61 is exposed
  • a cathode electrode opening 52 is provided so that the surface of the lower cathode electrode 63 is exposed. It is provided.
  • the protective insulating layer 50 may not be provided.
  • the pixel region PX is defined by the region surrounded by the gate wiring 32, the source wiring 34, and the drive current wiring 36.
  • the anode electrode 61 is provided so as to extend from a region overlapping the opening 48 provided in the region overlapping the drain electrode 16 to a region below the pixel region PX.
  • the cathode electrode 63 is provided so as to extend from a region overlapping the opening 49 provided in the region overlapping the cathode electrode wiring 62 to a region above the pixel region PX.
  • the anode electrode 61 and the cathode electrode 63 are arranged in the pixel region PX in a manner in which they are separated from each other and face each other in a plan view.
  • the anode electrode opening 51 and the cathode electrode opening 52 are arranged so as to face each other in a plan view so that the lower layer anode electrode 61 and the cathode electrode 63 are exposed, respectively.
  • the TFT substrate 120 is configured as described above, and is arranged on the TFT substrate 120 so as to correspond to the anode electrode 61 and the cathode electrode 63 of each pixel region PX arranged in a matrix.
  • a self-luminous display device LED display
  • a plurality of LED element anode electrode terminals and cathode electrode terminals are mounted so as to be connected to each other (not shown), and each LED element is made to emit light to display an image.
  • each LED element is made to emit light to display an image.
  • FIGS. 29 to 43 a plan view having FIG. 27 as a final process view and a cross-sectional view having FIG. 28 as a final process view are alternately shown.
  • X1-X2 of FIG. 28 is shown.
  • a cross-sectional view along the line and a cross-sectional view along the Y1-Y2 line are shown on the left and right sides of the figure, respectively.
  • a Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas as the first conductive film. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the first photoplate-making step, and the Mo film is patterned by wet etching using a PAN chemical solution using the photoresist pattern as a mask. Then, by removing the photoresist pattern, as shown in FIGS. 29 and 30, the gate electrode 2 of the TFT 101, the source electrode 3 and the drain electrode 4 of the TFT 102, and the source wiring 34 and the drive current are further mounted on the substrate 1. Wiring 36 is formed at the same time.
  • the gate electrode 2 and the drain electrode 4 are formed in a continuous integrated pattern in a plan view. Further, the source wiring 34 and the drive current wiring 36 are formed so as to extend in parallel in the vertical direction (Y direction) so as to be adjacent to each other.
  • the source electrode 3 is a part of the source wiring 34. That is, the source wiring 34 is composed of the first conductive film, and the portion of the source wiring 34 extending toward the TFT 102 is the source electrode 3. The portion provided with the source electrode 3 is wider than the other portion of the source wiring 34.
  • the first insulating film is formed on the entire main surface of the substrate 1.
  • a SiO film having a thickness of 300 nm was formed by a CVD method under the substrate heating condition of about 300 ° C.
  • the first insulating film is not limited to the SiO film, and for example, a SiN film can be used.
  • the SiN film can also be formed by the CVD method in the same manner as the SiO film. Further, it may be a laminated film of a SiO film and a SiN film.
  • a photoresist pattern is formed on the SiO film which is the first insulating film, and the SiO film is etched using this as a mask.
  • a dry etching method using SF 6 gas or CF 4 gas can be used.
  • the opening 7 that exposes a part of the surface of the source electrode 3 and the surface of the drain electrode 4 Each of the openings 8 that exposes a part is formed.
  • the first insulating film of the first TFT portion functions as the gate insulating layer 5
  • the first insulating film of the second TFT portion is the second semiconductor formed in a later step.
  • it functions as a protective insulating layer 6 (second channel protective layer) that protects the second semiconductor layer from damage received from the source electrode 3 and the drain electrode 4.
  • a semiconductor film is formed on the first insulating film.
  • an oxide semiconductor film is formed as the semiconductor film. Specifically, sputtering using an InGaZnO target having an atomic composition ratio of In: Ga: Zn: O of 1: 1: 1: 4 and a mixed gas in which O 2 gas having a partial pressure ratio of 10% is added to Ar gas. By the method, an InGaZnO film, which is an oxide semiconductor film, was formed with a thickness of 50 nm.
  • the InGaZnO film is formed with an amorphous structure.
  • the InGaZnO film having an amorphous structure generally has a crystallization temperature of more than 500 ° C., and at room temperature, most of the film remains stable with an amorphous structure.
  • the amorphous structure can have higher structural uniformity than a partially crystallized microcrystal structure or a polycrystalline structure. Therefore, even when the size of the substrate is increased, there is an advantage that a semiconductor film having a small variation in characteristics can be formed on the entire substrate. That is, even when the TFT substrate used for a large display device is used for a large display device, the in-plane variation of the TFT characteristics can be reduced, so that display unevenness can be prevented.
  • a photoresist pattern is formed on the InGaZNO film in the third photoengraving process, and the InGaZnO film is etched using this as a mask.
  • wet etching with an oxalic acid chemical solution can be used.
  • the semiconductor layer 9 is formed in an island-like pattern in the region overlapping the gate electrode 2 on the gate insulating layer 5 in the first TFT portion. Will be done.
  • the semiconductor layer 10 is formed on the protective insulating layer 6.
  • the semiconductor layer 10 is formed so as to be in contact with the source electrode 3 of the lower layer through the opening 7 of the protective insulating layer 6 and to be in contact with the drain electrode 4 of the lower layer through the opening 8 of the protective insulating layer 6.
  • the source electrode 3 and the drain electrode 4 are formed so as to be separated from each other in a region overlapping the semiconductor layer 10 and have a separated region, and in the semiconductor layer 10, this separated region is the channel region CL2 of the TFT 102. Is defined as.
  • the oxide semiconductor film which is the material of the semiconductor layer 10
  • the metal films such as the source electrode 3 and the drain electrode 4 are exposed in the lower layer
  • the oxide semiconductor reacts with the metal during sputtering.
  • an oxide semiconductor film having deteriorated characteristics in the reduced (O ion deficient) state may be formed.
  • the protective insulating layer 6 of the channel region CL2 functions as the channel protective layer 6 of the semiconductor layer 10.
  • the substrate 1 is heat-treated at a temperature of 400 ° C. in an air atmosphere.
  • the amorphous InGaZnO film of the semiconductor layer 9 and the semiconductor layer 10 causes structural relaxation, and the semiconductor characteristics can be further stabilized.
  • the temperature of the heat treatment for causing the above-mentioned structural relaxation of the amorphous InGaZnO film is preferably at least 300 ° C. or higher.
  • the temperature exceeds 500 ° C. crystallization starts in the entire film and the semiconductor characteristics change significantly, for example, the film becomes a conductor due to an increase in carrier density. Therefore, here, it is preferable to heat-treat at least the substrate 1 at a temperature of 300 ° C. or higher and 500 ° C. or lower.
  • such a heat treatment may be carried out at the end of the manufacturing process.
  • a second insulating film is formed on the entire main surface of the substrate 1.
  • a SiO film having a thickness of 300 nm was formed by a CVD method under a substrate heating condition of about 200 ° C.
  • the second insulating film is not limited to the SiO film, and for example, a SiN film can be used. Further, it may be a laminated film of a SiO film and a SiN film.
  • a photoresist pattern is formed on the SiO film which is the second insulating film, and the SiO film is etched using this as a mask.
  • a dry etching method using SF 6 gas or CF 4 gas can be used.
  • the portion 14 is formed.
  • the second insulating film of the first TFT portion functions as a protective insulating layer 11 for preventing processing process damage from the source electrode 15 and the drain electrode 16 formed in a later step.
  • the second insulating film of the second TFT portion functions as the gate insulating layer 12 of the TFT 102.
  • an opening 30 is formed in the first insulating film and the second insulating film so as to expose a part of the surface of the drive current wiring 36.
  • a second conductive film is formed on the second insulating film.
  • the Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas as the second conductive film.
  • a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the fifth photoplate-making step, and the Mo film is patterned by wet etching using a PAN chemical solution using the photoresist pattern as a mask. After that, by removing the photoresist pattern, as shown in FIGS.
  • the source electrode 15 and the drain electrode 16 of the TFT 101 are formed, and at the same time, the gate electrode 17 of the TFT 102 is formed. Further, a cathode electrode wiring 62 composed of a conductive film is formed on the insulating film of the pixel region PX.
  • the source electrode 15 of the TFT 101 is formed so as to be in contact with the semiconductor layer 9 through the opening 13. Further, the drain electrode 16 is formed so as to be in contact with the semiconductor layer 9 through the opening 14.
  • the source electrode 15 and the drain electrode 16 are formed separately from each other in the region overlapping the semiconductor layer 9, and the separated region sandwiched between the source electrode 15 and the drain electrode 16 in the semiconductor layer 9 is the channel region CL1 of the TFT 101. Is specified as.
  • the oxide semiconductor film has poor chemical resistance, and the InGaZnO film, which is the material of the semiconductor layer 9, is easily dissolved in the PAN chemical solution used for wet etching of the second conductive film.
  • the protective insulating layer 11 formed of the second insulating film since the entire surface of the substrate 1 excluding the opening 13 and the opening 14 is covered with the protective insulating layer 11 formed of the second insulating film, the channel is particularly on the channel region CL1 of the semiconductor layer 9. It functions as a protective layer (etching stopper; ES layer). Therefore, a highly reliable TFT without process damage can be obtained.
  • the source electrode 15 extends to a region overlapping the drive current wiring 36, and is connected to the drive current wiring 36 through the opening 30. Further, the drain electrode 16 is formed so as to extend to a region overlapping the gate electrode 2 of the TFT 101 provided in an integral pattern continuous with the drain electrode 4 of the TFT 102. In a plan view, the drain electrode 16 of the TFT 101 is arranged so as to be a region protruding from the region overlapping the semiconductor layer 10 and widely overlapping the pattern of the gate electrode 2 and the drain electrode 4 of the TFT 102. Then, the holding capacity CsA is formed by the region where the drain electrode 16 and the gate electrode 2 overlap.
  • the cathode electrode wiring 62 is formed so as to extend in the pixel region PX on the opposite side of the TFT 101 and the TFT 102 so as to be adjacent to the gate wiring 32 and parallel to the lateral direction (X direction). ing.
  • the gate electrode 17 of the TFT 102 is formed so as to overlap the channel region CL2 of the lower semiconductor layer 10 in a region where the source electrode 3 and the drain electrode 4 are separated so as to face each other. Further, in a plan view, the gate electrode 17 is formed so as not to overlap the source electrode 3 and the drain electrode, and is configured so that a parasitic capacitance due to the overlap thereof is not formed. As a result, a TFT having excellent high-speed response can be obtained. Further, since the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained as in the case of the TFT 101.
  • the gate wiring 32 extending from the gate electrode 17 is formed so as to extend in the lateral direction (X direction) so as to be orthogonal to the source wiring 34 and the drive current wiring 36.
  • a third insulating film to be the protective insulating layer 18 is formed on the entire main surface of the substrate 1.
  • a photosensitive transparent acrylic resin film is applied and formed as a third insulating film by a spin coating method.
  • the transparent acrylic resin film was coated and formed so that the thickness was 1.5 ⁇ m at the portion where the film thickness was the thinnest.
  • a SiO film or a SiN film may be formed by, for example, a CVD method before the transparent acrylic resin film is applied and formed.
  • the resin-based coating film an SOG-based, epoxy-based, polyimide-based, or polyolefin-based resin film can be used in addition to the acrylic-based coating film.
  • the drain of the TFT 101 is drained to the protective insulating layer 18 in the region where the holding capacity CsA is formed.
  • the opening 48 is formed so that a part of the surface of the electrode 16 is exposed.
  • an opening 49 is formed in the protective insulating layer 18 in the region overlapping the cathode electrode wiring 62 so that a part of the surface of the cathode electrode wiring 62 is exposed.
  • SF 6 gas or CF 4 gas is used as a mask using the transparent acrylic resin in which the openings 48 and 49 are formed.
  • a fifth conductive film is formed on the third protective insulating layer including the opening 48 and the opening 49.
  • a transparent ITO film is used as the fifth conductive film.
  • the ITO film generally has a stable crystalline (polycrystalline) structure at room temperature, but here, a gas containing hydrogen (H) in Ar gas, for example, hydrogen (H 2 ) gas or water vapor (H 2 O). ) And the like were subjected to sputtering to form an ITO film having a thickness of 100 nm in an amorphous state (amorphous ITO film).
  • a photoresist pattern is formed on the amorphous ITO film in the 7th photoplate making process, and the amorphous ITO film is etched using this as a mask.
  • wet etching with an oxalic acid chemical solution can be used.
  • the anode electrode 61 and the cathode electrode 63 made of a transparent ITO film are formed.
  • the anode electrode 61 is provided so as to extend from a region overlapping the opening 48 provided in the region overlapping the drain electrode 16 to a region below the pixel region PX.
  • the cathode electrode 63 is provided so as to extend from a region overlapping the opening 49 provided in the region overlapping the cathode electrode wiring 62 to a region above the pixel region PX.
  • the anode electrode 61 and the cathode electrode 63 are arranged in the pixel region PX in a manner in which they are separated from each other and face each other in a plan view.
  • a fifth insulating film to be the protective insulating layer 50 is formed on the entire main surface of the substrate 1.
  • a photosensitive transparent acrylic resin film is coated and formed so as to have a thickness of 1.5 ⁇ m by a spin coating method.
  • acrylic type SOG type, epoxy type, polyimide type, or polyolefin type resin films can be used.
  • the anode electrode is opened so that the surface of the anode electrode 61 is exposed in the pixel region PX as shown in FIGS. 27 and 28.
  • the portion 51 is formed, and the cathode electrode opening 52 is formed so that the surface of the cathode electrode 63 is exposed.
  • the anode electrode opening 51 and the cathode electrode opening 52 are formed so as to face each other.
  • the TFT substrate 120 according to the third embodiment is completed in eight photoengraving steps. It is also possible to omit the formation of the fifth insulating film. In this case, the TFT substrate 120 according to the third embodiment can be completed in seven photoplate-making steps.
  • the anode electrode terminal 201 and the lower electrode terminal 202 of the LED element 200 correspond to the anode electrode 61 and the cathode electrode 63 of the pixel region PX, respectively. Implemented to be connected.
  • a facing substrate 47 is attached to the TFT substrate 120 on which the LED element 200 is mounted, if necessary, and a self-luminous display device 310 provided with an LED display using the LED element is provided. Complete.
  • the self-luminous display device 310 can realize a display device with a high aperture ratio and bright display quality at low cost with few display defects.
  • the self-luminous display device 310 provided with an LED display has lower power consumption, a wider viewing angle, and a higher contrast ratio than the self-luminous display device of the second embodiment provided with an organic EL display. It is possible to realize a high-quality image display.
  • the TFT 102 is electrically connected to the gate wiring 32 and the source wiring 34, and the display pixels are selected according to the signals of the gate wiring 32 and the source wiring 34. Functions as a selection TFT of.
  • the gate electrode 17 of the TFT 102, the source electrode 3 and the drain electrode 4 are configured so that parasitic capacitances are not formed on each other, a TFT having excellent responsiveness can be obtained.
  • the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained. Therefore, high performance can be exhibited as a selective TFT.
  • the TFT 101 is electrically connected to the drain electrode 4, the drive current wiring 36, and the LED element 200 of the TFT 102, and functions as a pixel drive TFT of the LED element 200.
  • the TFT 101 operates according to the written voltage, the signal current from the drive current wiring 36 is supplied to the LED element 200, and the LED The element 200 emits light.
  • the channel region CL1 of the TFT 101 is protected by the protective insulating layer 11, the reliability is high, the signal current can be stably supplied to the LED element 200, the LED element 200 is made to emit light stably, and the value is high. It is possible to display quality images.
  • the drain electrode 4 of the TFT 102 and the gate electrode 2 of the TFT 101 are formed and integrated in the same continuous pattern of the first conductive film. Therefore, for example, they are separated from each other. Compared with a configuration in which the body is formed and electrically connected via a contact hole, the occurrence rate of display defects due to poor signal transmission from the TFT 102 to the TFT 101 can be suppressed to a low rate.
  • the continuously integrated gate electrode 2 and drain electrode 4 can be used as a capacitance electrode having a holding capacitance of CsA, Fig. 9721973 of US Pat. No.
  • the holding capacity CsA can be formed much more efficiently in the area, so that the formation region of the TFT circuit can be reduced and the pixel region can be reduced.
  • the aperture ratio of the PX can be improved.
  • the cathode electrode 63 can be formed at the same time as the anode electrode 61 by using the fifth conductive film. Further, the cathode electrode wiring 62 that supplies the signal current to the cathode electrode 63 can be formed at the same time as the drain electrode 16 and the like of the TFT 101 by using the second conductive film. Therefore, a TFT substrate for a self-luminous display device (LED display) equipped with an LED element can be manufactured at low cost without increasing the number of steps.
  • LED display self-luminous display device
  • the first modification of the third embodiment is a modification of the configuration of the holding capacity CsA of the third embodiment.
  • the configuration of the TFT substrate 130 according to the first modification of the third embodiment will be described with reference to FIGS. 45 and 46.
  • the same components as those of the TFT substrate 120 of the third embodiment are designated by the same reference numerals, and redundant description will be omitted.
  • FIG. 45 is a diagram showing the configuration of the pixel portion drive circuit LEDC2 of the pixels of the TFT substrate 130 according to the first modification of the third embodiment.
  • FIG. 46 is a partial plan view showing a planar configuration of pixels including the TFT 101, the TFT 102, the holding capacity CsA, and the pixel region PX provided on the TFT substrate 130.
  • the TFT substrate 120 of the third embodiment has a configuration in which the holding capacity CsA is connected between the gate electrode 2 and the drain electrode 16 of the TFT 101.
  • the TFT substrate 130 of the first modification of the third embodiment has a configuration in which the holding capacity CsB is connected between the gate electrode 2 of the TFT 101 and the source electrode 15.
  • the TFT 101 when the selection signal output from the drain electrode 4 of the TFT 102 is written to the holding capacitance CsB, the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is transferred to the anode electrode 61 and the cathode. It is supplied to the LED element 200 by the potential difference from the electrode 63, and the LED element 200 emits light.
  • the holding capacitance CsB has a pattern shape of a capacitance electrode composed of a first conductive film and composed of a drain electrode 4 of the TFT 102 and a gate electrode 2 of the TFT 101 arranged in a continuous integrated pattern, and a second conductivity. It can be configured by changing the pattern shape of the source electrode 15 and the drain electrode 16 of the TFT 101 made of a film.
  • the source electrode 15 protrudes from the region where the semiconductor layer 9 overlaps, and overlaps the capacitance electrode formed of the integrated pattern of the gate electrode 2 and the drain electrode 4. It is arranged so as to extend to. As a result, the holding capacitance CsB is formed by the region where the source electrode 15 and the gate electrode 2 overlap.
  • a first insulating film forming the gate insulating layer 5 and a second insulating film forming the protective insulating layer 11 are laminated and provided between the capacitance electrode and the source electrode 15. Needless to say, the configuration of the holding capacity CsA of the second embodiment may be changed to the holding capacity CsB described above.
  • the second modification of the third embodiment is a modification of the configuration of the holding capacity CsA of the third embodiment.
  • the configuration of the TFT substrate 140 according to the second modification of the third embodiment will be described with reference to FIGS. 47 and 48.
  • the same components as those of the TFT substrate 120 of the third embodiment are designated by the same reference numerals, and redundant description will be omitted.
  • FIG. 47 is a diagram showing the configuration of the pixel portion drive circuit LEDC3 of the pixels of the TFT substrate 140 according to the second modification of the third embodiment.
  • FIG. 48 is a partial plan view showing a planar configuration of pixels including the TFT 101, the TFT 102, the holding capacity CsAB, and the pixel region PX provided on the TFT substrate 140.
  • the TFT substrate 120 of the third embodiment has a configuration in which the holding capacity CsA is connected between the gate electrode 2 and the drain electrode 16 of the TFT 101.
  • the holding capacity CsAB is between the gate electrode 2 of the TFT 101 and the source electrode 15, and the gate electrode 2 of the TFT 101. It is configured to be connected in parallel with the drain electrode 16.
  • the TFT 101 when the selection signal output from the drain electrode 4 of the TFT 102 is written to the holding capacitance CsAB, the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is transferred to the anode electrode 61 and the cathode. It is supplied to the LED element 200 by the potential difference from the electrode 63, and the LED element 200 emits light.
  • the holding capacitance CsAB is the pattern shape of the capacitance electrode composed of the drain electrode 4 of the TFT 102 composed of the first conductive film and the gate electrode 2 of the TFT 101 arranged in a continuous integrated pattern, and the second conductivity. It can be configured by changing the pattern shape of the source electrode 15 and the drain electrode 16 of the TFT 101 made of a film.
  • the drain electrode 16 protrudes from the region where the semiconductor layer 9 overlaps, and overlaps with the capacitance electrode formed of the integrated pattern of the gate electrode 2 and the drain electrode 4. It is arranged so as to extend to.
  • the holding capacity CsA first holding capacity
  • a first insulating film forming the gate insulating layer 5 and a second insulating film forming the protective insulating layer 11 are laminated and provided between the capacitance electrode and the drain electrode 16.
  • the source electrode 15 is a region protruding from the region overlapping the semiconductor layer 9, and is arranged so as to extend so as to overlap the capacitive electrode formed of an integrated pattern of the gate electrode 2 and the drain electrode 4. ing.
  • the holding capacity CsB (second holding capacity) is formed by the region where the source electrode 15 and the capacitance electrode overlap.
  • a first insulating film forming the gate insulating layer 5 and a second insulating film forming the protective insulating layer 11 are laminated and provided between the capacitance electrode and the source electrode 15.
  • the holding capacity CsAB is composed of the holding capacity CsA and the holding capacity CsB connected in parallel. Needless to say, the configuration of the holding capacity CsA of the second embodiment may be changed to the holding capacity CsAB described above.
  • the TFT substrate 130 of the first modification of the third embodiment and the TFT substrate 140 of the second modification described above can also obtain the same effect as the TFT substrate 120 of the third embodiment.
  • the scanning signal drive circuit 170 provided in the frame region 160 of the TFT substrate 110 according to the second embodiment shown in FIG. 6 includes a plurality of signal generation circuits (not shown).
  • the configurations of TFT 101 and TFT 102 can be applied.
  • FIG. 49 shows the configuration of the signal generation circuit GSC to which the TFT 101 and the TFT 102 are applied.
  • the clock signal CLK is supplied to the source electrode of the drive transistor 103.
  • the drain electrode of the drive transistor 103 is connected to the source electrode of the drive transistor 104, and the ground potential VSS is given to the drain electrode of the drive transistor 104.
  • the connection node N1 between the drive transistors 103 and 104 is connected to the gate electrode of the drive transistor 103 and the drain electrode of the drive transistor 105 via the holding capacitance C1.
  • the power supply potential VDD is supplied to the source electrode of the drive transistor 105.
  • the connection node N1 between the drive transistors 103 and 104 is an output node of the signal generation circuit GSC, from which a scan signal is supplied to the corresponding gate wiring 32.
  • the drive transistor 105 When the drive transistor 105 is turned on by the drive signal supplied to the gate electrode of the drive transistor 105, the drive transistor 103 is turned on and the clock signal CLK is output from the connection node N1.
  • the drive transistor 104 when the drive transistor 104 is turned on by the drive signal supplied to the gate electrode of the drive transistor 104, the potential of the connection node N1 is fixed to the ground potential VSS.
  • the configurations of the drive transistors 103 and 105 which are the components of the signal generation circuit GSC, can be the same as those of the TFTs 101 and 102 of the second embodiment, the third embodiment, and the modifications thereof.
  • the configuration of these signal generation circuits GSC can be suitably used not only for a self-luminous display device but also for a TFT substrate for a liquid crystal display device using a liquid crystal (Liquid Crystal).
  • the present disclosure is not limited to the TFT substrate for the display device, and can be applied to other semiconductor devices including, for example, a shift register circuit having a similar transistor configuration, and the scope of these disclosures.
  • each embodiment can be freely combined, and each embodiment can be appropriately modified.
  • the oxide semiconductor film can be directly electrically connected to the metal film and the alloy film. Therefore, as in the present disclosure, the TFT 101 in which the source electrode 15 and the drain electrode 16 are provided on the upper surface (front surface) of the semiconductor layer 9 and the source electrode 3 and the drain electrode 4 are provided on the lower surface (back surface) of the semiconductor layer 10. In the case of a configuration in which the TFT 102 and the TFT 102 are arranged at the same time, it is preferable to use an oxide semiconductor film as the semiconductor layer.
  • the oxide semiconductor material is not limited to InGaZnO oxide semiconductor, and for example, In—O, Ga—O, Zn—O, In—Zn—O, which are oxide semiconductors in which In, Ga, and Zn are appropriately combined.
  • In—Ga—O and Ga—Zn—O and other metal oxides can be used.
  • oxide semiconductors in which oxides such as hafnium (Hf), tin (Sn), yttrium (Y), and aluminum (Al) are appropriately combined can also be applied. ..
  • oxide semiconductors elements selected from Group 13 Al, Ga, and In and elements selected from Group 15 nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb) can be used.
  • Group III-V compound semiconductors such as Ga-As, Ga-P, In-P, In-Sb, In-As, Al-N, Ga-N, Al-Ga-N or these.
  • a semiconductor material to which other elements have been added may be used.
  • carbon nanotubes and graphene using carbon (C), which is a group 14 semiconductor element, and a semiconductor material in which Si and Ge elements are combined with these.
  • each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted within the scope of the disclosure.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

Ce substrat de transistor à couches minces est configuré de telle sorte qu'un premier transistor à couches minces de type à grille inférieure et qu'un second transistor à couches minces de type à grille supérieure sont disposés sur un substrat, des couches semi-conductrices respectives peuvent être formées en tant que même couche semi-conductrice, et chaque couche comprenant chaque électrode peut avoir une structure commune. Une électrode de grille du premier transistor à couches minces et une électrode de drain du second transistor à couches minces sont formées selon un motif intégré continu et fonctionnent en tant qu'électrodes capacitives formant une capacité de maintien, et la capacité de maintien est formée entre l'électrode capacitive et une première électrode de drain du premier transistor à couches minces.
PCT/JP2020/006233 2020-02-18 2020-02-18 Substrat de transistor à couches minces et dispositif d'affichage WO2021166067A1 (fr)

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JP7437359B2 (ja) 2021-08-30 2024-02-22 シャープディスプレイテクノロジー株式会社 アクティブマトリクス基板およびその製造方法

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WO2023148852A1 (fr) * 2022-02-02 2023-08-10 シャープディスプレイテクノロジー株式会社 Dispositif d'affichage et procédé de production de dispositif d'affichage

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