WO2021166067A1 - Thin film transistor substrate and display device - Google Patents

Thin film transistor substrate and display device Download PDF

Info

Publication number
WO2021166067A1
WO2021166067A1 PCT/JP2020/006233 JP2020006233W WO2021166067A1 WO 2021166067 A1 WO2021166067 A1 WO 2021166067A1 JP 2020006233 W JP2020006233 W JP 2020006233W WO 2021166067 A1 WO2021166067 A1 WO 2021166067A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
tft
gate
wiring
film
Prior art date
Application number
PCT/JP2020/006233
Other languages
French (fr)
Japanese (ja)
Inventor
井上　和式
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2020/006233 priority Critical patent/WO2021166067A1/en
Priority to JP2020536705A priority patent/JP6806956B1/en
Publication of WO2021166067A1 publication Critical patent/WO2021166067A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/14—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • the present disclosure relates to a thin film transistor substrate having a thin film transistor (TFT) and a display device provided with the thin film transistor.
  • TFT thin film transistor
  • An active matrix substrate using a TFT as a switching element (hereinafter referred to as a TFT substrate) is known to be used in such an electro-optical display device.
  • An electro-optical display device using a TFT substrate is required not only to have high performance and high reliability of TFT characteristics necessary for improving display performance, but also to simplify the manufacturing process and efficiently perform manufacturing. There is also a demand for cost reduction.
  • the organic EL element has a basic structure in which an electric field light emitting layer containing an organic EL element is sandwiched between an anode electrode and a cathode electrode, and an anode is formed by applying a voltage between the anode electrode and the cathode electrode.
  • the organic EL element emits light by controlling the current in which holes are injected from the side and electrons are injected from the cathode side.
  • the basic pixel drive circuit for driving the organic EL elements is composed of two TFTs and one holding capacitance. ing.
  • the two TFTs one is a switching (selection) TFT for selecting display pixels, and the other is a pixel-driven TFT that supplies a current for causing the organic EL element to emit light.
  • the holding capacitance is configured such that, for example, the gate electrode of the pixel-driven TFT is used as one electrode and the source electrode or drain electrode of the pixel-driven TFT is used as the other electrode so as to face each other with an insulating layer interposed therebetween.
  • the scanning line (gate line) connected to the gate electrode of the selected TFT is selected, the selected TFT is turned on, and the signal voltage from the signal line (source line) connected to the selected TFT is accumulated in the holding capacitance.
  • the pixel-driven TFT is turned on by the signal voltage stored in the holding capacitance, the set current is output from the drain electrode of the pixel-driven TFT, and the anode electrode (pixel electrode) connected to the drain electrode of the pixel-driven TFT is organic. It is supplied to the EL element and becomes a light emitting state. This light emitting state is maintained until the next writing is performed.
  • Patent Document 1 A specific basic configuration of such a pixel drive circuit is disclosed in, for example, Patent Document 1.
  • Amorphous silicon has generally been used for the semiconductor channel layer of the TFT of the conventional TFT substrate for an electro-optical display device.
  • the main reasons for this are that a film with good uniformity of characteristics can be formed even on a large-area substrate because it is amorphous, and that it can be manufactured on an inexpensive glass substrate that is inferior in heat resistance because it can be formed at a relatively low temperature. It is possible to reduce the manufacturing cost of a display for a display device, and it is possible to manufacture a display for a display device that can be bent because it can be manufactured on a resin substrate having inferior heat resistance.
  • TFTs oxide semiconductor TFTs
  • oxide semiconductors examples include zinc oxide (ZnO) type and InGaZnO type in which gallium oxide (Ga 2 O 3 ) and indium oxide (In 2 O 3) are added to zinc oxide (ZnO).
  • oxide semiconductors generally have poor chemical resistance and have the property of being easily dissolved even in weak acid chemicals such as oxalic acid. Therefore, when an oxide semiconductor is used for the BCE (back channel etching) type TFT that is the mainstream in a-Si, the source electrode and drain electrode directly above the channel layer are formed by performing wet etching using an acid chemical solution. When formed, the oxide semiconductor of the channel layer is also etched, and there is a problem that a highly reliable channel region cannot be formed.
  • BCE back channel etching
  • Fig. 2. Fig. 3 and Fig. No. 5 discloses a TFT substrate for an organic EL display in which a selection TFT is arranged on the substrate and a pixel-driven TFT is arranged on the selection TFT.
  • the TFT substrate includes a part of BCE type TFT. Therefore, when an oxide semiconductor having high mobility is used for the channel layer of these TFT substrates, all TFTs are composed of ES type TFTs in order to secure chemical resistance and environmental resistance and obtain high reliability. There is a need to. Therefore, in order to complete the TFT substrate before the formation of the organic EL element, it is considered that at least 10 photoplate-making steps (1) to (10) shown below are required.
  • Forming step of gate electrode of selective TFT (2) Forming step of channel layer of selective TFT (3) Forming step of etching stopper (ES) layer on channel layer of selective TFT (4) Source electrode of selective TFT, Drain electrode, gate electrode of drive TFT forming step (5) Channel layer forming step of pixel-driven TFT (6) ES layer forming step on channel layer of pixel-driven TFT (7) Source electrode of pixel-driven TFT (7) Drive current supply electrode), drain electrode forming process (8) Contact hole forming process of protective insulating layer (9) Pixel electrode forming process (10) Pixel opening forming process of pixel separating layer (bank layer)
  • both the selective TFT and the pixel-driven TFT are composed of the ES type TFT, and the TFT substrate before the formation of the organic EL layer is formed by eight photoplate making steps.
  • the present disclosure has been made in order to solve the above problems, and an object of the present disclosure is to provide a technique for obtaining a TFT substrate having a TFT by simplifying a manufacturing process with high productivity and low cost.
  • the thin film semiconductor substrate includes at least a substrate, a bottom gate type first thin film film provided on the substrate, and a top gate type second thin film thin film.
  • a first gate electrode provided on the substrate, a first gate insulating layer provided on the first gate electrode, and a first semiconductor layer provided on the first gate insulating layer.
  • a second protective insulating layer provided on the source electrode and the second drain electrode of the above, and a third opening provided on the second protective insulating layer and penetrating the second protective insulating layer, respectively.
  • a second semiconductor layer in contact with the second source electrode and the second drain electrode through the portion and the fourth opening, and a second gate insulating layer provided on the second semiconductor layer. It has a second gate electrode provided on the second gate insulating layer, and the first gate electrode, the second source electrode, and the second drain electrode are the same in the same layer.
  • the first gate insulating layer and the second protective insulating layer are formed of the same conductive film of 1, and the same first insulating film is formed of the same layer, and the first semiconductor layer and the second semiconductor are formed.
  • the layer is formed of the same semiconductor film in the same layer, and the first protective insulating layer and the second gate insulating layer are formed of the same second insulating film in the same layer, and the first source electrode, The first drain electrode and the second gate electrode are formed of the same second conductive film in the same layer.
  • the manufacturing process can be simplified and the production can be carried out with high productivity, so that the manufacturing cost can be reduced. Can be reduced.
  • FIG. 1 shows schematic the structure of the TFT substrate which concerns on Embodiment 1.
  • FIG. 2 is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 1.
  • FIG. 2 is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 1.
  • FIG. is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 1.
  • FIG. is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 1.
  • FIG. is a top view which shows typically the whole structure of the TFT substrate which concerns on Embodiment 2.
  • It is a top view which shows schematic the plane structure of the TFT substrate which concerns on Embodiment 2.
  • FIG. 1 shows typically the whole structure of the TFT substrate which concerns on Embodiment 2.
  • FIG. 2 It is sectional drawing which shows schematic the structure of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. 2 It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the
  • FIG. 2 It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a perspective view which shows typically the display device provided with the TFT substrate which concerns on Embodiment 2.
  • FIG. It is a figure which shows typically the structure of the pixel part drive circuit of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view which shows the plan structure of the TFT substrate which concerns on Embodiment 3 schematically.
  • FIG. drawing which shows schematic the structure of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3.
  • FIG. It is sectional drawing explaining the manufacturing method of the TFT substrate which
  • FIG. 1 shows typically the structure of the pixel part drive circuit of the TFT substrate which concerns on the modification 1 of Embodiment 3.
  • FIG. 2 shows typically the structure of the pixel part drive circuit of the TFT substrate which concerns on the modification 2 of Embodiment 3.
  • FIG. 2 shows roughly the structure of the TFT substrate which concerns on the modification 2 of Embodiment 3.
  • FIG. 2 shows roughly the structure of the signal generation circuit.
  • the TFT substrate according to the embodiment described below can be used as an active matrix substrate for a self-luminous display device using a light emitting body such as an organic EL element or an LED element as a display element. It can also be applied to a TFT substrate having a signal drive circuit including a display device (Liquid Crystal display; LCD).
  • a display device Liquid Crystal display; LCD
  • FIG. 1 is a cross-sectional view schematically showing the configuration of the TFT substrate 100 according to the first embodiment.
  • the TFT substrate 100 includes a TFT 101 (first thin film transistor) and a TFT 102 (second thin film transistor).
  • the first TFT portion on which the TFT 101 is formed is shown on the right side of the figure, and the first TFT portion on which the TFT 102 is formed is shown on the left side of the figure.
  • the TFT 101 and the TFT 102 are arranged on the same substrate 1 having transparent insulation, for example, a glass substrate.
  • the TFT 101 has a structure in which a bottom gate reverse stagger structure is used to protect the channel, and a gate electrode 2 (first gate electrode) composed of a first conductive film is provided on the substrate 1 to cover the gate electrode 2.
  • the gate insulating layer 5 first gate insulating layer
  • a semiconductor layer 9 first semiconductor layer
  • a protective insulating layer 11 first protective insulating layer
  • a second insulating film is provided on the gate insulating layer 5 and the semiconductor layer 9.
  • the protective insulating layer 11 in the region overlapping the semiconductor layer 9 has an opening 13 (first opening) and an opening 14 (second opening), respectively, so that the surface of the lower semiconductor layer 9 is exposed. It is provided.
  • the opening 13 is a source region contact hole that exposes the surface of the semiconductor layer 9 that is the source region
  • the opening 14 is a drain region contact hole that exposes the surface of the semiconductor layer 9 that is the drain region.
  • a source electrode 15 (first source electrode) composed of a second conductive film is provided on the protective insulating layer 11 so as to come into contact with the semiconductor layer 9 through the opening 13, and the semiconductor is provided through the opening 14.
  • a drain electrode 16 (first drain electrode) composed of a second conductive film is provided so as to be in contact with the layer 9.
  • the source electrode 15 and the drain electrode 16 are provided separately from each other in the region overlapping the semiconductor layer 9, and the separated region sandwiched between the source electrode 15 and the drain electrode 16 in the semiconductor layer 9 is the channel region CL1 of the TFT 101. It is defined as (first channel region).
  • the protective insulating layer 11 on the channel region CL1 functions as a channel protection layer (first channel protection layer) that protects the channel region CL1 of the semiconductor layer 9 from process damage and the like. Therefore, the TFT 101 is a TFT having excellent characteristics and reliability.
  • the TFT 102 has a structure in which channels are protected by a top gate forward staggered structure, and a source electrode 3 (second source electrode) and a drain electrode 4 (second source electrode) composed of a first conductive film are formed on a glass substrate 1. Drain electrodes) are provided separately from each other, and a protective insulating layer 6 (second protective insulating layer) composed of a first insulating film is provided on the drain electrodes).
  • the protective insulating layer 6 has an opening 7 (third opening) that exposes a part of the surface of the source electrode 3 and an opening 8 (fourth opening) that exposes a part of the surface of the drain electrode 4. ) Is provided.
  • the semiconductor layer 10 (second semiconductor layer) formed of a semiconductor film is in contact with the source electrode 3 of the lower layer through the opening 7 and is in contact with the drain electrode 4 of the lower layer through the opening 8. ) Is provided.
  • the lower source electrode 3 and the drain electrode 4 are provided separately from each other in the region overlapping the semiconductor layer 10, and the separated region sandwiched between the source electrode 3 and the drain electrode 4 in the semiconductor layer 10 is the channel of the TFT 102. It is defined as region CL2 (second channel region).
  • a gate insulating layer 12 (second gate insulating layer) composed of a second insulating film is provided on the protective insulating layer 6 and the semiconductor layer 10, and further overlaps with the channel region CL2 of the semiconductor layer 10.
  • a gate electrode 17 (second gate electrode) composed of a second conductive film is provided on the gate insulating layer 12 of the above.
  • the protective insulating layer 6 of the channel region CL2 functions as a channel protection layer (second channel protection layer) that protects the channel region CL2 of the semiconductor layer 10 from process damage and the like. Therefore, the TFT 102 is a TFT having excellent characteristics and reliability.
  • the gate electrode 17 so as not to overlap the source electrode 3 and the drain electrode 4 in the lower layer, it is possible to eliminate the parasitic capacitance formed between the gate electrode and the source electrode and the drain electrode. It is possible to obtain characteristics having excellent responsiveness.
  • the TFT 101 having a bottom gate reverse stagger structure and the channel protection type TFT 102 having a top gate forward stagger structure have different structures and characteristics. Can be arranged on the same substrate.
  • Fig. 2 First, the substrate 1 having transparent insulation such as glass is washed with a cleaning liquid or pure water. In the first embodiment, a glass substrate having a thickness of 0.5 mm was used as the substrate 1. Then, the first conductive film is formed on one main surface of the washed substrate 1.
  • the first conductive film examples include metals such as chromium (Cr), molybdenum (Mo), titanium (Ti), copper (Cu), tantalum (Ta), tungsten (W), and aluminum (Al), or these.
  • An alloy or the like to which a small amount of other elements is added can be used.
  • a laminated structure containing two or more layers of these metals or alloys may be used. By using these metals and alloys, a low resistance conductive film having a specific resistance value of 50 ⁇ cm or less can be obtained.
  • Mo was used as the first conductive film, and the Mo film was formed to a thickness of 200 nm by a sputtering method using Ar (argon) gas. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the first photoplate-making step, and the Mo film is patterned by etching using the photoresist pattern as a mask.
  • wet etching with a solution (PAN chemical solution) containing phosphoric acid (Phosphoric Acid), acetic acid (Acetic Acid) and nitric acid (Nitric Acid) was used. After that, by removing the photoresist pattern, as shown in FIG. 2, the gate electrode 2 of the TFT 101, the source electrode 3 of the TFT 102, and the drain electrode 4 are simultaneously formed on the substrate 1.
  • the first insulating film is formed on the entire main surface of the substrate 1.
  • a silicon oxide film SiO film
  • CVD chemical vapor deposition
  • a SiO film having a thickness of 300 nm was formed under substrate heating conditions of about 300 ° C.
  • the first insulating film is not limited to the SiO film, and for example, a silicon nitride film (SiN film) can be used.
  • the SiN film can also be formed by the CVD method in the same manner as the SiO film. Further, it may be a laminated film of a SiO film and a SiN film.
  • a photoresist pattern is formed on the SiO film which is the first insulating film, and the SiO film is etched using this as a mask.
  • a dry etching method using a gas containing fluorine (F), for example, sulfur hexafluoride (SF 6 ) gas or carbon tetrafluoride (CF 4) gas can be used.
  • an opening 7 that exposes a part of the surface of the source electrode 3 and an opening that exposes a part of the surface of the drain electrode 4 8 are formed respectively.
  • the first insulating film of the first TFT portion functions as the gate insulating layer 5, and the first insulating film of the second TFT portion is used when the second semiconductor layer formed in a later step is formed. 2
  • the semiconductor layer functions as a protective insulating layer 6 (second channel protective layer) that protects the semiconductor layer from damage received from the source electrode 3 and the drain electrode 4.
  • a semiconductor film is formed on the first insulating film.
  • an oxide semiconductor film is formed as the semiconductor film.
  • an oxide (InGaZnO) containing indium (In), gallium (Ga), zinc (Zn) and oxygen (O) is used.
  • an oxide semiconductor film (InGaZnO film) was formed by a sputtering method using Ar gas using an InGaZnO target having an atomic composition ratio of In: Ga: Zn: O of 1: 1: 1: 4.
  • the atomic composition ratio of O is usually smaller than that of the stoichiometric composition, resulting in an oxide film in an O ion-deficient state (in the above example, the composition ratio of O is less than 4). Therefore, it is preferable to mix Ar gas with oxygen (O 2 ) gas and perform sputtering.
  • Ar gas oxygen
  • an InGaZnO film having a thickness of 50 nm was formed by sputtering using a mixed gas in which O 2 gas having a partial pressure ratio of 10% was added to Ar gas.
  • the InGaZnO film is formed with an amorphous structure.
  • the InGaZnO film having an amorphous structure generally has a crystallization temperature of more than 500 ° C., and at room temperature, most of the film remains stable with an amorphous structure.
  • the amorphous structure can have higher structural uniformity than a partially crystallized microcrystal structure or a polycrystalline structure. Therefore, even when the size of the substrate is increased, there is an advantage that a semiconductor film having a small variation in characteristics can be formed on the entire substrate.
  • a photoresist pattern is formed on the InGaZnO film in the third photoengraving process, and the InGaZnO film is etched using this as a mask.
  • wet etching with an oxalic acid chemical solution can be used.
  • the semiconductor layer 10 is formed on the protective insulating layer 6.
  • the semiconductor layer 10 is formed so as to be in contact with the source electrode 3 of the lower layer through the opening 7 of the protective insulating layer 6 and to be in contact with the drain electrode 4 of the lower layer through the opening 8 of the protective insulating layer 6.
  • the source electrode 3 and the drain electrode 4 are formed so as to have a separated region separated from each other in a region overlapping the semiconductor layer 10, and in the semiconductor layer 10, this separated region is a channel region (second channel) of the TFT 102. Region) CL2.
  • the oxide semiconductor film which is the material of the semiconductor layer 10
  • the metal films such as the source electrode 3 and the drain electrode 4 are exposed in the lower layer
  • the oxide semiconductor reacts with the metal during sputtering.
  • an oxide semiconductor film having deteriorated characteristics in the reduced (O ion deficient) state may be formed.
  • the protective insulating layer 6 of the channel region CL2 functions as the channel protective layer 6 (second channel protective layer) of the semiconductor layer 10.
  • the glass substrate 1 is heat-treated at a temperature of 400 ° C. in an air atmosphere.
  • the amorphous InGaZnO film of the semiconductor layer 9 and the semiconductor layer 10 causes structural relaxation, and the semiconductor characteristics can be further stabilized.
  • Structural relaxation is a phenomenon in which lattice defects of constituent atoms due to process damage such as film formation and wet etching are reduced, and the amorphous structure is more stabilized.
  • the temperature of the heat treatment for causing the above-mentioned structural relaxation of the amorphous InGaZnO film is preferably at least 300 ° C. or higher.
  • the temperature exceeds 500 ° C. crystallization starts in the entire film and the semiconductor characteristics change significantly, and for example, it becomes a conductor due to an increase in carrier density. Therefore, here, it is preferable to heat-treat at least the glass substrate 1 at a temperature of 300 ° C. or higher and 500 ° C. or lower.
  • such a heat treatment may be carried out at the end of the manufacturing process.
  • a second insulating film is formed on the entire main surface of the substrate 1.
  • a SiO film having a thickness of 300 nm was formed by a CVD method under a substrate heating condition of about 200 ° C.
  • the second insulating film is not limited to the SiO film, and for example, a SiN film can be used. Further, it may be a laminated film of a SiO film and a SiN film.
  • a photoresist pattern is formed on the SiO film which is the second insulating film, and the SiO film is etched using this as a mask.
  • a dry etching method using SF 6 gas or CF 4 gas can be used.
  • the second insulating film of the first TFT portion functions as a protective insulating layer 11 (first channel protective layer) for preventing processing process damage from the source electrode 15 and the drain electrode 16 formed in a later step. .. Further, the second insulating film of the second TFT portion functions as the gate insulating layer 12.
  • a second conductive film is formed on the second insulating film.
  • a metal such as Cr, Mo, Ti, Cu, Ta, W, Al, or an alloy obtained by adding a small amount of other elements to these, or the like. Can be used. Further, a laminated structure containing two or more layers of these metals or alloys may be used. By using these metals or alloys, a low resistance conductive film having a specific resistance value of 50 ⁇ cm or less can be obtained.
  • a Mo film was used as the second conductive film, and the Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the fifth photoplate-making step, and the Mo film is patterned by etching using the photoresist pattern as a mask. Here, wet etching with a PAN chemical solution was used. After that, by removing the photoresist pattern, as shown in FIG. 1, the source electrode 15 and the drain electrode 16 of the TFT 101 are formed on the substrate 1, and at the same time, the gate electrode 17 of the TFT 102 is formed.
  • the source electrode 15 of the TFT 101 is formed so as to be in contact with the semiconductor layer 9 through the opening 13. Further, the drain electrode 16 is formed so as to be in contact with the semiconductor layer 9 through the opening 14.
  • the source electrode 15 and the drain electrode 16 are provided separately from each other in the region overlapping the semiconductor layer 9, and the separated region sandwiched between the source electrode 15 and the drain electrode 16 in the semiconductor layer 9 is the channel region CL1 of the TFT 101. Is specified as.
  • the oxide semiconductor film has poor chemical resistance, and the InGaZnO film, which is the material of the semiconductor layer 9, is easily dissolved in the PAN chemical solution used for wet etching of the second conductive film.
  • the entire surface of the glass substrate 1 excluding the opening 13 and the opening 14 is covered with the protective insulating layer 11 formed of an insulating film, and the protective insulating layer 11 is particularly provided on the channel region CL1 of the semiconductor layer 9. Functions as a channel protection layer (etching stopper; ES). Therefore, a highly reliable TFT without process damage can be obtained.
  • the gate electrode 17 of the TFT 102 is formed so as to overlap the channel region CL2 of the lower second semiconductor layer. Further, by forming the source electrode 3 and the drain electrode 4 in the lower layer so as not to overlap with each other, it is possible to eliminate the parasitic capacitance formed between the gate electrode 17 and the source electrode 3 and the drain electrode 4, and the response is excellent. A high-speed response TFT can be obtained. Further, since the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained as in the case of the TFT 101.
  • the first TFT and the second TFT have different positional (upper and lower layers) relationships between the gate electrode, the source electrode, and the drain electrode. Both semiconductor layers are composed of the same semiconductor layer, and the structure of each layer including the respective electrodes can be made common. Therefore, the channel is a channel-protected first TFT with a bottom gate reverse staggered structure that is excellent in operation stability and reliability, and a top gate forward staggered structure that is excellent in reliability and has a small parasitic capacitance between electrodes and is excellent in responsiveness.
  • a TFT having a structure and characteristics different from that of the protective type second TFT can be manufactured with high productivity and low cost by using five photoplate-making steps.
  • each layer is standardized, for example, a TFT circuit in which the TFT 101 and the TFT 102 are combined is formed so as to connect the gate electrode 2 of the TFT 101 and either the source electrode 3 or the drain electrode 4 of the TFT 102.
  • a TFT circuit in which the TFT 101 and the TFT 102 are combined is formed so as to connect the gate electrode 2 of the TFT 101 and either the source electrode 3 or the drain electrode 4 of the TFT 102.
  • the gate electrode 2 and the source electrode 3 or the drain electrode 4 into a continuous integrated pattern, for example, as compared with a configuration in which both are formed separately and electrically connected via a contact hole.
  • the occurrence rate of defects due to poor signal transmission from the TFT 102 to the TFT 101 can be suppressed to a low level.
  • the same effect can be obtained by forming them in a continuous integrated pattern. ..
  • FIG. 6 is a plan view schematically showing the overall configuration of the TFT substrate 110 according to the second embodiment.
  • the TFT substrate 110 has a display region 150 in which pixels including at least the TFT 101, the TFT 102, and the pixel region PX are arranged in a matrix on the substrate 1, and a frame region 160 adjacent to the display region 150. It can be roughly divided.
  • An EL element 44 electroluminescence element
  • An organic material is arranged in the pixel region PX, and can be suitably used as a TFT substrate for a self-luminous display device provided with an organic EL display. can.
  • the contour shape of the TFT substrate 110 is shown as a quadrangle in FIG. 6, the contour shape is not limited to this, and may be a shape including a curved line such as a circular shape or an elliptical shape. Further, the TFT substrate 110 is not limited to being flat and may be curved.
  • a plurality of gate wirings 32 and a plurality of source wirings 34 are arranged so as to intersect each other so as to be orthogonal to each other, and are defined by the gate wirings 32 and the source wirings 34.
  • Is provided with a pixel and a pixel unit drive circuit ELC1 for driving the pixel is provided in the pixel.
  • a plurality of drive current wirings 36 are arranged adjacent to and parallel to the plurality of source wirings 34.
  • the pixel unit drive circuit ELC1 has a TFT 102 provided at the intersection of the gate wiring 32 and the source wiring 34, and a TFT 101 provided at the intersection of the gate wiring 32 and the drive current wiring 36.
  • the gate electrode 17 of the TFT 102 is electrically connected to the gate wiring 32
  • the source electrode 3 of the TFT 102 is electrically connected to the source wiring 34.
  • the TFT 102 functions as a selection TFT for selecting display pixels corresponding to the signals of the gate wiring and the source wiring.
  • the gate electrode 2 of the TFT 101 is electrically connected to the drain electrode 4 of the TFT 102. Further, the source electrode 15 of the TFT 101 is electrically connected to the drive current wiring 36, and the drain electrode 16 is electrically connected to the anode electrode 41 for driving the EL element 44. The cathode electrode 45 of the EL element 44 is connected to the ground potential.
  • the TFT 101 is provided with a holding capacity CsA connected between the gate electrode 2 and the drain electrode 16.
  • the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is used as the drive current from the TFT 101 through the anode electrode 41. It is supplied to the EL element 44, and the EL element 44 emits light.
  • a scanning signal drive circuit 170 that applies a signal voltage to the gate wiring 32 is connected to a gate terminal 33 provided at the end of the gate wiring 32, and is also driven by the source wiring 34 and the drive current wiring 36.
  • the display signal drive circuit 180 that gives a signal is provided at the end of the source wiring 34 and the end of the drive current wiring 36, respectively, at the source terminal 35 (second source terminal) and the source terminal 37 (first source terminal). It is connected to and arranged in. Further, alignment marks AM for alignment are provided at the four corners of the substrate 1.
  • the scanning signal drive circuit 170 and the display signal drive circuit 180 are arranged in the frame region 160 on the TFT substrate 110, but these are not arranged on the TFT substrate 110.
  • An external drive IC Integrated Circuit
  • TAB Tape Automated Bonding
  • COG Chip On Glass
  • FIG. 7 is a partial plan view showing a planar configuration of pixels including the TFT 101, TFT 102, holding capacity CsA, and pixel region PX provided in the display region 150 (FIG. 6) of the TFT substrate 110
  • FIG. 8 is a partial plan view of the pixels. It is a partial cross-sectional view which shows the cross-sectional structure.
  • the X1-X2 line in FIG. 7 is provided so as to extend over the TFT 101, the TFT 102 and the holding capacitance CsA, and the Y1-Y2 line extends from the drain electrode 16 of the TFT 101 to the pixel region PX.
  • the cross-sectional view in the direction shown and the cross-sectional view taken along the line Y1-Y2 are shown on the left side and the right side of FIG. 8, respectively.
  • the TFT 101 and the TFT 102 of the second embodiment have basically the same configuration as the TFT 101 and the TFT 102 of the first embodiment, the same components are designated by the same reference numerals, and redundant description will be omitted. ..
  • the TFT substrate 110 has various elements arranged on one main surface of the transparent insulating substrate 1.
  • the substrate 1 is made of a transparent and insulating material such as glass, plastic or resin.
  • the planar shape of the substrate 1 is not limited to the quadrangle illustrated in FIG.
  • the first TFT portion on the substrate 1 includes a gate electrode 2 (first gate electrode) composed of a first conductive film and a drive.
  • a current wiring 36 (first wiring) is provided, and a gate insulating layer 5 (first gate insulating layer) composed of a first insulating film is provided so as to cover the current wiring 36 (first wiring).
  • the second TFT portion is provided with a source electrode 3 (second source electrode) and a drain electrode 4 (second drain electrode), and is protected by a first insulating film so as to cover them.
  • An insulating layer 6 (second protective insulating layer) is provided.
  • the protective insulating layer 6 has an opening 7 (third opening) that exposes a part of the surface of the source electrode 3 and an opening 8 (fourth opening) that exposes a part of the surface of the drain electrode 4. ) Is provided.
  • the gate electrode 2 of the TFT 101 and the drain electrode 4 of the TFT 102 are provided in a continuous integrated pattern.
  • the drive current wiring 36 is arranged so as to extend in the vertical direction (Y direction), and the source wiring 34 is arranged so as to extend in parallel in the vertical direction so as to be adjacent to the drive current wiring 36. ..
  • the source electrode 3 of the TFT 102 is a part of the source wiring 34. That is, the source wiring 34 is composed of the first conductive film, and the portion of the source wiring 34 extending toward the TFT 102 is the source electrode 3. The portion provided with the source electrode 3 is wider than the other portion of the source wiring 34.
  • a semiconductor layer 9 (first semiconductor layer) composed of a semiconductor film is provided on the gate insulating layer 5 of the first TFT portion.
  • a semiconductor layer 10 (second semiconductor layer) composed of a semiconductor film is provided on the protective insulating layer 6 of the second TFT portion.
  • the semiconductor layer 10 is in contact with the source electrode 3 of the lower layer through the opening 7, and is in contact with the drain electrode 4 of the lower layer through the opening 8.
  • the semiconductor layer 9 of the TFT 101 is arranged in an island-like pattern in a region overlapping the gate electrode 2. Further, the source electrode 3 and the drain electrode 4 of the TFT 102 are separated and arranged so as to face each other, and the semiconductor layer 10 has an island shape so as to straddle the source electrode 3 and the drain electrode 4 separated from each other. It is arranged in the pattern of.
  • a second insulating film is provided so as to cover the first insulating film and the semiconductor film described above, and as shown in the cross-sectional view taken along the line X1-X2 of FIG. 8, the second TFT portion of the first TFT portion is provided.
  • the insulating film is provided with an opening 13 (first opening) and an opening 14 (second opening), respectively, so that a part of the surface of the lower semiconductor layer 9 is exposed.
  • the opening 13 is a contact hole that exposes a surface serving as a source region (first source region) of the semiconductor layer 9
  • the opening 14 is a surface serving as a drain region (first drain region) of the semiconductor layer 9. It is a contact hole that exposes.
  • the region between the opening 13 and the opening 14 of the second insulating film functions as a protective insulating layer 11 for protecting the semiconductor layer 9 from process damage.
  • the second insulating film on the semiconductor layer 10 of the second TFT portion functions as the gate insulating layer 12 of the TFT 102.
  • the source electrode 15 composed of the second conductive film so as to be in contact with the semiconductor layer 9 through the opening 13.
  • a drain electrode 16 (first drain electrode) composed of a second conductive film is provided so as to come into contact with the semiconductor layer 9 through the opening 14).
  • the source electrode 15 extends to a region overlapping the drive current wiring 36, and is provided so as to penetrate the first insulating film and the second insulating film so as to expose a part of the surface of the drive current wiring 36. It is connected to the drive current wiring 36 through the opening 30. Further, the drain electrode 16 is arranged so as to extend to a region overlapping the gate electrode 2 of the TFT 101 provided in an integral pattern continuous with the drain electrode 4 of the TFT 102. A gate electrode 17 (second gate electrode) composed of a second conductive film is provided on the gate insulating layer 12 in a region overlapping the semiconductor layer 10 of the TFT 102.
  • the drain electrode 16 of the TFT 101 overlaps the pattern of the gate electrode 2 and the drain electrode 4 of the TFT 102 in a region that does not overlap with the semiconductor layer 10, and is in the Y direction from these. It is arranged so that the width of the is wide. Then, the holding capacity CsA is formed by the region where the drain electrode 16 and the gate electrode 2 overlap.
  • the gate electrode 17 of the TFT 102 is arranged so as to overlap the semiconductor layer 10 in a region where the source electrode 3 and the drain electrode 4 are separated so as to face each other. Has been done. Further, the gate electrode 17 is arranged so as not to overlap the source electrode 3 and the drain electrode 4, and is configured so that a parasitic capacitance due to the overlap thereof is not formed.
  • the gate wiring 32 extending from the gate electrode 17 is provided so as to extend in the lateral direction (X direction) so as to be orthogonal to the source wiring 34 and the drive current wiring 36.
  • a protective insulating layer 18 (third protective insulating layer) composed of a third insulating film is provided on the entire surface of the substrate 1 so as to cover the 17 and the gate wiring 32.
  • the protective insulating layer 18 is provided with an opening 40 (fifth opening) so as to expose a part of the surface of the drain electrode 16 of the first TFT portion.
  • An anode electrode 41 composed of a fourth conductive film is provided on the protective insulating layer 18 so as to be connected to the drain electrode 16 through the opening 40 and extend to the pixel region PX.
  • a bank layer 42 composed of a fourth insulating film is provided on the anode electrode 41 and the protective insulating layer 18.
  • a bank opening 43 is provided in the bank layer 42 so that the surface of the anode electrode 41 is exposed, and an EL element 44 that functions as a pixel emitter is provided on the anode electrode 41 of the bank opening 43. ing.
  • the pixel region PX is defined by a region surrounded by the gate wiring 32, the source wiring 34, and the drive current wiring 36 in a plan view.
  • the anode electrode 41 is provided so as to extend from the region overlapping the opening 40 provided in the region overlapping the drain electrode 16 to the pixel region PX.
  • the anode electrode 41 is arranged so as not to overlap with the source wiring 34 or the drive current wiring 36, but may be arranged so as to partially overlap with each other.
  • the bank opening 43 provided in the bank layer 42 is arranged so as not to protrude from the anode electrode 41 in a region overlapping the anode electrode 41, and the adjacent bank openings 43 are separated (separated) by the bank layer 42. ), And are arranged in an manner independent of each other.
  • the EL element 44 is arranged on the entire region of the bank opening 43 so as not to protrude from the anode electrode 41.
  • the EL element 44 for example, an organic EL element composed of an organic material is used.
  • the organic EL element may have a three-layer structure in which a hole transport layer, an organic EL layer, and an electron transport layer are laminated in this order directly above the anode electrode 41. Further directly above it, a cathode electrode (not shown), which is the opposite electrode of the anode electrode 41, is provided. A current is supplied to the EL element 44 due to the potential difference between the anode electrode 41 and the cathode electrode, and the EL element 44 emits light. The emitted light is radiated downward through, for example, a substrate 1 made of glass, and an image is displayed.
  • the TFT substrate 110 according to the second embodiment is configured as described above, and the TFT substrate 110 including the EL element 44 is further provided with a sealing layer for blocking the EL element 44 from moisture and impurities. Further, a facing substrate is provided so as to face the TFT substrate 110, and the TFT substrate can be suitably used as a TFT substrate for a self-luminous display device using an organic EL element.
  • FIGS. 9 to 24 alternately show a plan view with FIG. 7 as the final process diagram and a cross-sectional view with FIG. 8 as the final process diagram.
  • a cross-sectional view along the line and a cross-sectional view along the Y1-Y2 line are shown on the left and right sides of the figure, respectively.
  • a Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the first photoplate-making step, and the Mo film is patterned by wet etching using a PAN chemical solution using the photoresist pattern as a mask. Then, by removing the photoresist pattern, as shown in FIGS. 9 and 10, the gate electrode 2 of the TFT 101, the source electrode 3 of the TFT 102, the drain electrode 4, the source wiring 34, and the drive current wiring 36 are placed on the substrate 1. Are formed at the same time.
  • the gate electrode 2 and the drain electrode 4 are formed in a continuous integrated pattern. Further, the source wiring 34 and the drive current wiring 36 are formed so as to extend in parallel in the vertical direction (Y direction) so as to be adjacent to each other.
  • the source electrode 3 is a part of the source wiring 34, and a portion having a width wider than the other parts of the source wiring 34 is formed as the source electrode 3.
  • the first insulating film is formed on the entire main surface of the substrate 1.
  • a SiO film having a thickness of 300 nm was formed by a CVD method under the substrate heating condition of about 300 ° C.
  • the first insulating film is not limited to the SiO film, and for example, a SiN film can be used.
  • the SiN film can also be formed by the CVD method in the same manner as the SiO film. Further, it may be a laminated film of a SiO film and a SiN film.
  • a photoresist pattern is formed on the SiO film which is the first insulating film, and the SiO film is etched using this as a mask.
  • a dry etching method using SF 6 gas or CF 4 gas can be used.
  • the opening 7 that exposes a part of the surface of the source electrode 3 and the surface of the drain electrode 4 Each of the openings 8 that exposes a part is formed.
  • the first insulating film of the first TFT portion functions as the gate insulating layer 5
  • the first insulating film of the second TFT portion is the second insulating film formed in a later step.
  • the semiconductor layer When the semiconductor layer is formed, it functions as a protective insulating layer 6 that protects the second semiconductor layer from damage received from the source electrode 3 and the drain electrode 4.
  • a semiconductor film is formed on the first insulating film.
  • an oxide semiconductor film is formed as the semiconductor film. Specifically, sputtering using an InGaZnO target having an atomic composition ratio of In: Ga: Zn: O of 1: 1: 1: 4 and a mixed gas in which O 2 gas having a partial pressure ratio of 10% is added to Ar gas. By the method, an InGaZnO film, which is an oxide semiconductor film, was formed with a thickness of 50 nm.
  • the InGaZnO film is formed with an amorphous structure.
  • the InGaZnO film having an amorphous structure generally has a crystallization temperature of more than 500 ° C., and at room temperature, most of the film remains stable with an amorphous structure.
  • the amorphous structure can have higher structural uniformity than the partially crystallized microcrystal structure and polycrystalline structure. Therefore, even when the size of the substrate is increased, there is an advantage that a semiconductor film having a small variation in characteristics can be formed on the entire substrate. That is, even when the TFT substrate used for a large display device is used for a large display device, the in-plane variation of the TFT characteristics can be reduced, so that display unevenness can be prevented.
  • a photoresist pattern is formed on the InGaZnO film in the third photoengraving process, and the InGaZnO film is etched using this as a mask.
  • wet etching with an oxalic acid chemical solution can be used.
  • the semiconductor layer 10 is formed on the protective insulating layer 6.
  • the semiconductor layer 10 is formed so as to be in contact with the source electrode 3 of the lower layer through the opening 7 of the protective insulating layer 6 and to be in contact with the drain electrode 4 of the lower layer through the opening 8 of the protective insulating layer 6.
  • the source electrode 3 and the drain electrode 4 are formed so as to be separated from each other in a region overlapping the semiconductor layer 10 and have a separated region, and in the semiconductor layer 10, this is formed.
  • the separation region is defined as the channel region CL2 (FIG. 14) of the TFT 102.
  • the oxide semiconductor film which is the material of the semiconductor layer 10
  • the metal films such as the source electrode 3 and the drain electrode 4 are exposed in the lower layer
  • the oxide semiconductor reacts with the metal during sputtering.
  • an oxide semiconductor film having deteriorated characteristics in the reduced (O ion deficient) state may be formed.
  • the protective insulating layer 6 of the channel region CL2 functions as the channel protective layer 6 of the semiconductor layer 10.
  • the substrate 1 is heat-treated at a temperature of 400 ° C. in an air atmosphere.
  • the amorphous InGaZnO film of the semiconductor layer 9 and the semiconductor layer 10 causes structural relaxation, and the semiconductor characteristics can be further stabilized.
  • the temperature of the heat treatment for causing the above-mentioned structural relaxation of the amorphous InGaZnO film is preferably at least 300 ° C. or higher.
  • the temperature exceeds 500 ° C. crystallization starts in the entire film and the semiconductor characteristics change significantly, and for example, it becomes a conductor due to an increase in carrier density. Therefore, here, it is preferable to heat-treat at least the substrate 1 at a temperature of 300 ° C. or higher and 500 ° C. or lower.
  • such a heat treatment may be carried out at the end of the manufacturing process.
  • a second insulating film is formed on the entire main surface of the substrate 1.
  • a SiO film having a thickness of 300 nm was formed by a CVD method under a substrate heating condition of about 200 ° C.
  • the second insulating film is not limited to the SiO film, and for example, a SiN film can be used. Further, it may be a laminated film of a SiO film and a SiN film.
  • a photoresist pattern is formed on the SiO film which is the second insulating film, and the SiO film is etched using this as a mask.
  • a dry etching method using SF 6 gas or CF 4 gas can be used.
  • the portion 14 is formed.
  • the second insulating film of the first TFT portion functions as a protective insulating layer 11 for preventing processing process damage from the source electrode 15 and the drain electrode 16 formed in a later step.
  • the second insulating film of the second TFT portion functions as the gate insulating layer 12 of the TFT 102. Further, an opening 30 penetrating the first insulating film and the second insulating film is formed so as to expose a part of the surface of the drive current wiring 36.
  • a second conductive film is formed on the second insulating film.
  • the Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas as the second conductive film.
  • a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the fifth photoplate-making step, and the Mo film is patterned by wet etching using a PAN chemical solution using the photoresist pattern as a mask.
  • the source electrode 15 and the drain electrode 16 of the TFT 101 are formed, and at the same time, the gate electrode 17 of the TFT 102 is formed.
  • the source electrode 15 of the TFT 101 is formed so as to be in contact with the semiconductor layer 9 through the opening 13. Further, the drain electrode 16 is formed so as to be in contact with the semiconductor layer 9 through the opening 14.
  • the source electrode 15 and the drain electrode 16 are formed separately from each other in a region overlapping the semiconductor layer 9, and the separated region sandwiched between the source electrode 15 and the drain electrode 16 in the semiconductor layer 9 is the channel region CL1 of the TFT 101. Is defined as.
  • the oxide semiconductor film has poor chemical resistance, and the InGaZnO film, which is the material of the semiconductor layer 9, is easily dissolved in the PAN chemical solution used for wet etching of the second conductive film.
  • the protective insulating layer 11 formed of the second insulating film since the entire surface of the substrate 1 excluding the opening 13 and the opening 14 is covered with the protective insulating layer 11 formed of the second insulating film, the channel is particularly on the channel region CL1 of the semiconductor layer 9. It functions as a protective layer (etching stopper; ES layer). Therefore, a highly reliable TFT without process damage can be obtained.
  • the source electrode 15 extends to a region overlapping the drive current wiring 36, and is connected to the drive current wiring 36 through the opening 30. Further, the drain electrode 16 is formed so as to extend to a region overlapping the gate electrode 2 of the TFT 101 provided in an integral pattern continuous with the drain electrode 4 of the TFT 102.
  • the drain electrode 16 of the TFT 101 overlaps the pattern of the gate electrode 2 and the drain electrode 4 of the TFT 102 in a region that does not overlap with the semiconductor layer 10, and is wider in the Y direction than these. Is formed to be wide.
  • the holding capacity CsA is formed by the region where the drain electrode 16 and the gate electrode 2 overlap.
  • the gate wiring 32 extending from the gate electrode 17 is formed so as to extend in the lateral direction (X direction) so as to be orthogonal to the source wiring 34 and the drive current wiring 36.
  • the gate electrode 17 of the second TFT portion is separated from the channel region CL2 of the lower semiconductor layer 10 in the region where the source electrode 3 and the drain electrode 4 are separated from each other. It is formed so as to overlap. Further, the gate electrode 17 is formed so as not to overlap the source electrode 3 and the drain electrode, and is configured so that a parasitic capacitance due to the overlap thereof is not formed. Thereby, a TFT having excellent responsiveness can be obtained. Further, since the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained as in the case of the TFT 101.
  • a third insulating film is formed on the entire main surface of the substrate 1.
  • a resin-based coating film is used as the third insulating film.
  • a photosensitive transparent acrylic resin film was applied and formed by using a spin coating method.
  • the transparent acrylic resin film was coated and formed so that the thickness was 1.5 ⁇ m at the portion where the film thickness was the thinnest.
  • a SiO film or a SiN film may be formed by, for example, a CVD method before the transparent acrylic resin film is applied and formed as the third insulating film.
  • an SOG (Spin-On Glass) -based, epoxy-based, polyimide-based, or polyolefin-based resin film can be used in addition to the acrylic-based coating film.
  • the protective insulating layer 18 in the region where the holding capacity CsA was formed was first covered with the first protective insulating layer 18.
  • the opening 40 is formed so that a part of the surface of the drain electrode 16 of the TFT portion is exposed.
  • dry etching using SF 6 gas or CF 4 gas is performed using the protective insulating layer 18 (transparent acrylic resin) on which the opening 40 is formed as a mask.
  • a fourth conductive film is formed on the protective insulating layer 18 including the opening 40.
  • a transparent ITO film an oxide conductive film containing indium oxide In 2 O 3 and tin oxide Sn O 2
  • the ITO film generally has a stable crystalline (polycrystalline) structure at room temperature, but here, a gas containing hydrogen (H) in Ar gas, for example, hydrogen (H 2 ) gas or water vapor (H 2 O).
  • H hydrogen
  • H 2 O water vapor
  • a photoresist pattern is formed on the amorphous ITO film in the 7th photoplate making process, and the amorphous ITO film is etched using this as a mask.
  • wet etching with an oxalic acid chemical solution can be used.
  • the anode electrode 41 made of a transparent ITO film is formed.
  • the anode electrode 41 is formed so as to be connected to the drain electrode 16 of the lower layer through the opening 40 of the protective insulating layer 18 and extend to the pixel region PX in the holding capacity CsA.
  • the pixel area PX is defined by the area surrounded by the gate wiring 32, the source wiring 34, and the drive current wiring 36.
  • the anode electrode 41 is formed so as to extend from a region overlapping the opening 40 provided in the region overlapping the drain electrode 16 to the pixel region PX.
  • the anode electrode 41 is formed so as not to overlap with the source wiring 34 or the drive current wiring 36, but may be formed so as to partially overlap. Since the amorphous ITO film formed as the fourth conductive film in the second embodiment has no crystal grain boundaries, the flatness of the film surface can be made extremely high.
  • a current signal having high in-plane uniformity can be supplied from the anode electrode 41 to the EL element 44 (FIG. 7), so that uniform light emission with little unevenness can be generated from the entire in-plane of the EL element 44. ..
  • a fourth insulating film to be the bank layer 42 is formed on the entire main surface of the substrate 1.
  • a resin-based coating film is used as the fourth insulating film.
  • a photosensitive transparent acrylic resin film was applied and formed so as to have a thickness of 1.5 ⁇ m by a spin coating method.
  • the acrylic type, SOG type, epoxy type, polyimide type, or polyolefin type resin films can be used.
  • the polyimide resin film is preferable because it has a small amount of adsorbed water and does not affect the characteristics and reliability of the EL element formed in the subsequent steps.
  • the bank opening 43 in which the surface of the anode electrode 41 is exposed in the pixel region PX is formed.
  • the bank layer 42 having the bank layer 42 is formed.
  • the bank openings 43 are formed only in the pixel display region on the anode electrode 41, that is, the region where the EL element 44 is formed in the subsequent step, and the bank openings 43 adjacent to each other are formed by the bank layer 42. It is an isolated aspect.
  • the EL element 44 is formed in the region of the bank opening 43 so as to be in contact with the anode electrode 41, thereby obtaining the configurations shown in FIGS. 7 and 8.
  • an organic organic EL material is used as the EL layer of the EL element 44.
  • an EL layer was formed by laminating a hole transport layer, an organic EL layer, and an electron transport layer in this order using an inkjet printing method. According to the inkjet printing method, the EL layer can be selectively formed only in the concave region of the bank opening 43, so that the EL element 44 can be formed without using the photoengraving process.
  • the whole transport layer can be widely selected from known organic materials such as triarylamines, aromatic hydrazones, aromatic-substituted pyrazolines, and stillbens, and can be selected from, for example, N, N'-diphenyl-N, N-. It is formed to an arbitrary thickness of 1 nm to 200 nm using a triphenylamine system (TPD) such as bis (3-methylphenyl) -1,1'-diphenyl-4,4'-diamine.
  • TPD triphenylamine system
  • Known organic EL layers include dicyanomethylenepyrane derivative (R color emission), coumarin type (G color emission), quinacridone type (G color emission), tetraphenylbutadiene type (B color emission), and distyrylbenzene type (B color emission).
  • a material such as (emission) is formed with an arbitrary thickness of 1 nm to 200 nm.
  • the electron transport layer is formed with an arbitrary thickness of 0.1 nm to 200 nm using a material selected from known oxadiazole derivatives, triazole derivatives, coumarin derivatives and the like.
  • the EL layer can be formed by using a vapor deposition method in addition to the printing method.
  • the EL element 44 is formed without using the photoengraving process by using a mask vapor deposition method in which, for example, a metal mask having the same opening pattern as the bank opening 43 is attached to the surface of the substrate 1. Can be done.
  • the TFT substrate 110 according to the second embodiment is completed through the steps described above. As shown in FIG. 25, a cathode electrode 45, which is a counter electrode of the anode electrode 41, is formed on the completed TFT substrate 110. Further, if necessary, a sealing layer 46 for further blocking the TFT substrate 110 including the EL element 44 from moisture and impurities is formed, and the opposing substrate 47 is further bonded so as to face the TFT substrate 110, so that the organic EL element is formed. A self-luminous display device 300 equipped with an organic EL display using the above is completed.
  • the self-luminous display device 300 can realize a display device with a high aperture ratio and bright display quality at low cost with few display defects.
  • the self-luminous display device 300 including the TFT substrate 110 according to the second embodiment emits the emitted light ELL of the EL element downward (opposite to the opposing substrate 47) through the TFT substrate 110 for display.
  • It will be a bottom emission type self-luminous display device.
  • it is not limited to the bottom emission type, and it is also possible to use a top emission type self-luminous display device that emits light from the emission light ELL of the EL element above the TFT substrate 110 (opposite substrate 47 side) for display. ..
  • the fourth conductive film which is the material of the anode electrode 41, is made of silver (Ag) -based or Al having high reflectance instead of the transparent ITO film.
  • the ITO film may be formed on the metal film.
  • the emitted light ELL from the organic EL element can be reflected by the anode electrode 41 to emit light upward, so that a top-emission type self-luminous display device can be obtained.
  • the TFT 102 is electrically connected to the gate wiring 32 and the source wiring 34, and is used to select display pixels according to the signals of the gate wiring 32 and the source wiring 34. Functions as a selective TFT.
  • the gate electrode 17 of the TFT 102, the source electrode 3 and the drain electrode 4 are configured so that parasitic capacitances are not formed on each other, a TFT having excellent responsiveness can be obtained.
  • the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained. Therefore, high performance can be exhibited as a selective TFT.
  • the TFT 101 is electrically connected to the drain electrode 4, the drive current wiring 36, and the EL element 44 of the TFT 102, and functions as a pixel drive TFT of the EL element 44.
  • the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is supplied to the EL element 44 as a drive current.
  • EL element 44 emits light.
  • the channel region CL1 of the TFT 101 is protected by the protective insulating layer 11, the reliability is high and the signal current can be stably supplied to the EL element 44, so that the EL element 44 is made to emit light stably. High quality image display is possible.
  • the drain electrode 4 of the TFT 102 and the gate electrode 2 of the TFT 101 are formed in the same continuous pattern of the first conductive film and integrated. Is formed as a separate body and electrically connected via a contact hole, and the occurrence rate of display defects due to poor signal transmission from the TFT 102 to the TFT 101 can be suppressed to a low level.
  • the continuously integrated gate electrode 2 and drain electrode 4 can be used as a capacitance electrode having a holding capacitance of CsA, Fig. 9721973 of US Pat. No.
  • the holding capacity CsA can be formed much more efficiently in the area, so that the formation region of the TFT circuit can be reduced and the pixel region can be reduced.
  • the aperture ratio of the PX can be improved. As a result, even in the case of a bottom-emission type self-luminous display device in which the EL element 44 emits light downward through the substrate 1 for display, bright and high-quality image display can be performed.
  • Section 3 shows a configuration example of a TFT substrate for a self-luminous display device (LED display) in which an LED element (LED chip) is mounted on the TFT substrate to display an image.
  • the configuration of the TFT substrate 120 according to the third embodiment will be described with reference to FIGS. 26 to 28.
  • the same components as those in the first and second embodiments are designated by the same reference numerals, and duplicate description will be omitted.
  • FIG. 26 is a diagram showing the configuration of the pixel portion drive circuit LEDC1 of the pixels of the TFT substrate 120 according to the third embodiment.
  • FIG. 27 is a partial plan view showing the planar configuration of the pixels including the TFT 101, TFT 102, the holding capacity CsA, and the pixel region PX provided on the TFT substrate 120
  • FIG. 28 is a partial cross-sectional view showing the cross-sectional configuration of the pixels. be.
  • the X1-X2 wire in FIG. 27 extends over the pixel region PX including the TFT 101, the TFT 102, the holding capacity CsA, and the LED element mounting portion, and the Y1-Y2 wire is provided so as to extend from the source electrode 15 of the TFT 101 to the drive current wiring portion.
  • the cross-sectional view taken along the line X1-X2 and the cross-sectional view taken along the line Y1-Y2 are shown on the left and right sides of FIG. 28, respectively.
  • an LED element is mounted on each pixel of the TFT substrate 120 to form a self-luminous display device. Therefore, unlike the pixel unit drive circuit ELC1 of the second embodiment shown in FIG. 6, as shown in FIG. 26, the anode electrode 61 (first electrode) and the cathode electrode 63 (second electrode) are on the TFT substrate 120. The electrode) is provided, and the LED element 200 (light emitting diode element) is arranged so as to be connected to the anode electrode 61 and the cathode electrode 63.
  • the TFT substrate 120 is arranged on the substrate so that a plurality of gate wirings 32 and a plurality of source wirings 34 intersect each other so as to be orthogonal to each other, and the gate wirings 32 are arranged.
  • a TFT 102 is provided at the intersection of the source wiring 34 and the source wiring 34.
  • the gate electrode 17 of the TFT 102 is electrically connected to the gate wiring 32, and the source electrode 3 of the TFT 102 is electrically connected to the source wiring 34.
  • the TFT 102 functions as a selection TFT for selecting display pixels corresponding to the signals of the gate wiring 32 and the source wiring 34.
  • a plurality of drive current wirings 36 are arranged in parallel adjacent to the plurality of source wirings 34, and a TFT 101 is provided at the intersection of the gate wiring 32 and the drive current wiring 36.
  • the gate electrode 2 of the TFT 101 is electrically connected to the drain electrode 4 of the TFT 102.
  • the source electrode 15 of the TFT 101 is electrically connected to the drive current wiring 36, and the drain electrode 16 is electrically connected to the anode electrode 61 for driving the LED element 200.
  • a plurality of cathode electrode wirings 62 (second wirings) are arranged adjacent to and parallel to the plurality of gate wirings 32, and the cathode electrodes 63 electrically connected to the cathode electrode wirings 62 are connected to the LED element 200. It is connected.
  • the TFT 101 is provided with a holding capacity CsA connected between the gate electrode 2 and the drain electrode 16.
  • the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is transferred to the anode electrode 61 and the cathode electrode 63. It is supplied to the LED element 200 by the potential difference, and the LED element 200 emits light.
  • the TFT 101 on the substrate 1 has a gate electrode 2 composed of a first conductive film and a driving current.
  • Wiring 36 is provided, and a gate insulating layer 5 composed of a first insulating film is provided so as to cover the wiring 36.
  • the TFT 102 is provided with a source electrode 3 and a drain electrode 4, and is provided with a protective insulating layer 6 formed of a first insulating film so as to cover them.
  • the protective insulating layer 6 is provided with an opening 7 for exposing a part of the surface of the source electrode 3 and an opening 8 for exposing a part of the surface of the drain electrode 4.
  • the gate electrode 2 of the TFT 101 and the drain electrode 4 of the TFT 102 are provided as a continuous integrated pattern.
  • the drive current wiring 36 is arranged so as to extend in the vertical direction (Y direction), and the source wiring 34 is arranged so as to extend parallel to the vertical direction (Y direction) so as to be adjacent to the drive current wiring 36. It is installed.
  • the source electrode 3 of the TFT 102 is a part of the source wiring 34. That is, the source wiring 34 is composed of the first conductive film, and the portion of the source wiring 34 extending toward the TFT 102 is the source electrode 3. The portion provided with the source electrode 3 is wider than the other portion of the source wiring 34.
  • a semiconductor layer 9 composed of a semiconductor film is provided on the gate insulating layer 5 of the TFT 101. ing. Further, a semiconductor layer 10 made of a semiconductor film is provided on the protective insulating layer 6 of the TFT 102. The semiconductor layer 10 is in contact with the source electrode 3 of the lower layer through the opening 7, and is in contact with the drain electrode 4 of the lower layer through the opening 8.
  • the semiconductor layer 9 of the TFT 101 is arranged in an island-like pattern in a region overlapping the gate electrode 2. Further, the source electrode 3 and the drain electrode 4 of the TFT 102 of the TFT 102 are separated and arranged so as to face each other, and the semiconductor layer 10 is an island so as to straddle the source electrode 3 and the drain electrode 4 separated from each other. It is arranged in a similar pattern.
  • a second insulating film is provided so as to cover the first insulating film and the semiconductor film described above, and as shown in the cross-sectional view taken along the line X1-X2 and the cross-sectional view taken along the line Y1-Y2 in FIG. 28.
  • the second insulating film of the TFT 101 is provided with an opening 13 and an opening 14, respectively, so that a part of the surface of the lower semiconductor layer 9 is exposed.
  • the region between the opening 13 and the opening 14 of the second insulating film functions as a protective insulating layer 11 for protecting the semiconductor layer 9 from process damage.
  • the second insulating film on the semiconductor layer 10 of the TFT 102 functions as the gate insulating layer 12 of the TFT 102.
  • a source electrode 15 composed of a second conductive film is provided so as to be in contact with the semiconductor layer 9 through the opening 13, and the opening is further provided.
  • a drain electrode 16 composed of a second conductive film is provided so as to come into contact with the semiconductor layer 9 through 14.
  • a cathode electrode wiring 62 composed of a second conductive film is provided on the second insulating film of the pixel region PX.
  • the source electrode 15 extends to a region overlapping the drive current wiring 36, and is provided so as to penetrate the first insulating film and the second insulating film so as to expose a part of the surface of the drive current wiring 36. It is connected to the drive current wiring 36 through the opening 30. Further, the drain electrode 16 is arranged so as to extend to a region overlapping the gate electrode 2 of the TFT 101 provided in an integral pattern continuous with the drain electrode 4 of the TFT 102 portion. A gate electrode 17 composed of a second conductive film is provided on the gate insulating layer 12 in a region overlapping the semiconductor layer 10 of the TFT 102.
  • the drain electrode 16 of the TFT 101 is arranged so as to be a region protruding from the region overlapping the semiconductor layer 9 and widely overlapping the pattern of the gate electrode 2 and the drain electrode 4 of the TFT 102. It is installed. Then, the holding capacity CsA is formed by the region where the drain electrode 16 and the gate electrode 2 overlap.
  • the gate electrode 17 of the TFT 102 is arranged so as to overlap the semiconductor layer 10 in a region where the source electrode 3 and the drain electrode 4 are separated from each other so as to face each other. ing. Further, the gate electrode 17 is arranged so as not to overlap the source electrode 3 and the drain electrode 4, and is configured so that a parasitic capacitance due to the overlap thereof is not formed.
  • the gate wiring 32 extending from the gate electrode 17 is provided so as to extend in the lateral direction (X direction) so as to be orthogonal to the source wiring 34 and the drive current wiring 36. Further, the cathode electrode wiring 62 is arranged so as to extend in parallel in the lateral direction so as to be adjacent to the gate wiring 32 in the pixel region PX on the side opposite to the TFT 101 and the TFT 102.
  • the source electrode 15 and the drain electrode 16 of the TFT 101, and the gate electrode 17 and the gate wiring 32 of the TFT 102 are provided.
  • a protective insulating layer 18 composed of a third insulating film is provided on the entire surface of the substrate 1 so as to cover it.
  • the protective insulating layer 18 is provided with an opening 48 (fifth opening) so as to expose a part of the surface of the drain electrode 16 of the FT101 portion so as to expose a part of the surface of the cathode electrode wiring 62.
  • anode electrode 61 (first electrode) composed of a fifth conductive film is arranged on the protective insulating layer 18 of the pixel region PX so as to be connected to the drain electrode 16 through the opening 48. .. Further, a cathode electrode 63 (second electrode) composed of a fifth conductive film is arranged so as to be connected to the cathode electrode wiring 62 through the opening 49.
  • a protective insulating layer 50 composed of a fifth insulating film is provided on the protective insulating layer 18 including the anode electrode 61 and the cathode electrode 63.
  • an anode electrode opening 51 is provided so that the surface of the lower anode electrode 61 is exposed
  • a cathode electrode opening 52 is provided so that the surface of the lower cathode electrode 63 is exposed. It is provided.
  • the protective insulating layer 50 may not be provided.
  • the pixel region PX is defined by the region surrounded by the gate wiring 32, the source wiring 34, and the drive current wiring 36.
  • the anode electrode 61 is provided so as to extend from a region overlapping the opening 48 provided in the region overlapping the drain electrode 16 to a region below the pixel region PX.
  • the cathode electrode 63 is provided so as to extend from a region overlapping the opening 49 provided in the region overlapping the cathode electrode wiring 62 to a region above the pixel region PX.
  • the anode electrode 61 and the cathode electrode 63 are arranged in the pixel region PX in a manner in which they are separated from each other and face each other in a plan view.
  • the anode electrode opening 51 and the cathode electrode opening 52 are arranged so as to face each other in a plan view so that the lower layer anode electrode 61 and the cathode electrode 63 are exposed, respectively.
  • the TFT substrate 120 is configured as described above, and is arranged on the TFT substrate 120 so as to correspond to the anode electrode 61 and the cathode electrode 63 of each pixel region PX arranged in a matrix.
  • a self-luminous display device LED display
  • a plurality of LED element anode electrode terminals and cathode electrode terminals are mounted so as to be connected to each other (not shown), and each LED element is made to emit light to display an image.
  • each LED element is made to emit light to display an image.
  • FIGS. 29 to 43 a plan view having FIG. 27 as a final process view and a cross-sectional view having FIG. 28 as a final process view are alternately shown.
  • X1-X2 of FIG. 28 is shown.
  • a cross-sectional view along the line and a cross-sectional view along the Y1-Y2 line are shown on the left and right sides of the figure, respectively.
  • a Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas as the first conductive film. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the first photoplate-making step, and the Mo film is patterned by wet etching using a PAN chemical solution using the photoresist pattern as a mask. Then, by removing the photoresist pattern, as shown in FIGS. 29 and 30, the gate electrode 2 of the TFT 101, the source electrode 3 and the drain electrode 4 of the TFT 102, and the source wiring 34 and the drive current are further mounted on the substrate 1. Wiring 36 is formed at the same time.
  • the gate electrode 2 and the drain electrode 4 are formed in a continuous integrated pattern in a plan view. Further, the source wiring 34 and the drive current wiring 36 are formed so as to extend in parallel in the vertical direction (Y direction) so as to be adjacent to each other.
  • the source electrode 3 is a part of the source wiring 34. That is, the source wiring 34 is composed of the first conductive film, and the portion of the source wiring 34 extending toward the TFT 102 is the source electrode 3. The portion provided with the source electrode 3 is wider than the other portion of the source wiring 34.
  • the first insulating film is formed on the entire main surface of the substrate 1.
  • a SiO film having a thickness of 300 nm was formed by a CVD method under the substrate heating condition of about 300 ° C.
  • the first insulating film is not limited to the SiO film, and for example, a SiN film can be used.
  • the SiN film can also be formed by the CVD method in the same manner as the SiO film. Further, it may be a laminated film of a SiO film and a SiN film.
  • a photoresist pattern is formed on the SiO film which is the first insulating film, and the SiO film is etched using this as a mask.
  • a dry etching method using SF 6 gas or CF 4 gas can be used.
  • the opening 7 that exposes a part of the surface of the source electrode 3 and the surface of the drain electrode 4 Each of the openings 8 that exposes a part is formed.
  • the first insulating film of the first TFT portion functions as the gate insulating layer 5
  • the first insulating film of the second TFT portion is the second semiconductor formed in a later step.
  • it functions as a protective insulating layer 6 (second channel protective layer) that protects the second semiconductor layer from damage received from the source electrode 3 and the drain electrode 4.
  • a semiconductor film is formed on the first insulating film.
  • an oxide semiconductor film is formed as the semiconductor film. Specifically, sputtering using an InGaZnO target having an atomic composition ratio of In: Ga: Zn: O of 1: 1: 1: 4 and a mixed gas in which O 2 gas having a partial pressure ratio of 10% is added to Ar gas. By the method, an InGaZnO film, which is an oxide semiconductor film, was formed with a thickness of 50 nm.
  • the InGaZnO film is formed with an amorphous structure.
  • the InGaZnO film having an amorphous structure generally has a crystallization temperature of more than 500 ° C., and at room temperature, most of the film remains stable with an amorphous structure.
  • the amorphous structure can have higher structural uniformity than a partially crystallized microcrystal structure or a polycrystalline structure. Therefore, even when the size of the substrate is increased, there is an advantage that a semiconductor film having a small variation in characteristics can be formed on the entire substrate. That is, even when the TFT substrate used for a large display device is used for a large display device, the in-plane variation of the TFT characteristics can be reduced, so that display unevenness can be prevented.
  • a photoresist pattern is formed on the InGaZNO film in the third photoengraving process, and the InGaZnO film is etched using this as a mask.
  • wet etching with an oxalic acid chemical solution can be used.
  • the semiconductor layer 9 is formed in an island-like pattern in the region overlapping the gate electrode 2 on the gate insulating layer 5 in the first TFT portion. Will be done.
  • the semiconductor layer 10 is formed on the protective insulating layer 6.
  • the semiconductor layer 10 is formed so as to be in contact with the source electrode 3 of the lower layer through the opening 7 of the protective insulating layer 6 and to be in contact with the drain electrode 4 of the lower layer through the opening 8 of the protective insulating layer 6.
  • the source electrode 3 and the drain electrode 4 are formed so as to be separated from each other in a region overlapping the semiconductor layer 10 and have a separated region, and in the semiconductor layer 10, this separated region is the channel region CL2 of the TFT 102. Is defined as.
  • the oxide semiconductor film which is the material of the semiconductor layer 10
  • the metal films such as the source electrode 3 and the drain electrode 4 are exposed in the lower layer
  • the oxide semiconductor reacts with the metal during sputtering.
  • an oxide semiconductor film having deteriorated characteristics in the reduced (O ion deficient) state may be formed.
  • the protective insulating layer 6 of the channel region CL2 functions as the channel protective layer 6 of the semiconductor layer 10.
  • the substrate 1 is heat-treated at a temperature of 400 ° C. in an air atmosphere.
  • the amorphous InGaZnO film of the semiconductor layer 9 and the semiconductor layer 10 causes structural relaxation, and the semiconductor characteristics can be further stabilized.
  • the temperature of the heat treatment for causing the above-mentioned structural relaxation of the amorphous InGaZnO film is preferably at least 300 ° C. or higher.
  • the temperature exceeds 500 ° C. crystallization starts in the entire film and the semiconductor characteristics change significantly, for example, the film becomes a conductor due to an increase in carrier density. Therefore, here, it is preferable to heat-treat at least the substrate 1 at a temperature of 300 ° C. or higher and 500 ° C. or lower.
  • such a heat treatment may be carried out at the end of the manufacturing process.
  • a second insulating film is formed on the entire main surface of the substrate 1.
  • a SiO film having a thickness of 300 nm was formed by a CVD method under a substrate heating condition of about 200 ° C.
  • the second insulating film is not limited to the SiO film, and for example, a SiN film can be used. Further, it may be a laminated film of a SiO film and a SiN film.
  • a photoresist pattern is formed on the SiO film which is the second insulating film, and the SiO film is etched using this as a mask.
  • a dry etching method using SF 6 gas or CF 4 gas can be used.
  • the portion 14 is formed.
  • the second insulating film of the first TFT portion functions as a protective insulating layer 11 for preventing processing process damage from the source electrode 15 and the drain electrode 16 formed in a later step.
  • the second insulating film of the second TFT portion functions as the gate insulating layer 12 of the TFT 102.
  • an opening 30 is formed in the first insulating film and the second insulating film so as to expose a part of the surface of the drive current wiring 36.
  • a second conductive film is formed on the second insulating film.
  • the Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas as the second conductive film.
  • a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the fifth photoplate-making step, and the Mo film is patterned by wet etching using a PAN chemical solution using the photoresist pattern as a mask. After that, by removing the photoresist pattern, as shown in FIGS.
  • the source electrode 15 and the drain electrode 16 of the TFT 101 are formed, and at the same time, the gate electrode 17 of the TFT 102 is formed. Further, a cathode electrode wiring 62 composed of a conductive film is formed on the insulating film of the pixel region PX.
  • the source electrode 15 of the TFT 101 is formed so as to be in contact with the semiconductor layer 9 through the opening 13. Further, the drain electrode 16 is formed so as to be in contact with the semiconductor layer 9 through the opening 14.
  • the source electrode 15 and the drain electrode 16 are formed separately from each other in the region overlapping the semiconductor layer 9, and the separated region sandwiched between the source electrode 15 and the drain electrode 16 in the semiconductor layer 9 is the channel region CL1 of the TFT 101. Is specified as.
  • the oxide semiconductor film has poor chemical resistance, and the InGaZnO film, which is the material of the semiconductor layer 9, is easily dissolved in the PAN chemical solution used for wet etching of the second conductive film.
  • the protective insulating layer 11 formed of the second insulating film since the entire surface of the substrate 1 excluding the opening 13 and the opening 14 is covered with the protective insulating layer 11 formed of the second insulating film, the channel is particularly on the channel region CL1 of the semiconductor layer 9. It functions as a protective layer (etching stopper; ES layer). Therefore, a highly reliable TFT without process damage can be obtained.
  • the source electrode 15 extends to a region overlapping the drive current wiring 36, and is connected to the drive current wiring 36 through the opening 30. Further, the drain electrode 16 is formed so as to extend to a region overlapping the gate electrode 2 of the TFT 101 provided in an integral pattern continuous with the drain electrode 4 of the TFT 102. In a plan view, the drain electrode 16 of the TFT 101 is arranged so as to be a region protruding from the region overlapping the semiconductor layer 10 and widely overlapping the pattern of the gate electrode 2 and the drain electrode 4 of the TFT 102. Then, the holding capacity CsA is formed by the region where the drain electrode 16 and the gate electrode 2 overlap.
  • the cathode electrode wiring 62 is formed so as to extend in the pixel region PX on the opposite side of the TFT 101 and the TFT 102 so as to be adjacent to the gate wiring 32 and parallel to the lateral direction (X direction). ing.
  • the gate electrode 17 of the TFT 102 is formed so as to overlap the channel region CL2 of the lower semiconductor layer 10 in a region where the source electrode 3 and the drain electrode 4 are separated so as to face each other. Further, in a plan view, the gate electrode 17 is formed so as not to overlap the source electrode 3 and the drain electrode, and is configured so that a parasitic capacitance due to the overlap thereof is not formed. As a result, a TFT having excellent high-speed response can be obtained. Further, since the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained as in the case of the TFT 101.
  • the gate wiring 32 extending from the gate electrode 17 is formed so as to extend in the lateral direction (X direction) so as to be orthogonal to the source wiring 34 and the drive current wiring 36.
  • a third insulating film to be the protective insulating layer 18 is formed on the entire main surface of the substrate 1.
  • a photosensitive transparent acrylic resin film is applied and formed as a third insulating film by a spin coating method.
  • the transparent acrylic resin film was coated and formed so that the thickness was 1.5 ⁇ m at the portion where the film thickness was the thinnest.
  • a SiO film or a SiN film may be formed by, for example, a CVD method before the transparent acrylic resin film is applied and formed.
  • the resin-based coating film an SOG-based, epoxy-based, polyimide-based, or polyolefin-based resin film can be used in addition to the acrylic-based coating film.
  • the drain of the TFT 101 is drained to the protective insulating layer 18 in the region where the holding capacity CsA is formed.
  • the opening 48 is formed so that a part of the surface of the electrode 16 is exposed.
  • an opening 49 is formed in the protective insulating layer 18 in the region overlapping the cathode electrode wiring 62 so that a part of the surface of the cathode electrode wiring 62 is exposed.
  • SF 6 gas or CF 4 gas is used as a mask using the transparent acrylic resin in which the openings 48 and 49 are formed.
  • a fifth conductive film is formed on the third protective insulating layer including the opening 48 and the opening 49.
  • a transparent ITO film is used as the fifth conductive film.
  • the ITO film generally has a stable crystalline (polycrystalline) structure at room temperature, but here, a gas containing hydrogen (H) in Ar gas, for example, hydrogen (H 2 ) gas or water vapor (H 2 O). ) And the like were subjected to sputtering to form an ITO film having a thickness of 100 nm in an amorphous state (amorphous ITO film).
  • a photoresist pattern is formed on the amorphous ITO film in the 7th photoplate making process, and the amorphous ITO film is etched using this as a mask.
  • wet etching with an oxalic acid chemical solution can be used.
  • the anode electrode 61 and the cathode electrode 63 made of a transparent ITO film are formed.
  • the anode electrode 61 is provided so as to extend from a region overlapping the opening 48 provided in the region overlapping the drain electrode 16 to a region below the pixel region PX.
  • the cathode electrode 63 is provided so as to extend from a region overlapping the opening 49 provided in the region overlapping the cathode electrode wiring 62 to a region above the pixel region PX.
  • the anode electrode 61 and the cathode electrode 63 are arranged in the pixel region PX in a manner in which they are separated from each other and face each other in a plan view.
  • a fifth insulating film to be the protective insulating layer 50 is formed on the entire main surface of the substrate 1.
  • a photosensitive transparent acrylic resin film is coated and formed so as to have a thickness of 1.5 ⁇ m by a spin coating method.
  • acrylic type SOG type, epoxy type, polyimide type, or polyolefin type resin films can be used.
  • the anode electrode is opened so that the surface of the anode electrode 61 is exposed in the pixel region PX as shown in FIGS. 27 and 28.
  • the portion 51 is formed, and the cathode electrode opening 52 is formed so that the surface of the cathode electrode 63 is exposed.
  • the anode electrode opening 51 and the cathode electrode opening 52 are formed so as to face each other.
  • the TFT substrate 120 according to the third embodiment is completed in eight photoengraving steps. It is also possible to omit the formation of the fifth insulating film. In this case, the TFT substrate 120 according to the third embodiment can be completed in seven photoplate-making steps.
  • the anode electrode terminal 201 and the lower electrode terminal 202 of the LED element 200 correspond to the anode electrode 61 and the cathode electrode 63 of the pixel region PX, respectively. Implemented to be connected.
  • a facing substrate 47 is attached to the TFT substrate 120 on which the LED element 200 is mounted, if necessary, and a self-luminous display device 310 provided with an LED display using the LED element is provided. Complete.
  • the self-luminous display device 310 can realize a display device with a high aperture ratio and bright display quality at low cost with few display defects.
  • the self-luminous display device 310 provided with an LED display has lower power consumption, a wider viewing angle, and a higher contrast ratio than the self-luminous display device of the second embodiment provided with an organic EL display. It is possible to realize a high-quality image display.
  • the TFT 102 is electrically connected to the gate wiring 32 and the source wiring 34, and the display pixels are selected according to the signals of the gate wiring 32 and the source wiring 34. Functions as a selection TFT of.
  • the gate electrode 17 of the TFT 102, the source electrode 3 and the drain electrode 4 are configured so that parasitic capacitances are not formed on each other, a TFT having excellent responsiveness can be obtained.
  • the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained. Therefore, high performance can be exhibited as a selective TFT.
  • the TFT 101 is electrically connected to the drain electrode 4, the drive current wiring 36, and the LED element 200 of the TFT 102, and functions as a pixel drive TFT of the LED element 200.
  • the TFT 101 operates according to the written voltage, the signal current from the drive current wiring 36 is supplied to the LED element 200, and the LED The element 200 emits light.
  • the channel region CL1 of the TFT 101 is protected by the protective insulating layer 11, the reliability is high, the signal current can be stably supplied to the LED element 200, the LED element 200 is made to emit light stably, and the value is high. It is possible to display quality images.
  • the drain electrode 4 of the TFT 102 and the gate electrode 2 of the TFT 101 are formed and integrated in the same continuous pattern of the first conductive film. Therefore, for example, they are separated from each other. Compared with a configuration in which the body is formed and electrically connected via a contact hole, the occurrence rate of display defects due to poor signal transmission from the TFT 102 to the TFT 101 can be suppressed to a low rate.
  • the continuously integrated gate electrode 2 and drain electrode 4 can be used as a capacitance electrode having a holding capacitance of CsA, Fig. 9721973 of US Pat. No.
  • the holding capacity CsA can be formed much more efficiently in the area, so that the formation region of the TFT circuit can be reduced and the pixel region can be reduced.
  • the aperture ratio of the PX can be improved.
  • the cathode electrode 63 can be formed at the same time as the anode electrode 61 by using the fifth conductive film. Further, the cathode electrode wiring 62 that supplies the signal current to the cathode electrode 63 can be formed at the same time as the drain electrode 16 and the like of the TFT 101 by using the second conductive film. Therefore, a TFT substrate for a self-luminous display device (LED display) equipped with an LED element can be manufactured at low cost without increasing the number of steps.
  • LED display self-luminous display device
  • the first modification of the third embodiment is a modification of the configuration of the holding capacity CsA of the third embodiment.
  • the configuration of the TFT substrate 130 according to the first modification of the third embodiment will be described with reference to FIGS. 45 and 46.
  • the same components as those of the TFT substrate 120 of the third embodiment are designated by the same reference numerals, and redundant description will be omitted.
  • FIG. 45 is a diagram showing the configuration of the pixel portion drive circuit LEDC2 of the pixels of the TFT substrate 130 according to the first modification of the third embodiment.
  • FIG. 46 is a partial plan view showing a planar configuration of pixels including the TFT 101, the TFT 102, the holding capacity CsA, and the pixel region PX provided on the TFT substrate 130.
  • the TFT substrate 120 of the third embodiment has a configuration in which the holding capacity CsA is connected between the gate electrode 2 and the drain electrode 16 of the TFT 101.
  • the TFT substrate 130 of the first modification of the third embodiment has a configuration in which the holding capacity CsB is connected between the gate electrode 2 of the TFT 101 and the source electrode 15.
  • the TFT 101 when the selection signal output from the drain electrode 4 of the TFT 102 is written to the holding capacitance CsB, the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is transferred to the anode electrode 61 and the cathode. It is supplied to the LED element 200 by the potential difference from the electrode 63, and the LED element 200 emits light.
  • the holding capacitance CsB has a pattern shape of a capacitance electrode composed of a first conductive film and composed of a drain electrode 4 of the TFT 102 and a gate electrode 2 of the TFT 101 arranged in a continuous integrated pattern, and a second conductivity. It can be configured by changing the pattern shape of the source electrode 15 and the drain electrode 16 of the TFT 101 made of a film.
  • the source electrode 15 protrudes from the region where the semiconductor layer 9 overlaps, and overlaps the capacitance electrode formed of the integrated pattern of the gate electrode 2 and the drain electrode 4. It is arranged so as to extend to. As a result, the holding capacitance CsB is formed by the region where the source electrode 15 and the gate electrode 2 overlap.
  • a first insulating film forming the gate insulating layer 5 and a second insulating film forming the protective insulating layer 11 are laminated and provided between the capacitance electrode and the source electrode 15. Needless to say, the configuration of the holding capacity CsA of the second embodiment may be changed to the holding capacity CsB described above.
  • the second modification of the third embodiment is a modification of the configuration of the holding capacity CsA of the third embodiment.
  • the configuration of the TFT substrate 140 according to the second modification of the third embodiment will be described with reference to FIGS. 47 and 48.
  • the same components as those of the TFT substrate 120 of the third embodiment are designated by the same reference numerals, and redundant description will be omitted.
  • FIG. 47 is a diagram showing the configuration of the pixel portion drive circuit LEDC3 of the pixels of the TFT substrate 140 according to the second modification of the third embodiment.
  • FIG. 48 is a partial plan view showing a planar configuration of pixels including the TFT 101, the TFT 102, the holding capacity CsAB, and the pixel region PX provided on the TFT substrate 140.
  • the TFT substrate 120 of the third embodiment has a configuration in which the holding capacity CsA is connected between the gate electrode 2 and the drain electrode 16 of the TFT 101.
  • the holding capacity CsAB is between the gate electrode 2 of the TFT 101 and the source electrode 15, and the gate electrode 2 of the TFT 101. It is configured to be connected in parallel with the drain electrode 16.
  • the TFT 101 when the selection signal output from the drain electrode 4 of the TFT 102 is written to the holding capacitance CsAB, the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is transferred to the anode electrode 61 and the cathode. It is supplied to the LED element 200 by the potential difference from the electrode 63, and the LED element 200 emits light.
  • the holding capacitance CsAB is the pattern shape of the capacitance electrode composed of the drain electrode 4 of the TFT 102 composed of the first conductive film and the gate electrode 2 of the TFT 101 arranged in a continuous integrated pattern, and the second conductivity. It can be configured by changing the pattern shape of the source electrode 15 and the drain electrode 16 of the TFT 101 made of a film.
  • the drain electrode 16 protrudes from the region where the semiconductor layer 9 overlaps, and overlaps with the capacitance electrode formed of the integrated pattern of the gate electrode 2 and the drain electrode 4. It is arranged so as to extend to.
  • the holding capacity CsA first holding capacity
  • a first insulating film forming the gate insulating layer 5 and a second insulating film forming the protective insulating layer 11 are laminated and provided between the capacitance electrode and the drain electrode 16.
  • the source electrode 15 is a region protruding from the region overlapping the semiconductor layer 9, and is arranged so as to extend so as to overlap the capacitive electrode formed of an integrated pattern of the gate electrode 2 and the drain electrode 4. ing.
  • the holding capacity CsB (second holding capacity) is formed by the region where the source electrode 15 and the capacitance electrode overlap.
  • a first insulating film forming the gate insulating layer 5 and a second insulating film forming the protective insulating layer 11 are laminated and provided between the capacitance electrode and the source electrode 15.
  • the holding capacity CsAB is composed of the holding capacity CsA and the holding capacity CsB connected in parallel. Needless to say, the configuration of the holding capacity CsA of the second embodiment may be changed to the holding capacity CsAB described above.
  • the TFT substrate 130 of the first modification of the third embodiment and the TFT substrate 140 of the second modification described above can also obtain the same effect as the TFT substrate 120 of the third embodiment.
  • the scanning signal drive circuit 170 provided in the frame region 160 of the TFT substrate 110 according to the second embodiment shown in FIG. 6 includes a plurality of signal generation circuits (not shown).
  • the configurations of TFT 101 and TFT 102 can be applied.
  • FIG. 49 shows the configuration of the signal generation circuit GSC to which the TFT 101 and the TFT 102 are applied.
  • the clock signal CLK is supplied to the source electrode of the drive transistor 103.
  • the drain electrode of the drive transistor 103 is connected to the source electrode of the drive transistor 104, and the ground potential VSS is given to the drain electrode of the drive transistor 104.
  • the connection node N1 between the drive transistors 103 and 104 is connected to the gate electrode of the drive transistor 103 and the drain electrode of the drive transistor 105 via the holding capacitance C1.
  • the power supply potential VDD is supplied to the source electrode of the drive transistor 105.
  • the connection node N1 between the drive transistors 103 and 104 is an output node of the signal generation circuit GSC, from which a scan signal is supplied to the corresponding gate wiring 32.
  • the drive transistor 105 When the drive transistor 105 is turned on by the drive signal supplied to the gate electrode of the drive transistor 105, the drive transistor 103 is turned on and the clock signal CLK is output from the connection node N1.
  • the drive transistor 104 when the drive transistor 104 is turned on by the drive signal supplied to the gate electrode of the drive transistor 104, the potential of the connection node N1 is fixed to the ground potential VSS.
  • the configurations of the drive transistors 103 and 105 which are the components of the signal generation circuit GSC, can be the same as those of the TFTs 101 and 102 of the second embodiment, the third embodiment, and the modifications thereof.
  • the configuration of these signal generation circuits GSC can be suitably used not only for a self-luminous display device but also for a TFT substrate for a liquid crystal display device using a liquid crystal (Liquid Crystal).
  • the present disclosure is not limited to the TFT substrate for the display device, and can be applied to other semiconductor devices including, for example, a shift register circuit having a similar transistor configuration, and the scope of these disclosures.
  • each embodiment can be freely combined, and each embodiment can be appropriately modified.
  • the oxide semiconductor film can be directly electrically connected to the metal film and the alloy film. Therefore, as in the present disclosure, the TFT 101 in which the source electrode 15 and the drain electrode 16 are provided on the upper surface (front surface) of the semiconductor layer 9 and the source electrode 3 and the drain electrode 4 are provided on the lower surface (back surface) of the semiconductor layer 10. In the case of a configuration in which the TFT 102 and the TFT 102 are arranged at the same time, it is preferable to use an oxide semiconductor film as the semiconductor layer.
  • the oxide semiconductor material is not limited to InGaZnO oxide semiconductor, and for example, In—O, Ga—O, Zn—O, In—Zn—O, which are oxide semiconductors in which In, Ga, and Zn are appropriately combined.
  • In—Ga—O and Ga—Zn—O and other metal oxides can be used.
  • oxide semiconductors in which oxides such as hafnium (Hf), tin (Sn), yttrium (Y), and aluminum (Al) are appropriately combined can also be applied. ..
  • oxide semiconductors elements selected from Group 13 Al, Ga, and In and elements selected from Group 15 nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb) can be used.
  • Group III-V compound semiconductors such as Ga-As, Ga-P, In-P, In-Sb, In-As, Al-N, Ga-N, Al-Ga-N or these.
  • a semiconductor material to which other elements have been added may be used.
  • carbon nanotubes and graphene using carbon (C), which is a group 14 semiconductor element, and a semiconductor material in which Si and Ge elements are combined with these.
  • each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted within the scope of the disclosure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

This thin film transistor substrate is configured such that a bottom gate-type first thin film transistor and a top gate-type second thin film transistor are provided on a substrate, respective semiconductor layers can be formed as the same semiconductor layer, and each layer including each electrode can have a common structure. A gate electrode of the first thin film transistor and a drain electrode of the second thin film transistor are formed in a continuous integrated pattern and function as capacitive electrodes forming a holding capacitance, and the holding capacitance is formed between the capacitive electrode and a first drain electrode of the first thin film transistor.

Description

薄膜トランジスタ基板および表示装置Thin film transistor substrate and display device
　本開示は薄膜トランジスタ（Thin Film Transistor；ＴＦＴ）を有する薄膜トランジスタ基板およびそれを備えた表示装置に関する。 The present disclosure relates to a thin film transistor substrate having a thin film transistor (TFT) and a display device provided with the thin film transistor.
　近年、表示素子として有機ＥＬ（Electro Luminescence；ＥＬ）素子およびＬＥＤ（Light Emitting Diode；ＬＥＤ）素子のような発光体を用いたディスプレイが、自発光型表示装置の表示パネルのひとつとして一般に用いられるようになってきた。 In recent years, displays using light emitters such as organic EL (ElectroLuminescence; EL) elements and LED (LightEmittingDiode; LED) elements as display elements have been generally used as one of the display panels of self-luminous display devices. Has become.
　ＴＦＴをスイッチング素子として用いたアクティブマトリックス基板（以下、ＴＦＴ基板と呼称）が、このような電気光学表示装置に利用されるものとして知られている。ＴＦＴ基板を用いた電気光学表示装置では、表示性能の向上に必要なＴＦＴ特性の高性能化および高信頼性化が要求されるだけでなく、製造工程を簡略化して製造を効率的に行うことによる低コスト化も要求されている。 An active matrix substrate using a TFT as a switching element (hereinafter referred to as a TFT substrate) is known to be used in such an electro-optical display device. An electro-optical display device using a TFT substrate is required not only to have high performance and high reliability of TFT characteristics necessary for improving display performance, but also to simplify the manufacturing process and efficiently perform manufacturing. There is also a demand for cost reduction.
　有機ＥＬ素子とは、アノード電極とカソード電極の間に有機ＥＬ素子を含む電界発光層を挟んだ構造を基本構成とするものであり、アノード電極とカソード電極の間に電圧を加えることで、アノード側から正孔（ホール）が、カソード側から電子が注入される電流制御によって有機ＥＬ素子が発光する。 The organic EL element has a basic structure in which an electric field light emitting layer containing an organic EL element is sandwiched between an anode electrode and a cathode electrode, and an anode is formed by applying a voltage between the anode electrode and the cathode electrode. The organic EL element emits light by controlling the current in which holes are injected from the side and electrons are injected from the cathode side.
　有機ＥＬ素子を平面状にアレイ状に複数形成して構成される有機ＥＬディスプレイの場合、有機ＥＬ素子を駆動するための基本的な画素駆動回路は、２つのＴＦＴと１つの保持容量で構成されている。 In the case of an organic EL display formed by forming a plurality of organic EL elements in a planar array, the basic pixel drive circuit for driving the organic EL elements is composed of two TFTs and one holding capacitance. ing.
　２つのＴＦＴのうち、１つは表示画素を選択するためのスイッチング（選択）ＴＦＴであり、もう１つは有機ＥＬ素子を発光させるための電流を供給する画素駆動ＴＦＴである。保持容量は、例えば画素駆動ＴＦＴのゲート電極を一方の電極とし、画素駆動ＴＦＴのソース電極またはドレイン電極をもう一方の電極として、絶縁層を挟んで互いに対向させた態様で構成される。選択ＴＦＴのゲート電極に接続された走査線（ゲート線）が選択されると選択ＴＦＴがオンとなり、選択ＴＦＴに接続された信号線（ソース線）から信号電圧が保持容量に蓄積される。保持容量に蓄積された信号電圧によって画素駆動ＴＦＴがオンとなり、設定された電流が画素駆動ＴＦＴのドレイン電極から出力され、さらに画素駆動ＴＦＴのドレイン電極に接続されたアノード電極（画素電極）から有機ＥＬ素子に供給されて発光状態となる。この発光状態は次の書き込みが行われるまで保持される。このような画素駆動回路の具体的な基本構成は、例えば特許文献１に開示されている。 Of the two TFTs, one is a switching (selection) TFT for selecting display pixels, and the other is a pixel-driven TFT that supplies a current for causing the organic EL element to emit light. The holding capacitance is configured such that, for example, the gate electrode of the pixel-driven TFT is used as one electrode and the source electrode or drain electrode of the pixel-driven TFT is used as the other electrode so as to face each other with an insulating layer interposed therebetween. When the scanning line (gate line) connected to the gate electrode of the selected TFT is selected, the selected TFT is turned on, and the signal voltage from the signal line (source line) connected to the selected TFT is accumulated in the holding capacitance. The pixel-driven TFT is turned on by the signal voltage stored in the holding capacitance, the set current is output from the drain electrode of the pixel-driven TFT, and the anode electrode (pixel electrode) connected to the drain electrode of the pixel-driven TFT is organic. It is supplied to the EL element and becomes a light emitting state. This light emitting state is maintained until the next writing is performed. A specific basic configuration of such a pixel drive circuit is disclosed in, for example, Patent Document 1.
　従来の電気光学表示装置用ＴＦＴ基板のＴＦＴの半導体チャネル層には、一般的にアモルファス（非晶質）シリコン（ａ－Ｓｉ）が用いられてきた。その主な理由として、アモルファスであるために大面積の基板上でも特性の均一性がよい膜が形成できること、また、比較的低温で形成できるので耐熱性に劣る安価なガラス基板上でも製造でき、表示装置用ディスプレイの製造コストを抑えることができること、さらには耐熱性に劣る樹脂製基板上でも製造できるので、折り曲げが可能な表示装置用ディスプレイを製造できること、などが挙げられる。 Amorphous silicon (a-Si) has generally been used for the semiconductor channel layer of the TFT of the conventional TFT substrate for an electro-optical display device. The main reasons for this are that a film with good uniformity of characteristics can be formed even on a large-area substrate because it is amorphous, and that it can be manufactured on an inexpensive glass substrate that is inferior in heat resistance because it can be formed at a relatively low temperature. It is possible to reduce the manufacturing cost of a display for a display device, and it is possible to manufacture a display for a display device that can be bent because it can be manufactured on a resin substrate having inferior heat resistance.
　一方、近年になって、例えば、特許文献２および３、非特許文献１に開示されるように、酸化物半導体をチャネル層に用いたＴＦＴ（酸化物半導体ＴＦＴ）が開発され、実用化が進められている。酸化物半導体としては、酸化亜鉛（ＺｎＯ）系、酸化亜鉛（ＺｎＯ）に酸化ガリウム（Ｇａ２Ｏ３）および酸化インジウム（Ｉｎ２Ｏ３）を添加したＩｎＧａＺｎＯ系などが挙げられる。 On the other hand, in recent years, for example, as disclosed in Patent Documents 2 and 3 and Non-Patent Document 1, TFTs (oxide semiconductor TFTs) using oxide semiconductors in the channel layer have been developed and put into practical use. Has been done. Examples of the oxide semiconductor include zinc oxide (ZnO) type and InGaZnO type in which gallium oxide (Ga 2 O 3 ) and indium oxide (In 2 O 3) are added to zinc oxide (ZnO).
　酸化物半導体は、組成を適正化することによって、比較的低温でも均一性がよいアモルファス状態の膜が安定的に得られるだけでなく、従来のａ－Ｓｉよりも高い移動度を有するため、小型で高性能なＴＦＴを実現できるという利点がある。 By optimizing the composition of oxide semiconductors, not only can stable amorphous films with good uniformity be obtained even at relatively low temperatures, but also they have higher mobility than conventional a-Si, so they are compact. There is an advantage that a high-performance TFT can be realized.
　しかし、酸化物半導体は、一般的に薬液耐性に乏しく、シュウ酸（Oxalic Acid）系のような弱酸系の薬液でも容易に溶けてしまうという性質がある。従って、ａ－Ｓｉで主流となっているＢＣＥ（バックチャネルエッチング）型ＴＦＴに酸化物半導体を用いる場合、酸薬液を用いたウエットエッチングを行うことによって、チャネル層の直上のソース電極およびドレイン電極を形成すると、チャネル層の酸化物半導体もエッチングされ、信頼性の高いチャネル領域を形成することができないという問題があった。 However, oxide semiconductors generally have poor chemical resistance and have the property of being easily dissolved even in weak acid chemicals such as oxalic acid. Therefore, when an oxide semiconductor is used for the BCE (back channel etching) type TFT that is the mainstream in a-Si, the source electrode and drain electrode directly above the channel layer are formed by performing wet etching using an acid chemical solution. When formed, the oxide semiconductor of the channel layer is also etched, and there is a problem that a highly reliable channel region cannot be formed.
米国特許第９７０４８８７号明細書U.S. Pat. No. 9,704,887 特開２００４－１０３９５７号公報Japanese Unexamined Patent Publication No. 2004-103957 特開２００５－７７８２２号公報Japanese Unexamined Patent Publication No. 2005-77722 米国特許第９７２１９７３号明細書U.S. Pat. No. 9721973
　特許文献１の例えばＦｉｇ．２、Ｆｉｇ．３およびＦｉｇ．５には、基板上に選択ＴＦＴと、選択ＴＦＴ上に画素駆動ＴＦＴが配設された有機ＥＬディスプレイ用のＴＦＴ基板が開示されている。ＴＦＴ基板には、一部ＢＣＥ型のＴＦＴが含まれている。従って、これらのＴＦＴ基板のチャネル層に、高移動度を有する酸化物半導体を用いる場合は、薬液耐性および環境耐性を確保して高信頼性を得るために、すべてのＴＦＴをＥＳ型ＴＦＴで構成する必要がある。このために、有機ＥＬ素子形成前までのＴＦＴ基板を完成させるためには、少なくとも以下に示される(1)～(10)の１０回の写真製版工程が必要であると考えられる。 For example, Fig. 2. Fig. 3 and Fig. No. 5 discloses a TFT substrate for an organic EL display in which a selection TFT is arranged on the substrate and a pixel-driven TFT is arranged on the selection TFT. The TFT substrate includes a part of BCE type TFT. Therefore, when an oxide semiconductor having high mobility is used for the channel layer of these TFT substrates, all TFTs are composed of ES type TFTs in order to secure chemical resistance and environmental resistance and obtain high reliability. There is a need to. Therefore, in order to complete the TFT substrate before the formation of the organic EL element, it is considered that at least 10 photoplate-making steps (1) to (10) shown below are required.
　(1) 選択ＴＦＴのゲート電極の形成工程
　(2) 選択ＴＦＴのチャネル層の形成工程
　(3) 選択ＴＦＴのチャネル層上のエッチングストッパ（ＥＳ）層の形成工程
　(4) 選択ＴＦＴのソース電極、ドレイン電極、駆動用ＴＦＴのゲート電極の形成工程
　(5) 画素駆動ＴＦＴのチャネル層の形成工程
　(6) 画素駆動ＴＦＴのチャネル層上のＥＳ層の形成工程
　(7) 画素駆動ＴＦＴのソース電極（駆動電流供給電極）、ドレイン電極の形成工程
　(8) 保護絶縁層のコンタクトホールの形成工程
　(9) 画素電極の形成工程
　(10) 画素分離層（バンク層）の画素開口部の形成工程 (1) Forming step of gate electrode of selective TFT (2) Forming step of channel layer of selective TFT (3) Forming step of etching stopper (ES) layer on channel layer of selective TFT (4) Source electrode of selective TFT, Drain electrode, gate electrode of drive TFT forming step (5) Channel layer forming step of pixel-driven TFT (6) ES layer forming step on channel layer of pixel-driven TFT (7) Source electrode of pixel-driven TFT (7) Drive current supply electrode), drain electrode forming process (8) Contact hole forming process of protective insulating layer (9) Pixel electrode forming process (10) Pixel opening forming process of pixel separating layer (bank layer)
　また、特許文献４の例えばＦｉｇ．７に開示される有機ＥＬディスプレイ用のＴＦＴ基板の構成では、選択ＴＦＴおよび画素駆動ＴＦＴともにＥＳ型ＴＦＴで構成され、有機ＥＬ層形成前までのＴＦＴ基板を８回の写真製版工程で形成することができ、特許文献１の方法に比べて製造を効率よく行うことができるが、これ以上に写真製版工程を減らすことは難しい。 Also, for example, Fig. In the configuration of the TFT substrate for the organic EL display disclosed in 7, both the selective TFT and the pixel-driven TFT are composed of the ES type TFT, and the TFT substrate before the formation of the organic EL layer is formed by eight photoplate making steps. However, it is difficult to further reduce the number of photoplate-making processes, although the production can be performed more efficiently than the method of Patent Document 1.
　本開示は上記のような問題を解決するためになされたものであり、ＴＦＴを有するＴＦＴ基板を、製造工程を簡略化して生産性よく低コストで得る技術を提供することを目的とする。 The present disclosure has been made in order to solve the above problems, and an object of the present disclosure is to provide a technique for obtaining a TFT substrate having a TFT by simplifying a manufacturing process with high productivity and low cost.
　本開示に係る薄膜トランジスタ基板は、基板と、前記基板上に設けられた、ボトムゲート型の第１の薄膜トランジスタと、トップゲート型の第２の薄膜トランジスタと、を少なくとも備え、前記第１の薄膜トランジスタは、前記基板上に設けられた第１のゲート電極と、前記第１のゲート電極上に設けられた第１のゲート絶縁層と、前記第１のゲート絶縁層上に設けられた第１の半導体層と、前記第１の半導体層上に設けられた第１の保護絶縁層と、前記第１の保護絶縁層を貫通する第１の開口部および第２の開口部を通して前記第１の半導体層にそれぞれ接する、第１のソース電極および第１のドレイン電極と、を有し、前記第２の薄膜トランジスタは、前記基板上に設けられた第２のソース電極および第２のドレイン電極と、前記第２のソース電極および前記第２のドレイン電極上に設けられた第２の保護絶縁層と、前記第２の保護絶縁層上に設けられ、それぞれ前記第２の保護絶縁層を貫通する第３の開口部および第４の開口部を通して、前記第２のソース電極および前記第２のドレイン電極に接する第２の半導体層と、前記第２の半導体層上に設けられた第２のゲート絶縁層と、前記第２のゲート絶縁層上に設けられた第２のゲート電極と、を有し、前記第１のゲート電極、前記第２のソース電極および前記第２のドレイン電極は、同層で同じ第１の導電膜で形成され、前記第１のゲート絶縁層および前記第２の保護絶縁層は、同層で同じ第１の絶縁膜で形成され、前記第１の半導体層および前記第２の半導体層は、同層で同じ半導体膜で形成され、前記第１の保護絶縁層および前記第２のゲート絶縁層は、同層で同じ第２の絶縁膜で形成され、前記第１のソース電極、前記第１のドレイン電極および第２のゲート電極は、同層で同じ第２の導電膜で形成される。 The thin film semiconductor substrate according to the present disclosure includes at least a substrate, a bottom gate type first thin film film provided on the substrate, and a top gate type second thin film thin film. A first gate electrode provided on the substrate, a first gate insulating layer provided on the first gate electrode, and a first semiconductor layer provided on the first gate insulating layer. To the first semiconductor layer through the first protective insulating layer provided on the first semiconductor layer and the first opening and the second opening penetrating the first protective insulating layer. It has a first source electrode and a first drain electrode that are in contact with each other, and the second thin film has a second source electrode and a second drain electrode provided on the substrate and the second drain electrode. A second protective insulating layer provided on the source electrode and the second drain electrode of the above, and a third opening provided on the second protective insulating layer and penetrating the second protective insulating layer, respectively. A second semiconductor layer in contact with the second source electrode and the second drain electrode through the portion and the fourth opening, and a second gate insulating layer provided on the second semiconductor layer. It has a second gate electrode provided on the second gate insulating layer, and the first gate electrode, the second source electrode, and the second drain electrode are the same in the same layer. The first gate insulating layer and the second protective insulating layer are formed of the same conductive film of 1, and the same first insulating film is formed of the same layer, and the first semiconductor layer and the second semiconductor are formed. The layer is formed of the same semiconductor film in the same layer, and the first protective insulating layer and the second gate insulating layer are formed of the same second insulating film in the same layer, and the first source electrode, The first drain electrode and the second gate electrode are formed of the same second conductive film in the same layer.
　本開示によれば、ボトムゲート型の第１の薄膜トランジスタおよびトップゲート型の第２の薄膜トランジスタの各層の構成が共通化されるので、製造工程を簡略化して生産性よく製造できるので、製造コストを低減できる。 According to the present disclosure, since the configurations of each layer of the bottom gate type first thin film transistor and the top gate type second thin film transistor are standardized, the manufacturing process can be simplified and the production can be carried out with high productivity, so that the manufacturing cost can be reduced. Can be reduced.
実施の形態１に係るＴＦＴ基板の構成を概略的に示す断面図である。It is sectional drawing which shows schematic the structure of the TFT substrate which concerns on Embodiment 1. FIG. 実施の形態１に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 1. FIG. 実施の形態１に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 1. FIG. 実施の形態１に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 1. FIG. 実施の形態１に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 1. FIG. 実施の形態２に係るＴＦＴ基板の全体構成を模式的に示す平面図である。It is a top view which shows typically the whole structure of the TFT substrate which concerns on Embodiment 2. 実施の形態２に係るＴＦＴ基板の平面構成を概略的に示す平面図である。It is a top view which shows schematic the plane structure of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の構成を概略的に示す断面図である。It is sectional drawing which shows schematic the structure of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態２に係るＴＦＴ基板を備えた表示装置を模式的に示す斜視図である。It is a perspective view which shows typically the display device provided with the TFT substrate which concerns on Embodiment 2. FIG. 実施の形態３に係るＴＦＴ基板の画素部駆動回路の構成を模式的に示す図である。It is a figure which shows typically the structure of the pixel part drive circuit of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の平面構成を概略的に示す平面図である。It is a top view which shows the plan structure of the TFT substrate which concerns on Embodiment 3 schematically. 実施の形態３に係るＴＦＴ基板の構成を概略的に示す断面図である。It is sectional drawing which shows schematic the structure of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３に係るＴＦＴ基板にＬＥＤ素子を実装した構成を示す断面図である。It is sectional drawing which shows the structure which mounted the LED element on the TFT substrate which concerns on Embodiment 3. 実施の形態３に係るＴＦＴ基板を備えた表示装置を模式的に示す斜視図である。It is a perspective view which shows typically the display device provided with the TFT substrate which concerns on Embodiment 3. FIG. 実施の形態３の変形例１に係るＴＦＴ基板の画素部駆動回路の構成を模式的に示す図である。It is a figure which shows typically the structure of the pixel part drive circuit of the TFT substrate which concerns on the modification 1 of Embodiment 3. 実施の形態３の変形例１に係るＴＦＴ基板の構成を概略的に示す平面図である。It is a top view which shows roughly the structure of the TFT substrate which concerns on the modification 1 of Embodiment 3. 実施の形態３の変形例２に係るＴＦＴ基板の画素部駆動回路の構成を模式的に示す図である。It is a figure which shows typically the structure of the pixel part drive circuit of the TFT substrate which concerns on the modification 2 of Embodiment 3. 実施の形態３の変形例２に係るＴＦＴ基板の構成を概略的に示す平面図である。It is a top view which shows roughly the structure of the TFT substrate which concerns on the modification 2 of Embodiment 3. 信号発生回路の構成を示す図である。It is a figure which shows the structure of the signal generation circuit.
　以下に説明する実施の形態におけるＴＦＴ基板は、表示素子として有機ＥＬ素子またはＬＥＤ素子のような発光体を用いた自発光型表示装置用のアクティブマトリックス基板として用いることができるが、その他にも液晶表示装置（Liquid Crystal display；ＬＣＤ）も含めた信号駆動回路を有するＴＦＴ基板にも適用することができる。 The TFT substrate according to the embodiment described below can be used as an active matrix substrate for a self-luminous display device using a light emitting body such as an organic EL element or an LED element as a display element. It can also be applied to a TFT substrate having a signal drive circuit including a display device (Liquid Crystal display; LCD).
　＜実施の形態１＞
　＜ＴＦＴ基板の構成＞
　図１は、実施の形態１に係るＴＦＴ基板１００の構成を概略的に示す断面図である。ＴＦＴ基板１００は、ＴＦＴ１０１（第１の薄膜トランジスタ）およびＴＦＴ１０２（第２の薄膜トランジスタ）を備えている。図においては、ＴＦＴ１０１が形成される第１のＴＦＴ部を図の右側に、ＴＦＴ１０２が形成される第１のＴＦＴ部を図の左側に示している。ＴＦＴ１０１およびＴＦＴ１０２は、透明絶縁性を有する同一の基板１、例えばガラス基板上に配設されている。 <Embodiment 1>
<Construction of TFT substrate>
FIG. 1 is a cross-sectional view schematically showing the configuration of the TFT substrate 100 according to the first embodiment. The TFT substrate 100 includes a TFT 101 (first thin film transistor) and a TFT 102 (second thin film transistor). In the figure, the first TFT portion on which the TFT 101 is formed is shown on the right side of the figure, and the first TFT portion on which the TFT 102 is formed is shown on the left side of the figure. The TFT 101 and the TFT 102 are arranged on the same substrate 1 having transparent insulation, for example, a glass substrate.
　　＜第１のＴＦＴの構成＞
　ＴＦＴ１０１は、ボトムゲート逆スタガ構造でチャネルを保護する構成を採り、基板１上に、第１の導電膜で構成されるゲート電極２（第１のゲート電極）が設けられ、ゲート電極２を覆うように、第１の絶縁膜で構成されるゲート絶縁層５（第１のゲート絶縁層）が設けられている。そして、ゲート絶縁層５上のゲート電極２と重なる領域に、半導体膜で構成される半導体層９（第１の半導体層）が設けられている。さらに、ゲート絶縁層５上および半導体層９上に、第２の絶縁膜で構成される保護絶縁層１１（第１の保護絶縁層）が設けられている。 <Structure of the first TFT>
The TFT 101 has a structure in which a bottom gate reverse stagger structure is used to protect the channel, and a gate electrode 2 (first gate electrode) composed of a first conductive film is provided on the substrate 1 to cover the gate electrode 2. As described above, the gate insulating layer 5 (first gate insulating layer) composed of the first insulating film is provided. A semiconductor layer 9 (first semiconductor layer) composed of a semiconductor film is provided in a region on the gate insulating layer 5 that overlaps with the gate electrode 2. Further, a protective insulating layer 11 (first protective insulating layer) composed of a second insulating film is provided on the gate insulating layer 5 and the semiconductor layer 9.
　半導体層９と重なる領域の保護絶縁層１１には、下層の半導体層９の表面が露出するように、それぞれ開口部１３（第１の開口部）および開口部１４（第２の開口部）が設けられている。 The protective insulating layer 11 in the region overlapping the semiconductor layer 9 has an opening 13 (first opening) and an opening 14 (second opening), respectively, so that the surface of the lower semiconductor layer 9 is exposed. It is provided.
　開口部１３は、半導体層９のソース領域となる表面を露出させるソース領域コンタクトホールであり、開口部１４は、半導体層９のドレイン領域となる表面を露出させるドレイン領域コンタクトホールである。そして、保護絶縁層１１上には、開口部１３を通して半導体層９と接するように、第２の導電膜で構成されるソース電極１５（第１のソース電極）が設けられ、開口部１４を通して半導体層９と接するように、第２の導電膜で構成されるドレイン電極１６（第１のドレイン電極）が設けられている。 The opening 13 is a source region contact hole that exposes the surface of the semiconductor layer 9 that is the source region, and the opening 14 is a drain region contact hole that exposes the surface of the semiconductor layer 9 that is the drain region. A source electrode 15 (first source electrode) composed of a second conductive film is provided on the protective insulating layer 11 so as to come into contact with the semiconductor layer 9 through the opening 13, and the semiconductor is provided through the opening 14. A drain electrode 16 (first drain electrode) composed of a second conductive film is provided so as to be in contact with the layer 9.
　ソース電極１５とドレイン電極１６は、半導体層９と重なる領域内で互いに分離して設けられており、半導体層９においてソース電極１５とドレイン電極１６とで挟まれる離間領域が、ＴＦＴ１０１のチャネル領域ＣＬ１（第１のチャネル領域）として規定される。 The source electrode 15 and the drain electrode 16 are provided separately from each other in the region overlapping the semiconductor layer 9, and the separated region sandwiched between the source electrode 15 and the drain electrode 16 in the semiconductor layer 9 is the channel region CL1 of the TFT 101. It is defined as (first channel region).
　チャネル領域ＣＬ１上の保護絶縁層１１は、半導体層９のチャネル領域ＣＬ１をプロセスダメージ等から保護するチャネル保護層（第１のチャネル保護層）として機能する。従って、ＴＦＴ１０１は、特性および信頼性に優れたＴＦＴとなる。 The protective insulating layer 11 on the channel region CL1 functions as a channel protection layer (first channel protection layer) that protects the channel region CL1 of the semiconductor layer 9 from process damage and the like. Therefore, the TFT 101 is a TFT having excellent characteristics and reliability.
　＜第２のＴＦＴの構成＞
　ＴＦＴ１０２は、トップゲート順スタガ構造でチャネルを保護する構成を採り、ガラス基板１上に、第１の導電膜で構成されるソース電極３（第２のソース電極）とドレイン電極４（第２のドレイン電極）が互いに分離して設けられ、その上に第１の絶縁膜で構成される保護絶縁層６（第２の保護絶縁層）が設けられている。保護絶縁層６には、ソース電極３の表面の一部を露出させる開口部７（第３の開口部）と、ドレイン電極４の表面の一部を露出させる開口部８（第４の開口部）が設けられている。 <Structure of second TFT>
The TFT 102 has a structure in which channels are protected by a top gate forward staggered structure, and a source electrode 3 (second source electrode) and a drain electrode 4 (second source electrode) composed of a first conductive film are formed on a glass substrate 1. Drain electrodes) are provided separately from each other, and a protective insulating layer 6 (second protective insulating layer) composed of a first insulating film is provided on the drain electrodes). The protective insulating layer 6 has an opening 7 (third opening) that exposes a part of the surface of the source electrode 3 and an opening 8 (fourth opening) that exposes a part of the surface of the drain electrode 4. ) Is provided.
　保護絶縁層６上には、開口部７を通して下層のソース電極３と接するとともに、開口部８を通して下層のドレイン電極４と接するように、半導体膜で構成される半導体層１０（第２の半導体層）が設けられている。下層のソース電極３およびドレイン電極４は、半導体層１０と重なる領域内で互いに分離して設けられており、半導体層１０においてソース電極３とドレイン電極４とで挟まれる離間領域が、ＴＦＴ１０２のチャネル領域ＣＬ２（第２のチャネル領域）として規定される。 On the protective insulating layer 6, the semiconductor layer 10 (second semiconductor layer) formed of a semiconductor film is in contact with the source electrode 3 of the lower layer through the opening 7 and is in contact with the drain electrode 4 of the lower layer through the opening 8. ) Is provided. The lower source electrode 3 and the drain electrode 4 are provided separately from each other in the region overlapping the semiconductor layer 10, and the separated region sandwiched between the source electrode 3 and the drain electrode 4 in the semiconductor layer 10 is the channel of the TFT 102. It is defined as region CL2 (second channel region).
　そして、保護絶縁層６上および半導体層１０上に、第２の絶縁膜で構成されるゲート絶縁層１２（第２のゲート絶縁層）が設けられ、さらに半導体層１０のチャネル領域ＣＬ２と重なる領域のゲート絶縁層１２上に、第２の導電膜で構成されるゲート電極１７（第２のゲート電極）が設けられている。 A gate insulating layer 12 (second gate insulating layer) composed of a second insulating film is provided on the protective insulating layer 6 and the semiconductor layer 10, and further overlaps with the channel region CL2 of the semiconductor layer 10. A gate electrode 17 (second gate electrode) composed of a second conductive film is provided on the gate insulating layer 12 of the above.
　チャネル領域ＣＬ２の保護絶縁層６は、半導体層１０のチャネル領域ＣＬ２をプロセスダメージ等から保護するチャネル保護層（第２のチャネル保護層）として機能する。従って、ＴＦＴ１０２は、特性および信頼性に優れたＴＦＴとなる。 The protective insulating layer 6 of the channel region CL2 functions as a channel protection layer (second channel protection layer) that protects the channel region CL2 of the semiconductor layer 10 from process damage and the like. Therefore, the TFT 102 is a TFT having excellent characteristics and reliability.
　さらに、ゲート電極１７を、下層のソース電極３およびドレイン電極４と重ならないように配設することで、ゲート電極とソース電極、ドレイン電極との間で形成される寄生容量をなくすことができ、応答性に優れた特性を得ることができる。 Further, by disposing the gate electrode 17 so as not to overlap the source electrode 3 and the drain electrode 4 in the lower layer, it is possible to eliminate the parasitic capacitance formed between the gate electrode and the source electrode and the drain electrode. It is possible to obtain characteristics having excellent responsiveness.
　以上説明したように、実施の形態１のＴＦＴ基板１００によれば、ボトムゲート逆スタガ構造のチャネル保護型のＴＦＴ１０１と、トップゲート順スタガ構造のチャネル保護型のＴＦＴ１０２の異なる構造および特性を有するＴＦＴを、同じ基板上に配設することができる。 As described above, according to the TFT substrate 100 of the first embodiment, the TFT 101 having a bottom gate reverse stagger structure and the channel protection type TFT 102 having a top gate forward stagger structure have different structures and characteristics. Can be arranged on the same substrate.
　＜ＴＦＴ基板の製造方法＞　
　以下、実施の形態１に係るＴＦＴ基板１００の製造方法について、図２～図５を用いて説明する。なお、製造の最終工程図は、図１に対応している。 <Manufacturing method of TFT substrate>
Hereinafter, the method for manufacturing the TFT substrate 100 according to the first embodiment will be described with reference to FIGS. 2 to 5. The final manufacturing process diagram corresponds to FIG.
　　＜１回目の写真製版工程：図２＞
　まず、ガラス等の透明絶縁性を有する基板１を洗浄液または純水を用いて洗浄する。本実施の形態１では、厚さ０．５ｍｍのガラス基板を基板１として用いた。そして、洗浄された基板１の一方の主面上に第１の導電膜を形成する。 <First photoengraving process: Fig. 2>
First, the substrate 1 having transparent insulation such as glass is washed with a cleaning liquid or pure water. In the first embodiment, a glass substrate having a thickness of 0.5 mm was used as the substrate 1. Then, the first conductive film is formed on one main surface of the washed substrate 1.
　第１の導電膜としては、例えばクロム（Ｃｒ）、モリブデン（Ｍｏ）、チタン（Ｔｉ）、銅（Ｃｕ）、タンタル（Ｔａ）、タングステン（Ｗ）、アルミニウム（Ａｌ）等の金属、またはこれらに他の元素を微量に添加した合金等を用いることができる。また、これらの金属または合金を２層以上含む積層構造としてもよい。これらの金属、合金を用いることによって、比抵抗値が５０μΩｃｍ以下の低抵抗な導電膜を得ることができる。 Examples of the first conductive film include metals such as chromium (Cr), molybdenum (Mo), titanium (Ti), copper (Cu), tantalum (Ta), tungsten (W), and aluminum (Al), or these. An alloy or the like to which a small amount of other elements is added can be used. Further, a laminated structure containing two or more layers of these metals or alloys may be used. By using these metals and alloys, a low resistance conductive film having a specific resistance value of 50 μΩcm or less can be obtained.
　本実施の形態１では、第１の導電膜としてＭｏを使用し、Ａｒ（アルゴン）ガスを用いたスパッタリング法でＭｏ膜を２００ｎｍの厚さに形成した。その後、Ｍｏ膜上にフォトレジスト材を塗布し、１回目の写真製版工程でフォトレジストパターンを形成し、当該フォトレジストパターンをマスクにして、Ｍｏ膜をエッチングによりパターニングする。ここでは、リン酸（Phosphoric Acid）、酢酸（Acetic Acid）および硝酸（Nitric Acid）を含む溶液（ＰＡＮ薬液）によるウエットエッチングを用いた。その後、フォトレジストパターンを除去することで、図２に示すように、基板１上に、ＴＦＴ１０１のゲート電極２およびＴＦＴ１０２のソース電極３およびドレイン電極４が同時に形成される。 In the first embodiment, Mo was used as the first conductive film, and the Mo film was formed to a thickness of 200 nm by a sputtering method using Ar (argon) gas. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the first photoplate-making step, and the Mo film is patterned by etching using the photoresist pattern as a mask. Here, wet etching with a solution (PAN chemical solution) containing phosphoric acid (Phosphoric Acid), acetic acid (Acetic Acid) and nitric acid (Nitric Acid) was used. After that, by removing the photoresist pattern, as shown in FIG. 2, the gate electrode 2 of the TFT 101, the source electrode 3 of the TFT 102, and the drain electrode 4 are simultaneously formed on the substrate 1.
　　＜２回目の写真製版工程：図３＞
　次に、基板１の主面上の全体に第１の絶縁膜を形成する。本実施の形態１では、化学的気相成膜（Chemical Vapor Deposition；ＣＶＤ）法を用いて、第１の絶縁膜として酸化シリコン膜（ＳｉＯ膜）を形成した。ここでは、厚さ３００ｎｍのＳｉＯ膜を、約３００℃の基板加熱条件下で形成した。なお、第１の絶縁膜は、ＳｉＯ膜に限ることなく、他にも例えば窒化シリコン膜（ＳｉＮ膜）を用いることができる。ＳｉＮ膜もＳｉＯ膜と同様にＣＶＤ法で成膜することができる。また、ＳｉＯ膜とＳｉＮ膜との積層膜としてもよい。 <Second photoengraving process: Fig. 3>
Next, the first insulating film is formed on the entire main surface of the substrate 1. In the first embodiment, a silicon oxide film (SiO film) is formed as a first insulating film by using a chemical vapor deposition (CVD) method. Here, a SiO film having a thickness of 300 nm was formed under substrate heating conditions of about 300 ° C. The first insulating film is not limited to the SiO film, and for example, a silicon nitride film (SiN film) can be used. The SiN film can also be formed by the CVD method in the same manner as the SiO film. Further, it may be a laminated film of a SiO film and a SiN film.
　次に、２回目の写真製版工程で第１の絶縁膜であるＳｉＯ膜上にフォトレジストパターンを形成し、これをマスクとしてＳｉＯ膜をエッチングする。このエッチング工程では、フッ素（Ｆ）を含むガス、例えば六フッ化硫黄（ＳＦ６）ガスまたは四フッ化炭素（ＣＦ４）ガスを用いたドライエッチング法を用いることができる。 Next, in the second photoplate making step, a photoresist pattern is formed on the SiO film which is the first insulating film, and the SiO film is etched using this as a mask. In this etching step, a dry etching method using a gas containing fluorine (F), for example, sulfur hexafluoride (SF 6 ) gas or carbon tetrafluoride (CF 4) gas can be used.
　その後、フォトレジストパターンを除去することで、図３に示すように、ＴＦＴ１０２において、ソース電極３の表面の一部を露出させる開口部７、およびドレイン電極４の表面の一部を露出させる開口部８がそれぞれ形成される。なお、第１のＴＦＴ部の第１の絶縁膜はゲート絶縁層５として機能し、第２のＴＦＴ部の第１の絶縁膜は、後の工程で形成される第２半導体層形成時に、第２半導体層をソース電極３およびドレイン電極４から受けるダメージから保護する保護絶縁層６（第２のチャネル保護層）として機能する。 After that, by removing the photoresist pattern, as shown in FIG. 3, in the TFT 102, an opening 7 that exposes a part of the surface of the source electrode 3 and an opening that exposes a part of the surface of the drain electrode 4 8 are formed respectively. The first insulating film of the first TFT portion functions as the gate insulating layer 5, and the first insulating film of the second TFT portion is used when the second semiconductor layer formed in a later step is formed. 2 The semiconductor layer functions as a protective insulating layer 6 (second channel protective layer) that protects the semiconductor layer from damage received from the source electrode 3 and the drain electrode 4.
　　＜３回目の写真製版工程：図４＞
　次に、第１の絶縁膜上に半導体膜を形成する。本実施の形態１では、半導体膜として酸化物半導体膜を形成する。具体的には、インジウム（Ｉｎ）とガリウム（Ｇａ）と亜鉛（Ｚｎ）と酸素（Ｏ）を含む酸化物（ＩｎＧａＺｎＯ）を用いる。ここでは、Ｉｎ：Ｇａ：Ｚｎ：Ｏの原子組成比が１：１：１：４であるＩｎＧａＺｎＯターゲットを用い、Ａｒガスを用いたスパッタリング法で酸化物半導体膜（ＩｎＧａＺｎＯ膜）を形成した。 <Third photoengraving process: Fig. 4>
Next, a semiconductor film is formed on the first insulating film. In the first embodiment, an oxide semiconductor film is formed as the semiconductor film. Specifically, an oxide (InGaZnO) containing indium (In), gallium (Ga), zinc (Zn) and oxygen (O) is used. Here, an oxide semiconductor film (InGaZnO film) was formed by a sputtering method using Ar gas using an InGaZnO target having an atomic composition ratio of In: Ga: Zn: O of 1: 1: 1: 4.
　この場合、通常は、Ｏの原子組成比が化学量論組成よりも少なく、Ｏイオン欠乏状態（上記の例ではＯの組成比が４未満）の酸化物膜となってしまう。従って、Ａｒガスに酸素（Ｏ２）ガスを混合させてスパッタリングすることが好ましい。本実施の形態１では、Ａｒガスに対して分圧比で１０％のＯ２ガスを添加した混合ガスを用いて、スパッタリングし、ＩｎＧａＺｎＯ膜を５０ｎｍの厚さで形成した。ＩｎＧａＺｎＯ膜は、アモルファス構造で形成される。アモルファス構造のＩｎＧａＺｎＯ膜は、一般的に結晶化温度が５００℃超であり、常温では膜中の大部分がアモルファス構造のままで安定する。アモルファス構造は、一部が結晶化された微結晶構造や多結晶構造に比べて構造の均一性を高くすることができる。従って、基板が大型化した場合でも基板全体に特性のバラツキが小さい半導体膜を形成することができる利点がある。 In this case, the atomic composition ratio of O is usually smaller than that of the stoichiometric composition, resulting in an oxide film in an O ion-deficient state (in the above example, the composition ratio of O is less than 4). Therefore, it is preferable to mix Ar gas with oxygen (O 2 ) gas and perform sputtering. In the first embodiment, an InGaZnO film having a thickness of 50 nm was formed by sputtering using a mixed gas in which O 2 gas having a partial pressure ratio of 10% was added to Ar gas. The InGaZnO film is formed with an amorphous structure. The InGaZnO film having an amorphous structure generally has a crystallization temperature of more than 500 ° C., and at room temperature, most of the film remains stable with an amorphous structure. The amorphous structure can have higher structural uniformity than a partially crystallized microcrystal structure or a polycrystalline structure. Therefore, even when the size of the substrate is increased, there is an advantage that a semiconductor film having a small variation in characteristics can be formed on the entire substrate.
　次に、３回目の写真製版工程でＩｎＧａＺｎＯ膜上にフォトレジストパターンを形成し、これをマスクとしてＩｎＧａＺｎＯ膜をエッチングする。このエッチング工程では、シュウ酸（Oxalic Acid）薬液によるウエットエッチングを用いることができる。その後、フォトレジストパターンを除去することで、図４に示すように、第１のＴＦＴ部においては、ゲート絶縁層５上のゲート電極２と重なる領域に半導体層９が形成される。 Next, a photoresist pattern is formed on the InGaZnO film in the third photoengraving process, and the InGaZnO film is etched using this as a mask. In this etching step, wet etching with an oxalic acid chemical solution can be used. After that, by removing the photoresist pattern, as shown in FIG. 4, in the first TFT portion, the semiconductor layer 9 is formed in the region overlapping the gate electrode 2 on the gate insulating layer 5.
　また、第２のＴＦＴ部においては、保護絶縁層６上に半導体層１０が形成される。半導体層１０は、保護絶縁層６の開口部７を通して下層のソース電極３と接するとともに、保護絶縁層６の開口部８を通して下層のドレイン電極４と接するように形成される。ソース電極３およびドレイン電極４は、半導体層１０と重なる領域内で互いに分離して離間領域を有するように形成されており、半導体層１０において、この離間領域がＴＦＴ１０２のチャネル領域（第２のチャネル領域）ＣＬ２として規定される。 Further, in the second TFT portion, the semiconductor layer 10 is formed on the protective insulating layer 6. The semiconductor layer 10 is formed so as to be in contact with the source electrode 3 of the lower layer through the opening 7 of the protective insulating layer 6 and to be in contact with the drain electrode 4 of the lower layer through the opening 8 of the protective insulating layer 6. The source electrode 3 and the drain electrode 4 are formed so as to have a separated region separated from each other in a region overlapping the semiconductor layer 10, and in the semiconductor layer 10, this separated region is a channel region (second channel) of the TFT 102. Region) CL2.
　半導体層１０の材料である酸化物半導体膜をスパッタリング法で形成する場合、下層にソース電極３およびドレイン電極４のような金属膜が露出していると、スパッタリング中に酸化物半導体が金属と反応し、還元（Ｏイオン欠乏）状態の特性が劣化した酸化物半導体膜が形成されてしまう場合がある。しかしながら、本実施の形態１のＴＦＴ１０２の場合は、開口部７および開口部８を除く基板１全体が保護絶縁層６で覆われているので、この影響を防止することができる。すなわち、チャネル領域ＣＬ２の保護絶縁層６は、半導体層１０のチャネル保護層６（第２のチャネル保護層）として機能する。 When the oxide semiconductor film, which is the material of the semiconductor layer 10, is formed by the sputtering method, if the metal films such as the source electrode 3 and the drain electrode 4 are exposed in the lower layer, the oxide semiconductor reacts with the metal during sputtering. However, an oxide semiconductor film having deteriorated characteristics in the reduced (O ion deficient) state may be formed. However, in the case of the TFT 102 of the first embodiment, since the entire substrate 1 excluding the opening 7 and the opening 8 is covered with the protective insulating layer 6, this influence can be prevented. That is, the protective insulating layer 6 of the channel region CL2 functions as the channel protective layer 6 (second channel protective layer) of the semiconductor layer 10.
　その後、ガラス基板１を大気雰囲気下で４００℃の温度で熱処理する。この熱処理によって半導体層９および半導体層１０の非晶質のＩｎＧａＺｎＯ膜が構造緩和を起こし、半導体特性をさらに安定させることができる。なお、構造緩和とは、膜形成およびウエットエッチング等のプロセスダメージに起因する構成原子の格子欠陥を減らし、非晶質構造がより安定化する現象である。 After that, the glass substrate 1 is heat-treated at a temperature of 400 ° C. in an air atmosphere. By this heat treatment, the amorphous InGaZnO film of the semiconductor layer 9 and the semiconductor layer 10 causes structural relaxation, and the semiconductor characteristics can be further stabilized. Structural relaxation is a phenomenon in which lattice defects of constituent atoms due to process damage such as film formation and wet etching are reduced, and the amorphous structure is more stabilized.
　非晶質のＩｎＧａＺｎＯ膜に上記の構造緩和を起こさせるための熱処理の温度は、少なくとも３００℃以上であることが好ましい。一方、５００℃を超えると膜全体で結晶化が始まり半導体特性が大きく変化し、例えばキャリア密度増大により導体化してしまう。従って、ここでは少なくともガラス基板１を３００℃以上５００℃以下の温度で熱処理することが好ましい。なお、このような熱処理は、製造工程の最後に実施するようにしてもよい。 The temperature of the heat treatment for causing the above-mentioned structural relaxation of the amorphous InGaZnO film is preferably at least 300 ° C. or higher. On the other hand, when the temperature exceeds 500 ° C., crystallization starts in the entire film and the semiconductor characteristics change significantly, and for example, it becomes a conductor due to an increase in carrier density. Therefore, here, it is preferable to heat-treat at least the glass substrate 1 at a temperature of 300 ° C. or higher and 500 ° C. or lower. In addition, such a heat treatment may be carried out at the end of the manufacturing process.
　＜４回目の写真製版工程：図５＞
　次に、基板１の主面上の全体に第２の絶縁膜を形成する。本実施の形態１では、第２の絶縁膜として、ＣＶＤ法で厚さ３００ｎｍのＳｉＯ膜を約２００℃の基板加熱条件下で形成した。なお、第２の絶縁膜は、ＳｉＯ膜に限ることなく、他にも例えばＳｉＮ膜を用いることができる。また、ＳｉＯ膜とＳｉＮ膜との積層膜としてもよい。 <Fourth photoengraving process: Fig. 5>
Next, a second insulating film is formed on the entire main surface of the substrate 1. In the first embodiment, as the second insulating film, a SiO film having a thickness of 300 nm was formed by a CVD method under a substrate heating condition of about 200 ° C. The second insulating film is not limited to the SiO film, and for example, a SiN film can be used. Further, it may be a laminated film of a SiO film and a SiN film.
　次に、４回目の写真製版工程で第２の絶縁膜であるＳｉＯ膜上にフォトレジストパターンを形成し、これをマスクとしてＳｉＯ膜をエッチングする。このエッチング工程では、ＳＦ６ガスまたはＣＦ４ガスを用いたドライエッチング法を用いることができる。 Next, in the fourth photoplate making step, a photoresist pattern is formed on the SiO film which is the second insulating film, and the SiO film is etched using this as a mask. In this etching step, a dry etching method using SF 6 gas or CF 4 gas can be used.
　その後、フォトレジストパターンを除去することで、図５に示すように、第１のＴＦＴ部の第２の絶縁膜に、半導体層９の表面の一部を露出させる開口部１３および開口部１４が形成される。第１のＴＦＴ部の第２の絶縁膜は、後の工程で形成されるソース電極１５およびドレイン電極１６からの加工プロセスダメージを防止する保護絶縁層１１（第１のチャネル保護層）として機能する。また、第２のＴＦＴ部の第２の絶縁膜は、ゲート絶縁層１２として機能する。 After that, by removing the photoresist pattern, as shown in FIG. 5, an opening 13 and an opening 14 that expose a part of the surface of the semiconductor layer 9 are formed on the second insulating film of the first TFT portion. It is formed. The second insulating film of the first TFT portion functions as a protective insulating layer 11 (first channel protective layer) for preventing processing process damage from the source electrode 15 and the drain electrode 16 formed in a later step. .. Further, the second insulating film of the second TFT portion functions as the gate insulating layer 12.
　　＜５回目の写真製版工程：図１＞
　次に、第２の絶縁膜上に第２の導電膜を形成する。第２の導電膜としては、第１の導電膜と同じように、例えばＣｒ、Ｍｏ、Ｔｉ、Ｃｕ、Ｔａ、Ｗ、Ａｌ等の金属、またはこれらに他の元素を微量に添加した合金等を用いることができる。また、これらの金属または合金を２層以上含む積層構造としてもよい。これらの金属または合金を用いることによって、比抵抗値が５０μΩｃｍ以下の低抵抗な導電膜を得ることができる。 <Fifth photoengraving process: Fig. 1>
Next, a second conductive film is formed on the second insulating film. As the second conductive film, as in the case of the first conductive film, for example, a metal such as Cr, Mo, Ti, Cu, Ta, W, Al, or an alloy obtained by adding a small amount of other elements to these, or the like. Can be used. Further, a laminated structure containing two or more layers of these metals or alloys may be used. By using these metals or alloys, a low resistance conductive film having a specific resistance value of 50 μΩcm or less can be obtained.
　本実施の形態１では、第２の導電膜としてＭｏ膜を用い、Ａｒガスを用いたスパッタリング法でＭｏ膜を２００ｎｍの厚さに形成した。その後、Ｍｏ膜上にフォトレジスト材を塗布し、５回目の写真製版工程でフォトレジストパターンを形成し、当該フォトレジストパターンをマスクにして、Ｍｏ膜をエッチングによりパターニングする。ここでは、ＰＡＮ薬液によるウエットエッチングを用いた。その後、フォトレジストパターンを除去することで、図１に示すように、基板１上に、ＴＦＴ１０１のソース電極１５およびドレイン電極１６が形成され、同時にＴＦＴ１０２のゲート電極１７が形成される。 In the first embodiment, a Mo film was used as the second conductive film, and the Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the fifth photoplate-making step, and the Mo film is patterned by etching using the photoresist pattern as a mask. Here, wet etching with a PAN chemical solution was used. After that, by removing the photoresist pattern, as shown in FIG. 1, the source electrode 15 and the drain electrode 16 of the TFT 101 are formed on the substrate 1, and at the same time, the gate electrode 17 of the TFT 102 is formed.
　ＴＦＴ１０１のソース電極１５は、開口部１３を通して半導体層９と接するように形成される。また、ドレイン電極１６は、開口部１４を通して半導体層９と接するように形成される。ソース電極１５とドレイン電極１６は、半導体層９と重なる領域内で互いに分離して設けられており、半導体層９においてソース電極１５とドレイン電極１６とで挟まれる離間領域が、ＴＦＴ１０１のチャネル領域ＣＬ１として規定されている。 The source electrode 15 of the TFT 101 is formed so as to be in contact with the semiconductor layer 9 through the opening 13. Further, the drain electrode 16 is formed so as to be in contact with the semiconductor layer 9 through the opening 14. The source electrode 15 and the drain electrode 16 are provided separately from each other in the region overlapping the semiconductor layer 9, and the separated region sandwiched between the source electrode 15 and the drain electrode 16 in the semiconductor layer 9 is the channel region CL1 of the TFT 101. Is specified as.
　一般的に酸化物半導体膜は薬液耐性に乏しく、半導体層９の材料であるＩｎＧａＺｎＯ膜は、第２の導電膜のウエットエッチングに用いられるＰＡＮ薬液にも容易に溶けてしまう。しかしながら、ＴＦＴ１０１では、開口部１３および開口部１４を除くガラス基板１の全面が絶縁膜で構成される保護絶縁層１１で覆われており、特に半導体層９のチャネル領域ＣＬ１上では保護絶縁層１１はチャネル保護層（エッチングストッパ；ＥＳ）として機能する。従って、プロセスダメージのない信頼性の高いＴＦＴを得ることができる。 Generally, the oxide semiconductor film has poor chemical resistance, and the InGaZnO film, which is the material of the semiconductor layer 9, is easily dissolved in the PAN chemical solution used for wet etching of the second conductive film. However, in the TFT 101, the entire surface of the glass substrate 1 excluding the opening 13 and the opening 14 is covered with the protective insulating layer 11 formed of an insulating film, and the protective insulating layer 11 is particularly provided on the channel region CL1 of the semiconductor layer 9. Functions as a channel protection layer (etching stopper; ES). Therefore, a highly reliable TFT without process damage can be obtained.
　ＴＦＴ１０２のゲート電極１７は、下層の第２半導体層のチャネル領域ＣＬ２と重なるように形成される。また下層のソース電極３およびドレイン電極４と重ならないように形成することで、ゲート電極１７とソース電極３およびドレイン電極４との間で形成される寄生容量をなくすことができ、応答性に優れた高速応答のＴＦＴを得ることができる。さらに、半導体層１０のチャネル領域ＣＬ２は、保護絶縁層６で保護されているので、ＴＦＴ１０１と同様に、プロセスダメージのない信頼性の高いＴＦＴを得ることができる。 The gate electrode 17 of the TFT 102 is formed so as to overlap the channel region CL2 of the lower second semiconductor layer. Further, by forming the source electrode 3 and the drain electrode 4 in the lower layer so as not to overlap with each other, it is possible to eliminate the parasitic capacitance formed between the gate electrode 17 and the source electrode 3 and the drain electrode 4, and the response is excellent. A high-speed response TFT can be obtained. Further, since the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained as in the case of the TFT 101.
　以上のように、本実施の形態１に係るＴＦＴ基板１００は、第１のＴＦＴと第２のＴＦＴとが、互いにゲート電極とソース電極およびドレイン電極との位置（上下層）関係は異なるものの、両者の半導体層が同一の半導体層で構成され、かつそれぞれの電極を含めた各層の構造が共通化できるように構成されている。従って、動作安定性および信頼性に優れるボトムゲート逆スタガ構造でチャネル保護型の第１のＴＦＴと、信頼性に優れるとともに電極間の寄生容量が小さく応答性に優れたトップゲート順スタガ構造でチャネル保護型の第２のＴＦＴとの、異なる構造および特性を有するＴＦＴを、５回の写真製版工程を用いて生産性よく低コストで製造することができる。 As described above, in the TFT substrate 100 according to the first embodiment, the first TFT and the second TFT have different positional (upper and lower layers) relationships between the gate electrode, the source electrode, and the drain electrode. Both semiconductor layers are composed of the same semiconductor layer, and the structure of each layer including the respective electrodes can be made common. Therefore, the channel is a channel-protected first TFT with a bottom gate reverse staggered structure that is excellent in operation stability and reliability, and a top gate forward staggered structure that is excellent in reliability and has a small parasitic capacitance between electrodes and is excellent in responsiveness. A TFT having a structure and characteristics different from that of the protective type second TFT can be manufactured with high productivity and low cost by using five photoplate-making steps.
　また、各層の構造を共通化しているので、例えば、ＴＦＴ１０１のゲート電極２とＴＦＴ１０２のソース電極３もしくはドレイン電極４のいずれかと、を接続するようにＴＦＴ１０１とＴＦＴ１０２とを組み合わせたＴＦＴ回路を形成する場合には、ゲート電極２とソース電極３もしくはドレイン電極４を連続した一体パターンとすることで、例えば、両者を別体で形成し、コンタクトホールを介して電気的に接続した構成に比べると、ＴＦＴ１０２からＴＦＴ１０１への信号の伝達不良による欠陥の発生率を低く抑えることができる。さらに、ゲート電極２とドレイン電極４に限らず、ゲート電極１７とソース電極１５もしくはドレイン電極１６のいずれかを接続する場合でも、これらを連続した一体パターンとすることで同じ効果を得ることができる。 Further, since the structure of each layer is standardized, for example, a TFT circuit in which the TFT 101 and the TFT 102 are combined is formed so as to connect the gate electrode 2 of the TFT 101 and either the source electrode 3 or the drain electrode 4 of the TFT 102. In this case, by forming the gate electrode 2 and the source electrode 3 or the drain electrode 4 into a continuous integrated pattern, for example, as compared with a configuration in which both are formed separately and electrically connected via a contact hole, The occurrence rate of defects due to poor signal transmission from the TFT 102 to the TFT 101 can be suppressed to a low level. Further, not only the gate electrode 2 and the drain electrode 4 but also the gate electrode 17 and either the source electrode 15 or the drain electrode 16 are connected, the same effect can be obtained by forming them in a continuous integrated pattern. ..
　＜実施の形態２＞
　　＜装置構成＞
　図６は、実施の形態２に係るＴＦＴ基板１１０の全体構成を模式的に示す平面図である。図６に示すように、ＴＦＴ基板１１０は、基板１上に少なくともＴＦＴ１０１、ＴＦＴ１０２および画素領域ＰＸを含む画素がマトリックス状に配列された表示領域１５０と、表示領域１５０に隣接する額縁領域１６０とに大きく分けられる。画素領域ＰＸには例えば有機系の材料で構成されるＥＬ素子４４（エレクトロルミネッセンス素子）が配設されており、有機ＥＬディスプレイを備えた自発光型表示装置用のＴＦＴ基板として好適に用いることができる。なお、図６において、ＴＦＴ基板１１０の輪郭形状は四角形で示されているが、これに限ることはなく例えば円形または楕円形のような曲線を含む形状であってもよい。また、ＴＦＴ基板１１０は、平坦に限ることはなく湾曲していてもよい。 <Embodiment 2>
<Device configuration>
FIG. 6 is a plan view schematically showing the overall configuration of the TFT substrate 110 according to the second embodiment. As shown in FIG. 6, the TFT substrate 110 has a display region 150 in which pixels including at least the TFT 101, the TFT 102, and the pixel region PX are arranged in a matrix on the substrate 1, and a frame region 160 adjacent to the display region 150. It can be roughly divided. An EL element 44 (electroluminescence element) made of, for example, an organic material is arranged in the pixel region PX, and can be suitably used as a TFT substrate for a self-luminous display device provided with an organic EL display. can. Although the contour shape of the TFT substrate 110 is shown as a quadrangle in FIG. 6, the contour shape is not limited to this, and may be a shape including a curved line such as a circular shape or an elliptical shape. Further, the TFT substrate 110 is not limited to being flat and may be curved.
　図６に示すように、表示領域１５０には、複数のゲート配線３２と複数のソース配線３４とが互いに直交するように交差して配設され、ゲート配線３２とソース配線３４で規定される領域に画素が設けられ、画素内には画素の駆動のための画素部駆動回路ＥＬＣ１が設けられている。また、表示領域１５０には、複数の駆動電流配線３６（第１の配線）が、複数のソース配線３４と隣接して平行に配設されている。 As shown in FIG. 6, in the display area 150, a plurality of gate wirings 32 and a plurality of source wirings 34 are arranged so as to intersect each other so as to be orthogonal to each other, and are defined by the gate wirings 32 and the source wirings 34. Is provided with a pixel, and a pixel unit drive circuit ELC1 for driving the pixel is provided in the pixel. Further, in the display area 150, a plurality of drive current wirings 36 (first wirings) are arranged adjacent to and parallel to the plurality of source wirings 34.
　画素部駆動回路ＥＬＣ１は、ゲート配線３２とソース配線３４との交差部に設けられたＴＦＴ１０２と、ゲート配線３２と駆動電流配線３６との交差部に設けたれたＴＦＴ１０１とを有している。ＴＦＴ１０２のゲート電極１７はゲート配線３２と電気的に接続され、ＴＦＴ１０２のソース電極３はソース配線３４と電気的に接続されている。ＴＦＴ１０２は、ゲート配線とソース配線の信号に対応して表示画素を選択するための選択ＴＦＴとして機能する。 The pixel unit drive circuit ELC1 has a TFT 102 provided at the intersection of the gate wiring 32 and the source wiring 34, and a TFT 101 provided at the intersection of the gate wiring 32 and the drive current wiring 36. The gate electrode 17 of the TFT 102 is electrically connected to the gate wiring 32, and the source electrode 3 of the TFT 102 is electrically connected to the source wiring 34. The TFT 102 functions as a selection TFT for selecting display pixels corresponding to the signals of the gate wiring and the source wiring.
　ＴＦＴ１０１のゲート電極２は、ＴＦＴ１０２のドレイン電極４と電気的に接続される。また、ＴＦＴ１０１のソース電極１５は駆動電流配線３６と電気的に接続され、ドレイン電極１６はＥＬ素子４４を駆動させるためのアノード電極４１と電気的に接続されている。ＥＬ素子４４のカソード電極４５は接地電位に接続されている。 The gate electrode 2 of the TFT 101 is electrically connected to the drain electrode 4 of the TFT 102. Further, the source electrode 15 of the TFT 101 is electrically connected to the drive current wiring 36, and the drain electrode 16 is electrically connected to the anode electrode 41 for driving the EL element 44. The cathode electrode 45 of the EL element 44 is connected to the ground potential.
　また、ＴＦＴ１０１には、ゲート電極２とドレイン電極１６との間に接続された保持容量ＣｓＡが設けられている。ＴＦＴ１０２のドレイン電極４から出力された選択信号が保持容量ＣｓＡに書き込まれると、書き込まれた電圧によってＴＦＴ１０１が動作して、駆動電流配線３６からの信号電流が、駆動電流としてＴＦＴ１０１からアノード電極４１を通してＥＬ素子４４に供給され、ＥＬ素子４４が発光する。 Further, the TFT 101 is provided with a holding capacity CsA connected between the gate electrode 2 and the drain electrode 16. When the selection signal output from the drain electrode 4 of the TFT 102 is written to the holding capacitance CsA, the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is used as the drive current from the TFT 101 through the anode electrode 41. It is supplied to the EL element 44, and the EL element 44 emits light.
　額縁領域１６０には、ゲート配線３２に信号電圧を与える走査信号駆動回路１７０が、ゲート配線３２の端部に設けられたゲート端子３３に接続され、また、ソース配線３４および駆動電流配線３６に駆動信号を与える表示信号駆動回路１８０が、ソース配線３４の端部および駆動電流配線３６の端部にそれぞれ設けられたソース端子３５（第２のソース端子）およびソース端子３７（第１のソース端子）に接続されて配設されている。また、基板１の四隅には、位置合わせのためのアライメントマークＡＭが設けられている。 In the frame region 160, a scanning signal drive circuit 170 that applies a signal voltage to the gate wiring 32 is connected to a gate terminal 33 provided at the end of the gate wiring 32, and is also driven by the source wiring 34 and the drive current wiring 36. The display signal drive circuit 180 that gives a signal is provided at the end of the source wiring 34 and the end of the drive current wiring 36, respectively, at the source terminal 35 (second source terminal) and the source terminal 37 (first source terminal). It is connected to and arranged in. Further, alignment marks AM for alignment are provided at the four corners of the substrate 1.
　なお、本実施の形態２では、ＴＦＴ基板１１０上の額縁領域１６０に走査信号駆動回路１７０および表示信号駆動回路１８０を配設するようにしたが、これらをＴＦＴ基板１１０上に配設せずに、外部の駆動ＩＣ（Integrated Circuit）を、ＴＡＢ（Tape Automated Bonding）方式またはＣＯＧ（Chip On Glass）方式等でＴＦＴ基板１１０上のゲート端子３３上、ソース端子３５上およびソース端子３７上に実装するようにしてもよい。 In the second embodiment, the scanning signal drive circuit 170 and the display signal drive circuit 180 are arranged in the frame region 160 on the TFT substrate 110, but these are not arranged on the TFT substrate 110. , An external drive IC (Integrated Circuit) is mounted on the gate terminal 33, the source terminal 35, and the source terminal 37 on the TFT substrate 110 by the TAB (Tape Automated Bonding) method, the COG (Chip On Glass) method, or the like. You may do so.
　次に、図７および図８を参照して、本実施の形態２に係るＴＦＴ基板１１０のより詳細な構成について説明する。図７は、ＴＦＴ基板１１０の表示領域１５０（図６）に設けられたＴＦＴ１０１、ＴＦＴ１０２、保持容量ＣｓＡおよび画素領域ＰＸを含む画素の平面構成を示す部分平面図であり、図８は、画素の断面構成を示す部分断面図である。 Next, with reference to FIGS. 7 and 8, a more detailed configuration of the TFT substrate 110 according to the second embodiment will be described. FIG. 7 is a partial plan view showing a planar configuration of pixels including the TFT 101, TFT 102, holding capacity CsA, and pixel region PX provided in the display region 150 (FIG. 6) of the TFT substrate 110, and FIG. 8 is a partial plan view of the pixels. It is a partial cross-sectional view which shows the cross-sectional structure.
　図７におけるＸ１－Ｘ２線は、ＴＦＴ１０１、ＴＦＴ１０２および保持容量ＣｓＡに渡り、Ｙ１－Ｙ２線は、ＴＦＴ１０１のドレイン電極１６から画素領域ＰＸに渡るように設けられており、Ｘ１－Ｘ２線での矢示方向断面図およびＹ１－Ｙ２線での矢示方向断面図を、それぞれ図８の左側および右側に示す。 The X1-X2 line in FIG. 7 is provided so as to extend over the TFT 101, the TFT 102 and the holding capacitance CsA, and the Y1-Y2 line extends from the drain electrode 16 of the TFT 101 to the pixel region PX. The cross-sectional view in the direction shown and the cross-sectional view taken along the line Y1-Y2 are shown on the left side and the right side of FIG. 8, respectively.
　なお、本実施の形態２のＴＦＴ１０１およびＴＦＴ１０２は、実施の形態１のＴＦＴ１０１およびＴＦＴ１０２と基本的に同じ構成であるため、これらと同じ構成要素には同一符号を付し、重複する説明は省略する。 Since the TFT 101 and the TFT 102 of the second embodiment have basically the same configuration as the TFT 101 and the TFT 102 of the first embodiment, the same components are designated by the same reference numerals, and redundant description will be omitted. ..
　ＴＦＴ基板１１０は透明絶縁性の基板１の一方の主面上に各種の要素が配設されている。基板１は、例えばガラス、プラスチックまたは樹脂等の透明かつ絶縁性の材料で構成される。なお、基板１の平面形状は、図６に例示した四角形に限定されるものではない。 The TFT substrate 110 has various elements arranged on one main surface of the transparent insulating substrate 1. The substrate 1 is made of a transparent and insulating material such as glass, plastic or resin. The planar shape of the substrate 1 is not limited to the quadrangle illustrated in FIG.
　図８のＸ１－Ｘ２線に沿った断面図に示すように、基板１上の第１のＴＦＴ部には、第１の導電膜で構成されるゲート電極２（第１のゲート電極）および駆動電流配線３６（第１の配線）が設けられ、これらを覆うように第１の絶縁膜で構成されるゲート絶縁層５（第１のゲート絶縁層）が設けられている。 As shown in the cross-sectional view taken along the line X1-X2 of FIG. 8, the first TFT portion on the substrate 1 includes a gate electrode 2 (first gate electrode) composed of a first conductive film and a drive. A current wiring 36 (first wiring) is provided, and a gate insulating layer 5 (first gate insulating layer) composed of a first insulating film is provided so as to cover the current wiring 36 (first wiring).
　また、第２のＴＦＴ部には、ソース電極３（第２のソース電極）およびドレイン電極４（第２のドレイン電極）が設けられ、これらを覆うように第１の絶縁膜で構成される保護絶縁層６（第２の保護絶縁層）が設けられている。保護絶縁層６には、ソース電極３の表面の一部を露出させる開口部７（第３の開口部）と、ドレイン電極４の表面の一部を露出させる開口部８（第４の開口部）が設けられている。 Further, the second TFT portion is provided with a source electrode 3 (second source electrode) and a drain electrode 4 (second drain electrode), and is protected by a first insulating film so as to cover them. An insulating layer 6 (second protective insulating layer) is provided. The protective insulating layer 6 has an opening 7 (third opening) that exposes a part of the surface of the source electrode 3 and an opening 8 (fourth opening) that exposes a part of the surface of the drain electrode 4. ) Is provided.
　また、図７に示されるように、平面視で、ＴＦＴ１０１のゲート電極２とＴＦＴ１０２のドレイン電極４は、連続した一体パターンで設けられている。駆動電流配線３６は縦方向（Ｙ方向）に延在するように配設され、ソース配線３４が駆動電流配線３６と隣接するように縦方向に平行して延在するように配設されている。ＴＦＴ１０２のソース電極３は、ソース配線３４の一部分である。すなわち、ソース配線３４は、第１の導電膜で構成され、ソース配線３４におけるＴＦＴ１０２側に延在する部分がソース電極３となっている。ソース電極３が設けられた部分は、ソース配線３４の他の部分よりも幅が広くなっている。 Further, as shown in FIG. 7, in a plan view, the gate electrode 2 of the TFT 101 and the drain electrode 4 of the TFT 102 are provided in a continuous integrated pattern. The drive current wiring 36 is arranged so as to extend in the vertical direction (Y direction), and the source wiring 34 is arranged so as to extend in parallel in the vertical direction so as to be adjacent to the drive current wiring 36. .. The source electrode 3 of the TFT 102 is a part of the source wiring 34. That is, the source wiring 34 is composed of the first conductive film, and the portion of the source wiring 34 extending toward the TFT 102 is the source electrode 3. The portion provided with the source electrode 3 is wider than the other portion of the source wiring 34.
　図８のＸ１－Ｘ２線に沿った断面図に示すように、第１のＴＦＴ部のゲート絶縁層５上に、半導体膜で構成される半導体層９（第１の半導体層）が設けられている。また、第２のＴＦＴ部の保護絶縁層６上に、半導体膜で構成される半導体層１０（第２の半導体層）が設けられている。半導体層１０は、開口部７を通して下層のソース電極３に接するとともに、開口部８を通して下層のドレイン電極４に接している。 As shown in the cross-sectional view taken along the line X1-X2 of FIG. 8, a semiconductor layer 9 (first semiconductor layer) composed of a semiconductor film is provided on the gate insulating layer 5 of the first TFT portion. There is. Further, a semiconductor layer 10 (second semiconductor layer) composed of a semiconductor film is provided on the protective insulating layer 6 of the second TFT portion. The semiconductor layer 10 is in contact with the source electrode 3 of the lower layer through the opening 7, and is in contact with the drain electrode 4 of the lower layer through the opening 8.
　また、図７に示されるように、平面視で、ＴＦＴ１０１の半導体層９は、ゲート電極２と重なる領域に島状のパターンで配設されている。また、ＴＦＴ１０２のソース電極３とドレイン電極４とは、互いに対向して分離されて配設されており、半導体層１０は、互いに分離されたソース電極３とドレイン電極４とに跨るように島状のパターンで配設されている。 Further, as shown in FIG. 7, in a plan view, the semiconductor layer 9 of the TFT 101 is arranged in an island-like pattern in a region overlapping the gate electrode 2. Further, the source electrode 3 and the drain electrode 4 of the TFT 102 are separated and arranged so as to face each other, and the semiconductor layer 10 has an island shape so as to straddle the source electrode 3 and the drain electrode 4 separated from each other. It is arranged in the pattern of.
　上述した第１の絶縁膜および半導体膜を覆うように、第２の絶縁膜が設けられ、図８のＸ１－Ｘ２線に沿った断面図に示すように、第１のＴＦＴ部の第２の絶縁膜には、下層の半導体層９の表面の一部が露出するように、それぞれ開口部１３（第１の開口部）および開口部１４（第２の開口部）が設けられている。開口部１３は、半導体層９のソース領域（第１のソース領域）となる表面を露出させるコンタクトホールであり、開口部１４は、半導体層９のドレイン領域（第１のドレイン領域）となる表面を露出させるコンタクトホールである。半導体層９と重なる領域において、第２の絶縁膜の開口部１３と開口部１４との間の領域は、半導体層９をプロセスダメージから保護するための保護絶縁層１１として機能する。また、第２のＴＦＴ部の半導体層１０上の第２の絶縁膜は、ＴＦＴ１０２のゲート絶縁層１２として機能する。 A second insulating film is provided so as to cover the first insulating film and the semiconductor film described above, and as shown in the cross-sectional view taken along the line X1-X2 of FIG. 8, the second TFT portion of the first TFT portion is provided. The insulating film is provided with an opening 13 (first opening) and an opening 14 (second opening), respectively, so that a part of the surface of the lower semiconductor layer 9 is exposed. The opening 13 is a contact hole that exposes a surface serving as a source region (first source region) of the semiconductor layer 9, and the opening 14 is a surface serving as a drain region (first drain region) of the semiconductor layer 9. It is a contact hole that exposes. In the region overlapping the semiconductor layer 9, the region between the opening 13 and the opening 14 of the second insulating film functions as a protective insulating layer 11 for protecting the semiconductor layer 9 from process damage. Further, the second insulating film on the semiconductor layer 10 of the second TFT portion functions as the gate insulating layer 12 of the TFT 102.
　また、第１のＴＦＴ部の保護絶縁層１１を含む第２の絶縁膜上には、開口部１３を通して半導体層９と接するように、第２の導電膜で構成されるソース電極１５（第１のソース電極）が設けられ、さらに開口部１４を通して半導体層９と接するように、第２の導電膜で構成されるドレイン電極１６（第１のドレイン電極）が設けられている。 Further, on the second insulating film including the protective insulating layer 11 of the first TFT portion, the source electrode 15 (first) composed of the second conductive film so as to be in contact with the semiconductor layer 9 through the opening 13. A drain electrode 16 (first drain electrode) composed of a second conductive film is provided so as to come into contact with the semiconductor layer 9 through the opening 14).
　ソース電極１５は、駆動電流配線３６に重なる領域まで延在しており、駆動電流配線３６の表面の一部を露出させるように第１の絶縁膜と第２の絶縁膜を貫通して設けられた開口部３０を通して駆動電流配線３６に接続されている。また、ドレイン電極１６は、ＴＦＴ１０２のドレイン電極４と連続した一体パターンで設けられたＴＦＴ１０１のゲート電極２と重なる領域まで延在するよう配設されている。そして、ＴＦＴ１０２の半導体層１０と重なる領域のゲート絶縁層１２上には、第２の導電膜で構成されるゲート電極１７（第２のゲート電極）が設けられている。 The source electrode 15 extends to a region overlapping the drive current wiring 36, and is provided so as to penetrate the first insulating film and the second insulating film so as to expose a part of the surface of the drive current wiring 36. It is connected to the drive current wiring 36 through the opening 30. Further, the drain electrode 16 is arranged so as to extend to a region overlapping the gate electrode 2 of the TFT 101 provided in an integral pattern continuous with the drain electrode 4 of the TFT 102. A gate electrode 17 (second gate electrode) composed of a second conductive film is provided on the gate insulating layer 12 in a region overlapping the semiconductor layer 10 of the TFT 102.
　また、図７に示されるように、平面視で、ＴＦＴ１０１のドレイン電極１６は、半導体層１０と重ならない領域で、ゲート電極２およびＴＦＴ１０２のドレイン電極４のパターンと重なって、これらよりもＹ方向の幅が広くなるように配設されている。そしてドレイン電極１６とゲート電極２が重なる領域によって保持容量ＣｓＡが形成される。 Further, as shown in FIG. 7, in a plan view, the drain electrode 16 of the TFT 101 overlaps the pattern of the gate electrode 2 and the drain electrode 4 of the TFT 102 in a region that does not overlap with the semiconductor layer 10, and is in the Y direction from these. It is arranged so that the width of the is wide. Then, the holding capacity CsA is formed by the region where the drain electrode 16 and the gate electrode 2 overlap.
　また、図７に示されるように、平面視で、ＴＦＴ１０２のゲート電極１７は、ソース電極３とドレイン電極４とが互いに対向するように分離された領域において、半導体層１０と重なるように配設されている。また、ゲート電極１７は、ソース電極３およびドレイン電極４とは重ならないように配設されており、これらの重なりによる寄生容量が形成されないように構成されている。そして、ゲート電極１７から延在するゲート配線３２が、ソース配線３４および駆動電流配線３６と直交するように横方向（Ｘ方向）に延在して設けられている。 Further, as shown in FIG. 7, in a plan view, the gate electrode 17 of the TFT 102 is arranged so as to overlap the semiconductor layer 10 in a region where the source electrode 3 and the drain electrode 4 are separated so as to face each other. Has been done. Further, the gate electrode 17 is arranged so as not to overlap the source electrode 3 and the drain electrode 4, and is configured so that a parasitic capacitance due to the overlap thereof is not formed. The gate wiring 32 extending from the gate electrode 17 is provided so as to extend in the lateral direction (X direction) so as to be orthogonal to the source wiring 34 and the drive current wiring 36.
　図８のＸ１－Ｘ２線に沿った断面図またはＹ１－Ｙ２線に沿った断面図に示すように、第１のＴＦＴ部のソース電極１５とドレイン電極１６、および第２のＴＦＴ部のゲート電極１７とゲート配線３２を覆うように、基板１全面に第３の絶縁膜で構成される保護絶縁層１８（第３の保護絶縁層）が設けられている。保護絶縁層１８には、第１のＴＦＴ部のドレイン電極１６の表面の一部を露出させるように開口部４０（第５の開口部）が設けられている。そして、保護絶縁層１８上に、開口部４０を通してドレイン電極１６に接続されるとともに画素領域ＰＸまで延在するように、第４の導電膜で構成されるアノード電極４１が設けられている。 As shown in the cross-sectional view taken along the line X1-X2 or the cross-sectional view taken along the line Y1-Y2 in FIG. 8, the source electrode 15 and the drain electrode 16 of the first TFT section, and the gate electrode of the second TFT section. A protective insulating layer 18 (third protective insulating layer) composed of a third insulating film is provided on the entire surface of the substrate 1 so as to cover the 17 and the gate wiring 32. The protective insulating layer 18 is provided with an opening 40 (fifth opening) so as to expose a part of the surface of the drain electrode 16 of the first TFT portion. An anode electrode 41 composed of a fourth conductive film is provided on the protective insulating layer 18 so as to be connected to the drain electrode 16 through the opening 40 and extend to the pixel region PX.
　さらに、アノード電極４１上および保護絶縁層１８上には、第４の絶縁膜で構成されるバンク層４２が設けられている。画素領域ＰＸではアノード電極４１の表面が露出するようにバンク層４２にはバンク開口部４３が設けられ、バンク開口部４３のアノード電極４１上には画素発光体として機能するＥＬ素子４４が設けられている。 Further, a bank layer 42 composed of a fourth insulating film is provided on the anode electrode 41 and the protective insulating layer 18. In the pixel region PX, a bank opening 43 is provided in the bank layer 42 so that the surface of the anode electrode 41 is exposed, and an EL element 44 that functions as a pixel emitter is provided on the anode electrode 41 of the bank opening 43. ing.
　また、図７に示されるように、画素領域ＰＸは、平面視で、ゲート配線３２、ソース配線３４および駆動電流配線３６によって囲まれた領域で規定されている。アノード電極４１は、ドレイン電極１６と重なる領域に設けられた開口部４０と重なる領域から、画素領域ＰＸまで延在するように設けられている。図７では、アノード電極４１はソース配線３４または駆動電流配線３６と重ならないように配設されているが、一部が重なるように配設されていてもよい。また、バンク層４２に設けられるバンク開口部４３は、アノード電極４１と重なる領域でアノード電極４１からはみ出さないように配設されるとともに、隣り合うバンク開口部４３がバンク層４２によって隔離（分離）され、互いに独立した態様で配設されている。そしてＥＬ素子４４が、バンク開口部４３の領域全面にアノード電極４１からはみ出さないように配設されている。 Further, as shown in FIG. 7, the pixel region PX is defined by a region surrounded by the gate wiring 32, the source wiring 34, and the drive current wiring 36 in a plan view. The anode electrode 41 is provided so as to extend from the region overlapping the opening 40 provided in the region overlapping the drain electrode 16 to the pixel region PX. In FIG. 7, the anode electrode 41 is arranged so as not to overlap with the source wiring 34 or the drive current wiring 36, but may be arranged so as to partially overlap with each other. Further, the bank opening 43 provided in the bank layer 42 is arranged so as not to protrude from the anode electrode 41 in a region overlapping the anode electrode 41, and the adjacent bank openings 43 are separated (separated) by the bank layer 42. ), And are arranged in an manner independent of each other. The EL element 44 is arranged on the entire region of the bank opening 43 so as not to protrude from the anode electrode 41.
　実施の形態２において、ＥＬ素子４４は、例えば有機系材料で構成される有機ＥＬ素子が用いられる。有機ＥＬ素子の構成としては、アノード電極４１の直上にホール輸送層、有機ＥＬ層および電子輸送層が順に積層された３層構造とすることができる。さらにその直上に、アノード電極４１の対極となる図示されないカソード電極が設けられる。アノード電極４１とカソード電極との間の電位差によりＥＬ素子４４に電流が供給され、ＥＬ素子４４が発光する。発光した光は、例えばガラスで構成される基板１を通して下方に放射されて画像が表示される。 In the second embodiment, as the EL element 44, for example, an organic EL element composed of an organic material is used. The organic EL element may have a three-layer structure in which a hole transport layer, an organic EL layer, and an electron transport layer are laminated in this order directly above the anode electrode 41. Further directly above it, a cathode electrode (not shown), which is the opposite electrode of the anode electrode 41, is provided. A current is supplied to the EL element 44 due to the potential difference between the anode electrode 41 and the cathode electrode, and the EL element 44 emits light. The emitted light is radiated downward through, for example, a substrate 1 made of glass, and an image is displayed.
　本実施の形態２に係るＴＦＴ基板１１０は以上のように構成されるが、ＥＬ素子４４を含むＴＦＴ基板１１０には、さらにＥＬ素子４４を水分および不純物から遮断するための封止層が設けられ、さらにＴＦＴ基板１１０と対向するように対向基板が設けられ、有機ＥＬ素子を用いた自発光型表示装置用のＴＦＴ基板として好適に用いることができる。 The TFT substrate 110 according to the second embodiment is configured as described above, and the TFT substrate 110 including the EL element 44 is further provided with a sealing layer for blocking the EL element 44 from moisture and impurities. Further, a facing substrate is provided so as to face the TFT substrate 110, and the TFT substrate can be suitably used as a TFT substrate for a self-luminous display device using an organic EL element.
　　＜製造方法＞
　次に、本実施の形態２に係るＴＦＴ基板１１０の製造方法について、図９～図２４を用いて説明する。なお、図９～図２４では、図７を最終工程図とする平面図と、図８を最終工程図とする断面図とを交互に示しており、断面図においては、図８のＸ１－Ｘ２線に沿った断面図およびＹ１－Ｙ２線に沿った断面図を、それぞれ図の左側および右側に示す。 <Manufacturing method>
Next, the method of manufacturing the TFT substrate 110 according to the second embodiment will be described with reference to FIGS. 9 to 24. Note that FIGS. 9 to 24 alternately show a plan view with FIG. 7 as the final process diagram and a cross-sectional view with FIG. 8 as the final process diagram. A cross-sectional view along the line and a cross-sectional view along the Y1-Y2 line are shown on the left and right sides of the figure, respectively.
　　＜１回目の写真製版工程：図９、図１０＞
　まず、基板１を洗浄液または純水を用いて洗浄する。本実施の形態２では、厚さ０．５ｍｍのガラス基板を基板１として用いた。そして、洗浄された基板１の一方の主面上に、第１の導電膜を成膜する。 <First photoengraving process: Fig. 9, Fig. 10>
First, the substrate 1 is cleaned with a cleaning liquid or pure water. In the second embodiment, a glass substrate having a thickness of 0.5 mm was used as the substrate 1. Then, a first conductive film is formed on one main surface of the washed substrate 1.
　第１の導電膜としては、Ａｒガスを用いたスパッタリング法でＭｏ膜を２００ｎｍの厚さに形成した。その後、Ｍｏ膜上にフォトレジスト材を塗布し、１回目の写真製版工程でフォトレジストパターンを形成し、当該フォトレジストパターンをマスクにして、Ｍｏ膜をＰＡＮ薬液を用いたウエットエッチングによりパターニングする。その後、フォトレジストパターンを除去することによって、図９および図１０に示すように、基板１上に、ＴＦＴ１０１のゲート電極２、ＴＦＴ１０２のソース電極３、ドレイン電極４、ソース配線３４および駆動電流配線３６が同時に形成される。 As the first conductive film, a Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the first photoplate-making step, and the Mo film is patterned by wet etching using a PAN chemical solution using the photoresist pattern as a mask. Then, by removing the photoresist pattern, as shown in FIGS. 9 and 10, the gate electrode 2 of the TFT 101, the source electrode 3 of the TFT 102, the drain electrode 4, the source wiring 34, and the drive current wiring 36 are placed on the substrate 1. Are formed at the same time.
　また、図９に示されるように、平面視で、ゲート電極２とドレイン電極４は、連続した一体パターンで形成されている。また、ソース配線３４と駆動電流配線３６は隣接するように縦方向（Ｙ方向）に平行して延在するように形成されている。なお、ソース電極３は、ソース配線３４の一部分であり、ソース配線３４の他の部分よりも幅が広くなっている部分がソース電極３として形成されている。 Further, as shown in FIG. 9, in a plan view, the gate electrode 2 and the drain electrode 4 are formed in a continuous integrated pattern. Further, the source wiring 34 and the drive current wiring 36 are formed so as to extend in parallel in the vertical direction (Y direction) so as to be adjacent to each other. The source electrode 3 is a part of the source wiring 34, and a portion having a width wider than the other parts of the source wiring 34 is formed as the source electrode 3.
　　＜２回目の写真製版工程：図１１、図１２＞
　次に、基板１の主面上の全体に第１の絶縁膜を形成する。本実施の形態２では、第１の絶縁膜として、ＣＶＤ法を用いて厚さ３００ｎｍのＳｉＯ膜を、約３００℃の基板加熱条件下で形成した。なお、第１の絶縁膜は、ＳｉＯ膜に限ることなく、他にも例えばＳｉＮ膜を用いることができる。ＳｉＮ膜もＳｉＯ膜と同様にＣＶＤ法で成膜することができる。また、ＳｉＯ膜とＳｉＮ膜との積層膜としてもよい。 <Second photoengraving process: Fig. 11, Fig. 12>
Next, the first insulating film is formed on the entire main surface of the substrate 1. In the second embodiment, as the first insulating film, a SiO film having a thickness of 300 nm was formed by a CVD method under the substrate heating condition of about 300 ° C. The first insulating film is not limited to the SiO film, and for example, a SiN film can be used. The SiN film can also be formed by the CVD method in the same manner as the SiO film. Further, it may be a laminated film of a SiO film and a SiN film.
　次に、２回目の写真製版工程で第１の絶縁膜であるＳｉＯ膜上にフォトレジストパターンを形成し、これをマスクとしてＳｉＯ膜をエッチングする。このエッチング工程では、ＳＦ６ガスまたはＣＦ４ガスを用いたドライエッチング法を用いることができる。 Next, in the second photoplate making step, a photoresist pattern is formed on the SiO film which is the first insulating film, and the SiO film is etched using this as a mask. In this etching step, a dry etching method using SF 6 gas or CF 4 gas can be used.
　その後、フォトレジストパターンを除去することで、図１１および図１２に示すように、第２のＴＦＴ部において、ソース電極３の表面の一部を露出させる開口部７、およびドレイン電極４の表面の一部を露出させる開口部８が、それぞれ形成される。図１２に示すように、第１のＴＦＴ部の第１の絶縁膜はゲート絶縁層５として機能し、第２のＴＦＴ部の第１の絶縁膜は、後の工程で形成される第２の半導体層形成時に、第２の半導体層をソース電極３およびドレイン電極４から受けるダメージから保護する保護絶縁層６として機能する。 After that, by removing the photoresist pattern, as shown in FIGS. 11 and 12, in the second TFT portion, the opening 7 that exposes a part of the surface of the source electrode 3 and the surface of the drain electrode 4 Each of the openings 8 that exposes a part is formed. As shown in FIG. 12, the first insulating film of the first TFT portion functions as the gate insulating layer 5, and the first insulating film of the second TFT portion is the second insulating film formed in a later step. When the semiconductor layer is formed, it functions as a protective insulating layer 6 that protects the second semiconductor layer from damage received from the source electrode 3 and the drain electrode 4.
　＜３回目の写真製版工程：図１３、図１４＞
　次に、第１の絶縁膜上に半導体膜を形成する。本実施の形態２では、半導体膜として酸化物半導体膜を形成する。具体的にはＩｎ：Ｇａ：Ｚｎ：Ｏの原子組成比が１：１：１：４であるＩｎＧａＺｎＯターゲットを用い、Ａｒガスに分圧比１０％のＯ２ガスを添加した混合ガスを用いたスパッタリング法で酸化物半導体膜であるＩｎＧａＺｎＯ膜を５０ｎｍの厚さで形成した。 <Third photoengraving process: FIGS. 13 and 14>
Next, a semiconductor film is formed on the first insulating film. In the second embodiment, an oxide semiconductor film is formed as the semiconductor film. Specifically, sputtering using an InGaZnO target having an atomic composition ratio of In: Ga: Zn: O of 1: 1: 1: 4 and a mixed gas in which O 2 gas having a partial pressure ratio of 10% is added to Ar gas. By the method, an InGaZnO film, which is an oxide semiconductor film, was formed with a thickness of 50 nm.
　このとき、ＩｎＧａＺｎＯ膜は、アモルファス構造で形成される。アモルファス構造のＩｎＧａＺｎＯ膜は、一般的に結晶化温度が５００℃超であり、常温では膜中の大部分がアモルファス構造のままで安定する。アモルファス構造は、一部が結晶化された微結晶構造および多結晶構造に比べて構造の均一性を高くすることができる。従って、基板が大型化した場合でも基板全体に特性のバラツキが小さい半導体膜を形成することができる利点がある。すなわち、大型の表示装置に用いるＴＦＴ基板を大型の表示装置に用いた場合であっても、ＴＦＴ特性の面内バラツキを小さくすることができるので、表示ムラを防止することができる。 At this time, the InGaZnO film is formed with an amorphous structure. The InGaZnO film having an amorphous structure generally has a crystallization temperature of more than 500 ° C., and at room temperature, most of the film remains stable with an amorphous structure. The amorphous structure can have higher structural uniformity than the partially crystallized microcrystal structure and polycrystalline structure. Therefore, even when the size of the substrate is increased, there is an advantage that a semiconductor film having a small variation in characteristics can be formed on the entire substrate. That is, even when the TFT substrate used for a large display device is used for a large display device, the in-plane variation of the TFT characteristics can be reduced, so that display unevenness can be prevented.
　次に、３回目の写真製版工程でＩｎＧａＺｎＯ膜上にフォトレジストパターンを形成し、これをマスクとしてＩｎＧａＺｎＯ膜をエッチングする。このエッチング工程では、シュウ酸薬液によるウエットエッチングを用いることができる。その後、フォトレジストパターンを除去することで、図１３および図１４に示すように、第１のＴＦＴ部においてゲート絶縁層５上のゲート電極２と重なる領域に半導体層９が島状のパターンで形成される。 Next, a photoresist pattern is formed on the InGaZnO film in the third photoengraving process, and the InGaZnO film is etched using this as a mask. In this etching step, wet etching with an oxalic acid chemical solution can be used. After that, by removing the photoresist pattern, as shown in FIGS. 13 and 14, the semiconductor layer 9 is formed in an island-like pattern in the region overlapping the gate electrode 2 on the gate insulating layer 5 in the first TFT portion. Will be done.
　また、第２のＴＦＴ部において、保護絶縁層６上に半導体層１０が形成される。半導体層１０は、保護絶縁層６の開口部７を通して下層のソース電極３と接するとともに、保護絶縁層６の開口部８を通して下層のドレイン電極４と接するように形成される。図１３に示されるように、平面視で、ソース電極３およびドレイン電極４は、半導体層１０と重なる領域内で互いに分離して離間領域を有するように形成されており、半導体層１０において、この離間領域がＴＦＴ１０２のチャネル領域ＣＬ２（図１４）として規定される。 Further, in the second TFT portion, the semiconductor layer 10 is formed on the protective insulating layer 6. The semiconductor layer 10 is formed so as to be in contact with the source electrode 3 of the lower layer through the opening 7 of the protective insulating layer 6 and to be in contact with the drain electrode 4 of the lower layer through the opening 8 of the protective insulating layer 6. As shown in FIG. 13, in a plan view, the source electrode 3 and the drain electrode 4 are formed so as to be separated from each other in a region overlapping the semiconductor layer 10 and have a separated region, and in the semiconductor layer 10, this is formed. The separation region is defined as the channel region CL2 (FIG. 14) of the TFT 102.
　半導体層１０の材料である酸化物半導体膜をスパッタリング法で形成する場合、下層にソース電極３およびドレイン電極４のような金属膜が露出していると、スパッタリング中に酸化物半導体が金属と反応し、還元（Ｏイオン欠乏）状態の特性が劣化した酸化物半導体膜が形成されてしまう場合がある。しかしながら、本実施の形態２のＴＦＴ１０２では、開口部７および開口部８を除くＴＦＴ１０２の全体が保護絶縁層６で覆われているので、この影響を防止することができる。すなわち、チャネル領域ＣＬ２の保護絶縁層６は、半導体層１０のチャネル保護層６として機能する。 When the oxide semiconductor film, which is the material of the semiconductor layer 10, is formed by the sputtering method, if the metal films such as the source electrode 3 and the drain electrode 4 are exposed in the lower layer, the oxide semiconductor reacts with the metal during sputtering. However, an oxide semiconductor film having deteriorated characteristics in the reduced (O ion deficient) state may be formed. However, in the TFT 102 of the second embodiment, since the entire TFT 102 excluding the opening 7 and the opening 8 is covered with the protective insulating layer 6, this influence can be prevented. That is, the protective insulating layer 6 of the channel region CL2 functions as the channel protective layer 6 of the semiconductor layer 10.
　その後、基板１を大気雰囲気下で４００℃の温度で熱処理する。この熱処理によって半導体層９および半導体層１０の非晶質のＩｎＧａＺｎＯ膜が構造緩和を起こし、半導体特性をさらに安定させることができる。非晶質ＩｎＧａＺｎＯ膜に上記の構造緩和を起こさせるための熱処理の温度は、少なくとも３００℃以上であることが好ましい。一方、５００℃を超えると膜全体で結晶化が始まり半導体特性が大きく変化し、例えばキャリア密度増大により導体化してしまう。従って、ここでは少なくとも基板１を３００℃以上５００℃以下の温度で熱処理することが好ましい。なお、このような熱処理は、製造工程の最後に実施するようにしてもよい。 After that, the substrate 1 is heat-treated at a temperature of 400 ° C. in an air atmosphere. By this heat treatment, the amorphous InGaZnO film of the semiconductor layer 9 and the semiconductor layer 10 causes structural relaxation, and the semiconductor characteristics can be further stabilized. The temperature of the heat treatment for causing the above-mentioned structural relaxation of the amorphous InGaZnO film is preferably at least 300 ° C. or higher. On the other hand, when the temperature exceeds 500 ° C., crystallization starts in the entire film and the semiconductor characteristics change significantly, and for example, it becomes a conductor due to an increase in carrier density. Therefore, here, it is preferable to heat-treat at least the substrate 1 at a temperature of 300 ° C. or higher and 500 ° C. or lower. In addition, such a heat treatment may be carried out at the end of the manufacturing process.
　　＜４回目の写真製版工程：図１５、図１６＞
　次に、基板１の主面上の全体に第２の絶縁膜を形成する。本実施の形態２では、第２の絶縁膜として、ＣＶＤ法で厚さ３００ｎｍのＳｉＯ膜を約２００℃の基板加熱条件下で形成した。なお、第２の絶縁膜は、ＳｉＯ膜に限ることなく、他にも例えばＳｉＮ膜を用いることができる。また、ＳｉＯ膜とＳｉＮ膜との積層膜としてもよい。 <Fourth photoengraving process: FIGS. 15 and 16>
Next, a second insulating film is formed on the entire main surface of the substrate 1. In the second embodiment, as the second insulating film, a SiO film having a thickness of 300 nm was formed by a CVD method under a substrate heating condition of about 200 ° C. The second insulating film is not limited to the SiO film, and for example, a SiN film can be used. Further, it may be a laminated film of a SiO film and a SiN film.
　次に、４回目の写真製版工程で第２の絶縁膜であるＳｉＯ膜上にフォトレジストパターンを形成し、これをマスクとしてＳｉＯ膜をエッチングする。このエッチング工程では、ＳＦ６ガスまたはＣＦ４ガスを用いたドライエッチング法を用いることができる。 Next, in the fourth photoplate making step, a photoresist pattern is formed on the SiO film which is the second insulating film, and the SiO film is etched using this as a mask. In this etching step, a dry etching method using SF 6 gas or CF 4 gas can be used.
　その後、フォトレジストパターンを除去することで、図１５および図１６に示すように、第１のＴＦＴ部の第２の絶縁膜に、半導体層９の表面の一部を露出させる開口部１３および開口部１４が形成される。第１のＴＦＴ部の第２の絶縁膜は、後の工程で形成されるソース電極１５およびドレイン電極１６からの加工プロセスダメージを防止する保護絶縁層１１として機能する。 After that, by removing the photoresist pattern, as shown in FIGS. 15 and 16, the opening 13 and the opening that expose a part of the surface of the semiconductor layer 9 to the second insulating film of the first TFT portion. The portion 14 is formed. The second insulating film of the first TFT portion functions as a protective insulating layer 11 for preventing processing process damage from the source electrode 15 and the drain electrode 16 formed in a later step.
　また、第２のＴＦＴ部の第２の絶縁膜は、ＴＦＴ１０２のゲート絶縁層１２として機能する。さらに、駆動電流配線３６の表面の一部を露出させるように、第１の絶縁膜および第２の絶縁膜を貫通する開口部３０が形成される。 Further, the second insulating film of the second TFT portion functions as the gate insulating layer 12 of the TFT 102. Further, an opening 30 penetrating the first insulating film and the second insulating film is formed so as to expose a part of the surface of the drive current wiring 36.
　　＜５回目の写真製版工程：図１７、図１８＞
　次に、第２の絶縁膜上に第２の導電膜を形成する。本実施の形態２では、第２の導電膜としてＡｒガスを用いたスパッタリング法でＭｏ膜を２００ｎｍの厚さに形成した。その後、Ｍｏ膜上にフォトレジスト材を塗布し、５回目の写真製版工程でフォトレジストパターンを形成し、当該フォトレジストパターンをマスクにして、Ｍｏ膜をＰＡＮ薬液を用いたウエットエッチングによりパターニングする。その後、フォトレジストパターンを除去することによって、図１７および図１８に示すように、ＴＦＴ１０１のソース電極１５およびドレイン電極１６が形成され、同時にＴＦＴ１０２のゲート電極１７が形成される。 <Fifth photoengraving process: Fig. 17, Fig. 18>
Next, a second conductive film is formed on the second insulating film. In the second embodiment, the Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas as the second conductive film. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the fifth photoplate-making step, and the Mo film is patterned by wet etching using a PAN chemical solution using the photoresist pattern as a mask. After that, by removing the photoresist pattern, as shown in FIGS. 17 and 18, the source electrode 15 and the drain electrode 16 of the TFT 101 are formed, and at the same time, the gate electrode 17 of the TFT 102 is formed.
　ＴＦＴ１０１のソース電極１５は、開口部１３を通して半導体層９と接するように形成される。またドレイン電極１６は、開口部１４を通して半導体層９と接するように形成される。ソース電極１５とドレイン電極１６は、半導体層９と重なる領域内で互いに分離して形成されており、半導体層９におけるソース電極１５とドレイン電極１６とで挟まれる離間領域が、ＴＦＴ１０１のチャネル領域ＣＬ１として規定される。 The source electrode 15 of the TFT 101 is formed so as to be in contact with the semiconductor layer 9 through the opening 13. Further, the drain electrode 16 is formed so as to be in contact with the semiconductor layer 9 through the opening 14. The source electrode 15 and the drain electrode 16 are formed separately from each other in a region overlapping the semiconductor layer 9, and the separated region sandwiched between the source electrode 15 and the drain electrode 16 in the semiconductor layer 9 is the channel region CL1 of the TFT 101. Is defined as.
　一般的に酸化物半導体膜は薬液耐性に乏しく、半導体層９の材料であるＩｎＧａＺｎＯ膜は、第２の導電膜のウエットエッチングに用いられるＰＡＮ薬液にも容易に溶けてしまう。しかしながら、ＴＦＴ１０１では、開口部１３および開口部１４を除く基板１の全面が第２の絶縁膜で構成される保護絶縁層１１で覆われているので、特に半導体層９のチャネル領域ＣＬ１上ではチャネル保護層（エッチングストッパ；ＥＳ層）として機能する。従って、プロセスダメージのない信頼性の高いＴＦＴを得ることができる。 Generally, the oxide semiconductor film has poor chemical resistance, and the InGaZnO film, which is the material of the semiconductor layer 9, is easily dissolved in the PAN chemical solution used for wet etching of the second conductive film. However, in the TFT 101, since the entire surface of the substrate 1 excluding the opening 13 and the opening 14 is covered with the protective insulating layer 11 formed of the second insulating film, the channel is particularly on the channel region CL1 of the semiconductor layer 9. It functions as a protective layer (etching stopper; ES layer). Therefore, a highly reliable TFT without process damage can be obtained.
　ソース電極１５は、駆動電流配線３６に重なる領域まで延在しており、開口部３０を通して駆動電流配線３６に接続されている。また、ドレイン電極１６は、ＴＦＴ１０２のドレイン電極４と連続した一体パターンで設けられたＴＦＴ１０１のゲート電極２と重なる領域まで延在するように形成されている。 The source electrode 15 extends to a region overlapping the drive current wiring 36, and is connected to the drive current wiring 36 through the opening 30. Further, the drain electrode 16 is formed so as to extend to a region overlapping the gate electrode 2 of the TFT 101 provided in an integral pattern continuous with the drain electrode 4 of the TFT 102.
　図１７に示されるように、平面視で、ＴＦＴ１０１のドレイン電極１６は、半導体層１０と重ならない領域で、ゲート電極２およびＴＦＴ１０２のドレイン電極４のパターンと重なって、これらよりもＹ方向の幅が広くなるように形成されている。ドレイン電極１６とゲート電極２が重なる領域によって保持容量ＣｓＡが形成される。 As shown in FIG. 17, in a plan view, the drain electrode 16 of the TFT 101 overlaps the pattern of the gate electrode 2 and the drain electrode 4 of the TFT 102 in a region that does not overlap with the semiconductor layer 10, and is wider in the Y direction than these. Is formed to be wide. The holding capacity CsA is formed by the region where the drain electrode 16 and the gate electrode 2 overlap.
　そして、ゲート電極１７から延在するゲート配線３２が、ソース配線３４および駆動電流配線３６と直交するように横方向（Ｘ方向）に延在されて形成されている。 Then, the gate wiring 32 extending from the gate electrode 17 is formed so as to extend in the lateral direction (X direction) so as to be orthogonal to the source wiring 34 and the drive current wiring 36.
　また、図１８に示されるように、第２のＴＦＴ部のゲート電極１７は、ソース電極３とドレイン電極４とが互いに対向して分離された領域において、下層の半導体層１０のチャネル領域ＣＬ２と重なるように形成されている。また、ゲート電極１７は、ソース電極３およびドレイン電極とは重ならないように形成されており、これらの重なりによる寄生容量が形成されないように構成されている。これにより、応答性に優れたＴＦＴを得ることができる。さらに、半導体層１０のチャネル領域ＣＬ２は、保護絶縁層６で保護されているので、ＴＦＴ１０１と同様に、プロセスダメージのない信頼性の高いＴＦＴを得ることができる。 Further, as shown in FIG. 18, the gate electrode 17 of the second TFT portion is separated from the channel region CL2 of the lower semiconductor layer 10 in the region where the source electrode 3 and the drain electrode 4 are separated from each other. It is formed so as to overlap. Further, the gate electrode 17 is formed so as not to overlap the source electrode 3 and the drain electrode, and is configured so that a parasitic capacitance due to the overlap thereof is not formed. Thereby, a TFT having excellent responsiveness can be obtained. Further, since the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained as in the case of the TFT 101.
　　＜６回目の写真製版工程：図１９、図２０＞
　次に、基板１の主面上の全体に第３の絶縁膜を形成する。本実施の形態２では、第３の絶縁膜として、樹脂系の塗布膜を用いる。具体的には感光性を有する透明アクリル樹脂膜を、スピンコート法を用いて塗布形成した。このような透明アクリル樹脂膜を形成することにより、下層の電極パターンの段差および絶縁膜の開口部パターンの段差等に起因する基板表面の凹凸形状をほぼ平坦にすることができる。 <Sixth photoengraving process: Fig. 19, Fig. 20>
Next, a third insulating film is formed on the entire main surface of the substrate 1. In the second embodiment, a resin-based coating film is used as the third insulating film. Specifically, a photosensitive transparent acrylic resin film was applied and formed by using a spin coating method. By forming such a transparent acrylic resin film, the uneven shape of the substrate surface due to the step difference of the electrode pattern of the lower layer and the step difference of the opening pattern of the insulating film can be made substantially flat.
　本実施の形態２では、透明アクリル樹脂膜の膜厚が最も薄くなる部分で厚さが１．５μｍになるように塗布形成した。また、第３の絶縁膜として透明アクリル樹脂膜を塗布形成する前に、例えばＣＶＤ法でＳｉＯ膜またはＳｉＮ膜を形成するようにしてもよい。なお、樹脂系の塗布膜は、アクリル系以外にも、ＳＯＧ（Spin-On Glass）系、エポキシ系、ポリイミド系、あるいはポリオレフィン系の樹脂膜を用いることができる。 In the second embodiment, the transparent acrylic resin film was coated and formed so that the thickness was 1.5 μm at the portion where the film thickness was the thinnest. Further, a SiO film or a SiN film may be formed by, for example, a CVD method before the transparent acrylic resin film is applied and formed as the third insulating film. As the resin-based coating film, an SOG (Spin-On Glass) -based, epoxy-based, polyimide-based, or polyolefin-based resin film can be used in addition to the acrylic-based coating film.
　その後、６回目の写真製版工程で透明アクリル系樹脂を露光し、現像することによって、図１９および図２０に示すように、保持容量ＣｓＡが形成された領域の保護絶縁層１８に、第１のＴＦＴ部のドレイン電極１６の表面の一部が露出されるように開口部４０が形成される。下層にＳｉＯ膜またはＳｉＮ膜が形成されている場合には、開口部４０が形成された保護絶縁層１８（透明アクリル系樹脂）をマスクにして、ＳＦ６ガスまたはＣＦ４ガスを用いたドライエッチング法を用いてＳｉＯ膜またはＳｉＮ膜をエッチングすることにより、ドレイン電極１６の表面の一部を露出させて開口部４０を形成する。 Then, by exposing and developing the transparent acrylic resin in the sixth photoengraving step, as shown in FIGS. 19 and 20, the protective insulating layer 18 in the region where the holding capacity CsA was formed was first covered with the first protective insulating layer 18. The opening 40 is formed so that a part of the surface of the drain electrode 16 of the TFT portion is exposed. When a SiO film or SiN film is formed on the lower layer, dry etching using SF 6 gas or CF 4 gas is performed using the protective insulating layer 18 (transparent acrylic resin) on which the opening 40 is formed as a mask. By etching the SiO film or SiN film using the method, a part of the surface of the drain electrode 16 is exposed to form the opening 40.
　　＜７回目の写真製版工程：図２１、図２２＞
　次に、開口部４０を含む保護絶縁層１８上に、第４の導電膜を形成する。本実施の形態２では、第４の導電膜として、透明性を有するＩＴＯ膜（酸化インジウムＩｎ２Ｏ３と酸化すずＳｎＯ２とを含む酸化物導電膜）を用いる。具体的には、Ｉｎ２Ｏ３とＳｎＯ２との混合比が９０：１０（重量％）のＩＴＯ膜をスパッタリング法で形成する。ＩＴＯ膜は一般的に、常温中では結晶質（多結晶）構造が安定であるが、ここではＡｒガスに水素（Ｈ）を含むガス、例えば、水素（Ｈ２）ガスまたは水蒸気（Ｈ２Ｏ）などを混合したガスを用いてスパッタリングを行い、厚さ１００ｎｍのＩＴＯ膜をアモルファス状態（アモルファスＩＴＯ膜）で形成した。 <7th photoengraving process: Fig. 21, Fig. 22>
Next, a fourth conductive film is formed on the protective insulating layer 18 including the opening 40. In the second embodiment, as the fourth conductive film, a transparent ITO film (an oxide conductive film containing indium oxide In 2 O 3 and tin oxide Sn O 2 ) is used. Specifically, an ITO film having a mixing ratio of In 2 O 3 and Sn O 2 of 90:10 (% by weight) is formed by a sputtering method. The ITO film generally has a stable crystalline (polycrystalline) structure at room temperature, but here, a gas containing hydrogen (H) in Ar gas, for example, hydrogen (H 2 ) gas or water vapor (H 2 O). ) And the like were subjected to sputtering to form an ITO film having a thickness of 100 nm in an amorphous state (amorphous ITO film).
　その後、７回目の写真製版工程でアモルファスＩＴＯ膜上にフォトレジストパターンを形成し、これをマスクとしてアモルファスＩＴＯ膜をエッチングする。このエッチング工程では、シュウ酸薬液によるウエットエッチングを用いることができる。その後、フォトレジストパターンを除去することで、図２１および図２２に示すように、透明性を有するＩＴＯ膜で構成されるアノード電極４１が形成される。アノード電極４１は、保持容量ＣｓＡにおいて、保護絶縁層１８の開口部４０を通して下層のドレイン電極１６に接続されるとともに、画素領域ＰＸまで延在するように形成されている。 After that, a photoresist pattern is formed on the amorphous ITO film in the 7th photoplate making process, and the amorphous ITO film is etched using this as a mask. In this etching step, wet etching with an oxalic acid chemical solution can be used. After that, by removing the photoresist pattern, as shown in FIGS. 21 and 22, the anode electrode 41 made of a transparent ITO film is formed. The anode electrode 41 is formed so as to be connected to the drain electrode 16 of the lower layer through the opening 40 of the protective insulating layer 18 and extend to the pixel region PX in the holding capacity CsA.
　図２１に示されるように、平面視で、画素領域ＰＸは、ゲート配線３２、ソース配線３４および駆動電流配線３６によって囲まれた領域で規定されている。アノード電極４１は、ドレイン電極１６と重なる領域に設けられた開口部４０と重なる領域から、画素領域ＰＸまで延在するように形成される。本実施の形態２では、アノード電極４１はソース配線３４または駆動電流配線３６と重ならないように形成したが、一部が重なるような態様で形成してもよい。本実施の形態２において第４の導電膜として形成したアモルファスＩＴＯ膜は、結晶粒界がないために膜表面の平坦性を極めて高くすることができる。これにより、アノード電極４１から面内均一性の高い電流信号をＥＬ素子４４（図７）に供給することができるので、ＥＬ素子４４の面内全体からムラの少ない均一な発光をさせることができる。 As shown in FIG. 21, in plan view, the pixel area PX is defined by the area surrounded by the gate wiring 32, the source wiring 34, and the drive current wiring 36. The anode electrode 41 is formed so as to extend from a region overlapping the opening 40 provided in the region overlapping the drain electrode 16 to the pixel region PX. In the second embodiment, the anode electrode 41 is formed so as not to overlap with the source wiring 34 or the drive current wiring 36, but may be formed so as to partially overlap. Since the amorphous ITO film formed as the fourth conductive film in the second embodiment has no crystal grain boundaries, the flatness of the film surface can be made extremely high. As a result, a current signal having high in-plane uniformity can be supplied from the anode electrode 41 to the EL element 44 (FIG. 7), so that uniform light emission with little unevenness can be generated from the entire in-plane of the EL element 44. ..
　　＜８回目の写真製版工程：図２３、図２４＞
　次に、基板１の主面上の全体に、バンク層４２となる第４の絶縁膜を形成する。本実施の形態２では、第４の絶縁膜として、樹脂系の塗布膜を用いる。具体的には感光性を有する透明アクリル樹脂膜を、スピンコート法を用いて厚さが１．５μｍとなるように塗布形成した。なお、アクリル系以外にも、ＳＯＧ系、エポキシ系、ポリイミド系、あるいはポリオレフィン系の樹脂膜を用いることができる。特にポリイミド系樹脂膜は吸着水分が少ないため、この後の工程で形成されるＥＬ素子の特性および信頼性に影響を及ぼすことがないために好ましい。 <8th photoengraving process: Fig. 23, Fig. 24>
Next, a fourth insulating film to be the bank layer 42 is formed on the entire main surface of the substrate 1. In the second embodiment, a resin-based coating film is used as the fourth insulating film. Specifically, a photosensitive transparent acrylic resin film was applied and formed so as to have a thickness of 1.5 μm by a spin coating method. In addition to the acrylic type, SOG type, epoxy type, polyimide type, or polyolefin type resin films can be used. In particular, the polyimide resin film is preferable because it has a small amount of adsorbed water and does not affect the characteristics and reliability of the EL element formed in the subsequent steps.
　その後、８回目の写真製版工程で透明アクリル系樹脂を露光し、現像することによって、図２３および図２４に示すように、画素領域ＰＸにアノード電極４１の表面が露出されるバンク開口部４３を有するバンク層４２が形成される。バンク開口部４３は、アノード電極４１上の画素表示領域、すなわち、この後の工程でＥＬ素子４４が形成される領域のみに形成され、互いに隣り合うバンク開口部４３どうしは、バンク層４２によって互いに隔離された態様となる。 Then, by exposing and developing the transparent acrylic resin in the eighth photoengraving step, as shown in FIGS. 23 and 24, the bank opening 43 in which the surface of the anode electrode 41 is exposed in the pixel region PX is formed. The bank layer 42 having the bank layer 42 is formed. The bank openings 43 are formed only in the pixel display region on the anode electrode 41, that is, the region where the EL element 44 is formed in the subsequent step, and the bank openings 43 adjacent to each other are formed by the bank layer 42. It is an isolated aspect.
　次に、最終工程で、バンク開口部４３の領域内に、アノード電極４１と接するようにＥＬ素子４４を形成することで、図７および図８に示す構成を得る。本実施の形態２では、ＥＬ素子４４のＥＬ層として有機系の有機ＥＬ材料を用いる。具体的にはインクジェットによる印刷法を用いてホール輸送層、有機ＥＬ層、電子輸送層をこの順に積層してＥＬ層を形成した。インクジェットによる印刷法によれば、バンク開口部４３の凹領域内のみにＥＬ層を選択的に形成することができるので、写真製版工程を用いることなくＥＬ素子４４を形成することができる。 Next, in the final step, the EL element 44 is formed in the region of the bank opening 43 so as to be in contact with the anode electrode 41, thereby obtaining the configurations shown in FIGS. 7 and 8. In the second embodiment, an organic organic EL material is used as the EL layer of the EL element 44. Specifically, an EL layer was formed by laminating a hole transport layer, an organic EL layer, and an electron transport layer in this order using an inkjet printing method. According to the inkjet printing method, the EL layer can be selectively formed only in the concave region of the bank opening 43, so that the EL element 44 can be formed without using the photoengraving process.
　ホール輸送層としては公知のトリアリールアミン類、芳香族ヒドラゾン類、芳香族置換ピラゾリン類、スチルベン類等の有機系材料から幅広く選択することができ、例えばＮ，Ｎ’－ジフェニル－Ｎ，Ｎ－ビス（３－メチルフェニル）－１，１‘－ジフェニル－４，４’－ジアミン等のトリフェニルアミン系（ＴＰＤ）等を用いて１ｎｍ～２００ｎｍの任意の厚さで形成する。 The whole transport layer can be widely selected from known organic materials such as triarylamines, aromatic hydrazones, aromatic-substituted pyrazolines, and stillbens, and can be selected from, for example, N, N'-diphenyl-N, N-. It is formed to an arbitrary thickness of 1 nm to 200 nm using a triphenylamine system (TPD) such as bis (3-methylphenyl) -1,1'-diphenyl-4,4'-diamine.
　有機ＥＬ層としては公知のジシアノメチレンピラン誘導体（Ｒ色発光）、クマリン系（Ｇ色発光）、キナクリドン系（Ｇ色発光）、テトラフェニルブタジエン系（Ｂ色発光）、ジスチリルベンゼン系（Ｂ色発光）等の材料が１ｎｍ～２００ｎｍの任意の厚さで形成される。電子輸送層としては公知のオキサジアゾール誘導体、トリアゾール誘導体、クマリン誘導体等から選ばれる材料を用いて０．１ｎｍ～２００ｎｍの任意の厚さで形成する。 Known organic EL layers include dicyanomethylenepyrane derivative (R color emission), coumarin type (G color emission), quinacridone type (G color emission), tetraphenylbutadiene type (B color emission), and distyrylbenzene type (B color emission). A material such as (emission) is formed with an arbitrary thickness of 1 nm to 200 nm. The electron transport layer is formed with an arbitrary thickness of 0.1 nm to 200 nm using a material selected from known oxadiazole derivatives, triazole derivatives, coumarin derivatives and the like.
　ＥＬ層は、印刷法の他にも蒸着法を用いて形成することができる。蒸着法の場合は、基板１の表面に、例えばバンク開口部４３と同じ開口パターンを有する金属マスクを付けたマスク蒸着法を用いることによって、写真製版工程を用いることなくＥＬ素子４４を形成することができる。 The EL layer can be formed by using a vapor deposition method in addition to the printing method. In the case of the vapor deposition method, the EL element 44 is formed without using the photoengraving process by using a mask vapor deposition method in which, for example, a metal mask having the same opening pattern as the bank opening 43 is attached to the surface of the substrate 1. Can be done.
　以上説明した工程を経て本実施の形態２に係るＴＦＴ基板１１０が完成される。図２５に示すように、完成されたＴＦＴ基板１１０上には、アノード電極４１の対向電極となるカソード電極４５が形成される。さらに必要に応じてさらにＥＬ素子４４を含むＴＦＴ基板１１０を水分および不純物から遮断するための封止層４６が形成され、さらにＴＦＴ基板１１０と対向するように対向基板４７が貼り合わされ、有機ＥＬ素子を用いた有機ＥＬディスプレイを備えた自発光型表示装置３００が完成する。 The TFT substrate 110 according to the second embodiment is completed through the steps described above. As shown in FIG. 25, a cathode electrode 45, which is a counter electrode of the anode electrode 41, is formed on the completed TFT substrate 110. Further, if necessary, a sealing layer 46 for further blocking the TFT substrate 110 including the EL element 44 from moisture and impurities is formed, and the opposing substrate 47 is further bonded so as to face the TFT substrate 110, so that the organic EL element is formed. A self-luminous display device 300 equipped with an organic EL display using the above is completed.
　自発光型表示装置３００は、表示欠陥が少なく、高開口率で明るい表示品質の表示装置を低コストで実現することができる。 The self-luminous display device 300 can realize a display device with a high aperture ratio and bright display quality at low cost with few display defects.
　なお、本実施の形態２に係るＴＦＴ基板１１０を備える自発光型表示装置３００は、ＥＬ素子の発光光ＥＬＬをＴＦＴ基板１１０を通して下方（対向基板４７とは反対側）に発光させて表示を行うボトムエミッション型の自発光型表示装置となる。ただし、ボトムエミッション型に限らず、ＥＬ素子の発光光ＥＬＬをＴＦＴ基板１１０の上方（対向基板４７側）に発光させて表示を行うトップエミッション型の自発光型表示装置とすることも可能である。この場合は、上述した７回目の写真製版工程において、アノード電極４１の材料となる第４の導電膜を、透明性を有するＩＴＯ膜の代わりに、高い反射率を有する銀（Ａｇ）系またはＡｌ系の金属膜で形成する。なお、金属膜上にＩＴＯ膜を形成するようにしてもよい。これにより、有機ＥＬ素子からの発光光ＥＬＬをアノード電極４１で反射させて上方に発光させることができるので、トップエミッション型の自発光型表示装置を得ることができる。 The self-luminous display device 300 including the TFT substrate 110 according to the second embodiment emits the emitted light ELL of the EL element downward (opposite to the opposing substrate 47) through the TFT substrate 110 for display. It will be a bottom emission type self-luminous display device. However, it is not limited to the bottom emission type, and it is also possible to use a top emission type self-luminous display device that emits light from the emission light ELL of the EL element above the TFT substrate 110 (opposite substrate 47 side) for display. .. In this case, in the seventh photoplate-making step described above, the fourth conductive film, which is the material of the anode electrode 41, is made of silver (Ag) -based or Al having high reflectance instead of the transparent ITO film. It is formed of a system metal film. The ITO film may be formed on the metal film. As a result, the emitted light ELL from the organic EL element can be reflected by the anode electrode 41 to emit light upward, so that a top-emission type self-luminous display device can be obtained.
　本実施の形態２に係るＴＦＴ基板１１０において、ＴＦＴ１０２は、ゲート配線３２およびソース配線３４と電気的に接続されており、ゲート配線３２とソース配線３４の信号に応じて表示画素を選択するための選択ＴＦＴとして機能する。 In the TFT substrate 110 according to the second embodiment, the TFT 102 is electrically connected to the gate wiring 32 and the source wiring 34, and is used to select display pixels according to the signals of the gate wiring 32 and the source wiring 34. Functions as a selective TFT.
　ＴＦＴ１０２のゲート電極１７と、ソース電極３およびドレイン電極４とは、互いに寄生容量が形成されないように構成されているので、応答性に優れたＴＦＴを得ることができる。 Since the gate electrode 17 of the TFT 102, the source electrode 3 and the drain electrode 4 are configured so that parasitic capacitances are not formed on each other, a TFT having excellent responsiveness can be obtained.
　さらに半導体層１０のチャネル領域ＣＬ２は、保護絶縁層６で保護されているので、プロセスダメージのない信頼性の高いＴＦＴを得ることができる。従って、選択ＴＦＴとして高い性能を発揮させることができる。 Further, since the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained. Therefore, high performance can be exhibited as a selective TFT.
　一方、ＴＦＴ１０１は、ＴＦＴ１０２のドレイン電極４、駆動電流配線３６およびＥＬ素子４４と電気的に接続されており、ＥＬ素子４４の画素駆動ＴＦＴとして機能する。ＴＦＴ１０２のドレイン電極４から出力された選択信号が保持容量ＣｓＡに書き込まれると、書き込まれた電圧によってＴＦＴ１０１が動作して、駆動電流配線３６からの信号電流が、駆動電流としてＥＬ素子４４に供給され、ＥＬ素子４４が発光する。 On the other hand, the TFT 101 is electrically connected to the drain electrode 4, the drive current wiring 36, and the EL element 44 of the TFT 102, and functions as a pixel drive TFT of the EL element 44. When the selection signal output from the drain electrode 4 of the TFT 102 is written to the holding capacitance CsA, the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is supplied to the EL element 44 as a drive current. , EL element 44 emits light.
　ＴＦＴ１０１のチャネル領域ＣＬ１は、保護絶縁層１１で保護されているので、信頼性が高く、ＥＬ素子４４に安定的に信号電流を供給することができるので、ＥＬ素子４４を安定的に発光させ、高品質の画像表示をすることができる。 Since the channel region CL1 of the TFT 101 is protected by the protective insulating layer 11, the reliability is high and the signal current can be stably supplied to the EL element 44, so that the EL element 44 is made to emit light stably. High quality image display is possible.
　また、本実施の形態２に係るＴＦＴ基板１１０によれば、ＴＦＴ１０２のドレイン電極４とＴＦＴ１０１のゲート電極２とを同じ第１の導電膜の連続パターンで形成して一体としているので、例えば、両者を別体で形成し、コンタクトホールを介して電気的に接続した構成に比べると、ＴＦＴ１０２からＴＦＴ１０１への信号の伝達不良による表示欠陥の発生率を低く抑えることができる。 Further, according to the TFT substrate 110 according to the second embodiment, the drain electrode 4 of the TFT 102 and the gate electrode 2 of the TFT 101 are formed in the same continuous pattern of the first conductive film and integrated. Is formed as a separate body and electrically connected via a contact hole, and the occurrence rate of display defects due to poor signal transmission from the TFT 102 to the TFT 101 can be suppressed to a low level.
　さらに連続して一体化されたゲート電極２およびドレイン電極４を保持容量ＣｓＡの容量電極として用いることができるため、米国特許第９７２１９７３号公報のＦｉｇ．７のような電荷蓄積部にコンタクトホールが形成されている構成と比べると、はるかに面積効率よく保持容量ＣｓＡを形成することができるので、ＴＦＴ回路の形成領域を小さくすることができ、画素領域ＰＸの開口率を向上させることができる。これにより、基板１を通してＥＬ素子４４を下方に発光させて表示を行うボトムエミッション型の自発光型表示装置の場合でも、明るく高品質の画像表示をすることができる。 Further, since the continuously integrated gate electrode 2 and drain electrode 4 can be used as a capacitance electrode having a holding capacitance of CsA, Fig. 9721973 of US Pat. No. Compared with the configuration in which the contact hole is formed in the charge storage portion such as No. 7, the holding capacity CsA can be formed much more efficiently in the area, so that the formation region of the TFT circuit can be reduced and the pixel region can be reduced. The aperture ratio of the PX can be improved. As a result, even in the case of a bottom-emission type self-luminous display device in which the EL element 44 emits light downward through the substrate 1 for display, bright and high-quality image display can be performed.
　＜実施の形態３＞
　以上説明した実施の形態２では、ＴＦＴ基板上に配設されるアノード電極上に、直接に有機ＥＬ層を作り込む自発光型表示装置用のＴＦＴ基板の構成例を示したが、実施の形態３では、ＴＦＴ基板上にＬＥＤ素子（ＬＥＤチップ）を実装して、画像表示を行う方式の自発光型表示装置（ＬＥＤディスプレイ）用のＴＦＴ基板の構成例を示す。 <Embodiment 3>
In the second embodiment described above, a configuration example of a TFT substrate for a self-luminous display device in which an organic EL layer is directly formed on an anode electrode arranged on the TFT substrate has been shown. Section 3 shows a configuration example of a TFT substrate for a self-luminous display device (LED display) in which an LED element (LED chip) is mounted on the TFT substrate to display an image.
　以下、図２６～図２８を用いて、本実施の形態３に係るＴＦＴ基板１２０の構成について説明する。なお、実施の形態１および実施の形態２と同じ構成要素には同一符号を付け、重複する説明は省略する。 Hereinafter, the configuration of the TFT substrate 120 according to the third embodiment will be described with reference to FIGS. 26 to 28. The same components as those in the first and second embodiments are designated by the same reference numerals, and duplicate description will be omitted.
　図２６は、本実施の形態３に係るＴＦＴ基板１２０の画素の画素部駆動回路ＬＥＤＣ１の構成を示す図である。図２７は、ＴＦＴ基板１２０に設けられたＴＦＴ１０１、ＴＦＴ１０２、保持容量ＣｓＡおよび画素領域ＰＸを含む画素の平面構成を示す部分平面図であり、図２８は、画素の断面構成を示す部分断面図である。 FIG. 26 is a diagram showing the configuration of the pixel portion drive circuit LEDC1 of the pixels of the TFT substrate 120 according to the third embodiment. FIG. 27 is a partial plan view showing the planar configuration of the pixels including the TFT 101, TFT 102, the holding capacity CsA, and the pixel region PX provided on the TFT substrate 120, and FIG. 28 is a partial cross-sectional view showing the cross-sectional configuration of the pixels. be.
　図２７におけるＸ１－Ｘ２線は、ＴＦＴ１０１、ＴＦＴ１０２、保持容量ＣｓＡおよびＬＥＤ素子実装部を含む画素領域ＰＸに渡り、Ｙ１－Ｙ２線は、ＴＦＴ１０１のソース電極１５から駆動電流配線部に渡るように設けられており、Ｘ１－Ｘ２線での矢示方向断面図およびＹ１－Ｙ２線での矢示方向断面図を、それぞれ図２８の左側および右側に示す。 The X1-X2 wire in FIG. 27 extends over the pixel region PX including the TFT 101, the TFT 102, the holding capacity CsA, and the LED element mounting portion, and the Y1-Y2 wire is provided so as to extend from the source electrode 15 of the TFT 101 to the drive current wiring portion. The cross-sectional view taken along the line X1-X2 and the cross-sectional view taken along the line Y1-Y2 are shown on the left and right sides of FIG. 28, respectively.
　本実施の形態３では、ＴＦＴ基板１２０の個々の画素にＬＥＤ素子を実装して自発光型表示装置を構成する。従って、図６に示した実施の形態２の画素部駆動回路ＥＬＣ１とは異なり、図２６に示すように、ＴＦＴ基板１２０上にはアノード電極６１（第１の電極）とカソード電極６３（第２の電極）とが設けられ、ＬＥＤ素子２００（発光ダイオード素子）が、アノード電極６１およびカソード電極６３に接続されて配設されている。 In the third embodiment, an LED element is mounted on each pixel of the TFT substrate 120 to form a self-luminous display device. Therefore, unlike the pixel unit drive circuit ELC1 of the second embodiment shown in FIG. 6, as shown in FIG. 26, the anode electrode 61 (first electrode) and the cathode electrode 63 (second electrode) are on the TFT substrate 120. The electrode) is provided, and the LED element 200 (light emitting diode element) is arranged so as to be connected to the anode electrode 61 and the cathode electrode 63.
　また、図２６および図２７に示されるように、ＴＦＴ基板１２０は、基板上に複数のゲート配線３２と、複数のソース配線３４とが互いに直交するように交差して配設され、ゲート配線３２とソース配線３４との交差部にはＴＦＴ１０２が設けられている。ＴＦＴ１０２のゲート電極１７はゲート配線３２と電気的に接続され、ＴＦＴ１０２のソース電極３はソース配線３４と電気的に接続されている。ＴＦＴ１０２は、ゲート配線３２とソース配線３４の信号に対応して表示画素を選択するための選択ＴＦＴとして機能する。 Further, as shown in FIGS. 26 and 27, the TFT substrate 120 is arranged on the substrate so that a plurality of gate wirings 32 and a plurality of source wirings 34 intersect each other so as to be orthogonal to each other, and the gate wirings 32 are arranged. A TFT 102 is provided at the intersection of the source wiring 34 and the source wiring 34. The gate electrode 17 of the TFT 102 is electrically connected to the gate wiring 32, and the source electrode 3 of the TFT 102 is electrically connected to the source wiring 34. The TFT 102 functions as a selection TFT for selecting display pixels corresponding to the signals of the gate wiring 32 and the source wiring 34.
　さらに、複数の駆動電流配線３６が、複数のソース配線３４と隣接して平行に配設され、ゲート配線３２と駆動電流配線３６との交差部にはＴＦＴ１０１が設けられている。ＴＦＴ１０１のゲート電極２はＴＦＴ１０２のドレイン電極４と電気的に接続されている。ＴＦＴ１０１のソース電極１５は、駆動電流配線３６と電気的に接続され、ドレイン電極１６はＬＥＤ素子２００を駆動させるためのアノード電極６１と電気的に接続される。また、複数のカソード電極配線６２（第２の配線）が、複数のゲート配線３２と隣接して平行に配設され、カソード電極配線６２と電気的に接続されたカソード電極６３がＬＥＤ素子２００に接続されている。 Further, a plurality of drive current wirings 36 are arranged in parallel adjacent to the plurality of source wirings 34, and a TFT 101 is provided at the intersection of the gate wiring 32 and the drive current wiring 36. The gate electrode 2 of the TFT 101 is electrically connected to the drain electrode 4 of the TFT 102. The source electrode 15 of the TFT 101 is electrically connected to the drive current wiring 36, and the drain electrode 16 is electrically connected to the anode electrode 61 for driving the LED element 200. Further, a plurality of cathode electrode wirings 62 (second wirings) are arranged adjacent to and parallel to the plurality of gate wirings 32, and the cathode electrodes 63 electrically connected to the cathode electrode wirings 62 are connected to the LED element 200. It is connected.
　さらにＴＦＴ１０１には、ゲート電極２とドレイン電極１６との間に接続された保持容量ＣｓＡが設けられている。ＴＦＴ１０２のドレイン電極４から出力された選択信号が保持容量ＣｓＡに書き込まれると、書き込まれた電圧によってＴＦＴ１０１が動作して、駆動電流配線３６からの信号電流が、アノード電極６１とカソード電極６３との電位差によってＬＥＤ素子２００に供給され、ＬＥＤ素子２００が発光する。 Further, the TFT 101 is provided with a holding capacity CsA connected between the gate electrode 2 and the drain electrode 16. When the selection signal output from the drain electrode 4 of the TFT 102 is written to the holding capacitance CsA, the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is transferred to the anode electrode 61 and the cathode electrode 63. It is supplied to the LED element 200 by the potential difference, and the LED element 200 emits light.
　図２８のＸ１－Ｘ２線に沿った断面図およびＹ１－Ｙ２線に沿った断面図に示すように、基板１上のＴＦＴ１０１には、第１の導電膜で構成されるゲート電極２および駆動電流配線３６が設けられ、これらを覆うように第１の絶縁膜で構成されるゲート絶縁層５が設けられている。またＴＦＴ１０２には、ソース電極３およびドレイン電極４が設けられ、これらを覆うように第１の絶縁膜で構成される保護絶縁層６が設けられている。保護絶縁層６には、ソース電極３の表面の一部を露出させる開口部７と、ドレイン電極４の表面の一部を露出させる開口部８が設けられている。 As shown in the cross-sectional view taken along the line X1-X2 and the cross-sectional view taken along the line Y1-Y2 in FIG. 28, the TFT 101 on the substrate 1 has a gate electrode 2 composed of a first conductive film and a driving current. Wiring 36 is provided, and a gate insulating layer 5 composed of a first insulating film is provided so as to cover the wiring 36. Further, the TFT 102 is provided with a source electrode 3 and a drain electrode 4, and is provided with a protective insulating layer 6 formed of a first insulating film so as to cover them. The protective insulating layer 6 is provided with an opening 7 for exposing a part of the surface of the source electrode 3 and an opening 8 for exposing a part of the surface of the drain electrode 4.
　図２７に示されるように、平面視で、ＴＦＴ１０１のゲート電極２とＴＦＴ１０２のドレイン電極４は、連続した一体パターンとして設けられている。駆動電流配線３６は縦方向（Ｙ方向）に延在するように配設され、ソース配線３４が駆動電流配線３６と隣接するように縦方向（Ｙ方向）に平行して延在するように配設されている。ＴＦＴ１０２のソース電極３は、ソース配線３４の一部分である。すなわち、ソース配線３４は、第１の導電膜で構成され、ソース配線３４におけるＴＦＴ１０２側に延在する部分がソース電極３となっている。ソース電極３が設けられた部分は、ソース配線３４の他の部分よりも幅が広くなっている。 As shown in FIG. 27, in a plan view, the gate electrode 2 of the TFT 101 and the drain electrode 4 of the TFT 102 are provided as a continuous integrated pattern. The drive current wiring 36 is arranged so as to extend in the vertical direction (Y direction), and the source wiring 34 is arranged so as to extend parallel to the vertical direction (Y direction) so as to be adjacent to the drive current wiring 36. It is installed. The source electrode 3 of the TFT 102 is a part of the source wiring 34. That is, the source wiring 34 is composed of the first conductive film, and the portion of the source wiring 34 extending toward the TFT 102 is the source electrode 3. The portion provided with the source electrode 3 is wider than the other portion of the source wiring 34.
　また、図２８のＸ１－Ｘ２線に沿った断面図およびＹ１－Ｙ２線に沿った断面図に示すように、ＴＦＴ１０１のゲート絶縁層５上に、半導体膜で構成される半導体層９が設けられている。またＴＦＴ１０２の保護絶縁層６上に、半導体膜で構成される半導体層１０が設けられている。半導体層１０は、開口部７を通して下層のソース電極３と接するとともに、開口部８を通して下層のドレイン電極４と接している。 Further, as shown in the cross-sectional view taken along the line X1-X2 and the cross-sectional view taken along the line Y1-Y2 in FIG. 28, a semiconductor layer 9 composed of a semiconductor film is provided on the gate insulating layer 5 of the TFT 101. ing. Further, a semiconductor layer 10 made of a semiconductor film is provided on the protective insulating layer 6 of the TFT 102. The semiconductor layer 10 is in contact with the source electrode 3 of the lower layer through the opening 7, and is in contact with the drain electrode 4 of the lower layer through the opening 8.
　図２７に示されるように、平面視で、ＴＦＴ１０１の半導体層９は、ゲート電極２と重なる領域に島状のパターンで配設されている。また、のＴＦＴ１０２のソース電極３とドレイン電極４とは、互いに対向して分離されて配設されており、半導体層１０は、互いに分離されたソース電極３とドレイン電極４とに跨るように島状のパターンで配設されている。 As shown in FIG. 27, in a plan view, the semiconductor layer 9 of the TFT 101 is arranged in an island-like pattern in a region overlapping the gate electrode 2. Further, the source electrode 3 and the drain electrode 4 of the TFT 102 of the TFT 102 are separated and arranged so as to face each other, and the semiconductor layer 10 is an island so as to straddle the source electrode 3 and the drain electrode 4 separated from each other. It is arranged in a similar pattern.
　上述した第１の絶縁膜および半導体膜を覆うように、第２の絶縁膜が設けられ、図２８のＸ１－Ｘ２線に沿った断面図およびＹ１－Ｙ２線に沿った断面図に示すように、ＴＦＴ１０１の第２の絶縁膜には、下層の半導体層９の表面の一部が露出するように、それぞれ開口部１３および開口部１４が設けられている。 A second insulating film is provided so as to cover the first insulating film and the semiconductor film described above, and as shown in the cross-sectional view taken along the line X1-X2 and the cross-sectional view taken along the line Y1-Y2 in FIG. 28. The second insulating film of the TFT 101 is provided with an opening 13 and an opening 14, respectively, so that a part of the surface of the lower semiconductor layer 9 is exposed.
　半導体層９と重なる領域において、第２の絶縁膜の開口部１３と開口部１４との間の領域は、半導体層９をプロセスダメージから保護するための保護絶縁層１１として機能する。また、ＴＦＴ１０２の半導体層１０上の第２の絶縁膜は、ＴＦＴ１０２のゲート絶縁層１２として機能する。 In the region overlapping the semiconductor layer 9, the region between the opening 13 and the opening 14 of the second insulating film functions as a protective insulating layer 11 for protecting the semiconductor layer 9 from process damage. Further, the second insulating film on the semiconductor layer 10 of the TFT 102 functions as the gate insulating layer 12 of the TFT 102.
　また、ＴＦＴ１０１の保護絶縁層１１を含む第２の絶縁膜上には、開口部１３を通して半導体層９と接するように、第２の導電膜で構成されるソース電極１５が設けられ、さらに開口部１４を通して半導体層９と接するように、第２の導電膜で構成されるドレイン電極１６が設けられている。また、画素領域ＰＸの第２の絶縁膜上には、第２の導電膜で構成されるカソード電極配線６２が設けられている。 Further, on the second insulating film including the protective insulating layer 11 of the TFT 101, a source electrode 15 composed of a second conductive film is provided so as to be in contact with the semiconductor layer 9 through the opening 13, and the opening is further provided. A drain electrode 16 composed of a second conductive film is provided so as to come into contact with the semiconductor layer 9 through 14. Further, a cathode electrode wiring 62 composed of a second conductive film is provided on the second insulating film of the pixel region PX.
　ソース電極１５は、駆動電流配線３６に重なる領域まで延在しており、駆動電流配線３６の表面の一部を露出させるように第１の絶縁膜と第２の絶縁膜を貫通するように設けられた開口部３０を通して駆動電流配線３６に接続されている。また、ドレイン電極１６は、ＴＦＴ１０２部のドレイン電極４と連続した一体パターンで設けられたＴＦＴ１０１のゲート電極２と重なる領域まで延在するように配設されている。そして、ＴＦＴ１０２の半導体層１０と重なる領域のゲート絶縁層１２上には、第２の導電膜で構成されるゲート電極１７が設けられている。 The source electrode 15 extends to a region overlapping the drive current wiring 36, and is provided so as to penetrate the first insulating film and the second insulating film so as to expose a part of the surface of the drive current wiring 36. It is connected to the drive current wiring 36 through the opening 30. Further, the drain electrode 16 is arranged so as to extend to a region overlapping the gate electrode 2 of the TFT 101 provided in an integral pattern continuous with the drain electrode 4 of the TFT 102 portion. A gate electrode 17 composed of a second conductive film is provided on the gate insulating layer 12 in a region overlapping the semiconductor layer 10 of the TFT 102.
　図２７に示されるように、平面視で、ＴＦＴ１０１のドレイン電極１６は、半導体層９と重なる領域からはみ出した領域で、ゲート電極２およびＴＦＴ１０２のドレイン電極４のパターンと広く重なるような形状で配設されている。そしてドレイン電極１６とゲート電極２が重なる領域によって保持容量ＣｓＡが形成される。 As shown in FIG. 27, in a plan view, the drain electrode 16 of the TFT 101 is arranged so as to be a region protruding from the region overlapping the semiconductor layer 9 and widely overlapping the pattern of the gate electrode 2 and the drain electrode 4 of the TFT 102. It is installed. Then, the holding capacity CsA is formed by the region where the drain electrode 16 and the gate electrode 2 overlap.
　また、図２７に示されるように、平面視で、ＴＦＴ１０２のゲート電極１７は、ソース電極３とドレイン電極４とが互いに対向して分離された領域において、半導体層１０と重なるように配設されている。また、ゲート電極１７は、ソース電極３およびドレイン電極４とは重ならないように配設されており、これらの重なりによる寄生容量が形成されないように構成されている。そして、ゲート電極１７から延在するゲート配線３２が、ソース配線３４および駆動電流配線３６と直交するように横方向（Ｘ方向）に延在するように設けられている。また、カソード電極配線６２は、ＴＦＴ１０１およびＴＦＴ１０２とは反対側の画素領域ＰＸに、ゲート配線３２と隣接するように横方向に平行して延在するように配設されている。 Further, as shown in FIG. 27, in a plan view, the gate electrode 17 of the TFT 102 is arranged so as to overlap the semiconductor layer 10 in a region where the source electrode 3 and the drain electrode 4 are separated from each other so as to face each other. ing. Further, the gate electrode 17 is arranged so as not to overlap the source electrode 3 and the drain electrode 4, and is configured so that a parasitic capacitance due to the overlap thereof is not formed. The gate wiring 32 extending from the gate electrode 17 is provided so as to extend in the lateral direction (X direction) so as to be orthogonal to the source wiring 34 and the drive current wiring 36. Further, the cathode electrode wiring 62 is arranged so as to extend in parallel in the lateral direction so as to be adjacent to the gate wiring 32 in the pixel region PX on the side opposite to the TFT 101 and the TFT 102.
　また、図２８のＸ１－Ｘ２線に沿った断面図およびＹ１－Ｙ２線に沿った断面図に示すように、ＴＦＴ１０１のソース電極１５とドレイン電極１６、およびＴＦＴ１０２のゲート電極１７とゲート配線３２を覆うように、基板１全面に第３の絶縁膜で構成される保護絶縁層１８が設けられている。保護絶縁層１８には、ＦＴ１０１部のドレイン電極１６の表面の一部を露出させるように開口部４８（第５の開口部）が設けられ、カソード電極配線６２の表面の一部を露出させるように開口部４９（第６の開口部）が設けられている。 Further, as shown in the cross-sectional view taken along the line X1-X2 and the cross-sectional view taken along the line Y1-Y2 in FIG. 28, the source electrode 15 and the drain electrode 16 of the TFT 101, and the gate electrode 17 and the gate wiring 32 of the TFT 102 are provided. A protective insulating layer 18 composed of a third insulating film is provided on the entire surface of the substrate 1 so as to cover it. The protective insulating layer 18 is provided with an opening 48 (fifth opening) so as to expose a part of the surface of the drain electrode 16 of the FT101 portion so as to expose a part of the surface of the cathode electrode wiring 62. Is provided with an opening 49 (sixth opening).
　そして、画素領域ＰＸの保護絶縁層１８上に、開口部４８を通してドレイン電極１６と接続されるように、第５の導電膜で構成されるアノード電極６１（第１の電極）が配設される。また、開口部４９を通してカソード電極配線６２と接続されるように、第５の導電膜で構成されるカソード電極６３（第２の電極）が配設されている。 Then, an anode electrode 61 (first electrode) composed of a fifth conductive film is arranged on the protective insulating layer 18 of the pixel region PX so as to be connected to the drain electrode 16 through the opening 48. .. Further, a cathode electrode 63 (second electrode) composed of a fifth conductive film is arranged so as to be connected to the cathode electrode wiring 62 through the opening 49.
　さらに、アノード電極６１上およびカソード電極６３上を含む保護絶縁層１８上に、第５の絶縁膜で構成される保護絶縁層５０が設けられている。画素領域ＰＸの保護絶縁層５０には、下層のアノード電極６１の表面が露出されるようにアノード電極開口部５１、および下層のカソード電極６３の表面が露出されるようにカソード電極開口部５２が設けられている。なお、保護絶縁層５０は設けなくてもよい。 Further, a protective insulating layer 50 composed of a fifth insulating film is provided on the protective insulating layer 18 including the anode electrode 61 and the cathode electrode 63. In the protective insulating layer 50 of the pixel region PX, an anode electrode opening 51 is provided so that the surface of the lower anode electrode 61 is exposed, and a cathode electrode opening 52 is provided so that the surface of the lower cathode electrode 63 is exposed. It is provided. The protective insulating layer 50 may not be provided.
　図２７に示されるように、平面視で、画素領域ＰＸはゲート配線３２、ソース配線３４および駆動電流配線３６によって囲まれた領域で規定されている。アノード電極６１は、ドレイン電極１６と重なる領域に設けられた開口部４８と重なる領域から、画素領域ＰＸの下方の領域まで延在するように設けられている。また、カソード電極６３は、カソード電極配線６２と重なる領域に設けられた開口部４９と重なる領域から、画素領域ＰＸの上方の領域まで延在するように設けられている。アノード電極６１とカソード電極６３は、画素領域ＰＸにおいて、互いに分離して平面視で対向した態様で配設される。アノード電極開口部５１およびカソード電極開口部５２は、それぞれ下層のアノード電極６１およびカソード電極６３が露出されるように、平面視で互いに対向した態様で配設されている。 As shown in FIG. 27, in plan view, the pixel region PX is defined by the region surrounded by the gate wiring 32, the source wiring 34, and the drive current wiring 36. The anode electrode 61 is provided so as to extend from a region overlapping the opening 48 provided in the region overlapping the drain electrode 16 to a region below the pixel region PX. Further, the cathode electrode 63 is provided so as to extend from a region overlapping the opening 49 provided in the region overlapping the cathode electrode wiring 62 to a region above the pixel region PX. The anode electrode 61 and the cathode electrode 63 are arranged in the pixel region PX in a manner in which they are separated from each other and face each other in a plan view. The anode electrode opening 51 and the cathode electrode opening 52 are arranged so as to face each other in a plan view so that the lower layer anode electrode 61 and the cathode electrode 63 are exposed, respectively.
　本実施の形態３に係るＴＦＴ基板１２０は、以上のように構成され、ＴＦＴ基板１２０上には、マトリックス状に配置された各画素領域ＰＸのアノード電極６１およびカソード電極６３に対応するように、ＬＥＤ素子のアノード電極端子およびカソード電極端子がそれぞれ接続されるように複数個実装され（図示せず）、各ＬＥＤ素子を発光させて画像表示を行う方式の自発光型表示装置（ＬＥＤディスプレイ）用のＴＦＴ基板として好適に用いることができる。 The TFT substrate 120 according to the third embodiment is configured as described above, and is arranged on the TFT substrate 120 so as to correspond to the anode electrode 61 and the cathode electrode 63 of each pixel region PX arranged in a matrix. For a self-luminous display device (LED display) in which a plurality of LED element anode electrode terminals and cathode electrode terminals are mounted so as to be connected to each other (not shown), and each LED element is made to emit light to display an image. Can be suitably used as a TFT substrate of.
　　＜製造方法＞
　次に、本実施の形態３に係るＴＦＴ基板１２０の製造方法について、図２９～図４３を用いて説明する。なお、図２９～図４３では、図２７を最終工程図とする平面図と、図２８を最終工程図とする断面図とを交互に示しており、断面図においては、図２８のＸ１－Ｘ２線に沿った断面図およびＹ１－Ｙ２線に沿った断面図を、それぞれ図の左側および右側に示す。 <Manufacturing method>
Next, the method of manufacturing the TFT substrate 120 according to the third embodiment will be described with reference to FIGS. 29 to 43. In addition, in FIGS. 29 to 43, a plan view having FIG. 27 as a final process view and a cross-sectional view having FIG. 28 as a final process view are alternately shown. In the cross-sectional view, X1-X2 of FIG. 28 is shown. A cross-sectional view along the line and a cross-sectional view along the Y1-Y2 line are shown on the left and right sides of the figure, respectively.
　　＜１回目の写真製版工程：図２９、図３０＞
　まず、基板１を洗浄液または純水を用いて洗浄する。本実施の形態３では、厚さ０．５ｍｍのガラス基板を基板１として用いた。そして、洗浄された基板１の一方の主面上に、第１の導電膜を形成する。 <First photoengraving process: Fig. 29, Fig. 30>
First, the substrate 1 is cleaned with a cleaning liquid or pure water. In the third embodiment, a glass substrate having a thickness of 0.5 mm was used as the substrate 1. Then, a first conductive film is formed on one main surface of the washed substrate 1.
　本実施の形態３では、第１の導電膜としてＡｒガスを用いたスパッタリング法でＭｏ膜を２００ｎｍの厚さに成膜した。その後、Ｍｏ膜上にフォトレジスト材を塗布し、１回目の写真製版工程でフォトレジストパターンを形成し、当該フォトレジストパターンをマスクにして、Ｍｏ膜をＰＡＮ薬液を用いたウエットエッチングによりパターニングする。その後、フォトレジストパターンを除去することによって、図２９および図３０に示すように、基板１上に、ＴＦＴ１０１のゲート電極２、およびＴＦＴ１０２のソース電極３およびドレイン電極４、さらにソース配線３４および駆動電流配線３６が同時に形成される。 In the third embodiment, a Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas as the first conductive film. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the first photoplate-making step, and the Mo film is patterned by wet etching using a PAN chemical solution using the photoresist pattern as a mask. Then, by removing the photoresist pattern, as shown in FIGS. 29 and 30, the gate electrode 2 of the TFT 101, the source electrode 3 and the drain electrode 4 of the TFT 102, and the source wiring 34 and the drive current are further mounted on the substrate 1. Wiring 36 is formed at the same time.
　図２９に示されるように、平面視で、ゲート電極２とドレイン電極４は、連続した一体パターンで形成されている。また、ソース配線３４と駆動電流配線３６は隣接するように縦方向（Ｙ方向）に平行して延在するように形成されている。なお、ソース電極３は、ソース配線３４の一部分である。すなわち、ソース配線３４は、第１の導電膜で構成され、ソース配線３４におけるＴＦＴ１０２側に延在する部分がソース電極３となっている。ソース電極３が設けられた部分は、ソース配線３４の他の部分よりも幅が広くなっている。 As shown in FIG. 29, the gate electrode 2 and the drain electrode 4 are formed in a continuous integrated pattern in a plan view. Further, the source wiring 34 and the drive current wiring 36 are formed so as to extend in parallel in the vertical direction (Y direction) so as to be adjacent to each other. The source electrode 3 is a part of the source wiring 34. That is, the source wiring 34 is composed of the first conductive film, and the portion of the source wiring 34 extending toward the TFT 102 is the source electrode 3. The portion provided with the source electrode 3 is wider than the other portion of the source wiring 34.
　　＜２回目の写真製版工程：図３１、図３２＞
　次に、基板１の主面上の全体に第１の絶縁膜を形成する。本実施の形態３では、第１の絶縁膜として、ＣＶＤ法を用いて厚さ３００ｎｍのＳｉＯ膜を、約３００℃の基板加熱条件下で形成した。なお、第１の絶縁膜は、ＳｉＯ膜に限ることなく、他にも例えばＳｉＮ膜を用いることができる。ＳｉＮ膜もＳｉＯ膜と同様にＣＶＤ法で形成することができる。また、ＳｉＯ膜とＳｉＮ膜との積層膜としてもよい。 <Second photoengraving process: Fig. 31, Fig. 32>
Next, the first insulating film is formed on the entire main surface of the substrate 1. In the third embodiment, as the first insulating film, a SiO film having a thickness of 300 nm was formed by a CVD method under the substrate heating condition of about 300 ° C. The first insulating film is not limited to the SiO film, and for example, a SiN film can be used. The SiN film can also be formed by the CVD method in the same manner as the SiO film. Further, it may be a laminated film of a SiO film and a SiN film.
　次に、２回目の写真製版工程で第１の絶縁膜であるＳｉＯ膜上にフォトレジストパターンを形成し、これをマスクとしてＳｉＯ膜をエッチングする。このエッチング工程では、ＳＦ６ガスまたはＣＦ４ガスを用いたドライエッチング法を用いることができる。 Next, in the second photoplate making step, a photoresist pattern is formed on the SiO film which is the first insulating film, and the SiO film is etched using this as a mask. In this etching step, a dry etching method using SF 6 gas or CF 4 gas can be used.
　その後、フォトレジストパターンを除去することで、図３１および図３２に示すように、第２のＴＦＴ部において、ソース電極３の表面の一部を露出させる開口部７、およびドレイン電極４の表面の一部を露出させる開口部８がそれぞれ形成される。図３２に示すように、第１のＴＦＴ部の第１の絶縁膜はゲート絶縁層５として機能し、第２のＴＦＴ部の第１の絶縁膜は、後の工程で形成される第２半導体層形成時に、第２半導体層をソース電極３およびドレイン電極４から受けるダメージから守る保護絶縁層６（第２のチャネル保護層）として機能する。 After that, by removing the photoresist pattern, as shown in FIGS. 31 and 32, in the second TFT portion, the opening 7 that exposes a part of the surface of the source electrode 3 and the surface of the drain electrode 4 Each of the openings 8 that exposes a part is formed. As shown in FIG. 32, the first insulating film of the first TFT portion functions as the gate insulating layer 5, and the first insulating film of the second TFT portion is the second semiconductor formed in a later step. During layer formation, it functions as a protective insulating layer 6 (second channel protective layer) that protects the second semiconductor layer from damage received from the source electrode 3 and the drain electrode 4.
　　＜３回目の写真製版工程：図３３、図３４＞
　次に、第１の絶縁膜上に半導体膜を形成する。本実施の形態３では、半導体膜として酸化物半導体膜を形成する。具体的にはＩｎ：Ｇａ：Ｚｎ：Ｏの原子組成比が１：１：１：４であるＩｎＧａＺｎＯターゲットを用い、Ａｒガスに分圧比１０％のＯ２ガスを添加した混合ガスを用いたスパッタリング法で酸化物半導体膜であるＩｎＧａＺｎＯ膜を５０ｎｍの厚さで形成した。 <Third photoengraving process: Fig. 33, Fig. 34>
Next, a semiconductor film is formed on the first insulating film. In the third embodiment, an oxide semiconductor film is formed as the semiconductor film. Specifically, sputtering using an InGaZnO target having an atomic composition ratio of In: Ga: Zn: O of 1: 1: 1: 4 and a mixed gas in which O 2 gas having a partial pressure ratio of 10% is added to Ar gas. By the method, an InGaZnO film, which is an oxide semiconductor film, was formed with a thickness of 50 nm.
　このとき、ＩｎＧａＺｎＯ膜は、アモルファス構造で形成される。アモルファス構造のＩｎＧａＺｎＯ膜は、一般的に結晶化温度が５００℃超であり、常温では膜中の大部分がアモルファス構造のままで安定する。アモルファス構造は、一部が結晶化された微結晶構造や多結晶構造に比べて構造の均一性を高くすることができる。従って、基板が大型化した場合でも基板全体に特性のバラツキが小さい半導体膜を形成することができる利点がある。すなわち、大型の表示装置に用いるＴＦＴ基板を大型の表示装置に用いた場合であっても、ＴＦＴ特性の面内バラツキを小さくすることができるので、表示ムラを防止することができる。 At this time, the InGaZnO film is formed with an amorphous structure. The InGaZnO film having an amorphous structure generally has a crystallization temperature of more than 500 ° C., and at room temperature, most of the film remains stable with an amorphous structure. The amorphous structure can have higher structural uniformity than a partially crystallized microcrystal structure or a polycrystalline structure. Therefore, even when the size of the substrate is increased, there is an advantage that a semiconductor film having a small variation in characteristics can be formed on the entire substrate. That is, even when the TFT substrate used for a large display device is used for a large display device, the in-plane variation of the TFT characteristics can be reduced, so that display unevenness can be prevented.
　３回目の写真製版工程でＩｎＧａＺｎＯ膜上にフォトレジストパターンを形成し、これをマスクとしてＩｎＧａＺｎＯ膜をエッチングする。このエッチング工程では、シュウ酸薬液によるウエットエッチングを用いることができる。その後、フォトレジストパターンを除去することで、図３３および図３４に示すように、第１のＴＦＴ部においてゲート絶縁層５上のゲート電極２と重なる領域に半導体層９が島状のパターンで形成される。 A photoresist pattern is formed on the InGaZNO film in the third photoengraving process, and the InGaZnO film is etched using this as a mask. In this etching step, wet etching with an oxalic acid chemical solution can be used. After that, by removing the photoresist pattern, as shown in FIGS. 33 and 34, the semiconductor layer 9 is formed in an island-like pattern in the region overlapping the gate electrode 2 on the gate insulating layer 5 in the first TFT portion. Will be done.
　また、第２のＴＦＴ部において、保護絶縁層６上に半導体層１０が形成される。半導体層１０は、保護絶縁層６の開口部７を通して下層のソース電極３と接するとともに、保護絶縁層６の開口部８を通して下層のドレイン電極４と接するように形成される。平面視で、ソース電極３およびドレイン電極４は、半導体層１０と重なる領域内で互いに分離して離間領域を有するように形成されており、半導体層１０において、この離間領域がＴＦＴ１０２のチャネル領域ＣＬ２として規定される。 Further, in the second TFT portion, the semiconductor layer 10 is formed on the protective insulating layer 6. The semiconductor layer 10 is formed so as to be in contact with the source electrode 3 of the lower layer through the opening 7 of the protective insulating layer 6 and to be in contact with the drain electrode 4 of the lower layer through the opening 8 of the protective insulating layer 6. In a plan view, the source electrode 3 and the drain electrode 4 are formed so as to be separated from each other in a region overlapping the semiconductor layer 10 and have a separated region, and in the semiconductor layer 10, this separated region is the channel region CL2 of the TFT 102. Is defined as.
　半導体層１０の材料である酸化物半導体膜をスパッタリング法で形成する場合、下層にソース電極３およびドレイン電極４のような金属膜が露出していると、スパッタリング中に酸化物半導体が金属と反応し、還元（Ｏイオン欠乏）状態の特性が劣化した酸化物半導体膜が形成されてしまう場合がある。しかしながら、本実施の形態３のＴＦＴ１０２では、開口部７および開口部８を除くＴＦＴ１０２の全体が保護絶縁層６で覆われているので、この影響を防止することができる。すなわち、チャネル領域ＣＬ２の保護絶縁層６は、半導体層１０のチャネル保護層６として機能する。 When the oxide semiconductor film, which is the material of the semiconductor layer 10, is formed by the sputtering method, if the metal films such as the source electrode 3 and the drain electrode 4 are exposed in the lower layer, the oxide semiconductor reacts with the metal during sputtering. However, an oxide semiconductor film having deteriorated characteristics in the reduced (O ion deficient) state may be formed. However, in the TFT 102 of the third embodiment, since the entire TFT 102 excluding the opening 7 and the opening 8 is covered with the protective insulating layer 6, this influence can be prevented. That is, the protective insulating layer 6 of the channel region CL2 functions as the channel protective layer 6 of the semiconductor layer 10.
　その後、基板１を大気雰囲気下で４００℃の温度で熱処理する。この熱処理によって半導体層９および半導体層１０の非晶質のＩｎＧａＺｎＯ膜が構造緩和を起こし、半導体特性をさらに安定させることができる。非晶質ＩｎＧａＺｎＯ膜に上記の構造緩和を起こさせるための熱処理の温度は、少なくとも３００℃以上であることが好ましい。一方、５００℃を超えると膜全体で結晶化が始まり半導体特性が大きく変化し、例えばキャリア密度増大による導体化してしまう。従って、ここでは少なくとも基板１を３００℃以上５００℃以下の温度で熱処理することが好ましい。なお、このような熱処理は、製造工程の最後に実施するようにしてもよい。 After that, the substrate 1 is heat-treated at a temperature of 400 ° C. in an air atmosphere. By this heat treatment, the amorphous InGaZnO film of the semiconductor layer 9 and the semiconductor layer 10 causes structural relaxation, and the semiconductor characteristics can be further stabilized. The temperature of the heat treatment for causing the above-mentioned structural relaxation of the amorphous InGaZnO film is preferably at least 300 ° C. or higher. On the other hand, when the temperature exceeds 500 ° C., crystallization starts in the entire film and the semiconductor characteristics change significantly, for example, the film becomes a conductor due to an increase in carrier density. Therefore, here, it is preferable to heat-treat at least the substrate 1 at a temperature of 300 ° C. or higher and 500 ° C. or lower. In addition, such a heat treatment may be carried out at the end of the manufacturing process.
　　＜４回目の写真製版工程：図３５、図３６＞
　次に、基板１の主面上の全体に第２の絶縁膜を形成する。本実施の形態３では、第２の絶縁膜として、ＣＶＤ法で厚さ３００ｎｍのＳｉＯ膜を約２００℃の基板加熱条件下で形成した。なお、第２の絶縁膜は、ＳｉＯ膜に限ることなく、他にも例えばＳｉＮ膜を用いることができる。また、ＳｉＯ膜とＳｉＮ膜との積層膜としてもよい。 <Fourth photoengraving process: Fig. 35, Fig. 36>
Next, a second insulating film is formed on the entire main surface of the substrate 1. In the third embodiment, as the second insulating film, a SiO film having a thickness of 300 nm was formed by a CVD method under a substrate heating condition of about 200 ° C. The second insulating film is not limited to the SiO film, and for example, a SiN film can be used. Further, it may be a laminated film of a SiO film and a SiN film.
　次に、４回目の写真製版工程で第２の絶縁膜であるＳｉＯ膜上にフォトレジストパターンを形成し、これをマスクとしてＳｉＯ膜をエッチングする。このエッチング工程では、ＳＦ６ガスまたはＣＦ４ガスを用いたドライエッチング法を用いることができる。 Next, in the fourth photoplate making step, a photoresist pattern is formed on the SiO film which is the second insulating film, and the SiO film is etched using this as a mask. In this etching step, a dry etching method using SF 6 gas or CF 4 gas can be used.
　その後、フォトレジストパターンを除去することで、図３５および図３６に示すように、第１のＴＦＴ部の第２の絶縁膜に、半導体層９の表面の一部を露出させる開口部１３および開口部１４が形成される。第１のＴＦＴ部の第２の絶縁膜は、後の工程で形成されるソース電極１５およびドレイン電極１６からの加工プロセスダメージを防止する保護絶縁層１１として機能する。また、第２のＴＦＴ部の第２の絶縁膜は、ＴＦＴ１０２のゲート絶縁層１２として機能する。さらに、駆動電流配線３６の表面の一部を露出させるように、第１の絶縁膜および第２の絶縁膜に開口部３０が形成される。 After that, by removing the photoresist pattern, as shown in FIGS. 35 and 36, the opening 13 and the opening that expose a part of the surface of the semiconductor layer 9 to the second insulating film of the first TFT portion. The portion 14 is formed. The second insulating film of the first TFT portion functions as a protective insulating layer 11 for preventing processing process damage from the source electrode 15 and the drain electrode 16 formed in a later step. Further, the second insulating film of the second TFT portion functions as the gate insulating layer 12 of the TFT 102. Further, an opening 30 is formed in the first insulating film and the second insulating film so as to expose a part of the surface of the drive current wiring 36.
　　＜５回目の写真製版工程：図３７、図３８＞
　次に、第２の絶縁膜上に第２の導電膜を形成する。本実施の形態３では、第２の導電膜としてＡｒガスを用いたスパッタリング法でＭｏ膜を２００ｎｍの厚さに形成した。その後、Ｍｏ膜上にフォトレジスト材を塗布し、５回目の写真製版工程でフォトレジストパターンを形成し、当該フォトレジストパターンをマスクにして、Ｍｏ膜をＰＡＮ薬液を用いたウエットエッチングによりパターニングする。その後、フォトレジストパターンを除去することで、図３７および図３８に示すように、ＴＦＴ１０１のソース電極１５およびドレイン電極１６が形成され、同時にＴＦＴ１０２のゲート電極１７が形成される。また画素領域ＰＸの絶縁膜上には、導電膜で構成されるカソード電極配線６２が形成される。 <Fifth photoengraving process: Fig. 37, Fig. 38>
Next, a second conductive film is formed on the second insulating film. In the third embodiment, the Mo film was formed to a thickness of 200 nm by a sputtering method using Ar gas as the second conductive film. Then, a photoresist material is applied onto the Mo film, a photoresist pattern is formed in the fifth photoplate-making step, and the Mo film is patterned by wet etching using a PAN chemical solution using the photoresist pattern as a mask. After that, by removing the photoresist pattern, as shown in FIGS. 37 and 38, the source electrode 15 and the drain electrode 16 of the TFT 101 are formed, and at the same time, the gate electrode 17 of the TFT 102 is formed. Further, a cathode electrode wiring 62 composed of a conductive film is formed on the insulating film of the pixel region PX.
　ＴＦＴ１０１のソース電極１５は、開口部１３を通して半導体層９と接するように形成されている。また、ドレイン電極１６は、開口部１４を通して半導体層９と接するように形成されている。ソース電極１５とドレイン電極１６は、半導体層９と重なる領域内で互いに分離して形成されており、半導体層９においてソース電極１５とドレイン電極１６とで挟まれる離間領域が、ＴＦＴ１０１のチャネル領域ＣＬ１として規定されている。 The source electrode 15 of the TFT 101 is formed so as to be in contact with the semiconductor layer 9 through the opening 13. Further, the drain electrode 16 is formed so as to be in contact with the semiconductor layer 9 through the opening 14. The source electrode 15 and the drain electrode 16 are formed separately from each other in the region overlapping the semiconductor layer 9, and the separated region sandwiched between the source electrode 15 and the drain electrode 16 in the semiconductor layer 9 is the channel region CL1 of the TFT 101. Is specified as.
　一般的に酸化物半導体膜は薬液耐性に乏しく、半導体層９の材料であるＩｎＧａＺｎＯ膜は、第２の導電膜のウエットエッチングに用いられるＰＡＮ薬液にも容易に溶けてしまう。しかしながら、ＴＦＴ１０１では、開口部１３および開口部１４を除く基板１の全面が第２の絶縁膜で構成される保護絶縁層１１で覆われているので、特に半導体層９のチャネル領域ＣＬ１上ではチャネル保護層（エッチングストッパ；ＥＳ層）として機能する。従って、プロセスダメージのない信頼性の高いＴＦＴを得ることができる。 Generally, the oxide semiconductor film has poor chemical resistance, and the InGaZnO film, which is the material of the semiconductor layer 9, is easily dissolved in the PAN chemical solution used for wet etching of the second conductive film. However, in the TFT 101, since the entire surface of the substrate 1 excluding the opening 13 and the opening 14 is covered with the protective insulating layer 11 formed of the second insulating film, the channel is particularly on the channel region CL1 of the semiconductor layer 9. It functions as a protective layer (etching stopper; ES layer). Therefore, a highly reliable TFT without process damage can be obtained.
　ソース電極１５は、駆動電流配線３６に重なる領域まで延在しており、開口部３０を通して駆動電流配線３６に接続されている。また、ドレイン電極１６は、ＴＦＴ１０２のドレイン電極４と連続した一体パターンで設けられたＴＦＴ１０１のゲート電極２と重なる領域まで延在して形成されている。平面視で、ＴＦＴ１０１のドレイン電極１６は、半導体層１０と重なる領域からはみ出した領域で、ゲート電極２およびＴＦＴ１０２のドレイン電極４のパターンと広く重なるような形状で配設されている。そしてドレイン電極１６とゲート電極２が重なる領域によって保持容量ＣｓＡが形成される。また、平面視で、カソード電極配線６２は、ＴＦＴ１０１およびＴＦＴ１０２とは反対側の画素領域ＰＸに、ゲート配線３２と隣接するように横方向（Ｘ方向）に平行して延在するように形成されている。 The source electrode 15 extends to a region overlapping the drive current wiring 36, and is connected to the drive current wiring 36 through the opening 30. Further, the drain electrode 16 is formed so as to extend to a region overlapping the gate electrode 2 of the TFT 101 provided in an integral pattern continuous with the drain electrode 4 of the TFT 102. In a plan view, the drain electrode 16 of the TFT 101 is arranged so as to be a region protruding from the region overlapping the semiconductor layer 10 and widely overlapping the pattern of the gate electrode 2 and the drain electrode 4 of the TFT 102. Then, the holding capacity CsA is formed by the region where the drain electrode 16 and the gate electrode 2 overlap. Further, in a plan view, the cathode electrode wiring 62 is formed so as to extend in the pixel region PX on the opposite side of the TFT 101 and the TFT 102 so as to be adjacent to the gate wiring 32 and parallel to the lateral direction (X direction). ing.
　ＴＦＴ１０２のゲート電極１７は、ソース電極３とドレイン電極４とが互いに対向するように分離された領域において、下層の半導体層１０のチャネル領域ＣＬ２と重なるように形成されている。また平面視で、ゲート電極１７は、ソース電極３およびドレイン電極とは重ならないように形成されており、これらの重なりによる寄生容量が形成されないように構成されている。これにより、高速応答性に優れたＴＦＴを得ることができる。さらに、半導体層１０のチャネル領域ＣＬ２は、保護絶縁層６で保護されているので、ＴＦＴ１０１と同様に、プロセスダメージのない信頼性の高いＴＦＴを得ることができる。そして、ゲート電極１７から延在するゲート配線３２が、ソース配線３４および駆動電流配線３６と直交するように横方向（Ｘ方向）に延在するように形成されている。 The gate electrode 17 of the TFT 102 is formed so as to overlap the channel region CL2 of the lower semiconductor layer 10 in a region where the source electrode 3 and the drain electrode 4 are separated so as to face each other. Further, in a plan view, the gate electrode 17 is formed so as not to overlap the source electrode 3 and the drain electrode, and is configured so that a parasitic capacitance due to the overlap thereof is not formed. As a result, a TFT having excellent high-speed response can be obtained. Further, since the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained as in the case of the TFT 101. The gate wiring 32 extending from the gate electrode 17 is formed so as to extend in the lateral direction (X direction) so as to be orthogonal to the source wiring 34 and the drive current wiring 36.
　　＜６回目の写真製版工程：図３９、図４０＞
　次に、基板１の主面上の全体に、保護絶縁層１８となる第３の絶縁膜を形成する。本実施の形態３では、第３の絶縁膜として、感光性を有する透明アクリル樹脂膜を、スピンコート法を用いて塗布形成した。このような透明アクリル樹脂膜を形成することにより、下層の電極パターンの段差および絶縁膜の開口部パターンの段差等に起因する基板表面の凹凸形状をほぼ平坦にすることができる。 <Sixth photoengraving process: Fig. 39, Fig. 40>
Next, a third insulating film to be the protective insulating layer 18 is formed on the entire main surface of the substrate 1. In the third embodiment, a photosensitive transparent acrylic resin film is applied and formed as a third insulating film by a spin coating method. By forming such a transparent acrylic resin film, the uneven shape of the substrate surface due to the step difference of the electrode pattern of the lower layer and the step difference of the opening pattern of the insulating film can be made substantially flat.
　本実施の形態３では、透明アクリル樹脂膜の膜厚が最も薄くなる部分で厚さが１．５μｍになるように塗布形成した。また、保護絶縁層１８として、透明アクリル樹脂膜を塗布形成する前に、例えばＣＶＤ法でＳｉＯ膜またはＳｉＮ膜を形成するようにしてもよい。なお、樹脂系の塗布膜は、アクリル系以外にも、ＳＯＧ系、エポキシ系、ポリイミド系、あるいはポリオレフィン系の樹脂膜を用いることができる。 In the third embodiment, the transparent acrylic resin film was coated and formed so that the thickness was 1.5 μm at the portion where the film thickness was the thinnest. Further, as the protective insulating layer 18, a SiO film or a SiN film may be formed by, for example, a CVD method before the transparent acrylic resin film is applied and formed. As the resin-based coating film, an SOG-based, epoxy-based, polyimide-based, or polyolefin-based resin film can be used in addition to the acrylic-based coating film.
　その後、６回目の写真製版工程で透明アクリル系樹脂を露光し、現像することによって、図３９および図４０に示すように、保持容量ＣｓＡが形成された領域の保護絶縁層１８に、ＴＦＴ１０１のドレイン電極１６の表面の一部が露出されるように開口部４８が形成される。また、カソード電極配線６２と重なる領域の保護絶縁層１８に、カソード電極配線６２の表面の一部が露出されるように開口部４９が形成される。なお、有機アクリル樹脂膜の下層にＳｉＯ膜またはＳｉＮ膜が形成されている場合には、開口部４８および開口部４９が形成された透明アクリル系樹脂をマスクにして、ＳＦ６ガスまたはＣＦ４ガスを用いたドライエッチング法を用いてＳｉＯ膜またはＳｉＮ膜をエッチングすることで、ドレイン電極１６およびカソード電極配線６２の表面の一部を露出させて、開口部４８および開口部４９を形成する。 Then, by exposing and developing the transparent acrylic resin in the sixth photographic plate making step, as shown in FIGS. 39 and 40, the drain of the TFT 101 is drained to the protective insulating layer 18 in the region where the holding capacity CsA is formed. The opening 48 is formed so that a part of the surface of the electrode 16 is exposed. Further, an opening 49 is formed in the protective insulating layer 18 in the region overlapping the cathode electrode wiring 62 so that a part of the surface of the cathode electrode wiring 62 is exposed. When a SiO film or SiN film is formed under the organic acrylic resin film, SF 6 gas or CF 4 gas is used as a mask using the transparent acrylic resin in which the openings 48 and 49 are formed. By etching the SiO film or SiN film using the dry etching method using the above, a part of the surface of the drain electrode 16 and the cathode electrode wiring 62 is exposed to form the opening 48 and the opening 49.
　　＜７回目の写真製版工程：図４１、図４２＞
　次に、開口部４８および開口部４９を含む第３保護絶縁層上に、第５の導電膜を形成する。本実施の形態３では、第５の導電膜として、透明性を有するＩＴＯ膜を用いる。ＩＴＯ膜は一般的に、常温中では結晶質（多結晶）構造が安定であるが、ここではＡｒガスに水素（Ｈ）を含むガス、例えば、水素（Ｈ２）ガスまたは水蒸気（Ｈ２Ｏ）などを混合したガスを用いてスパッタリングを行い、厚さ１００ｎｍのＩＴＯ膜をアモルファス状態（アモルファスＩＴＯ膜）で形成した。 <7th photoengraving process: Fig. 41, Fig. 42>
Next, a fifth conductive film is formed on the third protective insulating layer including the opening 48 and the opening 49. In the third embodiment, a transparent ITO film is used as the fifth conductive film. The ITO film generally has a stable crystalline (polycrystalline) structure at room temperature, but here, a gas containing hydrogen (H) in Ar gas, for example, hydrogen (H 2 ) gas or water vapor (H 2 O). ) And the like were subjected to sputtering to form an ITO film having a thickness of 100 nm in an amorphous state (amorphous ITO film).
　その後、７回目の写真製版工程でアモルファスＩＴＯ膜上にフォトレジストパターンを形成し、これをマスクとしてアモルファスＩＴＯ膜をエッチングする。このエッチング工程では、シュウ酸薬液によるウエットエッチングを用いることができる。その後、フォトレジストパターンを除去することで、図４１および図４２に示すように、透明性を有するＩＴＯ膜で構成されるアノード電極６１およびカソード電極６３が形成される。平面視で、アノード電極６１は、ドレイン電極１６と重なる領域に設けられた開口部４８と重なる領域から、画素領域ＰＸの下方の領域まで延在するように設けられている。また、カソード電極６３は、カソード電極配線６２と重なる領域に設けられた開口部４９と重なる領域から、画素領域ＰＸの上方の領域まで延在するように設けられている。アノード電極６１とカソード電極６３は、画素領域ＰＸにおいて、互いに分離して平面視で対向した態様で配設される。 After that, a photoresist pattern is formed on the amorphous ITO film in the 7th photoplate making process, and the amorphous ITO film is etched using this as a mask. In this etching step, wet etching with an oxalic acid chemical solution can be used. After that, by removing the photoresist pattern, as shown in FIGS. 41 and 42, the anode electrode 61 and the cathode electrode 63 made of a transparent ITO film are formed. In a plan view, the anode electrode 61 is provided so as to extend from a region overlapping the opening 48 provided in the region overlapping the drain electrode 16 to a region below the pixel region PX. Further, the cathode electrode 63 is provided so as to extend from a region overlapping the opening 49 provided in the region overlapping the cathode electrode wiring 62 to a region above the pixel region PX. The anode electrode 61 and the cathode electrode 63 are arranged in the pixel region PX in a manner in which they are separated from each other and face each other in a plan view.
　　＜８回目の写真製版工程：図２７、図２８＞
　次に、基板１の主面上の全体に、保護絶縁層５０となる第５の絶縁膜を形成する。本実施の形態３では、第５の絶縁膜として、感光性を有する透明アクリル樹脂膜を、スピンコート法を用いて厚さが１．５μｍとなるように塗布形成した。なお、アクリル系以外にも、ＳＯＧ系、エポキシ系、ポリイミド系、あるいはポリオレフィン系の樹脂膜を用いることができる。 <8th photoengraving process: Fig. 27, Fig. 28>
Next, a fifth insulating film to be the protective insulating layer 50 is formed on the entire main surface of the substrate 1. In the third embodiment, as the fifth insulating film, a photosensitive transparent acrylic resin film is coated and formed so as to have a thickness of 1.5 μm by a spin coating method. In addition to the acrylic type, SOG type, epoxy type, polyimide type, or polyolefin type resin films can be used.
　その後、８回目の写真製版工程で透明アクリル系樹脂を露光し、現像することによって、図２７および図２８に示すように、画素領域ＰＸにアノード電極６１の表面が露出されるようにアノード電極開口部５１が形成され、カソード電極６３の表面が露出されるようにカソード電極開口部５２が形成される。平面視で、アノード電極開口部５１およびカソード電極開口部５２は、互いに対向するように形成されている。以上により、８回の写真製版工程で本実施の形態３に係るＴＦＴ基板１２０が完成する。なお、第５の絶縁膜の形成を省略することも可能である。この場合は、７回の写真製版工程で本実施の形態３に係るＴＦＴ基板１２０を完成させることができる。 Then, by exposing and developing the transparent acrylic resin in the eighth photoengraving step, the anode electrode is opened so that the surface of the anode electrode 61 is exposed in the pixel region PX as shown in FIGS. 27 and 28. The portion 51 is formed, and the cathode electrode opening 52 is formed so that the surface of the cathode electrode 63 is exposed. In a plan view, the anode electrode opening 51 and the cathode electrode opening 52 are formed so as to face each other. As described above, the TFT substrate 120 according to the third embodiment is completed in eight photoengraving steps. It is also possible to omit the formation of the fifth insulating film. In this case, the TFT substrate 120 according to the third embodiment can be completed in seven photoplate-making steps.
　さらに、図４３に示すように、完成されたＴＦＴ基板１２０上には、画素領域ＰＸのアノード電極６１およびカソード電極６３に対応して、ＬＥＤ素子２００のアノード電極端子２０１および下部電極端子２０２がそれぞれ接続されるように実装される。 Further, as shown in FIG. 43, on the completed TFT substrate 120, the anode electrode terminal 201 and the lower electrode terminal 202 of the LED element 200 correspond to the anode electrode 61 and the cathode electrode 63 of the pixel region PX, respectively. Implemented to be connected.
　図４４に示すように、ＬＥＤ素子２００が実装されたＴＦＴ基板１２０上には、必要に応じて対向基板４７が貼り合わせられ、ＬＥＤ素子を用いたＬＥＤディスプレイを備えた自発光型表示装置３１０が完成する。 As shown in FIG. 44, a facing substrate 47 is attached to the TFT substrate 120 on which the LED element 200 is mounted, if necessary, and a self-luminous display device 310 provided with an LED display using the LED element is provided. Complete.
　自発光型表示装置３１０は、表示欠陥が少なく、高開口率で明るい表示品質の表示装置を低コストで実現することができる。 The self-luminous display device 310 can realize a display device with a high aperture ratio and bright display quality at low cost with few display defects.
　ＬＥＤディスプレイを備えた自発光型表示装置３１０は、有機ＥＬディスプレイを備えた実施の形態２の自発光型表示装置に比べると、より低消費電力で、視野角が広く、さらにコントラスト比が高い高品質な画像表示を実現することができる。 The self-luminous display device 310 provided with an LED display has lower power consumption, a wider viewing angle, and a higher contrast ratio than the self-luminous display device of the second embodiment provided with an organic EL display. It is possible to realize a high-quality image display.
　本実施の形態３に係るＴＦＴ基板１２０によると、ＴＦＴ１０２は、ゲート配線３２およびソース配線３４と電気的に接続されており、ゲート配線３２とソース配線３４の信号に応じて表示画素を選択するための選択ＴＦＴとして機能する。 According to the TFT substrate 120 according to the third embodiment, the TFT 102 is electrically connected to the gate wiring 32 and the source wiring 34, and the display pixels are selected according to the signals of the gate wiring 32 and the source wiring 34. Functions as a selection TFT of.
　ＴＦＴ１０２のゲート電極１７と、ソース電極３およびドレイン電極４とは、互いに寄生容量が形成されないように構成されているので、応答性に優れたＴＦＴを得ることができる。 Since the gate electrode 17 of the TFT 102, the source electrode 3 and the drain electrode 4 are configured so that parasitic capacitances are not formed on each other, a TFT having excellent responsiveness can be obtained.
　さらに半導体層１０のチャネル領域ＣＬ２は、保護絶縁層６で保護されているので、プロセスダメージのない信頼性の高いＴＦＴを得ることができる。従って、選択ＴＦＴとして高い性能を発揮させることができる。 Further, since the channel region CL2 of the semiconductor layer 10 is protected by the protective insulating layer 6, a highly reliable TFT without process damage can be obtained. Therefore, high performance can be exhibited as a selective TFT.
　また、ＴＦＴ１０１は、ＴＦＴ１０２のドレイン電極４、駆動電流配線３６およびＬＥＤ素子２００と電気的に接続されており、ＬＥＤ素子２００の画素駆動ＴＦＴとして機能する。ＴＦＴ１０２の第２ドレイン電極４から出力された選択信号が保持容量ＣｓＡに書き込まれると、書き込まれた電圧によってＴＦＴ１０１が動作して、駆動電流配線３６からの信号電流がＬＥＤ素子２００に供給され、ＬＥＤ素子２００が発光する。 Further, the TFT 101 is electrically connected to the drain electrode 4, the drive current wiring 36, and the LED element 200 of the TFT 102, and functions as a pixel drive TFT of the LED element 200. When the selection signal output from the second drain electrode 4 of the TFT 102 is written to the holding capacitance CsA, the TFT 101 operates according to the written voltage, the signal current from the drive current wiring 36 is supplied to the LED element 200, and the LED The element 200 emits light.
　ＴＦＴ１０１のチャネル領域ＣＬ１は、保護絶縁層１１で保護されているので、信頼性が高く、ＬＥＤ素子２００に安定的に信号電流を供給することができ、ＬＥＤ素子２００を安定的に発光させ、高品質の画像表示をすることができる。 Since the channel region CL1 of the TFT 101 is protected by the protective insulating layer 11, the reliability is high, the signal current can be stably supplied to the LED element 200, the LED element 200 is made to emit light stably, and the value is high. It is possible to display quality images.
　本実施の形態３に係るＴＦＴ基板１２０によれば、ＴＦＴ１０２のドレイン電極４とＴＦＴ１０１のゲート電極２とを同じ第１の導電膜の連続パターンで形成して一体としているので、例えば、両者を別体で形成し、コンタクトホールを介して電気的に接続した構成に比べると、ＴＦＴ１０２からＴＦＴ１０１への信号の伝達不良による表示欠陥の発生率を低く抑えることができる。 According to the TFT substrate 120 according to the third embodiment, the drain electrode 4 of the TFT 102 and the gate electrode 2 of the TFT 101 are formed and integrated in the same continuous pattern of the first conductive film. Therefore, for example, they are separated from each other. Compared with a configuration in which the body is formed and electrically connected via a contact hole, the occurrence rate of display defects due to poor signal transmission from the TFT 102 to the TFT 101 can be suppressed to a low rate.
　さらに連続して一体化されたゲート電極２およびドレイン電極４を保持容量ＣｓＡの容量電極として用いることができるため、米国特許第９７２１９７３号公報のＦｉｇ．７のような電荷蓄積部にコンタクトホールが形成されている構成と比べると、はるかに面積効率よく保持容量ＣｓＡを形成することができるので、ＴＦＴ回路の形成領域を小さくすることができ、画素領域ＰＸの開口率を向上させることができる。 Further, since the continuously integrated gate electrode 2 and drain electrode 4 can be used as a capacitance electrode having a holding capacitance of CsA, Fig. 9721973 of US Pat. No. Compared with the configuration in which the contact hole is formed in the charge storage portion such as No. 7, the holding capacity CsA can be formed much more efficiently in the area, so that the formation region of the TFT circuit can be reduced and the pixel region can be reduced. The aperture ratio of the PX can be improved.
　ＬＥＤ素子をＴＦＴ基板に実装して動作させる場合は、ＴＦＴ基板の各画素領域にアノード電極とカソード電極とを配設する必要がある。本実施の形態３に係るＴＦＴ基板１２０によれば、カソード電極６３を、第５の導電膜を用いてアノード電極６１と同時に形成することができる。さらに、カソード電極６３に信号電流を供給するカソード電極配線６２を、第２の導電膜を用いて、ＴＦＴ１０１のドレイン電極１６等と同時に形成することができる。従って、ＬＥＤ素子を備えた自発光型表示装置（ＬＥＤディスプレイ）用のＴＦＴ基板を、工程を増やすことなく、低コストで製造できる。 When the LED element is mounted on the TFT substrate and operated, it is necessary to dispose the anode electrode and the cathode electrode in each pixel region of the TFT substrate. According to the TFT substrate 120 according to the third embodiment, the cathode electrode 63 can be formed at the same time as the anode electrode 61 by using the fifth conductive film. Further, the cathode electrode wiring 62 that supplies the signal current to the cathode electrode 63 can be formed at the same time as the drain electrode 16 and the like of the TFT 101 by using the second conductive film. Therefore, a TFT substrate for a self-luminous display device (LED display) equipped with an LED element can be manufactured at low cost without increasing the number of steps.
　　＜変形例１＞
　次に、実施の形態３の変形例１について説明する。実施の形態３の変形例１は、実施の形態３の保持容量ＣｓＡの構成を変えたものである。以下、図４５および図４６を用いて、実施の形態３の変形例１に係るＴＦＴ基板１３０の構成について説明する。なお、実施の形態３のＴＦＴ基板１２０と同じ構成要素には同一符号を付け、重複する説明は省略する。 <Modification example 1>
Next, a modification 1 of the third embodiment will be described. The first modification of the third embodiment is a modification of the configuration of the holding capacity CsA of the third embodiment. Hereinafter, the configuration of the TFT substrate 130 according to the first modification of the third embodiment will be described with reference to FIGS. 45 and 46. The same components as those of the TFT substrate 120 of the third embodiment are designated by the same reference numerals, and redundant description will be omitted.
　図４５は、実施の形態３の変形例１に係るＴＦＴ基板１３０の画素の画素部駆動回路ＬＥＤＣ２の構成を示す図である。図４６は、ＴＦＴ基板１３０に設けられたＴＦＴ１０１、ＴＦＴ１０２、保持容量ＣｓＡおよび画素領域ＰＸを含む画素の平面構成を示す部分平面図である。 FIG. 45 is a diagram showing the configuration of the pixel portion drive circuit LEDC2 of the pixels of the TFT substrate 130 according to the first modification of the third embodiment. FIG. 46 is a partial plan view showing a planar configuration of pixels including the TFT 101, the TFT 102, the holding capacity CsA, and the pixel region PX provided on the TFT substrate 130.
　図２６に示したように、実施の形態３のＴＦＴ基板１２０では、保持容量ＣｓＡがＴＦＴ１０１のゲート電極２とドレイン電極１６との間に接続された構成であった。これに対して、図４５に示すように、実施の形態３の変形例１のＴＦＴ基板１３０では、保持容量ＣｓＢがＴＦＴ１０１のゲート電極２とソース電極１５との間に接続された構成となっている。この場合も、ＴＦＴ１０２のドレイン電極４から出力された選択信号が保持容量ＣｓＢに書き込まれると、書き込まれた電圧によってＴＦＴ１０１が動作して、駆動電流配線３６からの信号電流が、アノード電極６１とカソード電極６３との電位差によってＬＥＤ素子２００に供給され、ＬＥＤ素子２００が発光する。 As shown in FIG. 26, the TFT substrate 120 of the third embodiment has a configuration in which the holding capacity CsA is connected between the gate electrode 2 and the drain electrode 16 of the TFT 101. On the other hand, as shown in FIG. 45, the TFT substrate 130 of the first modification of the third embodiment has a configuration in which the holding capacity CsB is connected between the gate electrode 2 of the TFT 101 and the source electrode 15. There is. Also in this case, when the selection signal output from the drain electrode 4 of the TFT 102 is written to the holding capacitance CsB, the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is transferred to the anode electrode 61 and the cathode. It is supplied to the LED element 200 by the potential difference from the electrode 63, and the LED element 200 emits light.
　保持容量ＣｓＢは、第１の導電膜で構成され、ＴＦＴ１０２のドレイン電極４と連続した一体パターンで配設されるＴＦＴ１０１のゲート電極２とで構成される容量電極のパターン形状と、第２の導電膜で構成されるＴＦＴ１０１のソース電極１５およびドレイン電極１６のパターン形状を変えることで構成することができる。 The holding capacitance CsB has a pattern shape of a capacitance electrode composed of a first conductive film and composed of a drain electrode 4 of the TFT 102 and a gate electrode 2 of the TFT 101 arranged in a continuous integrated pattern, and a second conductivity. It can be configured by changing the pattern shape of the source electrode 15 and the drain electrode 16 of the TFT 101 made of a film.
　すなわち、図４６に示されるように、平面視で、ソース電極１５が半導体層９と重なる領域からはみ出した領域で、ゲート電極２とドレイン電極４との一体パターンで構成される容量電極と重なるように延在して配設されている。これにより、ソース電極１５とゲート電極２が重なる領域によって保持容量ＣｓＢが形成される。なお、容量電極とソース電極１５との間には、ゲート絶縁層５を構成する第１の絶縁膜と保護絶縁層１１を構成する第２の絶縁膜とが積層されて設けられている。また、実施の形態２の保持容量ＣｓＡの構成についても、上述した保持容量ＣｓＢに変えても良いことは言うまでもない。 That is, as shown in FIG. 46, in a plan view, the source electrode 15 protrudes from the region where the semiconductor layer 9 overlaps, and overlaps the capacitance electrode formed of the integrated pattern of the gate electrode 2 and the drain electrode 4. It is arranged so as to extend to. As a result, the holding capacitance CsB is formed by the region where the source electrode 15 and the gate electrode 2 overlap. A first insulating film forming the gate insulating layer 5 and a second insulating film forming the protective insulating layer 11 are laminated and provided between the capacitance electrode and the source electrode 15. Needless to say, the configuration of the holding capacity CsA of the second embodiment may be changed to the holding capacity CsB described above.
　　＜変形例２＞
　次に、実施の形態３の変形例２について説明する。実施の形態３の変形例２は、実施の形態３の保持容量ＣｓＡの構成を変えたものである。以下、図４７および図４８を用いて、実施の形態３の変形例２に係るＴＦＴ基板１４０の構成についてに説明する。なお、実施の形態３のＴＦＴ基板１２０と同じ構成要素には同一符号を付け、重複する説明は省略する。 <Modification 2>
Next, a modification 2 of the third embodiment will be described. The second modification of the third embodiment is a modification of the configuration of the holding capacity CsA of the third embodiment. Hereinafter, the configuration of the TFT substrate 140 according to the second modification of the third embodiment will be described with reference to FIGS. 47 and 48. The same components as those of the TFT substrate 120 of the third embodiment are designated by the same reference numerals, and redundant description will be omitted.
　図４７は、実施の形態３の変形例２に係るＴＦＴ基板１４０の画素の画素部駆動回路ＬＥＤＣ３の構成を示す図である。図４８は、ＴＦＴ基板１４０に設けられたＴＦＴ１０１、ＴＦＴ１０２、保持容量ＣｓＡＢおよび画素領域ＰＸを含む画素の平面構成を示す部分平面図である。 FIG. 47 is a diagram showing the configuration of the pixel portion drive circuit LEDC3 of the pixels of the TFT substrate 140 according to the second modification of the third embodiment. FIG. 48 is a partial plan view showing a planar configuration of pixels including the TFT 101, the TFT 102, the holding capacity CsAB, and the pixel region PX provided on the TFT substrate 140.
　図２６に示したように、実施の形態３のＴＦＴ基板１２０では、保持容量ＣｓＡがＴＦＴ１０１のゲート電極２とドレイン電極１６との間に接続された構成であった。これに対して、図４７に示すように、実施の形態３の変形例２のＴＦＴ基板１４０では、保持容量ＣｓＡＢがＴＦＴ１０１のゲート電極２とソース電極１５との間、およびＴＦＴ１０１のゲート電極２とドレイン電極１６との間に並列で接続された構成となっている。この場合も、ＴＦＴ１０２のドレイン電極４から出力された選択信号が保持容量ＣｓＡＢに書き込まれると、書き込まれた電圧によってＴＦＴ１０１が動作して、駆動電流配線３６からの信号電流が、アノード電極６１とカソード電極６３との電位差によってＬＥＤ素子２００に供給され、ＬＥＤ素子２００が発光する。 As shown in FIG. 26, the TFT substrate 120 of the third embodiment has a configuration in which the holding capacity CsA is connected between the gate electrode 2 and the drain electrode 16 of the TFT 101. On the other hand, as shown in FIG. 47, in the TFT substrate 140 of the second modification of the third embodiment, the holding capacity CsAB is between the gate electrode 2 of the TFT 101 and the source electrode 15, and the gate electrode 2 of the TFT 101. It is configured to be connected in parallel with the drain electrode 16. Also in this case, when the selection signal output from the drain electrode 4 of the TFT 102 is written to the holding capacitance CsAB, the TFT 101 operates according to the written voltage, and the signal current from the drive current wiring 36 is transferred to the anode electrode 61 and the cathode. It is supplied to the LED element 200 by the potential difference from the electrode 63, and the LED element 200 emits light.
　保持容量ＣｓＡＢは、第１の導電膜で構成されたＴＦＴ１０２のドレイン電極４と連続した一体パターンで配設されるＴＦＴ１０１のゲート電極２とで構成される容量電極のパターン形状と、第２の導電膜で構成されるＴＦＴ１０１のソース電極１５およびドレイン電極１６のパターン形状を変えることで構成することができる。 The holding capacitance CsAB is the pattern shape of the capacitance electrode composed of the drain electrode 4 of the TFT 102 composed of the first conductive film and the gate electrode 2 of the TFT 101 arranged in a continuous integrated pattern, and the second conductivity. It can be configured by changing the pattern shape of the source electrode 15 and the drain electrode 16 of the TFT 101 made of a film.
　すなわち、図４８に示されるように、平面視で、ドレイン電極１６が半導体層９と重なる領域からはみ出した領域で、ゲート電極２とドレイン電極４との一体パターンで構成される容量電極と重なるように延在して配設されている。これにより、ドレイン電極１６と容量電極が重なる領域によって保持容量ＣｓＡ（第１の保持容量）が形成される。なお、容量電極とドレイン電極１６との間には、ゲート絶縁層５を構成する第１の絶縁膜と保護絶縁層１１を構成する第２の絶縁膜とが積層されて設けられている。 That is, as shown in FIG. 48, in a plan view, the drain electrode 16 protrudes from the region where the semiconductor layer 9 overlaps, and overlaps with the capacitance electrode formed of the integrated pattern of the gate electrode 2 and the drain electrode 4. It is arranged so as to extend to. As a result, the holding capacity CsA (first holding capacity) is formed by the region where the drain electrode 16 and the capacitance electrode overlap. A first insulating film forming the gate insulating layer 5 and a second insulating film forming the protective insulating layer 11 are laminated and provided between the capacitance electrode and the drain electrode 16.
　さらに、平面視で、ソース電極１５が半導体層９と重なる領域からはみ出した領域で、ゲート電極２とドレイン電極４との一体パターンで構成される容量電極と重なるように延在して配設されている。これにより、ソース電極１５と容量電極が重なる領域によって保持容量ＣｓＢ（第２の保持容量）が形成される。なお、容量電極とソース電極１５との間にも、ゲート絶縁層５を構成する第１の絶縁膜と保護絶縁層１１を構成する第２の絶縁膜とが積層されて設けられている。 Further, in a plan view, the source electrode 15 is a region protruding from the region overlapping the semiconductor layer 9, and is arranged so as to extend so as to overlap the capacitive electrode formed of an integrated pattern of the gate electrode 2 and the drain electrode 4. ing. As a result, the holding capacity CsB (second holding capacity) is formed by the region where the source electrode 15 and the capacitance electrode overlap. A first insulating film forming the gate insulating layer 5 and a second insulating film forming the protective insulating layer 11 are laminated and provided between the capacitance electrode and the source electrode 15.
　並列に接続された保持容量ＣｓＡと保持容量ＣｓＢによって、保持容量ＣｓＡＢが構成される。また、実施の形態２の保持容量ＣｓＡの構成についても、上述した保持容量ＣｓＡＢに変えても良いことは言うまでもない。 The holding capacity CsAB is composed of the holding capacity CsA and the holding capacity CsB connected in parallel. Needless to say, the configuration of the holding capacity CsA of the second embodiment may be changed to the holding capacity CsAB described above.
　以上説明した実施の形態３の変形例１のＴＦＴ基板１３０、および変形例２のＴＦＴ基板１４０においても、実施の形態３のＴＦＴ基板１２０と同様の効果を得ることができる。 The TFT substrate 130 of the first modification of the third embodiment and the TFT substrate 140 of the second modification described above can also obtain the same effect as the TFT substrate 120 of the third embodiment.
　また、上記の変形例１および変形例２は、ＬＥＤ素子２００を用いた実施の形態３に限らず、ＥＬ素子４４を用いた実施の形態２のＴＦＴ基板１１０にも適用することが可能であり、同様の効果を得ることができる。 Further, the above-mentioned modifications 1 and 2 can be applied not only to the third embodiment using the LED element 200 but also to the TFT substrate 110 of the second embodiment using the EL element 44. , The same effect can be obtained.
　　＜他の適用例＞
　以上説明した実施の形態２および実施の形態３では、ＴＦＴ１０１およびＴＦＴ１０２の構成を、自発光型表示装置用のＴＦＴ基板の画素駆動回路に適用した例を示したが、本開示の適用例は、これらに限られるものではない。 <Other application examples>
In the second embodiment and the third embodiment described above, an example in which the configurations of the TFT 101 and the TFT 102 are applied to the pixel drive circuit of the TFT substrate for the self-luminous display device is shown. It is not limited to these.
　例えば、図６に示した実施の形態２に係るＴＦＴ基板１１０の額縁領域１６０に設けられる走査信号駆動回路１７０には、図示されない複数の信号発生回路が含まれているが、この信号発生回路にＴＦＴ１０１およびＴＦＴ１０２の構成を適用することができる。 For example, the scanning signal drive circuit 170 provided in the frame region 160 of the TFT substrate 110 according to the second embodiment shown in FIG. 6 includes a plurality of signal generation circuits (not shown). The configurations of TFT 101 and TFT 102 can be applied.
　図４９には、ＴＦＴ１０１およびＴＦＴ１０２を適用した信号発生回路ＧＳＣの構成を示す。図４９に示されるように信号発生回路ＧＳＣは、クロック信号ＣＬＫが駆動トランジスタ１０３のソース電極に供給される。駆動トランジスタ１０３のドレイン電極は、駆動トランジスタ１０４のソース電極に接続され、駆動トランジスタ１０４のドレイン電極には接地電位ＶＳＳが与えられる。駆動トランジスタ１０３および１０４間の接続ノードＮ１は、保持容量Ｃ１を介して駆動トランジスタ１０３のゲート電極および駆動トランジスタ１０５のドレイン電極に接続されている。駆動トランジスタ１０５のソース電極には電源電位ＶＤＤが供給される。駆動トランジスタ１０３および１０４間の接続ノードＮ１は、信号発生回路ＧＳＣの出力ノードであり、ここから対応するゲート配線３２に走査信号が供給される。 FIG. 49 shows the configuration of the signal generation circuit GSC to which the TFT 101 and the TFT 102 are applied. As shown in FIG. 49, in the signal generation circuit GSC, the clock signal CLK is supplied to the source electrode of the drive transistor 103. The drain electrode of the drive transistor 103 is connected to the source electrode of the drive transistor 104, and the ground potential VSS is given to the drain electrode of the drive transistor 104. The connection node N1 between the drive transistors 103 and 104 is connected to the gate electrode of the drive transistor 103 and the drain electrode of the drive transistor 105 via the holding capacitance C1. The power supply potential VDD is supplied to the source electrode of the drive transistor 105. The connection node N1 between the drive transistors 103 and 104 is an output node of the signal generation circuit GSC, from which a scan signal is supplied to the corresponding gate wiring 32.
　駆動トランジスタ１０５のゲート電極に供給される駆動信号によって、駆動トランジスタ１０５がオンすると、駆動トランジスタ１０３がオンされてクロック信号ＣＬＫが接続ノードＮ１から出力される。他方、駆動トランジスタ１０４のゲート電極に供給される駆動信号によって駆動トランジスタ１０４がオンすると、接続ノードＮ１の電位は接地電位ＶＳＳに固定される。 When the drive transistor 105 is turned on by the drive signal supplied to the gate electrode of the drive transistor 105, the drive transistor 103 is turned on and the clock signal CLK is output from the connection node N1. On the other hand, when the drive transistor 104 is turned on by the drive signal supplied to the gate electrode of the drive transistor 104, the potential of the connection node N1 is fixed to the ground potential VSS.
　ここで、信号発生回路ＧＳＣの構成要素である駆動トランジスタ１０３および１０５の構成は、実施の形態２および実施の形態３およびその変形例のＴＦＴ１０１およびＴＦＴ１０２と同じ構成とすることができるため、これらの構成を適宜変形することによって、実施の形態２および実施の形態３およびその変形例と同様の効果を得ることができる。これらの信号発生回路ＧＳＣの構成は、自発光型表示装置用だけではなく、液晶（Liquid Crystal）を利用した液晶表示装置用のＴＦＴ基板にも好適に用いることが可能である。 Here, since the configurations of the drive transistors 103 and 105, which are the components of the signal generation circuit GSC, can be the same as those of the TFTs 101 and 102 of the second embodiment, the third embodiment, and the modifications thereof. By appropriately modifying the configuration, the same effects as those of the second embodiment, the third embodiment, and the modified examples thereof can be obtained. The configuration of these signal generation circuits GSC can be suitably used not only for a self-luminous display device but also for a TFT substrate for a liquid crystal display device using a liquid crystal (Liquid Crystal).
　さらに、本開示は、表示装置用のＴＦＴ基板に限らず、他にも例えば同様のトランジスタの構成を有するシフトレジスタ回路を備えた半導体装置にも適用することが可能であり、これらの開示の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形することも可能である。 Further, the present disclosure is not limited to the TFT substrate for the display device, and can be applied to other semiconductor devices including, for example, a shift register circuit having a similar transistor configuration, and the scope of these disclosures. Within, each embodiment can be freely combined, and each embodiment can be appropriately modified.
　以上説明した実施の形態１～３およびその変形例においては、半導体層９および半導体層１０を構成する半導体膜として、Ｉｎ、ＧａおよびＺｎを含むＩｎＧａＺｎＯ系の酸化物半導体を適用した構成を説明した。一般的に半導体層に金属膜または合金膜で構成されるソース電極およびドレイン電極を接続する場合、例えばａ－Ｓｉ半導体膜では接続界面にオーミックコンタクト層、例えばリン（Ｐ）をドープした低抵抗Ｓｉ膜を設ける必要があった。 In the first to third embodiments described above and modifications thereof, a configuration in which an InGaZnO-based oxide semiconductor containing In, Ga and Zn is applied as the semiconductor film constituting the semiconductor layer 9 and the semiconductor layer 10 has been described. .. Generally, when a source electrode and a drain electrode composed of a metal film or an alloy film are connected to a semiconductor layer, for example, in an a—Si semiconductor film, an ohmic contact layer, for example, phosphorus (P)-doped low resistance Si is doped in the connection interface. It was necessary to provide a film.
　一方、酸化物半導体膜は、金属膜および合金膜との直接的な電気接続が可能である。このため、本開示のように、ソース電極１５およびドレイン電極１６が半導体層９の上面（表面）に設けられるＴＦＴ１０１と、ソース電極３およびドレイン電極４が半導体層１０の下面（裏面）に設けられるＴＦＴ１０２とが同時に配設されるような構成の場合は、半導体層として酸化物半導体膜を用いるのが好ましい。 On the other hand, the oxide semiconductor film can be directly electrically connected to the metal film and the alloy film. Therefore, as in the present disclosure, the TFT 101 in which the source electrode 15 and the drain electrode 16 are provided on the upper surface (front surface) of the semiconductor layer 9 and the source electrode 3 and the drain electrode 4 are provided on the lower surface (back surface) of the semiconductor layer 10. In the case of a configuration in which the TFT 102 and the TFT 102 are arranged at the same time, it is preferable to use an oxide semiconductor film as the semiconductor layer.
　酸化物半導体材料としては、ＩｎＧａＺｎＯ酸化物半導体に限ることはなく、例えば、Ｉｎ、Ｇａ、Ｚｎを適宜組み合わせた酸化物半導体であるＩｎ－Ｏ、Ｇａ－Ｏ、Ｚｎ－Ｏ、Ｉｎ－Ｚｎ－Ｏ、Ｉｎ－Ｇａ－ＯおよびＧａ－Ｚｎ－Ｏなどの金属酸化物を用いることができる。また、これらの金属酸化物以外にも、例えばハフニウム（Ｈｆ）、すず（Ｓｎ）、イットリウム（Ｙ）、アルミニウム（Ａｌ）等の酸化物を適宜組み合わせた酸化物半導体を適用することも可能である。 The oxide semiconductor material is not limited to InGaZnO oxide semiconductor, and for example, In—O, Ga—O, Zn—O, In—Zn—O, which are oxide semiconductors in which In, Ga, and Zn are appropriately combined. , In—Ga—O and Ga—Zn—O and other metal oxides can be used. In addition to these metal oxides, oxide semiconductors in which oxides such as hafnium (Hf), tin (Sn), yttrium (Y), and aluminum (Al) are appropriately combined can also be applied. ..
　また、酸化物半導体に限らず、１３族のＡｌ、Ｇａ、Ｉｎから選ばれる元素と１５族の窒素（Ｎ）、リン（Ｐ）、ヒ素（Ａｓ）、アンチモン（Ｓｂ）から選ばれる元素とを組み合わせた、いわゆるＩＩＩ－Ｖ族の化合物半導体、例えば、Ｇａ－Ａｓ、Ｇａ－Ｐ、Ｉｎ－Ｐ、Ｉｎ－Ｓｂ、Ｉｎ－Ａｓ、Ａｌ－Ｎ、Ｇａ－Ｎ、Ａｌ－Ｇａ－Ｎあるいはこれらに他の元素を添加した半導体材料を用いてもよい。 Further, not limited to oxide semiconductors, elements selected from Group 13 Al, Ga, and In and elements selected from Group 15 nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb) can be used. Combined so-called Group III-V compound semiconductors, such as Ga-As, Ga-P, In-P, In-Sb, In-As, Al-N, Ga-N, Al-Ga-N or these. A semiconductor material to which other elements have been added may be used.
　さらに、１４族の半導体元素である炭素（Ｃ）を用いたカーボンナノチューブおよびグラフェン、およびこれらにＳｉおよびＧｅ元素を組み合わせた半導体材料を用いることも可能である。 Furthermore, it is also possible to use carbon nanotubes and graphene using carbon (C), which is a group 14 semiconductor element, and a semiconductor material in which Si and Ge elements are combined with these.
　以上のような半導体材料を半導体層９および半導体層１０に用いた場合でも、実施の形態１～３およびその変形例で説明した本開示の効果を得ることが可能である。特に酸化物半導体、化合物半導体または炭素系半導体のようにプロセスダメージの影響を大きく受けると考えられる材料の場合には大きな効果を得ることができる。 Even when the above-mentioned semiconductor materials are used for the semiconductor layer 9 and the semiconductor layer 10, the effects of the present disclosure described in the first to third embodiments and the modifications thereof can be obtained. In particular, a large effect can be obtained in the case of a material that is considered to be greatly affected by process damage, such as an oxide semiconductor, a compound semiconductor, or a carbon-based semiconductor.
　上記した説明は、すべての局面において、例示であって、この開示がそれに限定されるものではない。例示されていない無数の変形例が、この開示の範囲から外れることなく想定され得るものと解される。 The above explanation is an example in all aspects, and this disclosure is not limited thereto. It is understood that a myriad of variants not illustrated can be envisioned without departing from the scope of this disclosure.
　なお、本開示は、その開示の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。 In the present disclosure, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted within the scope of the disclosure.

Claims (11)

  1. 　基板と、
    　前記基板上に設けられた、ボトムゲート型の第１の薄膜トランジスタと、
    　トップゲート型の第２の薄膜トランジスタと、を少なくとも備え、
    　前記第１の薄膜トランジスタは、
    　前記基板上に設けられた第１のゲート電極と、
    　前記第１のゲート電極上に設けられた第１のゲート絶縁層と、
    　前記第１のゲート絶縁層上に設けられた第１の半導体層と、
    　前記第１の半導体層上に設けられた第１の保護絶縁層と、
    　前記第１の保護絶縁層を貫通する第１の開口部および第２の開口部を通して前記第１の半導体層にそれぞれ接する、第１のソース電極および第１のドレイン電極と、を有し、
    　前記第２の薄膜トランジスタは、
    　前記基板上に設けられた第２のソース電極および第２のドレイン電極と、
    　前記第２のソース電極および前記第２のドレイン電極上に設けられた第２の保護絶縁層と、
    　前記第２の保護絶縁層上に設けられ、それぞれ前記第２の保護絶縁層を貫通する第３の開口部および第４の開口部を通して、前記第２のソース電極および前記第２のドレイン電極に接する第２の半導体層と、
    　前記第２の半導体層上に設けられた第２のゲート絶縁層と、
    　前記第２のゲート絶縁層上に設けられた第２のゲート電極と、を有し、
    　前記第１のゲート電極、前記第２のソース電極および前記第２のドレイン電極は、同層で同じ第１の導電膜で形成され、
    　前記第１のゲート絶縁層および前記第２の保護絶縁層は、同層で同じ第１の絶縁膜で形成され、
    　前記第１の半導体層および前記第２の半導体層は、同層で同じ半導体膜で形成され、
    　前記第１の保護絶縁層および前記第２のゲート絶縁層は、同層で同じ第２の絶縁膜で形成され、
    　前記第１のソース電極、前記第１のドレイン電極および第２のゲート電極は、同層で同じ第２の導電膜で形成される、薄膜トランジスタ基板。     With the board
    A bottom gate type first thin film transistor provided on the substrate,
    At least equipped with a top gate type second thin film transistor,
    The first thin film transistor
    The first gate electrode provided on the substrate and
    The first gate insulating layer provided on the first gate electrode and
    The first semiconductor layer provided on the first gate insulating layer and
    The first protective insulating layer provided on the first semiconductor layer and
    It has a first source electrode and a first drain electrode that are in contact with the first semiconductor layer through a first opening and a second opening that penetrate the first protective insulating layer, respectively.
    The second thin film transistor
    A second source electrode and a second drain electrode provided on the substrate,
    A second protective insulating layer provided on the second source electrode and the second drain electrode, and
    Through the third opening and the fourth opening provided on the second protective insulating layer and penetrating the second protective insulating layer, the second source electrode and the second drain electrode are formed. The second semiconductor layer in contact with
    A second gate insulating layer provided on the second semiconductor layer and
    It has a second gate electrode provided on the second gate insulating layer, and has.
    The first gate electrode, the second source electrode, and the second drain electrode are formed of the same first conductive film in the same layer.
    The first gate insulating layer and the second protective insulating layer are formed of the same first insulating film in the same layer.
    The first semiconductor layer and the second semiconductor layer are formed of the same semiconductor film in the same layer.
    The first protective insulating layer and the second gate insulating layer are formed of the same second insulating film in the same layer.
    A thin film transistor substrate in which the first source electrode, the first drain electrode, and the second gate electrode are formed of the same second conductive film in the same layer.
  2. 　少なくとも前記第１の薄膜トランジスタおよび前記第２の薄膜トランジスタを有した画素が前記基板上にマトリックス状に配置され、
    　前記画素は、
    　エレクトロルミネッセンス素子と、
    　互いに直交するソース配線およびゲート配線と、
    　前記ソース配線と平行し、前記エレクトロルミネッセンス素子に前記第１の薄膜トランジスタを介して駆動電流を供給する駆動電流配線と、
    　前記第１のソース電極、前記第１のドレイン電極および前記第２のゲート電極上に設けられた第３の保護絶縁層と、
    　前記第３の保護絶縁層上に設けられ、前記第３の保護絶縁層を貫通する第５の開口部を通して、前記第１のドレイン電極と接するアノード電極と、を備え、
    　前記エレクトロルミネッセンス素子は、前記アノード電極上に設けられ、
    　前記ソース配線および前記駆動電流配線は、同層で同じ前記第１の導電膜で形成され、前記第２のソース電極は前記ソース配線の一部として形成され、
    　前記第１のゲート電極と前記第２のドレイン電極は、連続した一体パターンで構成され、保持容量を形成する容量電極として機能し、
    　前記ゲート配線は、前記第２の導電膜で形成され、前記第２のゲート電極は前記ゲート配線から延在して形成され、
    　前記第１のソース電極と前記駆動電流配線は電気的に接続される、請求項１記載の薄膜トランジスタ基板。     Pixels having at least the first thin film transistor and the second thin film transistor are arranged in a matrix on the substrate.
    The pixel is
    With electroluminescence elements
    Source wiring and gate wiring that are orthogonal to each other,
    A drive current wiring that is parallel to the source wiring and supplies a drive current to the electroluminescence element via the first thin film transistor.
    A third protective insulating layer provided on the first source electrode, the first drain electrode, and the second gate electrode.
    An anode electrode provided on the third protective insulating layer and in contact with the first drain electrode through a fifth opening penetrating the third protective insulating layer is provided.
    The electroluminescence element is provided on the anode electrode and is provided.
    The source wiring and the drive current wiring are formed of the same first conductive film in the same layer, and the second source electrode is formed as a part of the source wiring.
    The first gate electrode and the second drain electrode are formed of a continuous integrated pattern and function as a capacitance electrode that forms a holding capacitance.
    The gate wiring is formed of the second conductive film, and the second gate electrode is formed extending from the gate wiring.
    The thin film transistor substrate according to claim 1, wherein the first source electrode and the drive current wiring are electrically connected.
  3. 　少なくとも前記第１の薄膜トランジスタおよび前記第２の薄膜トランジスタを有した画素が前記基板上にマトリックス状に配置され、
    　前記画素は、
    　発光ダイオード素子と、
    　互いに直交するソース配線およびゲート配線と、
    　前記ソース配線と平行し、前記発光ダイオード素子に前記第１の薄膜トランジスタを介して電気的に接続される第１の配線と、
    　前記ゲート配線と平行し、前記発光ダイオード素子に電気的に接続される第２の配線と、
    　前記第１のソース電極、前記第１のドレイン電極および前記第２のゲート電極上に設けられた第３の保護絶縁層と、
    　前記第３の保護絶縁層上に設けられ、それぞれ前記第３の保護絶縁層を貫通する第５の開口部および第６の開口部を通して、前記第１のドレイン電極および前記第２の配線と接する第１の電極および第２の電極と、を備え、
    　前記発光ダイオード素子は、前記第１および第２の電極上に設けられ、
    　前記ソース配線および前記第１の配線は、同層で同じ前記第１の導電膜で形成され、前記第２のソース電極は前記ソース配線の一部として形成され、
    　前記第１のゲート電極と前記第２のドレイン電極は、連続した一体パターンで構成され、保持容量を形成する容量電極として機能し、
    　前記ゲート配線および前記第２の配線は、前記第２の導電膜で形成され、前記第２のゲート電極は前記ゲート配線から延在して形成され、
    　前記第１のソース電極と前記第１の配線は電気的に接続される、請求項１記載の薄膜トランジスタ基板。     Pixels having at least the first thin film transistor and the second thin film transistor are arranged in a matrix on the substrate.
    The pixel is
    Light emitting diode element and
    Source wiring and gate wiring that are orthogonal to each other,
    A first wiring that is parallel to the source wiring and is electrically connected to the light emitting diode element via the first thin film transistor.
    A second wiring parallel to the gate wiring and electrically connected to the light emitting diode element,
    A third protective insulating layer provided on the first source electrode, the first drain electrode, and the second gate electrode.
    It is provided on the third protective insulating layer, and is in contact with the first drain electrode and the second wiring through a fifth opening and a sixth opening that penetrate the third protective insulating layer, respectively. With a first electrode and a second electrode,
    The light emitting diode element is provided on the first and second electrodes.
    The source wiring and the first wiring are formed of the same first conductive film in the same layer, and the second source electrode is formed as a part of the source wiring.
    The first gate electrode and the second drain electrode are formed of a continuous integrated pattern and function as a capacitance electrode that forms a holding capacitance.
    The gate wiring and the second wiring are formed of the second conductive film, and the second gate electrode is formed extending from the gate wiring.
    The thin film transistor substrate according to claim 1, wherein the first source electrode and the first wiring are electrically connected.
  4. 　前記第１のゲート電極および前記第２のドレイン電極は、
    　連続した一体パターンで構成される、請求項１記載の薄膜トランジスタ基板。     The first gate electrode and the second drain electrode are
    The thin film transistor substrate according to claim 1, which is composed of a continuous integrated pattern.
  5. 　前記第２のゲート電極は、
    　平面視で、前記第２のソース電極および前記第２のドレイン電極と重ならないように設けられる、請求項１記載の薄膜トランジスタ基板。     The second gate electrode is
    The thin film transistor substrate according to claim 1, which is provided so as not to overlap the second source electrode and the second drain electrode in a plan view.
  6. 　前記半導体膜は、金属酸化物を含む酸化物半導体膜で構成される、請求項１記載の薄膜トランジスタ基板。 The thin film transistor substrate according to claim 1, wherein the semiconductor film is composed of an oxide semiconductor film containing a metal oxide.
  7. 　前記第１のドレイン電極は、前記容量電極の上方に前記第２の絶縁膜を介して設けられ、
    　前記保持容量は、
    　前記容量電極と前記第１のドレイン電極との間に形成される、請求項２または請求項３記載の薄膜トランジスタ基板。     The first drain electrode is provided above the capacitance electrode via the second insulating film.
    The holding capacity is
    The thin film transistor substrate according to claim 2 or 3, which is formed between the capacitance electrode and the first drain electrode.
  8. 　前記第１のソース電極は、前記容量電極の上方に前記第２の絶縁膜を介して設けられ、
    　前記保持容量は、
    　前記容量電極と前記第１のソース電極との間に形成される、請求項２または請求項３記載の薄膜トランジスタ基板。     The first source electrode is provided above the capacitive electrode via the second insulating film.
    The holding capacity is
    The thin film transistor substrate according to claim 2 or 3, which is formed between the capacitance electrode and the first source electrode.
  9. 　前記第１のドレイン電極は、前記容量電極の上方に前記第２のゲート絶縁層を介して設けられ、
    　前記第１のソース電極は、前記容量電極の上方に前記第２のゲート絶縁層を介して設けられ、
    　前記保持容量は、
    　前記容量電極と前記第１のドレイン電極との間に形成される第１の保持容量と、
    　前記容量電極と前記第１のソース電極との間に形成される第２の保持容量と、を含む、請求項２または請求項３記載の薄膜トランジスタ基板。     The first drain electrode is provided above the capacitance electrode via the second gate insulating layer.
    The first source electrode is provided above the capacitive electrode via the second gate insulating layer.
    The holding capacity is
    A first holding capacitance formed between the capacitance electrode and the first drain electrode, and
    The thin film transistor substrate according to claim 2 or 3, further comprising a second holding capacitance formed between the capacitive electrode and the first source electrode.
  10. 　前記第１の保護絶縁層は、
    　前記第１の薄膜トランジスタの前記第１の開口部と前記第２の開口部との間において、前記第１の半導体層の第１のチャネル領域を保護する第１のチャネル保護層として機能し、
    　前記第２の保護絶縁層は、
    　前記第２の薄膜トランジスタの前記第３の開口部と前記第４の開口部との間において、前記第２の半導体層の第２のチャネル領域を保護する第２のチャネル保護層として機能する、請求項１記載の薄膜トランジスタ基板。     The first protective insulating layer is
    Between the first opening and the second opening of the first thin film transistor, it functions as a first channel protection layer that protects the first channel region of the first semiconductor layer.
    The second protective insulating layer is
    A claim that functions as a second channel protection layer that protects a second channel region of the second semiconductor layer between the third opening and the fourth opening of the second thin film transistor. Item 1. The thin film transistor substrate according to item 1.
  11. 　請求項２または請求項３記載の薄膜トランジスタ基板を備えた表示装置。 A display device including the thin film transistor substrate according to claim 2 or 3.
PCT/JP2020/006233 2020-02-18 2020-02-18 Thin film transistor substrate and display device WO2021166067A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2020/006233 WO2021166067A1 (en) 2020-02-18 2020-02-18 Thin film transistor substrate and display device
JP2020536705A JP6806956B1 (en) 2020-02-18 2020-02-18 Thin film transistor substrate and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/006233 WO2021166067A1 (en) 2020-02-18 2020-02-18 Thin film transistor substrate and display device

Publications (1)

Publication Number Publication Date
WO2021166067A1 true WO2021166067A1 (en) 2021-08-26

Family

ID=73992978

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2020/006233 WO2021166067A1 (en) 2020-02-18 2020-02-18 Thin film transistor substrate and display device

Country Status (2)

Country Link
JP (1) JP6806956B1 (en)
WO (1) WO2021166067A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023033960A (en) * 2021-08-30 2023-03-13 シャープディスプレイテクノロジー株式会社 Active matrix substrate and method for manufacturing the same
WO2023148852A1 (en) * 2022-02-02 2023-08-10 シャープディスプレイテクノロジー株式会社 Display device and production method for display device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114335015A (en) * 2021-12-28 2022-04-12 Tcl华星光电技术有限公司 Display device and manufacturing method thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008102214A (en) * 2006-10-17 2008-05-01 Toshiba Matsushita Display Technology Co Ltd Active matrix type display device
JP2010016126A (en) * 2008-07-02 2010-01-21 Fujifilm Corp Thin film field effect transistor, fabrication process therefor, and display device using the same
JP2011023695A (en) * 2009-07-15 2011-02-03 Samsung Mobile Display Co Ltd Organic electroluminescence display device and method of manufacturing the same
WO2011142147A1 (en) * 2010-05-13 2011-11-17 シャープ株式会社 Circuit board and display device
JP2012049556A (en) * 2011-10-14 2012-03-08 Sony Corp Thin film transistor and manufacturing method therefor, and electronic apparatus
JP2014059531A (en) * 2012-09-19 2014-04-03 Toshiba Corp Display device
JP2019216236A (en) * 2019-05-15 2019-12-19 堺ディスプレイプロダクト株式会社 Organic el display device and manufacturing method of the organic el display device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8822995B2 (en) * 2008-07-24 2014-09-02 Samsung Display Co., Ltd. Display substrate and method of manufacturing the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008102214A (en) * 2006-10-17 2008-05-01 Toshiba Matsushita Display Technology Co Ltd Active matrix type display device
JP2010016126A (en) * 2008-07-02 2010-01-21 Fujifilm Corp Thin film field effect transistor, fabrication process therefor, and display device using the same
JP2011023695A (en) * 2009-07-15 2011-02-03 Samsung Mobile Display Co Ltd Organic electroluminescence display device and method of manufacturing the same
WO2011142147A1 (en) * 2010-05-13 2011-11-17 シャープ株式会社 Circuit board and display device
JP2012049556A (en) * 2011-10-14 2012-03-08 Sony Corp Thin film transistor and manufacturing method therefor, and electronic apparatus
JP2014059531A (en) * 2012-09-19 2014-04-03 Toshiba Corp Display device
JP2019216236A (en) * 2019-05-15 2019-12-19 堺ディスプレイプロダクト株式会社 Organic el display device and manufacturing method of the organic el display device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023033960A (en) * 2021-08-30 2023-03-13 シャープディスプレイテクノロジー株式会社 Active matrix substrate and method for manufacturing the same
JP7437359B2 (en) 2021-08-30 2024-02-22 シャープディスプレイテクノロジー株式会社 Active matrix substrate and its manufacturing method
WO2023148852A1 (en) * 2022-02-02 2023-08-10 シャープディスプレイテクノロジー株式会社 Display device and production method for display device

Also Published As

Publication number Publication date
JPWO2021166067A1 (en) 2021-08-26
JP6806956B1 (en) 2021-01-06

Similar Documents

Publication Publication Date Title
US7696518B2 (en) Flat panel display with anode electrode layer as power supply layer and fabrication method thereof
JP6262276B2 (en) Oxide thin film transistor and method for manufacturing the same
USRE48032E1 (en) Thin-film semiconductor substrate, light-emitting panel, and method of manufacturing the thin-film semiconductor substrate
US7311577B2 (en) Organic electroluminescent device with pixel regions and dummy pixel regions and method or fabricating the same
US6998770B2 (en) Organic electroluminescent device and fabricating method thereof
US9252268B2 (en) Array substrate for display device
US11056509B2 (en) Display device having a plurality of thin-film transistors with different semiconductors
US8405084B2 (en) Organic light emitting diode display and method for manufacturing the same
US20160240604A1 (en) Organic light emitting display devices and methods of manufacturing organic light emitting display devices
US8822995B2 (en) Display substrate and method of manufacturing the same
KR101878187B1 (en) Organic light emitting display and fabricating method thereof
JP6806956B1 (en) Thin film transistor substrate and display device
KR101878186B1 (en) Organic light emitting display and fabricating method thereof
US11495652B2 (en) Organic light emitting diode display device and method of manufacturing organic light emitting diode display device
US11839110B2 (en) Organic light-emitting display device
US8378946B2 (en) Display device
WO2021062640A1 (en) Electronic base plate and manufacturing method therefor, and display panel
US20080197354A1 (en) Thin film transistor, an organic light emitting device including the same, and a manufacturing method thereof
US12120915B2 (en) Display device with driving transistor having upper and lower gate electrodes
KR101429908B1 (en) Organic electroluminescence device
KR101475313B1 (en) Method of fabricating array substrate
JP2022085303A (en) Thin film transistor substrate and self-light-emitting device
WO2024176379A1 (en) Display device, and method for manufacturing same
KR20130027023A (en) Display device, thin film transistor used in the display device, and method for manufacturing the thin film transistor
US20240021695A1 (en) Semiconductor device

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2020536705

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20919575

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20919575

Country of ref document: EP

Kind code of ref document: A1