WO2021160089A1 - Panneau d'affichage et dispositif d'affichage - Google Patents

Panneau d'affichage et dispositif d'affichage Download PDF

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Publication number
WO2021160089A1
WO2021160089A1 PCT/CN2021/076022 CN2021076022W WO2021160089A1 WO 2021160089 A1 WO2021160089 A1 WO 2021160089A1 CN 2021076022 W CN2021076022 W CN 2021076022W WO 2021160089 A1 WO2021160089 A1 WO 2021160089A1
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WO
WIPO (PCT)
Prior art keywords
display
area
substrate
splicing
light
Prior art date
Application number
PCT/CN2021/076022
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English (en)
Chinese (zh)
Inventor
陶洪
徐苗
周雷
李民
李洪濛
徐华
陈子楷
邹建华
王磊
彭俊彪
Original Assignee
华南理工大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华南理工大学 filed Critical 华南理工大学
Publication of WO2021160089A1 publication Critical patent/WO2021160089A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Definitions

  • the present application relates to the field of display technology, for example, to a display panel and a display device.
  • the display panel and the display device formed by splicing a single display unit have a problem that the non-display area occupies a relatively large area.
  • the present application provides a display panel and a display device, which solves the problem of a relatively large non-display area in the display panel and display device spliced by a single display unit in the related art.
  • an embodiment of the present application provides a display panel, including:
  • each of the display units includes a carrier board, the carrier board includes a display carrying area and a splicing area located on at least one side of the display carrying area;
  • the light-emitting unit circuit layer is located on the surface of the substrate on the side away from the substrate, and includes at least one bonding pad;
  • At least one drive chip is located on the substrate extending out of the display carrying area of the carrier, on the surface on the side far from the circuit layer of the light-emitting unit or located in the splicing area, and is connected to the substrate through a conductive connection layer located on the side of the substrate At least one of the pads is electrically connected.
  • the carrier board includes a first splicing area located on a first side of the display carrying area, and at least a part of the substrate extends out of the display carrying area of the carrier board and a second splicing area disposed opposite to the first side. side.
  • the carrier board includes a second splicing area located on the second side of the display bearing area and a third splicing area located on the third side of the display bearing area, and the extension direction of the second splicing area is vertical In the extension direction of the third splicing area;
  • At least a part of the substrate extends out of a fourth side that is opposite to the second side and/or a fifth side that is opposite to the third side of the display bearing area of the carrier plate.
  • the included angle between the side surface of the substrate adjacent to the splicing area and the first surface of the carrier board is greater than or equal to 30 degrees and less than or equal to 70 degrees.
  • it further comprises at least one first groove located on the surface of the substrate extending out of the display carrying area of the carrier and away from the circuit layer of the light-emitting unit;
  • the driving chip is located in the first groove, is flush with the surface of the substrate on the side away from the circuit layer of the light-emitting unit, and is electrically connected to the pad through a conductive connection layer located on the side of the substrate.
  • it further includes at least one second groove located on the first surface of the splicing area, and the driving chip is located in the second groove, which is flat with the first surface or the second surface of the splicing area.
  • the first surface and the second surface are arranged opposite to each other, and the first surface is the first surface of the carrier board. ;or,
  • It also includes at least one conductive via located in the splicing area, the driving chip is located on the second surface of the splicing area, and the conductive connection layer extends to the first surface of the splicing area through the conductive via It is electrically connected with the driving chip.
  • the conductive connection layer includes one or more conductive film layers.
  • the light-emitting unit circuit layer further includes a metal circuit layer, and the metal circuit layer includes a plurality of data lines, a plurality of scan lines, and a light-emitting unit determined by each data line and each scan line.
  • the first electrode of the unit is electrically connected to the data line
  • the second electrode of the light-emitting unit is electrically connected to the scan line;
  • the data line and the scan line are electrically connected to the pads, respectively.
  • the carrier board includes a printed circuit board; and/or, the substrate includes glass.
  • an embodiment of the present application provides a display device, including the display panel described in any of the first aspect.
  • the light-emitting unit circuit layer is located on the surface of the substrate on the side away from the carrier, and the pads of the light-emitting unit circuit layer pass through the conductive connection layer on the side of the substrate and the substrate located in the display carrying area extending from the carrier.
  • the surface far away from the circuit layer of the light-emitting unit or the driving chip located in the splicing area is electrically connected.
  • the driving chip is located on the substrate extending from the display carrying area of the carrier board, on the surface on the side away from the circuit layer of the light-emitting unit or located in the splicing area, and does not occupy a part of the display area of the substrate.
  • the splicing of two adjacent display units can be completed in the following manner: two adjacent display units, one of the display units, and a part of the substrate extending from the carrier board is placed in the splicing area of the previous display unit.
  • the splicing gap between the display units is eliminated, and in the process of realizing a large-size display panel, the area ratio between the display area where multiple display units are spliced and the entire display panel is increased, and the production cost is reduced.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • FIG. 2 is a schematic structural diagram of another display panel provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a display unit provided by an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of another display unit provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of yet another display unit provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of another display unit provided by an embodiment of the application.
  • FIG. 7 is a schematic structural diagram of another display unit provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of a circuit layer of a light-emitting unit provided by an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of another light-emitting unit circuit layer provided by an embodiment of the application.
  • An embodiment of the present application provides a display panel. See FIGS. 1 and 2.
  • the display panel is formed by splicing multiple display units, at least two display units 1, and each display unit 1 includes: a carrier board 10, a carrier board 10 includes a display carrying area A1 and a splicing area A2 located on at least one side of the display carrying area A1; the substrate 20 is located on the first surface 100 of the carrier board 10 and is located in the display carrying area, and at least a part of the substrate 20 extends out of the carrier board 10 Display carrying area A1; light-emitting unit circuit layer, located on the surface of the substrate on the side away from the carrier, including at least one pad; at least one driving chip, located on the substrate extending from the display carrying area of the carrier, away from the side of the light-emitting unit circuit layer The surface of or is located in the splicing area, and is electrically connected to at least one pad through a conductive connection layer located on the side of the substrate.
  • FIG. 1 exemplarily shows two display units 1
  • the carrier board 10 includes a display bearing area A1, and a splicing area A2 located on one side of the display bearing area A1
  • FIG. 2 exemplarily shows
  • the four display units 1 and the carrier board 10 include a display carrying area A1 and a splicing area A2 located on both sides of the display carrying area A1.
  • the light-emitting unit circuit layer is located on the surface of the substrate 20 away from the carrier 10, and the pads of the light-emitting unit circuit layer pass through the conductive connection layer on the side of the substrate and the substrate located in the display carrying area extending from the carrier.
  • the surface far away from the circuit layer of the light-emitting unit or the driving chip located in the splicing area is electrically connected.
  • the driving chip is located on the substrate extending out of the display carrying area of the carrier, on the surface on the side away from the circuit layer of the light-emitting unit or located in the splicing area, and does not occupy part of the area of the substrate 20 for display.
  • two adjacent display units 1 can be spliced in the following manner: Referring to FIG. 1 and FIG. Placed in the mosaic area A2 of the previous display unit 1.
  • the display panel in the related art and the driving chip of the light-emitting unit circuit layer are often arranged on the carrier board, occupying the area of the display screen, resulting in a relatively small area ratio between the display area of a single display unit and the carrier board of the entire display unit Therefore, during the splicing process of the multiple display units, a splicing gap occupied by the driving circuit appears, which further causes the area ratio between the display area of the splicing of the multiple display units and the entire display panel to be relatively small.
  • the light-emitting unit circuit layer is located on the surface of the substrate on the side away from the carrier, and the pads of the light-emitting unit circuit layer pass through the conductive connection layer on the side of the substrate and the substrate located in the display carrying area extending from the carrier.
  • the surface far away from the circuit layer of the light-emitting unit or the driving chip located in the splicing area is electrically connected.
  • the driving chip is located on the substrate extending out of the display carrying area of the carrier, on the surface on the side away from the circuit layer of the light-emitting unit or located in the splicing area, and does not occupy part of the area of the substrate 20 for display.
  • the splicing of two adjacent display units 1 can be completed in the following manner: referring to Figs. 1 and 2, two adjacent display units 1, one of the display units 1 extending out of the carrier board 10 and a part of the substrate 20 placed on the previous display unit 1 of the splicing area A2.
  • the splicing gap between the display units 1 is eliminated, and in the process of realizing a large-size display panel, the area ratio between the display area of the multiple display units 1 and the entire display panel is increased, and the production cost is reduced.
  • the carrier 10 includes a first splicing area A21 located on the first side of the display carrying area A2, and at least part of the substrate 20 extends out of the display carrying area A1 and the second display carrying area A1 of the carrier. One side opposite to the second side.
  • two adjacent display units 1 can be spliced in the following way: two adjacent display units 1, one of the display units 1, and a part of the substrate 20 extending from the carrier board 10 is placed in the first splicing area of the previous display unit 1. A21.
  • the carrier board 10 includes a second splicing area A22 located on the second side of the display bearing area A1 and a third splicing area A23 located on the third side of the display bearing area A1 ,
  • the extension direction of the second splicing area A22 is perpendicular to the extension direction of the third splicing area A23; at least part of the substrate 20 extends out of the fourth side of the display carrying area A1 of the carrier board 10 opposite to the second side and/or to the third The fifth side opposite to the side.
  • two adjacent display units 1 can be spliced in the following manner: two adjacent display units 1, one of the display units 1, and a part of the substrate 20 extending from the carrier board 10 is placed in the second splicing area of the previous display unit 1. A22 or the third splicing area A23.
  • the angle between the side surface of the substrate 20 adjacent to the splicing area A2 and the first surface 100 of the carrier board 10 is greater than or equal to 30 degrees and less than or equal to 70 degrees.
  • the angle ⁇ 1 between the first side surface 201 of the substrate 20 adjacent to the second splicing area A22 and the first surface 100 of the carrier board 10 is greater than or equal to 30 degrees and less than or equal to 70 degrees; and/or, the angle ⁇ 2 between the second side 202 of the substrate 20 adjacent to the third splicing area A23 and the first surface 100 of the carrier board 10 is greater than or equal to 30 degrees, And less than or equal to 70 degrees.
  • the conductive connection layer 50 prepared by the solution processing method using a conductive solution is located on the first side surface 201 of the substrate 20 adjacent to the second splicing area A22 and the second side surface 202 adjacent to the third splicing area A23, and the first surface 100 of the carrier board 10
  • the included angle ⁇ 1 and/or ⁇ 2 is less than or equal to 70 degrees, and the first side surface 201 of the substrate 20 adjacent to the second splicing area A22 and the second side surface 202 of the substrate 20 adjacent to the third splicing area A23 can carry well
  • a conductive connection layer 50 of good quality can be prepared, so that during the splicing process of multiple display units 1, there will be no splicing gaps between adjacent display units 1.
  • the area ratio between the display area of the multiple display units and the entire display panel is increased, and the production cost is reduced.
  • ⁇ 1 and/or ⁇ 2 are less than 30 degrees, the thickness of the conductive connection layer 50 is too thin, which is not conducive to the production of the light-emitting unit circuit layer 40 on the surface of the substrate 20 away from the carrier board 10.
  • a third side surface of the substrate 20 opposite to the first side surface 201 is provided in parallel with the first side surface; and/or, the substrate 20 and the second side surface
  • the fourth side surface 202 opposite to the second side surface is parallel to the second side surface.
  • the display unit shown in FIG. 4 is taken as an example for description. See FIG.
  • the surface of the substrate 20 on the side away from the circuit layer 40 of the light-emitting unit; the drive chip 30 is located in the first groove 11, flush with the surface of the substrate 20 on the side away from the circuit layer 40 of the light-emitting unit, and is connected by a conductive connection on the side of the substrate 20
  • the layer 50 is electrically connected to the pad 41.
  • the light-emitting unit circuit layer is located on the surface of the substrate on the side away from the carrier.
  • the pad 41 of the light-emitting unit circuit layer 40 passes through the conductive connection layer 50 on the side of the substrate 20 and the substrate 20 located in the display carrying area A1 extending from the carrier 10,
  • the driving chip 30 on the surface on the side away from the circuit layer 40 of the light-emitting unit is electrically connected.
  • the driving chip 30 is located on the substrate 20 extending out of the display carrying area A1 of the carrier board 10, on the surface of the side away from the circuit layer 40 of the light-emitting unit, and does not occupy a part of the display area of the substrate 20.
  • the display unit shown in FIG. 4 is taken as an example for description, referring to FIG.
  • the driving chip 30 is located in the second groove 12, and is flush with the first surface or the second surface of the second splicing area A22 and the third splicing area A23 in the splicing area.
  • the conductive connection layer 50 on the side of the substrate 20 is electrically connected to at least one pad 41.
  • the first surface and the second surface are arranged opposite to each other.
  • the first surface is the first surface of the carrier board 10; the light-emitting unit circuit layer 40 is located on the substrate away from the carrier board.
  • the pad 41 of the light-emitting unit circuit layer 40 is electrically connected by the driving chip 30 in the second groove 12 of the second splicing area A22 and the third splicing area A23 in the splicing area.
  • the driving chip 30 is located in the second groove 12 of the second splicing area A22 and the third splicing area A23 in the splicing area, and does not occupy a part of the display area of the substrate 20.
  • the display unit shown in FIG. 4 is taken as an example for description. See FIG.
  • the driver chip 30 is located on the second surface of the second splicing area A22 and the third splicing area A23 in the splicing area, and the conductive connection layer 50 extends to the second splicing area A22 and the third splicing area A23 in the splicing area
  • the first surface is electrically connected to the driving chip 30 through the conductive via 13.
  • the light-emitting unit circuit layer is located on the surface of the substrate on the side away from the carrier, the pad 41 and the conductive via 13 of the light-emitting unit circuit layer 40 and the second surface of the second splicing area A22 and the third splicing area A23 located in the splicing area
  • the driving chip 30 is electrically connected. Wherein, the driving chip 30 is located on the second surface of the second splicing area A22 and the third splicing area A23 in the splicing area, and does not occupy a partial area of the substrate 20 for display.
  • the conductive connection layer 50 includes one or more conductive film layers.
  • the preparation process of the conductive connection layer 50 is as follows: select a conductive solution: a conductive ink containing Ag, Au, Cu, Al and other nanoparticles, or a conductive paste formed by Ag, Cu, Au, Al and other nanoparticles and a high molecular polymer.
  • the pad 41 and the connection pad of the drive chip 30 are used as the target connection point to make a conductive solution.
  • a conductive connection is made Layer 50.
  • the solution processing method in this embodiment is not limited to the inkjet printing method, spraying method, and screen printing method.
  • the conductive solution in this embodiment is not limited to conductive inks containing Ag, Au, Cu, Al and other nanoparticles, or conductive pastes formed by Ag, Cu, Au, Al and other nanoparticles and high molecular polymers.
  • the conductive connection layer 50 prepared by the solution processing method using a conductive solution is used to electrically connect the pad 41 and the connection pad of the driving chip 30.
  • the adjacent There are splicing gaps between the display units 1.
  • the thickness of the conductive connection layer 50 may be 20 nm-2000 nm.
  • the light-emitting unit circuit layer 40 further includes a metal circuit layer 42, and the metal circuit layer 42 includes a plurality of data lines 420, a plurality of scan lines 421, and each data line 420.
  • This driving scheme is called PM driving scheme.
  • the metal circuit layer 42 further includes a signal input circuit layer and a light-emitting drive circuit layer.
  • the signal input circuit layer is electrically connected to the data line 420 and the scan line 421, and the signal input circuit layer is used for Provide a driving power signal for the light-emitting drive circuit layer, and the light-emitting drive circuit layer is used to drive the light-emitting unit to emit light.
  • the signal input circuit layer includes a first thin film transistor T1 and a capacitor C
  • the light-emitting driving circuit layer includes a second thin film transistor T2.
  • the first thin film transistor T1 and the second thin film transistor T2 are both P-type thin film transistors. This driving scheme is called AM driving scheme.
  • the thin film transistors T1 and T2 may be one or more of metal oxide semiconductor thin film transistors, amorphous silicon thin film transistors, and low temperature polysilicon thin film transistors.
  • a thin film transistor array is fabricated, and pads 41 for driving wires are reserved in the display area, and then the light-emitting unit 422 is fabricated.
  • the substrate 20 is removed from the carrier, aligned, and placed on the carrier 10.
  • the silver paste is printed on the display bearing area A1 of the carrier board 10 through the inkjet printing method, and the silver paste is electrically connected to the driving chip 30 through the conductive connection layer 50.
  • the thickness of the substrate 20 is greater than or equal to 5 micrometers and less than or equal to 30 micrometers.
  • the substrate 20 less than 5 microns is not enough to support the light-emitting unit circuit layer 40; the thickness of the substrate 20 is greater than 30 microns, which will cause the weight of the entire display panel to be too large.
  • the light emitting unit 422 includes an organic light emitting diode or an inorganic light emitting diode, where the inorganic light emitting diode includes a micro light emitting diode and/or a mini light emitting diode.
  • Mini LEDs and/or mini LEDs are small in size, can reduce the pixel pitch from millimeters to micrometers, and have the advantages of self-luminescence, high brightness, low power consumption, high color gamut, etc., so that the display panel can display high-quality At the same time of the picture, the production cost is reduced.
  • the carrier board 10 includes a carrier board including a printed circuit board.
  • the substrate 20 includes glass.
  • the thickness of the glass may be 0.3-1 mm.
  • the embodiment of the present application also provides a display device. Since the display device provided in this embodiment adopts the above-mentioned display panel, the display device also has the same effect as the above-mentioned display panel.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

L'invention concerne un panneau d'affichage et un dispositif d'affichage. Le panneau d'affichage comprend : au moins deux unités d'affichage (1), chaque unité d'affichage (1) comprenant une plaque de support (10), et la plaque de support (10) comprenant une zone de support d'affichage et une zone de mosaïque positionnée sur au moins un côté de la zone de support d'affichage ; un substrat (20) positionné sur une première surface (100) de la plaque de support (10) et positionné sur la zone de support d'affichage, au moins une partie du substrat (20) s'étendant hors de la zone de support d'affichage de la plaque de support (10) ; une couche de circuit d'unité électroluminescente (40) positionnée sur la surface du substrat (20) sur le côté qui est éloigné de la plaque de support (10) et comprenant au moins une pastille (41) ; et au moins une puce d'attaque (30) positionnée sur le substrat (20) s'étendant hors de la zone d'appui d'affichage de la plaque d'appui (10) ou sur la surface sur le côté éloigné de la couche de circuit d'unité électroluminescente (40) ou sur la zone de mosaïque, et électriquement connectée à la ou aux pastilles (41) au moyen d'une couche de connexion conductrice (50) positionnée sur une surface latérale du substrat (20).
PCT/CN2021/076022 2020-02-14 2021-02-08 Panneau d'affichage et dispositif d'affichage WO2021160089A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010092723.4A CN111276474B (zh) 2020-02-14 2020-02-14 显示面板以及显示装置
CN202010092723.4 2020-02-14

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WO2021160089A1 true WO2021160089A1 (fr) 2021-08-19

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CN111276474B (zh) * 2020-02-14 2023-11-03 华南理工大学 显示面板以及显示装置
CN212380069U (zh) * 2020-06-22 2021-01-19 重庆康佳光电技术研究院有限公司 一种拼接显示装置
CN114141162B (zh) * 2021-12-07 2024-03-15 惠州华星光电显示有限公司 一种显示屏拼接方法及拼接显示屏
US11862051B2 (en) 2022-03-02 2024-01-02 Tcl China Star Optoelectronics Technology Co., Ltd. Display panel and light board
CN114488620B (zh) * 2022-03-02 2023-05-30 Tcl华星光电技术有限公司 显示面板和灯板
CN114627773B (zh) * 2022-03-11 2024-02-20 武汉华星光电半导体显示技术有限公司 拼接显示面板

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CN209265903U (zh) * 2018-11-08 2019-08-16 深圳市瑞丰光电子股份有限公司 一种光源组件、背光模组和显示模组及其显示装置
CN110379314A (zh) * 2019-07-23 2019-10-25 深圳市华星光电半导体显示技术有限公司 一种无缝拼接屏
CN111081158A (zh) * 2019-12-30 2020-04-28 深圳市华星光电半导体显示技术有限公司 拼接式显示屏及其制备方法、显示装置
CN111261057A (zh) * 2020-02-14 2020-06-09 华南理工大学 显示面板以及显示装置
CN111276474A (zh) * 2020-02-14 2020-06-12 华南理工大学 显示面板以及显示装置

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CN113745211A (zh) * 2021-08-31 2021-12-03 惠科股份有限公司 显示组件和显示装置

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