WO2021159664A1 - 像素电路、像素电路的驱动方法和显示面板 - Google Patents

像素电路、像素电路的驱动方法和显示面板 Download PDF

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Publication number
WO2021159664A1
WO2021159664A1 PCT/CN2020/103431 CN2020103431W WO2021159664A1 WO 2021159664 A1 WO2021159664 A1 WO 2021159664A1 CN 2020103431 W CN2020103431 W CN 2020103431W WO 2021159664 A1 WO2021159664 A1 WO 2021159664A1
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Prior art keywords
module
gate
terminal
pixel circuit
driving
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PCT/CN2020/103431
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English (en)
French (fr)
Inventor
徐苗
周雷
李民
李洪濛
徐华
陈子楷
邹建华
王磊
彭俊彪
陶洪
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South China University of Technology SCUT
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South China University of Technology SCUT
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Priority to US17/798,539 priority Critical patent/US11670227B2/en
Publication of WO2021159664A1 publication Critical patent/WO2021159664A1/zh
Anticipated expiration legal-status Critical
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element

Definitions

  • the embodiments of the present application relate to the field of display technology, such as a pixel circuit, a driving method of the pixel circuit, and a display panel.
  • Micro-Light Emitting Diode (Micro-LED) display devices can miniaturize the size of light-emitting diodes (LEDs), and have higher performance than organic light-emitting diode (OLED) display devices.
  • LEDs light-emitting diodes
  • OLED organic light-emitting diode
  • the Micro-LED works at low current density, the luminous efficiency is low.
  • the light-emitting wavelength is different from the light-emitting wavelength when the grayscale is high, which causes the color shift problem of the display color of the Micro-LED display device.
  • the Micro-LED display device displays, it can use a pulse width modulation (PWM) signal with a digital driving method to drive its light through the power supply, so as to improve the color shift problem of the display color of the Micro-LED display device.
  • PWM pulse width modulation
  • the data signal and the PWM signal of the power supply need to be accurately synchronized, which makes the design of the driving circuit for driving the Micro-LED to emit light very complicated.
  • the present application provides a pixel circuit, a driving method of the pixel circuit, and a display panel, so as to reduce the design complexity of the driving circuit on the basis of improving the color shift of the display panel.
  • an embodiment of the present application provides a pixel circuit, including a data writing module, a storage module, a driving module, and a light emitting device;
  • the driving module includes a first control terminal and a second control terminal.
  • the data writing module is used to write data signals into the first control terminal of the driving module during the data writing stage;
  • the storage module is used to maintain The potential of the first control terminal;
  • the second control terminal is electrically connected to the pulse width modulation signal input terminal of the pixel circuit, and is used to control the driving module to input the pulse width modulation signal input terminal in the light-emitting phase
  • the pulse width modulation signal provides a discontinuous drive current, and the light emitting device emits light in response to the drive current.
  • the embodiments of the present application also provide a method for driving a pixel circuit.
  • the pixel circuit includes a data writing module, a storage module, a driving module, and a light emitting device.
  • the driving module includes a first control terminal and a second control terminal. Control terminal; the method includes:
  • the data writing module of the pixel circuit writes a data signal into the first control terminal of the driving module of the pixel circuit; the storage module maintains the voltage of the first control terminal of the driving module;
  • the second control terminal of the driving module controls the driving module to provide a discontinuous driving current according to the pulse width modulation signal input from the pulse width modulation signal input terminal of the pixel circuit, and the light emitting device responds to the driving The current glows.
  • an embodiment of the present application also provides a display panel, including the pixel circuit provided in any embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a pixel circuit in the related art
  • Figure 2 is a graph showing the relationship between current and luminous efficiency of a light-emitting diode in the related art
  • FIG. 3 is a schematic structural diagram of a pixel circuit provided by an embodiment of the application.
  • Figure 4 is a schematic diagram of the structure of a dual-gate N-type transistor
  • 5 is a schematic diagram of the current of the dual-gate N-type transistor when different constant bias voltages are applied to the top gate of the dual-gate N-type transistor;
  • FIG. 6 is a schematic diagram of the transfer curve of the top gate of the dual-gate N-type transistor with different constant bias voltages applied;
  • FIG. 7 is a schematic diagram of the current of the dual-gate N-type transistor when different constant bias voltages are applied to the bottom gate of the dual-gate N-type transistor;
  • FIG. 8 is a schematic diagram of the transfer curve of the bottom gate of the dual-gate N-type transistor with different constant bias voltages applied;
  • FIG. 9 is a schematic diagram of the transfer curve of the top gate of the dual-gate N-type transistor with different constant bias voltages when the thickness of the second gate insulating layer is 500 nm;
  • FIG. 10 is a schematic diagram of the transfer curve of the bottom gate of the dual-gate N-type transistor with different constant bias voltages when the thickness of the second gate insulating layer is 500 nm;
  • FIG. 11 is a schematic diagram of the transfer curve of the top gate of the double-gate N-type transistor with different constant bias voltages when the thickness of the first gate insulating layer is 150 nm;
  • FIG. 12 is a schematic diagram of the transfer curve of the bottom gate of the dual-gate N-type transistor with different constant bias voltages when the thickness of the first gate insulating layer is 150 nm;
  • FIG. 13 is a schematic diagram of the transfer curve of the top gate of the double-gate N-type transistor with different constant bias voltages when the material of the first gate insulating layer is SiNx/SiO2;
  • FIG. 14 is a schematic diagram of the transfer curve of the bottom gate of the dual-gate N-type transistor with different constant bias voltages when the material of the first gate insulating layer is SiNx/SiO2;
  • Figure 15 shows that the material of the first gate insulating layer is CYTOP, the thickness is 300nm, the thickness of the active layer is 20nm, and the material of the second gate insulating layer is PDMS, the top gate of the double-gate N-type transistor is 600nm thick.
  • Figure 16 shows that the material of the first gate insulating layer is CYTOP, the thickness is 300nm, the thickness of the active layer is 20nm, the material of the second gate insulating layer is PDMS, and the bottom gate of the double-gate N-type transistor is 600nm thick.
  • FIG. 17 is a schematic diagram of the transfer characteristic curve of a dual-gate N-type transistor
  • FIG. 18 is a schematic diagram of a relationship curve between light intensity and current of a PWM signal modulated light-emitting device with a 1% duty cycle according to an embodiment of the application;
  • FIG. 19 is a schematic structural diagram of another pixel circuit provided by an embodiment of the application.
  • FIG. 20 is a timing diagram of the pixel circuit of FIG. 19;
  • FIG. 21 is a schematic structural diagram of another pixel circuit provided by an embodiment of the application.
  • FIG. 22 is a timing diagram corresponding to the pixel circuit of FIG. 21;
  • FIG. 23 is a schematic structural diagram of another pixel circuit provided by an embodiment of the application.
  • FIG. 24 is a timing diagram corresponding to the pixel circuit of FIG. 23;
  • FIG. 25 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the application.
  • FIG. 26 is a display panel provided by an embodiment of the application.
  • FIG. 1 is a schematic structural diagram of a pixel circuit in the related art.
  • the pixel circuit includes a switching transistor M1, a driving transistor M2, a storage capacitor c1, and a light emitting diode D1.
  • the gate of the switching transistor M1 is electrically connected to the scan signal line scan
  • the first electrode of the switching transistor M1 is electrically connected to the data line data
  • the second electrode of the switching transistor M1 is connected to the gate of the driving transistor M2 and the first electrode of the storage capacitor c1
  • the first electrode of the driving transistor M2 and the second electrode of the storage capacitor c1 are electrically connected to the first power signal line Vdd
  • the second electrode of the driving transistor M2 is electrically connected to the anode of the light emitting diode D1
  • the cathode of the light emitting diode D1 is electrically connected to The second power signal line Vss is electrically connected.
  • Fig. 2 is a graph showing the relationship between current and luminous efficiency of a light-emitting diode in the related art.
  • the abscissa is the current I flowing through the light-emitting diode
  • the ordinate is the luminous efficiency of the light-emitting diode.
  • the light-emitting efficiency of the light-emitting diode is relatively low, and the light-emitting wavelength is different from the high gray scale, which is likely to cause problems such as low light-emitting efficiency and color shift of the light-emitting diode.
  • the power supply can be used as a PWM signal to drive the light-emitting diode D1 to emit light with a digital driving method.
  • the light-emitting diode D1 works under the condition of high gray scale and high brightness. The problems of low luminous efficiency and color drift of the light-emitting diodes are avoided.
  • the light-emitting time of the light-emitting diode can be controlled by the PWM signal of the power supply. Due to the visual pause effect of the human eye, the brightness integral felt by the human eye within a frame time (including 12 sub-frames) is the actual gray-scale brightness of the pixel.
  • a frame can be divided into multiple sub-frames according to the gray scale, and the light-emitting brightness of the low-level gray scale is relatively small, and the corresponding sub-frame time is relatively short, and the light-emitting brightness of the high-level gray scale is relatively large, and the corresponding sub-frame time is relatively long.
  • the data signal and the PWM signal of the power supply need to be accurately synchronized, which makes the design of the driving circuit for driving the pixel circuit very complicated and increases the manufacturing cost of the display panel.
  • FIG. 3 is a schematic structural diagram of a pixel circuit provided by an embodiment of the application.
  • the pixel circuit includes a data writing module 110, a storage module 120, a driving module 130, and a light emitting device 140;
  • the driving module 130 includes a first control terminal 131 and a second control terminal 132, and the data writing module 110 is provided with To write data signals into the first control terminal 131 of the driving module 130 during the data writing stage;
  • the storage module 120 is set to maintain the potential of the first control terminal 131; the second control terminal 132 and the pulse width modulation signal input terminal of the pixel circuit
  • the Vpwm is electrically connected and configured to control the driving module 130 to provide a discontinuous driving current according to the pulse width modulation signal input from the pulse width modulation signal input terminal Vpwm during the light-emitting phase, and the light-emitting device 140 emits light in response to the driving current.
  • the first control terminal 131 of the driving module 130 receives the data signal during the data writing phase, and maintains the data voltage of the first control terminal 131 through the storage module 120.
  • the second control terminal 132 inputs the PWM signal of the pulse width modulation signal input terminal Vpwm.
  • the PWM signal has a first level and a second level.
  • the first level and the second level of the PWM signal directly affect the transfer characteristic curve of the driving module 130, so that the driving module 130 is in an on or off state when the PWM signal outputs different levels.
  • the driving module 130 may include a dual gate N-type transistor.
  • Fig. 4 is a schematic diagram of the structure of a dual-gate N-type transistor. As shown in FIG.
  • the dual-gate N-type transistor sequentially includes a substrate 401, a bottom gate 402, a first gate insulating layer 403, an active layer 404, a second gate insulating layer 405, a top gate 406, and a passivation layer. 407 and the source and drain electrode layer 408.
  • the substrate 401 may be glass.
  • the bottom gate 402, the top gate 406, and the drain electrode layer 408 are all formed by patterning a conductive layer.
  • the conductive layer can be molybdenum (Mo), aluminum (Al), silver (Ag), titanium (Ti), copper (Cu), indium tin oxide (Indium Tin Oxide, ITO), indium doped zinc oxide (Indium doped Zinc Oxide, IZO), Ag nanowires, carbon nanotubes, graphene conductive films, etc.
  • the conductive layer can be a single layer or a stacked layer.
  • the active layer 404 may be a lanthanide-doped metal oxide semiconductor layer, the first gate insulating layer 403.
  • the second gate insulating layer 405 and the passivation layer 407 can be inorganic insulating layers such as silicon dioxide (SiO2), silicon nitride (SiNx) or aluminum oxide (AlOx), or other organic insulating layers, and each layer can be Single layer or laminated structure.
  • the threshold voltage of the double-gate N-type transistor can be adjusted by adjusting the material and thickness of the first gate insulating layer 403 and the second gate insulating layer 405.
  • C ACT V gate2 when the voltage of the capacitor, C ACT V gate2 is applied to the top gate depletion of the active layer, C GI2 capacitance, C GI1 is a second gate insulating layer capacitance of the first gate insulating layer. This indicates the charge coupling effect between the bottom gate 402 and the top gate 406 when the channel of the dual-gate N-type transistor is completely depleted.
  • Table 1 shows the materials and thickness of each layer of a dual-gate N-type transistor.
  • Table 1 shows the materials and thickness of each layer of a dual-gate N-type transistor.
  • Table 1 shows the materials and thickness of each layer of a dual-gate N-type transistor.
  • Table 5 is a schematic diagram of the current of a dual-gate N-type transistor when different constant bias voltages are applied to the top gate of the dual-gate N-type transistor.
  • the abscissa is the voltage V G applied to the top gate and the ordinate is the current of the dual-gate N-type transistor. I DS . Fig.
  • FIG. 6 is a schematic diagram of the transfer curve of the top gate of the double-gate N-type transistor with different constant bias voltages applied, wherein the abscissa is the constant bias value V top of the top-gate of the double-gate N-type transistor, and the ordinate is the double-gate N-type
  • the change value of the threshold voltage of the transistor, the theoretical value is the threshold voltage change value calculated by formula (1), and the experimental value is the threshold voltage change value obtained in the experiment.
  • the constant voltage of the top grid is -20V to 20V
  • the step is 5V for a test record point.
  • the threshold voltage of the dual-gate N-type transistor When a negative constant voltage is applied to the top gate, the threshold voltage of the dual-gate N-type transistor will move in parallel to the positive direction; when a positive constant voltage is applied to the top gate, its threshold voltage will move in parallel to the negative direction. And from the comparison of the theoretical value and the experimental value in FIG. 6, the threshold voltage variation value obtained by the experimental test is very close to the theoretical value.
  • the formula (1) is applicable to the relationship between the threshold voltage of the dual-gate N-type transistor and the bias voltage of the top gate.
  • FIG. 7 is a schematic diagram of the current of a dual-gate N-type transistor when different constant bias voltages are applied to the bottom gate of a dual-gate N-type transistor, where the abscissa is the voltage V G applied to the bottom gate, and the ordinate is the current of the dual-gate N-type transistor I DS .
  • FIG. 7 is a schematic diagram of the current of a dual-gate N-type transistor when different constant bias voltages are applied to the bottom gate of a dual-gate N-type transistor, where the abscissa is the voltage V G applied to the bottom gate, and the ordinate is the current of the dual-gate N-type transistor I DS .
  • FIG. 8 is a schematic diagram of the transfer curve of the bottom gate of the dual-gate N-type transistor with different constant bias voltages applied, where the abscissa is the constant bias value V bottom of the bottom gate of the dual-gate N-type transistor, and the ordinate is the dual-gate N-type transistor
  • the change value of the threshold voltage of the transistor the theoretical value is the threshold voltage change value calculated by formula (1), and the experimental value is the threshold voltage change value obtained in the experiment.
  • the change rule of the threshold voltage is the same as the change rule of a different constant bias voltage applied to the top gate. It can be seen that an effective spatial alternating electric field is formed between the top gate and the bottom gate of the double-gate N-type transistor.
  • the cumulative effect of electrons in the front channel will change. That is, under the condition of applying a negative constant voltage, the vertically distributed spatial electric field will increase, so that more electrons are captured by the insulating layer/active layer interface, which in turn causes the threshold voltage of the dual-gate N-type transistor to be more positive; When a positive constant voltage is applied, the vertically distributed spatial electric field will be weakened, resulting in a negative threshold voltage of the dual-gate N-type transistor.
  • Table 2 shows the material and thickness of each layer of another dual-gate N-type transistor.
  • the difference from Table 1 is that the thickness of the second gate insulating layer is 500 nm.
  • 9 is a schematic diagram of the transfer curve of the top gate of the double-gate N-type transistor with different constant bias voltage when the thickness of the second gate insulating layer is 500 nm, where the abscissa is the constant bias voltage of the top gate of the double-gate N-type transistor
  • the value V top the ordinate is the change value of the threshold voltage of the dual-gate N-type transistor, the theoretical value is the change value of the threshold voltage calculated by formula (1), and the experimental value is the change value of the threshold voltage obtained in the experiment. It can be seen from FIG.
  • the threshold voltage of the double-gate N-type transistor with a second gate insulating layer with a thickness of 500 nm is less than the threshold voltage of a double-gate N-type transistor with a second gate insulating layer with a thickness of 300 nm.
  • the vertical electric field generated from the top gate to the bottom gate will be significantly weakened.
  • FIG. 10 is a schematic diagram of the transfer curve of the bottom gate of the double-gate N-type transistor with different constant bias voltage when the thickness of the second gate insulating layer is 500 nm, wherein the abscissa is the constant bias voltage of the bottom gate of the double-gate N-type transistor
  • the value V bottom the ordinate is the change value of the threshold voltage of the dual-gate N-type transistor
  • the theoretical value is the change value of the threshold voltage calculated by formula (1)
  • the experimental value is the change value of the threshold voltage obtained in the experiment.
  • the changing rule of the threshold voltage is the same as the changing rule of applying a different constant bias voltage to the top gate.
  • Table 3 shows the material and thickness of each layer of another dual-gate N-type transistor.
  • the difference from Table 1 is that the thickness of the first gate insulating layer is 150 nm.
  • 11 is a schematic diagram of the transfer curve of the top gate of the double-gate N-type transistor with different constant bias voltage when the thickness of the first gate insulating layer is 150 nm, where the abscissa is the constant bias voltage of the top gate of the double-gate N-type transistor
  • the value V top the ordinate is the change value of the threshold voltage of the dual-gate N-type transistor, the theoretical value is the change value of the threshold voltage calculated by formula (1), and the experimental value is the change value of the threshold voltage obtained in the experiment. It can be seen from FIG.
  • the threshold voltage of the dual-gate N-type transistor with a 150nm-thick first gate insulating layer is greater than the threshold voltage of a double-gate N-type transistor with a 200nm-thick first gate insulating layer, which indicates For the thinner first gate insulating layer, the vertical electric field generated from the top gate to the bottom gate will be significantly enhanced.
  • FIG. 12 is a schematic diagram of the transfer curve of the bottom gate of the double-gate N-type transistor with different constant bias voltage when the thickness of the first gate insulating layer is 150 nm, wherein the abscissa is the constant bias voltage of the bottom gate of the double-gate N-type transistor
  • the value V bottom the ordinate is the change value of the threshold voltage of the dual-gate N-type transistor
  • the theoretical value is the change value of the threshold voltage calculated by formula (1)
  • the experimental value is the change value of the threshold voltage obtained in the experiment.
  • the changing rule of the threshold voltage is the same as the changing rule of applying a different constant bias voltage to the top gate.
  • Table 4 shows the material and thickness of each layer of another dual-gate N-type transistor.
  • the difference from Table 1 is that the first gate insulating layer uses SiNx/SiO2 material.
  • 13 is a schematic diagram of the transfer curve of the top gate of the double-gate N-type transistor with different constant bias voltage when the material of the first gate insulating layer is SiNx/SiO2, where the abscissa is the constant of the top gate of the double-gate N-type transistor
  • the bias voltage value V top the ordinate is the change value of the threshold voltage of the double-gate N-type transistor, the theoretical value is the change value of the threshold voltage calculated by formula (1), and the experimental value is the change value of the threshold voltage obtained in the experiment. It can be seen from FIG.
  • the threshold voltage of the dual-gate N-type transistor with the first gate insulating layer of SiNx/SiO2 material is greater than the threshold voltage of the dual-gate N-type transistor with the first gate insulating layer of AlOx material. It shows that for the first gate insulating layer of silicon oxynitride material, the vertical electric field generated from the top gate to the bottom gate will be significantly enhanced.
  • FIG. 14 is a schematic diagram of the transfer curve of the bottom gate of the double-gate N-type transistor with different constant bias voltage when the material of the first gate insulating layer is SiNx/SiO2, wherein the abscissa is the bottom gate of the double-gate N-type transistor
  • the constant bias value Vbottom the ordinate is the change value of the threshold voltage of the dual-gate N-type transistor, the theoretical value is the change value of the threshold voltage calculated by formula (1), and the experimental value is the change value of the threshold voltage obtained in the experiment.
  • the changing rule of the threshold voltage is the same as the changing rule of applying a different constant bias voltage to the top gate.
  • Table 5 shows the materials and thickness of each layer of another dual-gate N-type transistor.
  • the material of the first gate insulating layer is CYTOP with a thickness of 300 nm
  • the thickness of the active layer is 20 nm
  • the material of the second gate insulating layer is polydimethylsiloxane (polydimethylsiloxane).
  • PDMS with a thickness of 600nm.
  • Figure 15 shows that the material of the first gate insulating layer is CYTOP, the thickness is 300nm, the thickness of the active layer is 20nm, and the material of the second gate insulating layer is PDMS, the top gate of the double-gate N-type transistor is 600nm thick.
  • a schematic diagram of the transfer curves of different constant bias voltages where the abscissa is the constant bias value V top of the top gate of the double-gate N-type transistor, and the ordinate is the change value of the threshold voltage of the double-gate N-type transistor.
  • the theoretical value is passed
  • the threshold voltage change value obtained by formula (1) is calculated, and the experimental value is the threshold voltage change value obtained by the test in the experiment. It can be seen from FIG. 15 that the first gate insulating layer with a thickness of 300nm and the material is CYTOP, and the thickness of the active layer is 20nm, the material of the second gate insulating layer is PDMS, and the thickness of the double-gate N-type transistor is 600nm.
  • the threshold voltage adjustment range is greater than the threshold voltage of the dual-gate N-type transistor in Table 1, which indicates that the vertical electric field generated by the dual-gate N-type transistor in Table 5 from the top gate to the bottom gate will be significantly enhanced.
  • Figure 16 shows that the material of the first gate insulating layer is CYTOP, the thickness is 300nm, the thickness of the active layer is 20nm, the material of the second gate insulating layer is PDMS, and the bottom gate of the double-gate N-type transistor is 600nm thick.
  • a schematic diagram of the transfer curves of different constant bias voltages where the abscissa is the constant bias value V bottom of the bottom gate of the double-gate N-type transistor, and the ordinate is the change value of the threshold voltage of the double-gate N-type transistor.
  • the theoretical value is passed
  • the threshold voltage change value obtained by formula (1) is calculated, and the experimental value is the threshold voltage change value obtained by the test in the experiment.
  • the changing rule of the threshold voltage is the same as the changing rule of applying a different constant bias voltage to the top gate.
  • FIG. 17 is a schematic diagram of the transfer characteristic curve of a dual-gate N-type transistor. Wherein, the abscissa is the voltage value written by the second gate, and the ordinate is the current of the dual-gate N-type transistor.
  • the threshold voltage of the double-gate N-type transistor shifts to the negative direction, that is, the threshold voltage of the double-gate N-type transistor decreases, so that the threshold voltage of the double-gate N-type transistor is reduced.
  • the voltage is less than the voltage difference between the gate and the source of the double-gate N-type transistor, and the double-gate N-type transistor is turned on to generate a driving current, thereby driving the light-emitting device 140 to emit light. From the current formula (2) of the double-gate N-type transistor, it can be seen that the lower the threshold voltage of the double-gate N-type transistor, the greater the current of the double-gate N-type transistor.
  • I OLED is the current flowing through the double-gate N-type transistor
  • ⁇ is the carrier mobility of the double-gate N-type transistor
  • W and L are the width and length of the channel of the double-gate N-type transistor, respectively
  • V GS is The voltage difference between the gate and source of the double-gate N-type transistor
  • V TH is the threshold voltage of the double-gate N-type transistor.
  • the threshold voltage of the double-gate N-type transistor shifts in the positive direction, that is, the threshold voltage of the double-gate N-type transistor increases, making the threshold voltage of the double-gate N-type transistor greater than that of the double-gate N-type transistor If the voltage difference between the gate and the source of the double-gate N-type transistor is cut off, that is, the driving current is not connected, and the light-emitting device 140 does not emit light. It can be seen that by adjusting the duty ratio of the PWM signal, the time during which the PWM signal is output at a high level can be adjusted, and thus the light-emitting time of the light-emitting device 140 can be adjusted.
  • the first control terminal 131 of the driving module 140 maintains the data voltage, so there is no need to synchronize the data voltage with the duty cycle of the PWM signal to control the light-emitting device 140 to emit light.
  • the design complexity of the driving circuit for driving the pixel circuit can be reduced, thereby reducing the manufacturing cost of the display panel.
  • the driving module 130 may also include a dual-gate P-type transistor.
  • the threshold voltage of the dual-gate P-type transistor shifts in the positive direction, that is, the threshold voltage of the dual-gate P-type transistor increases, making the threshold voltage of the dual-gate P-type transistor greater than that of the dual-gate P-type transistor Due to the voltage difference between the gate and the source of the double-gate P-type transistor, the driving current cannot be generated and the light-emitting device 140 does not emit light.
  • the threshold voltage of the dual-gate P-type transistor shifts in the reverse direction, that is, the threshold voltage of the dual-gate P-type transistor decreases, making the threshold voltage of the dual-gate P-type transistor smaller than that of the dual-gate P-type transistor. Due to the voltage difference between the gate and source of the transistor, the double-gate P-type transistor is turned on to generate a driving current, thereby driving the light-emitting device 140 to emit light.
  • FIG. 18 is a schematic diagram of a relationship curve between light intensity and current of a PWM signal modulated light emitting device with a duty ratio of 1% provided by an embodiment of the application.
  • the abscissa is the driving current I flowing through the light-emitting device
  • the ordinate is the luminous intensity L of the light-emitting device.
  • the curve L1L2 is the luminous intensity before the PWM signal modulates the light-emitting device
  • the curve L1'L2' is the luminous intensity after the PWM signal modulates the light-emitting device. It can be seen from the curve L1L2 and the curve L1'L2' that the light-emitting device works in the driving current area corresponding to the relatively high luminous efficiency and the stable light-emitting color, and then modulated by the PWM signal to make the light-emitting brightness of the light-emitting device correspond to the low current and low gray scale, thus achieving When the light-emitting device works in an area with high luminous efficiency and stable luminous color, the luminous brightness corresponding to different gray scales can be met.
  • the PWM signal is provided to the second control terminal of the driving module through the pulse width modulation signal input terminal, so that the driving module provides a discontinuous driving current to the light-emitting device, thereby controlling the light-emitting time of the light-emitting device.
  • the first control terminal of the driving module maintains the data voltage, so there is no need to synchronize the data voltage with the duty cycle of the PWM signal to control the light-emitting device to emit light, so driving pixels can be reduced
  • the design complexity of the driving circuit for the circuit operation further reduces the manufacturing cost of the display panel.
  • the light-emitting device works in the driving current region corresponding to the relatively high luminous efficiency and the stable light-emitting color.
  • the light-emitting brightness of the light-emitting device corresponds to low current and low grayscale, so that the light-emitting device works in high luminous efficiency and luminous color. Meet the luminous brightness corresponding to different gray scales in the stable area.
  • the first terminal of the data writing module 110 is electrically connected to the data signal input terminal Vdata of the pixel circuit, and the second terminal of the data writing module 110 is connected to the first control terminal 131 of the driving module 130 and the storage
  • the first terminal of the module 120 is electrically connected, the control terminal of the data writing module 110 is electrically connected to the scan signal input terminal Scan1 of the pixel circuit;
  • the first terminal of the driving module 130 is electrically connected to the first power signal input terminal VDD of the pixel circuit and the storage module
  • the second terminal of 120 is electrically connected, the second terminal of the driving module 130 is electrically connected to the anode of the light emitting device 140, and the cathode of the light emitting device 140 is electrically connected to the second power signal input terminal VSS of the pixel circuit.
  • the scan signal input terminal Scan1 of the pixel circuit controls the data signal input from the data signal input terminal Vdata to be written to the first control terminal 131 of the driving module 130 through the data writing module 110, and the first control terminal 131 of the driving module 130 is maintained through the storage module 120.
  • the scan signal input terminal Scan1 of the pixel circuit controls the data writing module 110 to stop writing the data voltage
  • the PWM signal at the pulse width modulation signal input terminal Vpwm controls the driving module 130 to provide a discontinuous current, thereby controlling the light-emitting device 140 to emit light time.
  • FIG. 19 is a schematic structural diagram of another pixel circuit provided by an embodiment of the application.
  • the data writing module 110 includes a first transistor T1
  • the storage module 120 includes a storage capacitor Cst
  • the driving module 130 includes a driving transistor Tdr;
  • the gate of the first transistor T1 is the control terminal of the data writing module 110.
  • the first terminal of a transistor T1 is the first terminal of the data writing module 110
  • the second terminal of the first transistor T1 is the second terminal of the data writing module 110
  • the first terminal of the storage capacitor Cst is the first terminal of the storage module 120
  • the second terminal of the storage capacitor Cst is the second terminal of the memory module 120
  • the driving transistor Tdr is a double-gate transistor.
  • the first terminal of the double-gate transistor drives the first terminal of the module 130
  • the second terminal of the double-gate transistor drives the first terminal of the module 130.
  • Two terminals; the bottom gate of the double-gate transistor is the first control terminal of the driving module 130
  • the top gate of the double-gate transistor is the second control terminal of the driving module 130
  • the top gate of the double-gate transistor is the first control terminal of the driving module 130
  • the control terminal, the bottom gate of the double-gate transistor is the second control terminal of the driving module 130.
  • FIG. 20 is a timing diagram of the pixel circuit of FIG. 19.
  • scan1 is the timing of the scan signal input from the scan signal input terminal Scan1
  • vdd is the timing of the first power signal input from the first power signal input terminal VDD
  • vss is the timing of the second power signal input from the second power signal input terminal VSS.
  • Timing pwm is the timing of the PWM signal input from the pulse width modulation signal input terminal Vpwm.
  • scan1 is at a high level, the first transistor T1 is controlled to be turned on, the data voltage is written to the gate of the driving transistor Tdr through the first transistor T1, and the data voltage is maintained through the storage capacitor Cst.
  • scan1 is at a high level, and the first transistor T1 is controlled to be turned off.
  • the first gate of the driving transistor Tdr is at a high level.
  • the driving transistor Tdr is turned on.
  • the driving transistor Tdr is in an off state. Therefore, the on-time of the driving transistor Tdr is controlled by controlling the duty ratio of the pwm signal, thereby controlling the time during which the driving transistor Tdr provides the driving current to the light-emitting device 140, thereby controlling the light-emitting time of the light-emitting device 140.
  • the driving current of the driving transistor Tdr is related to the magnitude of the data voltage. As shown in FIG. 19, when the driving transistor Tdr is an N-type transistor, the greater the data voltage, the greater the driving current output by the driving transistor Tdr, and the brighter the light-emitting brightness of the corresponding light-emitting device 140. The smaller the data voltage, the smaller the driving current output by the driving transistor Tdr, and the darker the light-emitting brightness of the corresponding light-emitting device 140.
  • FIG. 21 is a schematic structural diagram of another pixel circuit provided by an embodiment of the application.
  • the pixel circuit further includes a reset module 150; the control terminal of the reset module 150 is electrically connected to the scan signal input terminal Scan1 of the pixel circuit, and the first terminal of the reset module 150 is electrically connected to the reference signal input terminal Vref, The second end of the reset module 150 is electrically connected to the anode of the light emitting device 140; the reset module 150 is configured to reset the light emitting device 140.
  • the reset module 150 resets the anode of the light-emitting device 140 while the data writing module 110 writes the data voltage to the driving module 130, so as to avoid the voltage remaining after the light-emitting device 140 in the previous frame from affecting the light emission of the current frame.
  • the luminous brightness of the device 140 is the same as to be used for generating the light-emitting device 140.
  • the reset module 150 includes a second transistor T2; the gate of the second transistor T2 is the control terminal of the reset module 150, the first terminal of the second transistor T2 is the first terminal of the reset module 150, and the second transistor The second pole of T2 resets the second end of the module 150.
  • FIG. 22 is a timing diagram corresponding to the pixel circuit of FIG. 21, where vref is the timing of the reference signal provided by the reference signal input terminal Vref. The working process of the pixel circuit will be described with reference to FIG. 21 and FIG. 22.
  • scan1 is at a high level, and the first transistor T1 and the second transistor T2 are controlled to be turned on.
  • the data voltage is written to the gate of the driving transistor Tdr through the first transistor T1 and passes through the storage capacitor Cst. Maintain the data voltage.
  • the reference signal vref input from the reference signal input terminal Vref is written to the anode of the light emitting device 140 through the second transistor T2 to reset the light emitting device 140.
  • scan1 is at a high level, and the first transistor T1 and the second transistor T2 are controlled to be turned off.
  • the first gate of the driving transistor Tdr is at a high level.
  • the driving transistor Tdr is turned on.
  • the driving transistor Tdr is in an off state. Therefore, the on-time of the driving transistor Tdr is controlled by controlling the duty ratio of the pwm signal, thereby controlling the time during which the driving transistor Tdr provides the driving current to the light-emitting device 140, thereby controlling the light-emitting time of the light-emitting device 140.
  • FIG. 23 is a schematic structural diagram of another pixel circuit provided by an embodiment of the application.
  • the pixel circuit further includes a sensing module 160; the control terminal of the sensing module 160 is electrically connected to the sensing control signal input terminal SENSE of the pixel circuit, and the first terminal of the sensing module 160 is electrically connected to the anode of the light emitting device 140, The second end of the sensing module 160 is electrically connected to the sensing signal output terminal ISENSE; the sensing module 160 is set to sense the potential of the light emitting device 140.
  • the sensing control signal input terminal SENSE inputs the sensing control signal to control the sensing module 160 to be turned on, and the current of the driving module 130 is output to the sensing signal output terminal ISENSE, and is output to the outside through the sensing signal output terminal ISENSE
  • the external sensing circuit compensates the pixel circuit according to the current flowing through the driving module 130.
  • the sensing module includes a third transistor T3; the gate of the third transistor T3 is the control terminal of the sensing module 160, the first pole of the third transistor T3 is the first terminal of the sensing module 160, and the third transistor T3 The second pole is the second end of the sensing module 160.
  • FIG. 24 is a timing diagram corresponding to the pixel circuit of FIG. 23, where sense is the timing of the sensing control signal output by the sensing control signal input terminal SENSE. The working process of the pixel circuit will be described with reference to FIG. 23 and FIG. 24.
  • scan1 is at a high level, and the first transistor T1 and the second transistor T2 are controlled to be turned on.
  • the data voltage is written to the gate of the driving transistor Tdr through the first transistor T1 and passes through the storage capacitor Cst. Maintain the data voltage.
  • the reference signal vref input from the reference signal input terminal Vref is written to the anode of the light emitting device 140 through the second transistor T2 to reset the light emitting device 140.
  • the sensing control signal sense output by the sensing control signal input terminal SENSE is high, controlling the third transistor T3 to turn on, the current of the driving transistor Tdr is output to the external sensing circuit through the third transistor T3, and the external circuit passes the data Processing, adding a compensation signal to the data voltage, thereby improving the uniformity of light emission of the entire display panel.
  • scan1 is at a high level, and the first transistor T1 and the second transistor T2 are controlled to be turned off.
  • the first gate of the driving transistor Tdr is at a high level.
  • the driving transistor Tdr is turned on.
  • the driving transistor Tdr is in an off state. Therefore, the on-time of the driving transistor Tdr is controlled by controlling the duty ratio of the pwm signal, thereby controlling the time during which the driving transistor Tdr provides the driving current to the light-emitting device 140, thereby controlling the light-emitting time of the light-emitting device 140.
  • FIG. 25 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the application. As shown in FIG. 25, the method includes step S10 to step S20.
  • step S10 in the data writing stage, the data writing module of the pixel circuit writes the data signal into the first control terminal of the driving module of the pixel circuit; the storage module maintains the voltage of the first control terminal of the driving module.
  • step S20 in the light emitting phase, the second control terminal of the driving module controls the driving module to provide a discontinuous driving current according to the pulse width modulation signal input from the pulse width modulation signal input terminal of the pixel circuit, and the light emitting device emits light in response to the driving current.
  • the voltage of the first control terminal is maintained at the data Signal.
  • the PWM signal is provided to the second control terminal of the driving module in the light-emitting phase, so that the driving module provides a discontinuous driving current to the light-emitting device, thereby controlling the light-emitting time of the light-emitting device.
  • the first control terminal of the driving module maintains the data voltage, so there is no need to synchronize the data voltage with the duty cycle of the PWM signal to control the light-emitting device to emit light, so driving pixels can be reduced
  • the design complexity of the driving circuit for the circuit operation further reduces the manufacturing cost of the display panel.
  • the light-emitting device works in the driving current region corresponding to the relatively high luminous efficiency and the stable light-emitting color.
  • the light-emitting brightness of the light-emitting device corresponds to low current and low grayscale, so that the light-emitting device works in high luminous efficiency and luminous color. Meet the luminous brightness corresponding to different gray scales in the stable area.
  • FIG. 26 is a display panel provided by an embodiment of the application. As shown in FIG. 26, the display panel includes the pixel circuit 101 provided by any embodiment of the present application.
  • the display panel further includes a pulse width modulation signal line 210, a gate driving circuit 220, and a data driving circuit 230;
  • the pixel circuit 101 includes a scanning signal input terminal, a data signal input terminal, and a pulse width modulation signal input terminal; pulse width modulation
  • the signal line 210 is electrically connected to the pulse width modulation signal input terminal
  • the output terminal 221 of the gate driving circuit 220 is electrically connected to the scanning signal input terminal of the pixel circuit
  • the output terminal 231 of the data driving circuit 230 is electrically connected to the data signal input terminal of the pixel circuit. connect.
  • the pulse width modulation signal line 210 is configured to output a PWM signal and provide the PWM signal for the pulse width modulation signal input end of the pixel circuit.
  • the output terminal 221 of the gate driving circuit 220 is electrically connected to the scanning signal input terminal of the pixel circuit 101 through a scanning signal line to provide the pixel circuit 101 with a scanning signal row by row, so that the pixel circuit 101 is driven row by row.
  • the output terminal 231 of the data driving circuit 230 is electrically connected to the data signal input terminal of the pixel circuit 101 through a data signal line to provide the pixel circuit 101 with a data signal.
  • the pixel circuit 101 can communicate with the corresponding data signal line electrically connected to it under the action of the scanning signal input from the scanning signal line electrically connected to it, and the data signal line transmits the data signal to the corresponding pixel driving circuit 101, thereby realizing display The display function of the device.

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Abstract

一种像素电路、像素电路的驱动方法和显示面板。像素电路包括数据写入模块（110）、存储模块（120）、驱动模块（130）和发光器件（140）；驱动模块（130）包括第一控制端（131）和第二控制端（132），数据写入模块（110）设置为在数据写入阶段将数据信号(Vdata)写入驱动模块(130)的第一控制端(131)；存储模块(120)设置为维持第一控制端(131)的电位；第二控制端(132)与像素电路的脉冲宽度调制信号(Vpwm)输入端电连接，设置为控制驱动模块(130)在发光阶段根据脉冲宽度调制信号(Vpwm)输入端输入的脉冲宽度调制信号提供非连续驱动电流，发光器件(140)响应驱动电流发光。

Description

像素电路、像素电路的驱动方法和显示面板
本申请要求在2020年2月14日提交中国专利局、申请号为202010092739.5的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，例如一种像素电路、像素电路的驱动方法和显示面板。
背景技术
微发光二极管(Micro Light Emitting Diode，Micro-LED)显示装置由于可以将发光二极管(Light Emitting Diode，LED)的尺寸小型化，以及比有机发光二极管(Organic Light Emitting Diode，OLED)显示器件具有更高的发光亮度、发光效率以及更低的运行功耗等优势，逐渐受到人们的广泛关注。
Micro-LED在低电流密度下工作时，发光效率低。且发光波长与高灰阶时的发光波长不同，造成了Micro-LED显示装置显示颜色的色偏问题。Micro-LED显示装置显示时，可以通过电源采用脉冲宽度调制(Pulse Width Modulation，PWM)信号配合数字驱动方式驱动其发光，从而改善Micro-LED显示装置显示颜色的色偏问题。此时数据信号和电源的PWM信号需要精准同步，使得驱动Micro-LED发光的驱动电路设计十分复杂。
发明内容
本申请提供一种像素电路、像素电路的驱动方法和显示面板，以实现在改善显示面板色偏的基础上降低了驱动电路的设计复杂度。
第一方面，本申请实施例提供了一种像素电路，包括数据写入模块、存储模块、驱动模块和发光器件；
所述驱动模块包括第一控制端和第二控制端，所述数据写入模块用于在数据写入阶段将数据信号写入所述驱动模块的第一控制端；所述存储模块用于维持所述第一控制端的电位；所述第二控制端与所述像素电路的脉冲宽度调制信号输入端电连接，用于控制所述驱动模块在发光阶段根据所述脉冲宽度调制信号输入端输入的脉冲宽度调制信号提供非连续驱动电流，所述发光器件响应所述驱动电流发光。
第二方面，本申请实施例还提供了一种像素电路的驱动方法，所述像素电路包括数据写入模块、存储模块、驱动模块和发光器件，所述驱动模块包括第一控制端和第二控制端；所述方法包括：
在数据写入阶段，所述像素电路的数据写入模块将数据信号写入所述像素电路的驱动模块的第一控制端；所述存储模块维持所述驱动模块的第一控制端的电压；
在发光阶段，所述驱动模块的第二控制端控制所述驱动模块根据所述像素电路的脉冲宽度调制信号输入端输入的脉冲宽度调制信号提供非连续驱动电流，所述发光器件响应所述驱动电流发光。
第三方面，本申请实施例还提供了一种显示面板，包括本申请任意实施例提供的像素电路。
附图说明
图1为相关技术中的一种像素电路的结构示意图；
图2为相关技术中的一种发光二极管的电流与发光效率关系曲线图；
图3为本申请实施例提供的一种像素电路的结构示意图；
图4为一种双栅N型晶体管的结构示意图；
图5为双栅N型晶体管的顶栅施加不同的恒定偏压时双栅N型晶体管的电流示意图；
图6为双栅N型晶体管的顶栅施加不同的恒定偏压的转移曲线示意图；
图7为双栅N型晶体管的底栅施加不同的恒定偏压时双栅N型晶体管的电流示意图；
图8为双栅N型晶体管的底栅施加不同的恒定偏压的转移曲线示意图；
图9为第二栅极绝缘层的厚度为500nm时双栅N型晶体管的顶栅加不同的恒定偏压的转移曲线示意图；
图10为第二栅极绝缘层的厚度为500nm时双栅N型晶体管的底栅加不同的恒定偏压的转移曲线示意图；
图11为第一栅极绝缘层的厚度为150nm时双栅N型晶体管的顶栅加不同的恒定偏压的转移曲线示意图；
图12为第一栅极绝缘层的厚度为150nm时双栅N型晶体管的底栅加不同的恒定偏压的转移曲线示意图；
图13为第一栅极绝缘层的材料为SiNx/SiO2时双栅N型晶体管的顶栅加不同的恒定偏压的转移曲线示意图；
图14为第一栅极绝缘层的的材料为SiNx/SiO2时双栅N型晶体管的底栅加不同的恒定偏压的转移曲线示意图；
图15为第一栅极绝缘层的材料为CYTOP，厚度为300nm，有源层的厚度为20nm，第二栅极绝缘层的材料为PDMS，厚度为600nm时双栅N型晶体管的顶栅加不同的恒定偏压的转移曲线示意图；
图16为第一栅极绝缘层的材料为CYTOP，厚度为300nm，有源层的厚度为20nm，第二栅极绝缘层的材料为PDMS，厚度为600nm时双栅N型晶体管的底栅加不同的恒定偏压的转移曲线示意图；
图17为双栅N型晶体管的转移特性曲线示意图；
图18为本申请实施例提供的一种占空比为1％的PWM信号调制发光器件的光强与电流的关系曲线示意图；
图19为本申请实施例提供的另一种像素电路的结构示意图；
图20为图19的像素电路的一种时序图；
图21为本申请实施例提供的另一种像素电路的结构示意图；
图22为图21的像素电路对应的一种时序图；
图23为本申请实施例提供的另一种像素电路的结构示意图；
图24为图23的像素电路对应的一种时序图；
图25为本申请实施例提供的像素电路的驱动方法的流程图；
图26为本申请实施例提供的一种显示面板。
具体实施方式
图1为相关技术中的一种像素电路的结构示意图。如图1所示，该像素电路包括开关晶体管M1、驱动晶体管M2、存储电容c1和发光二极管D1。开关晶体管M1的栅极与扫描信号线scan电连接，开关晶体管M1的第一极与数据线data电连接，开关晶体管M1的第二极与驱动晶体管M2的栅极和存储电容c1的第一极电连接，驱动晶体管M2的第一极和存储电容c1的第二极与第一电源信号线Vdd电连接，驱动晶体管M2的第二极与发光二极管D1的阳极电连接，发光二极管D1的阴极与第二电源信号线Vss电连接。图2为相关技术中的一种发光二极管的电流与发光效率关系曲线图。其中，横坐标为流过发光二极管的电流I，纵坐标为发光二极管的发光效率。如图2所示，在发光二极管工作在低电流的情况下，发光二极管的发光效率比较低，且发光波长与高灰阶也不同，容易造成发光二极管的发光效率低和颜色漂移等问题。因此可以采用电源为PWM信号，配合数字驱动方式驱动发光二极管D1发光。在采用数字驱动方式驱动发光二极管D1发光的过程中，发光二极管D1工作在高灰阶高亮度的条件下。避免了发光二极管的发光效率低和颜色漂移等问题。另外，可以通过电源的PWM信号控制发光二极管的发光时间。由于人眼的视觉暂停效应，人眼在一帧时间内(包含12个子帧)感受到的亮度积分，就为该像素的实际灰阶亮度。 因此可以根据灰阶将一帧分为多个子帧，并且低位灰阶的发光亮度比较小，对应的子帧的时间比较短，高位灰阶的发光亮度比较大，对应的子帧时间比较长。在控制每一子帧发光时，数据信号和电源的PWM信号需要精准同步，从而使得驱动像素电路工作的驱动电路设计十分复杂，增加了显示面板的制作成本。
本申请实施例提供了一种像素电路。图3为本申请实施例提供的一种像素电路的结构示意图。如图3所示，该像素电路包括数据写入模块110、存储模块120、驱动模块130和发光器件140；驱动模块130包括第一控制端131和第二控制端132，数据写入模块110设置为在数据写入阶段将数据信号写入驱动模块130的第一控制端131；存储模块120设置为维持第一控制端131的电位；第二控制端132与像素电路的脉冲宽度调制信号输入端Vpwm电连接，设置为控制驱动模块130在发光阶段根据脉冲宽度调制信号输入端Vpwm输入的脉冲宽度调制信号提供非连续驱动电流，发光器件140响应驱动电流发光。
示例性地，驱动模块130的第一控制端131在数据写入阶段接收数据信号，并通过存储模块120维持第一控制端131的数据电压。第二控制端132输入脉冲宽度调制信号输入端Vpwm的PWM信号。PWM信号的具有第一电平和第二电平。且PWM信号的第一电平和第二电平直接影响驱动模块130的转移特性曲线，从而使得驱动模块130在PWM信号输出不同的电平时分别处于导通或关断状态。示例性地，驱动模块130可以包括双栅N型晶体管。图4为一种双栅N型晶体管的结构示意图。如图4所示，该双栅N型晶体管依次包括衬底401、底栅402、第一栅极绝缘层403、有源层404、第二栅极绝缘层405、顶栅406、钝化层407和源漏电极层408。衬底401可以为玻璃。底栅402、顶栅406和漏电极层408均由导电层图案化形成。导电层可以为钼(Mo)，铝(Al)，银(Ag)， 钛(Ti)，铜(Cu)，氧化铟锡(Indium Tin Oxide，ITO)，掺铟氧化锌(Indium doped Zinc Oxide，IZO)，Ag纳米线，碳纳米管，石墨烯导电膜等，导电层可以为单层或叠层。有源层404可以为镧系掺杂的金属氧化物半导体层，第一栅极绝缘层403。第二栅极绝缘层405和钝化层407可以为二氧化硅(SiO2)，氮化硅(SiNx)或氧化铝(AlOx)等无机绝缘层，也可以为其他有机绝缘层，每层可以为单层或叠层结构。双栅N型晶体管的制作过程中，可以通过调节第一栅极绝缘层403和第二栅极绝缘层405的材料和厚度调节双栅N型晶体管的阈值电压。在双栅N型晶体管的栅极上施加恒定偏压时，其关系如公式(1)：
Figure PCTCN2020103431-appb-000001
其中，V gate2为顶栅上施加的电压，C ACT为有源层耗尽时的电容，C GI2为第二栅极绝缘层的电容，C GI1为第一栅极绝缘层的电容。从而表明了双栅N型晶体管沟道完全耗尽时底栅402和顶栅406之间的电荷耦合效应。
表1为一种双栅N型晶体管各个膜层的材料和厚度。在此基础上，对双栅N型晶体管的顶栅施加不同的恒定偏压，测试双栅N型晶体管的转移曲线的变化情况。图5为双栅N型晶体管的顶栅施加不同的恒定偏压时双栅N型晶体管的电流示意图，其中，横坐标为顶栅施加的电压V G，纵坐标为双栅N型晶体管的电流I DS。图6为双栅N型晶体管的顶栅施加不同的恒定偏压的转移曲线示意图，其中，横坐标为双栅N型晶体管的顶栅的恒定偏压值V top，纵坐标为双栅N型晶体管的阈值电压的变化值，理论值为通过公式(1)计算获得的阈值电压变化值，实验值为实验中测试获得的阈值电压变化值。如图5和图6所示，顶栅的恒定电压为-20V～20V，步伐为5V一个测试记录点。在顶栅施加负向恒定电压时，双栅N型晶体管的阈值电压会平行地向正向移动；在顶栅施加正向恒 定电压时，其阈值电压会平行地向负向移动。并且由图6的理论值和实验值比较可知，实验测试获得的阈值电压变化值与理论值非常接近，公式(1)适用于双栅N型晶体管的阈值电压与顶栅的偏压的关系。图7为双栅N型晶体管的底栅施加不同的恒定偏压时双栅N型晶体管的电流示意图，其中，横坐标为底栅施加的电压V G，纵坐标为双栅N型晶体管的电流I DS。图8为双栅N型晶体管的底栅施加不同的恒定偏压的转移曲线示意图，其中，横坐标为双栅N型晶体管的底栅的恒定偏压值V bottom，纵坐标为双栅N型晶体管的阈值电压的变化值，理论值为通过公式(1)计算获得的阈值电压变化值，实验值为实验中测试获得的阈值电压变化值。如图7和图8所示，阈值电压的变化规律与顶栅施加不同的恒定偏压的变化规律相同。由此可知，双栅N型晶体管的顶栅和底栅之间形成了有效的空间交互电场，在施加一个恒定电压在顶栅的情况下，电子在前沟道的累积效应将会发生变化，即在施加负向的恒定电压的情况下，垂直分布的空间电场将会增强，从而使电子更多地被绝缘层/有源层界面捕获，进而引致双栅N型晶体管的阈值电压较正；而在施加正向的恒定电压的情况下，垂直分布的空间电场将会减弱，而导致双栅N型晶体管的阈值电压较负。
表1
Figure PCTCN2020103431-appb-000002
表2为另一种双栅N型晶体管各个膜层的材料和厚度。与表1的不同之处在于，第二栅极绝缘层的厚度为500nm。图9为第二栅极绝缘层的厚度为500nm 时双栅N型晶体管的顶栅加不同的恒定偏压的转移曲线示意图，其中，横坐标为双栅N型晶体管的顶栅的恒定偏压值V top，纵坐标为双栅N型晶体管的阈值电压的变化值，理论值为通过公式(1)计算获得的阈值电压变化值，实验值为实验中测试获得的阈值电压变化值。由图9可知，含有500nm厚度的第二栅极绝缘层的双栅N型晶体管的阈值电压调控的幅度要小于300nm厚度的第二栅极绝缘层的双栅N型晶体管的阈值电压，表明了对于较厚的第二栅极绝缘层，其从顶栅往底栅方向产生的垂直电场将会明显减弱。图10为第二栅极绝缘层的厚度为500nm时双栅N型晶体管的底栅加不同的恒定偏压的转移曲线示意图，其中，横坐标为双栅N型晶体管的底栅的恒定偏压值V bottom，纵坐标为双栅N型晶体管的阈值电压的变化值，理论值为通过公式(1)计算获得的阈值电压变化值，实验值为实验中测试获得的阈值电压变化值。阈值电压的变化规律与顶栅施加不同的恒定偏压的变化规律相同。
表2
Figure PCTCN2020103431-appb-000003
表3为另一种双栅N型晶体管各个膜层的材料和厚度。与表1的不同之处在于，第一栅极绝缘层的厚度为150nm。图11为第一栅极绝缘层的厚度为150nm时双栅N型晶体管的顶栅加不同的恒定偏压的转移曲线示意图，其中，横坐标为双栅N型晶体管的顶栅的恒定偏压值V top，纵坐标为双栅N型晶体管的阈值 电压的变化值，理论值为通过公式(1)计算获得的阈值电压变化值，实验值为实验中测试获得的阈值电压变化值。由图11可知，含有150nm厚度的第一栅极绝缘层的双栅N型晶体管的阈值电压调控的幅度要大于200nm厚度的第一栅极绝缘层的双栅N型晶体管的阈值电压，表明了对于较薄的第一栅极绝缘层，其从顶栅往底栅方向产生的垂直电场将会明显增强。图12为第一栅极绝缘层的厚度为150nm时双栅N型晶体管的底栅加不同的恒定偏压的转移曲线示意图，其中，横坐标为双栅N型晶体管的底栅的恒定偏压值V bottom，纵坐标为双栅N型晶体管的阈值电压的变化值，理论值为通过公式(1)计算获得的阈值电压变化值，实验值为实验中测试获得的阈值电压变化值。阈值电压的变化规律与顶栅施加不同的恒定偏压的变化规律相同。
表3
Figure PCTCN2020103431-appb-000004
表4为另一种双栅N型晶体管各个膜层的材料和厚度。与表1的不同之处在于，第一栅极绝缘层采用SiNx/SiO2材料。图13为第一栅极绝缘层的材料为SiNx/SiO2时双栅N型晶体管的顶栅加不同的恒定偏压的转移曲线示意图，其中，横坐标为双栅N型晶体管的顶栅的恒定偏压值V top，纵坐标为双栅N型晶体管的阈值电压的变化值，理论值为通过公式(1)计算获得的阈值电压变化值，实验值为实验中测试获得的阈值电压变化值。由图13可知，含有SiNx/SiO2材料 的第一栅极绝缘层的双栅N型晶体管的阈值电压调控的幅度要大于AlOx材料的第一栅极绝缘层的双栅N型晶体管的阈值电压，表明了对于氮硅氧化物材料的第一栅极绝缘层，其从顶栅往底栅方向产生的垂直电场将会明显增强。图14为第一栅极绝缘层的的材料为SiNx/SiO2时双栅N型晶体管的底栅加不同的恒定偏压的转移曲线示意图，其中，横坐标为双栅N型晶体管的底栅的恒定偏压值Vbottom，纵坐标为双栅N型晶体管的阈值电压的变化值，理论值为通过公式(1)计算获得的阈值电压变化值，实验值为实验中测试获得的阈值电压变化值。阈值电压的变化规律与顶栅施加不同的恒定偏压的变化规律相同。
表4
Figure PCTCN2020103431-appb-000005
表5为另一种双栅N型晶体管各个膜层的材料和厚度。与表1的不同之处在于，第一栅极绝缘层的材料为CYTOP，厚度为300nm，有源层的厚度为20nm，第二栅极绝缘层的材料为聚二甲基硅氧烷(polydimethylsiloxane)PDMS，厚度为600nm。图15为第一栅极绝缘层的材料为CYTOP，厚度为300nm，有源层的厚度为20nm，第二栅极绝缘层的材料为PDMS，厚度为600nm时双栅N型晶体管的顶栅加不同的恒定偏压的转移曲线示意图，其中，横坐标为双栅N型晶体管的顶栅的恒定偏压值V top，纵坐标为双栅N型晶体管的阈值电压的变化值，理论值为通过公式(1)计算获得的阈值电压变化值，实验值为实验中测试 获得的阈值电压变化值。由图15可知，含有300nm厚度，材料为CYTOP的第一栅极绝缘层，且有源层的厚度为20nm，第二栅极绝缘层的材料为PDMS，厚度为600nm的双栅N型晶体管的阈值电压调控的幅度要大于表1中的双栅N型晶体管的阈值电压，表明了表5中的双栅N型晶体管从顶栅往底栅方向产生的垂直电场将会明显增强。图16为第一栅极绝缘层的材料为CYTOP，厚度为300nm，有源层的厚度为20nm，第二栅极绝缘层的材料为PDMS，厚度为600nm时双栅N型晶体管的底栅加不同的恒定偏压的转移曲线示意图，其中，横坐标为双栅N型晶体管的底栅的恒定偏压值V bottom，纵坐标为双栅N型晶体管的阈值电压的变化值，理论值为通过公式(1)计算获得的阈值电压变化值，实验值为实验中测试获得的阈值电压变化值。阈值电压的变化规律与顶栅施加不同的恒定偏压的变化规律相同。
表5
Figure PCTCN2020103431-appb-000006
在驱动模块130包括双栅N型晶体管的情况下，第一控制端131为第一栅极，第二控制端132为第二栅极。第一栅极写入数据电压，第二栅极写入PWM信号。图17为双栅N型晶体管的转移特性曲线示意图。其中，横坐标为第二栅极写入的电压值，纵坐标为双栅N型晶体管的电流。如图17所示，在PWM信号输出高电平的情况下，双栅N型晶体管的阈值电压向负向漂移，即双栅N型 晶体管的阈值电压减小，使得双栅N型晶体管的阈值电压小于双栅N型晶体管的栅极和源极之间的电压差，双栅N型晶体管导通，产生驱动电流，从而驱动发光器件140发光。由双栅N型晶体管的电流公式(2)可知，双栅N型晶体管的阈值电压越小，双栅N型晶体管的电流越大。
Figure PCTCN2020103431-appb-000007
其中，I OLED为流过双栅N型晶体管的电流，μ为双栅N型晶体管的载流子迁移率，W和L分别为双栅N型晶体管的沟道的宽度和长度，V GS为双栅N型晶体管的栅极和源极之间的电压差，V TH为双栅N型晶体管的阈值电压。
在PWM信号输出低电平的情况下，双栅N型晶体管的阈值电压向正向漂移，即双栅N型晶体管的阈值电压增加，使得双栅N型晶体管的阈值电压大于双栅N型晶体管的栅极和源极之间的电压差，双栅N型晶体管截止，即驱动电流不连通，发光器件140不发光。由此可知，通过调节PWM信号的占空比可以调节PWM信号高电平输出的时间，进而可以调节发光器件140的发光时间。在通过PWM信号的占空比调节发光器件140的发光时间时，驱动模块140的第一控制端131维持数据电压，因此无需使数据电压与PWM信号控制发光器件140发光的占空比同步，因此可以降低驱动像素电路工作的驱动电路的设计复杂度，进而降低了显示面板的制作成本。
需要说明的是，上述过程示例性地示出了双栅N型晶体管的工作过程。在其他实施例中，驱动模块130还可以包括双栅P型晶体管。在PWM信号输出高电平的情况下，双栅P型晶体管的阈值电压向正向漂移，即双栅P型晶体管的阈值电压增加，使得双栅P型晶体管的阈值电压大于双栅P型晶体管的栅极和源极之间的电压差，双栅P型晶体管截止，无法产生驱动电流，从而发光器 件140不发光。在PWM信号输出低电平的情况下，双栅P型晶体管的阈值电压向反向漂移，即双栅P型晶体管的阈值电压减小，使得双栅P型晶体管的阈值电压小于双栅P型晶体管的栅极和源极之间的电压差，双栅P型晶体管导通，产生驱动电流，从而驱动发光器件140发光。
另外，发光器件140的发光亮度为发光器件140在PWM信号一个周期内的平均发光亮度。例如，设流过发光器件140的驱动电流为I 0，对应的发光亮度为L 0，PWM信号的占空比为η，则发光器件140的发光亮度L为L＝L 0*η。由此可知，可以使发光器件140工作在较高的发光效率下以稳定的颜色发光。然后通过调节PWM信号的占空比η调整发光器件140的平均发光亮度，使发光器件140的平均发光亮度在合理区间，满足发光器件140的发光亮度与灰阶的对应关系。示例性地，图18为本申请实施例提供的一种占空比为1％的PWM信号调制发光器件的光强与电流的关系曲线示意图。其中，横坐标为流过发光器件的驱动电流I，纵坐标为发光器件的发光强度L。曲线L1L2为PWM信号调制发光器件前的发光强度，曲线L1’L2’为PWM信号调制发光器件后的发光强度。由曲线L1L2和曲线L1’L2’可知，发光器件工作在发光效率比较高发光颜色稳定对应的驱动电流区域，然后通过PWM信号调制，使发光器件的发光亮度对应低电流低灰阶，从而实现了发光器件工作在发光效率高和发光颜色稳定的区域内时满足不同灰阶对应的发光亮度。
本实施例的技术方案，通过脉冲宽度调制信号输入端提供PWM信号至驱动模块的第二控制端，使驱动模块提供非连续驱动电流至发光器件，从而控制发光器件的发光时间。在通过PWM信号的占空比调节发光器件的发光时间时，驱动模块的第一控制端维持数据电压，因此无需使数据电压与PWM信号控制发光 器件发光的占空比同步，因此可以降低驱动像素电路工作的驱动电路的设计复杂度，进而降低了显示面板的制作成本。同时，发光器件工作在发光效率比较高发光颜色稳定对应的驱动电流区域，通过PWM信号调制，使发光器件的发光亮度对应低电流低灰阶，从而实现了发光器件工作在发光效率高和发光颜色稳定的区域内时满足不同灰阶对应的发光亮度。
示例性地，参考图3，数据写入模块110的第一端与像素电路的数据信号输入端Vdata电连接，数据写入模块110的第二端与驱动模块130的第一控制端131和存储模块120的第一端电连接，数据写入模块110的控制端与像素电路的扫描信号输入端Scan1电连接；驱动模块130的第一端与像素电路的第一电源信号输入端VDD和存储模块120的第二端电连接，驱动模块130的第二端与发光器件140的阳极电连接，发光器件140的阴极与像素电路的第二电源信号输入端VSS电连接。
在数据写入阶段，像素电路的扫描信号输入端Scan1控制数据信号输入端Vdata输入的数据信号通过数据写入模块110写入至驱动模块130的第一控制端131，并通过存储模块120维持第一控制端131的数据信号。
在发光阶段，像素电路的扫描信号输入端Scan1控制数据写入模块110停止写入数据电压，脉冲宽度调制信号输入端Vpwm的PWM信号控制驱动模块130提供非连续电流，从而控制发光器件140的发光时间。
图19为本申请实施例提供的另一种像素电路的结构示意图。如图19所示，数据写入模块110包括第一晶体管T1，存储模块120包括存储电容Cst，驱动模块130包括驱动晶体管Tdr；第一晶体管T1的栅极为数据写入模块110的控制端，第一晶体管T1的第一极为数据写入模块110的第一端，第一晶体管T1 的第二极为数据写入模块110的第二端；存储电容Cst的第一极为存储模块120的第一端，存储电容Cst的第二极为存储模块120的第二端；驱动晶体管Tdr为双栅晶体管，双栅晶体管的第一极为驱动模块130的第一端，双栅晶体管的第二极为驱动模块130的第二端；双栅晶体管的底栅极为驱动模块130的第一控制端，双栅晶体管的顶栅极为驱动模块130的第二控制端，或者，双栅晶体管的顶栅极为驱动模块130的第一控制端，双栅晶体管的底栅极为驱动模块130的第二控制端。
示例性地，图20为图19的像素电路的一种时序图。其中，scan1为扫描信号输入端Scan1输入的扫描信号的时序，vdd为第一电源信号输入端VDD输入的第一电源信号的时序，vss为第二电源信号输入端VSS输入的第二电源信号的时序，pwm为脉冲宽度调制信号输入端Vpwm输入的PWM信号的时序。以下结合图19和图20说明像素电路的工作原理。
在第一阶段t1，scan1为高电平，控制第一晶体管T1导通，数据电压通过第一晶体管T1写入至驱动晶体管Tdr的栅极，并通过存储电容Cst维持该数据电压。
在第二阶段t2，scan1为高电平，控制第一晶体管T1截止。同时驱动晶体管Tdr的第一栅极为高电平。在pwm信号为高电平的情况下，驱动晶体管Tdr为导通状态。在pwm信号为低电平的情况下，驱动晶体管Tdr为截止状态。因此，通过控制pwm信号的占空比控制驱动晶体管Tdr的导通时间，从而控制驱动晶体管Tdr为发光器件140提供驱动电流的时间，进而控制发光器件140的发光时间。
需要说明的是，驱动晶体管Tdr的驱动电流与数据电压的大小相关。如图 19所示，在驱动晶体管Tdr为N型晶体管的情况下，数据电压越大，驱动晶体管Tdr输出的驱动电流越大，对应的发光器件140的发光亮度越亮。数据电压越小，驱动晶体管Tdr输出的驱动电流越小，对应的发光器件140的发光亮度越暗。
图21为本申请实施例提供的另一种像素电路的结构示意图。如图21所示，该像素电路还包括复位模块150；复位模150块的控制端与像素电路的扫描信号输入端Scan1电连接，复位模块150的第一端与参考信号输入端Vref电连接，复位模块150的第二端与发光器件140的阳极电连接；复位模块150设置为对发光器件140进行复位。
示例性地，复位模块150在数据写入模块110向驱动模块130写入数据电压的同时对发光器件140的阳极进行复位，以避免上一帧发光器件140发光后残留的电压影响当前帧的发光器件140的发光亮度。
示例性地，参考图21，复位模块150包括第二晶体管T2；第二晶体管T2的栅极为复位模块150的控制端，第二晶体管T2的第一极为复位模块150的第一端，第二晶体管T2的第二极为复位模块150的第二端。
示例性地，图22为图21的像素电路对应的一种时序图，其中，vref为参考信号输入端Vref提供的参考信号的时序。结合图21和图22说明像素电路的工作过程。
在复位和数据写入阶段t3，scan1为高电平，控制第一晶体管T1和第二晶体管T2导通，数据电压通过第一晶体管T1写入至驱动晶体管Tdr的栅极，并通过存储电容Cst维持该数据电压。参考信号输入端Vref输入的参考信号vref通过第二晶体管T2写入至发光器件140的阳极，对发光器件140进行复位。
在发光阶段t4，scan1为高电平，控制第一晶体管T1和第二晶体管T2截止。同时驱动晶体管Tdr的第一栅极为高电平。在pwm信号为高电平的情况下，驱动晶体管Tdr为导通状态。在pwm信号为低电平的情况下，驱动晶体管Tdr为截止状态。因此，通过控制pwm信号的占空比控制驱动晶体管Tdr的导通时间，从而控制驱动晶体管Tdr为发光器件140提供驱动电流的时间，进而控制发光器件140的发光时间。
图23为本申请实施例提供的另一种像素电路的结构示意图。如图23所示，该像素电路还包括感应模块160；感应模块160的控制端与像素电路的感应控制信号输入端SENSE电连接，感应模块160的第一端与发光器件140的阳极电连接，感应模块160的第二端与感应信号输出端ISENSE电连接；感应模块160设置为感应发光器件140的电位。
示例性地，在发光阶段之前，感应控制信号输入端SENSE输入感应控制信号控制感应模块160导通，将驱动模块130的电流输出至感应信号输出端ISENSE，并通过感应信号输出端ISENSE输出至外部的感应电路，外部的感应电路根据流过驱动模块130的电流对像素电路进行补偿。
示例性地，参考图23，感应模块包括第三晶体管T3；第三晶体管T3的栅极为感应模块160的控制端，第三晶体管T3的第一极为感应模块160的第一端，第三晶体管T3的第二极为感应模块160的第二端。
示例性地，图24为图23的像素电路对应的一种时序图，其中，sense为感应控制信号输入端SENSE输出的感应控制信号的时序。结合图23和图24说明像素电路的工作过程。
在复位和数据写入阶段t5，scan1为高电平，控制第一晶体管T1和第二晶 体管T2导通，数据电压通过第一晶体管T1写入至驱动晶体管Tdr的栅极，并通过存储电容Cst维持该数据电压。参考信号输入端Vref输入的参考信号vref通过第二晶体管T2写入至发光器件140的阳极，对发光器件140进行复位。
在感应阶段t6，感应控制信号输入端SENSE输出的感应控制信号sense为高电平，控制第三晶体管T3导通，驱动晶体管Tdr的电流通过第三晶体管T3输出到外部感应电路，外部电路通过数据处理，添加一个补偿信号在数据电压上，从而提高整个显示面板的发光均匀性。
在发光阶段t7，scan1为高电平，控制第一晶体管T1和第二晶体管T2截止。同时驱动晶体管Tdr的第一栅极为高电平。在pwm信号为高电平的情况下，驱动晶体管Tdr为导通状态。在pwm信号为低电平的情况下，驱动晶体管Tdr为截止状态。因此，通过控制pwm信号的占空比控制驱动晶体管Tdr的导通时间，从而控制驱动晶体管Tdr为发光器件140提供驱动电流的时间，进而控制发光器件140的发光时间。
本申请实施例还提供一种像素电路的驱动方法，用于驱动上述各技术方案提供的像素电路。图25为本申请实施例提供的像素电路的驱动方法的流程图。如图25所示，该方法包括步骤S10至步骤S20。
在步骤S10中，在数据写入阶段，像素电路的数据写入模块将数据信号写入像素电路的驱动模块的第一控制端；存储模块维持驱动模块的第一控制端的电压。
在步骤S20中，在发光阶段，驱动模块的第二控制端控制驱动模块根据像素电路的脉冲宽度调制信号输入端输入的脉冲宽度调制信号提供非连续驱动电 流，发光器件响应驱动电流发光。
本实施例的技术方案，通过在数据写入阶段将数据信号写入至驱动模块的第一控制端，并通过存储模块维持驱动模块的第一控制端的电压，使第一控制端的电压维持在数据信号。然后在发光阶段PWM信号提供至驱动模块的第二控制端，使驱动模块提供非连续驱动电流至发光器件，从而控制发光器件的发光时间。在通过PWM信号的占空比调节发光器件的发光时间时，驱动模块的第一控制端维持数据电压，因此无需使数据电压与PWM信号控制发光器件发光的占空比同步，因此可以降低驱动像素电路工作的驱动电路的设计复杂度，进而降低了显示面板的制作成本。同时，发光器件工作在发光效率比较高发光颜色稳定对应的驱动电流区域，通过PWM信号调制，使发光器件的发光亮度对应低电流低灰阶，从而实现了发光器件工作在发光效率高和发光颜色稳定的区域内时满足不同灰阶对应的发光亮度。
本申请实施例还提供一种显示面板。图26为本申请实施例提供的一种显示面板。如图26所示，该显示面板包括本申请任意实施例提供的像素电路101。
参考图26，显示面板还包括脉冲宽度调制信号线210、栅极驱动电路220和数据驱动电路230；像素电路101包括扫描信号输入端、数据信号输入端和脉冲宽度调制信号输入端；脉冲宽度调制信号线210与脉冲宽度调制信号输入端电连接，栅极驱动电路220的输出端221与像素电路的扫描信号输入端电连接；数据驱动电路230的输出端231与像素电路的数据信号输入端电连接。
示例性地，脉冲宽度调制信号线210设置为输出PWM信号，为像素电路的脉冲宽度调制信号输入端提供PWM信号。栅极驱动电路220的输出端221通过 扫描信号线与像素电路101的扫描信号输入端电连接，为像素电路101逐行提供扫描信号，使像素电路101逐行驱动。数据驱动电路230的输出端231通过数据信号线与像素电路101的数据信号输入端电连接，为像素电路101提供数据信号。像素电路101可以在与之电连接的扫描信号线输入的扫描信号的作用下，连通与之对应电连接的数据信号线，数据信号线向对应的像素驱动电路101传输数据信号，依此实现显示装置的显示功能。

Claims (10)

  1. 一种像素电路，包括数据写入模块、存储模块、驱动模块和发光器件；
    所述驱动模块包括第一控制端和第二控制端，所述数据写入模块设置为在数据写入阶段将数据信号写入所述驱动模块的第一控制端；所述存储模块设置为维持所述第一控制端的电位；所述第二控制端与所述像素电路的脉冲宽度调制信号输入端电连接，设置为控制所述驱动模块在发光阶段根据所述脉冲宽度调制信号输入端输入的脉冲宽度调制信号提供非连续驱动电流，所述发光器件响应所述驱动电流发光。
  2. 根据权利要求1所述的像素电路，其中，所述数据写入模块的第一端与所述像素电路的数据信号输入端电连接，所述数据写入模块的第二端与所述驱动模块的第一控制端和所述存储模块的第一端电连接，所述数据写入模块的控制端与所述像素电路的扫描信号输入端电连接；所述驱动模块的第一端与所述像素电路的第一电源信号输入端和所述存储模块的第二端电连接，所述驱动模块的第二端与所述发光器件的阳极电连接，所述发光器件的阴极与所述像素电路的第二电源信号输入端电连接。
  3. 根据权利要求2所述的像素电路，其中，所述数据写入模块包括第一晶体管，所述存储模块包括存储电容，所述驱动模块包括驱动晶体管；
    所述第一晶体管的栅极为所述数据写入模块的控制端，所述第一晶体管的第一极为所述数据写入模块的第一端，所述第一晶体管的第二极为所述数据写入模块的第二端；所述存储电容的第一极为所述存储模块的第一端，所述存储电容的第二极为所述存储模块的第二端；
    所述驱动晶体管为双栅晶体管，所述双栅晶体管的第一极为所述驱动模块的第一端，所述双栅晶体管的第二极为所述驱动模块的第二端；所述双栅晶体管的底栅极为所述驱动模块的第一控制端，所述双栅晶体管的顶栅极为所述驱动模块的第二控制端，或者，所述双栅晶体管的顶栅极为所述驱动模块的第一控制端，所述双栅晶体管的底栅极为所述驱动模块的第二控制端。
  4. 根据权利要求1所述的像素电路，还包括复位模块；
    所述复位模块的控制端与所述像素电路的扫描信号输入端电连接，所述复位模块的第一端与参考信号输入端电连接，所述复位模块的第二端与所述发光器件的阳极电连接；所述复位模块设置为对所述发光器件进行复位。
  5. 根据权利要求4所述的像素电路，其中，所述复位模块包括第二晶体管；
    所述第二晶体管的栅极为所述复位模块的控制端，所述第二晶体管的第一极为所述复位模块的第一端，所述第二晶体管的第二极为所述复位模块的第二端。
  6. 根据权利要求1所述的像素电路，还包括感应模块；
    所述感应模块的控制端与所述像素电路的感应控制信号输入端电连接，所述感应模块的第一端与所述发光器件的阳极电连接，所述感应模块的第二端与感应信号输出端电连接；所述感应模块设置为感应所述发光器件的电位。
  7. 根据权利要求6所述的像素电路，其中，所述感应模块包括第三晶体管；
    所述第三晶体管的栅极为所述感应模块的控制端，所述第三晶体管的第一极为所述感应模块的第一端，所述第三晶体管的第二极为所述感应模块的第二端。
  8. 一种像素电路的驱动方法，所述像素电路包括数据写入模块、存储模块、驱动模块和发光器件，所述驱动模块包括第一控制端和第二控制端；所述方法包括：
    在数据写入阶段，所述像素电路的数据写入模块将数据信号写入所述像素电路的驱动模块的第一控制端；所述存储模块维持所述驱动模块的第一控制端的电压；
    在发光阶段，所述驱动模块的第二控制端控制所述驱动模块根据所述像素电路的脉冲宽度调制信号输入端输入的脉冲宽度调制信号提供非连续驱动电流，所述发光器件响应所述驱动电流发光。
  9. 一种显示面板，包括权利要求1-7任一所述的像素电路。
  10. 根据权利要求9所述的显示面板，还包括脉冲宽度调制信号线、栅极 驱动电路和数据驱动电路；
    所述像素电路包括扫描信号输入端、数据信号输入端和脉冲宽度调制信号输入端；所述脉冲宽度调制信号线与所述脉冲宽度调制信号输入端电连接，所述栅极驱动电路的输出端与所述像素电路的扫描信号输入端电连接，所述数据驱动电路的输出端与所述像素电路的数据信号输入端电连接。
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