WO2021159526A1 - 一种集成电路、控制方法及系统 - Google Patents

一种集成电路、控制方法及系统 Download PDF

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Publication number
WO2021159526A1
WO2021159526A1 PCT/CN2020/075421 CN2020075421W WO2021159526A1 WO 2021159526 A1 WO2021159526 A1 WO 2021159526A1 CN 2020075421 W CN2020075421 W CN 2020075421W WO 2021159526 A1 WO2021159526 A1 WO 2021159526A1
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WO
WIPO (PCT)
Prior art keywords
pull
switch
integrated circuit
target
resistor
Prior art date
Application number
PCT/CN2020/075421
Other languages
English (en)
French (fr)
Inventor
赵鹏飞
谭丽娟
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20918402.7A priority Critical patent/EP4099566A4/en
Priority to CN202080096598.2A priority patent/CN115104259A/zh
Priority to PCT/CN2020/075421 priority patent/WO2021159526A1/zh
Publication of WO2021159526A1 publication Critical patent/WO2021159526A1/zh
Priority to US17/887,176 priority patent/US11855616B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018557—Coupling arrangements; Impedance matching circuits

Definitions

  • This application relates to the field of integrated circuit technology, and in particular to an integrated circuit, a control method and a system.
  • SoC system on chip
  • the SoC can integrate most of the core components of the electronic device, and can control the working status of other chips in the electronic device.
  • the power control pin can be used to control the power on of the target chip.
  • the SoC can also configure the parameters in the target chip through the configuration pins.
  • the pull-up power supply of the pull-up resistor and the power supply of the SoC are usually the same power supply.
  • the pull-up power supply of the pull-up resistor will begin to discharge, causing the voltage of the configuration pin to be pulled up, which in turn causes the target chip to receive the signal from the SoC configuration pin before it is powered on Signal, causing the target chip to work abnormally.
  • the embodiments of the present application provide an integrated circuit, a control method, and a system to improve the reliability of the integrated circuit.
  • an embodiment of the present application provides an integrated circuit, which mainly includes a power supply pin, a configuration pin, a pull-up switch resistance, and a control unit.
  • the integrated circuit provided by the embodiment of the present application can target the configuration pin through its configuration pin.
  • the chip provides control signals.
  • the first end of the pull-up switch resistor is connected to the power pin
  • the second end of the pull-up switch resistor is connected to the configuration pin
  • the control end of the pull-up switch resistor is connected to the control unit
  • the power pin can receive The power supply voltage of the integrated circuit
  • the control unit can control the pull-up switch resistance to be in the off state before the target chip is powered on.
  • the pull-up switch resistance is a controllable switch resistance
  • the control unit controls the pull-up switch resistance to be in an off state before the target chip is powered on, so that the pull-up switch resistance receives the pull-up switch resistance.
  • the pull voltage (the power supply voltage of the integrated circuit) is not transmitted to the configuration pins, nor is it transmitted to the target chip. Therefore, the embodiments of the present application help prevent the target chip from receiving error signals from the configuration pins of the integrated circuit before powering on, thereby helping to improve the reliability of the integrated circuit.
  • the pull-up switch resistance is built into the integrated circuit, and the power supply voltage of the integrated circuit is used to provide a pull-up voltage for the pull-up switch resistance. Adopting this implementation mode is beneficial to simplify the structure of the peripheral circuit of the integrated circuit, and reduce the board area and production cost of the peripheral circuit.
  • the control unit controls the pull-up switch resistance to be in the off state before the target chip is powered on. Specifically, it may be that the control unit controls the pull-up switch resistance to be in the off state before the target time point, where the target time point is not A point in time before the power-on voltage of the target chip reaches the target voltage. It can be understood that during the power-on process of the target chip, the power-on voltage provided to the target chip may gradually increase from a lower initial voltage to the target voltage. In the embodiment of the present application, the control unit controls the upper The pull-up switch resistance is in the off state, that is, before the power-on voltage of the target chip reaches the target voltage, the pull-up switch resistance is controlled to be in the off state. It is helpful to prevent the target chip from receiving error signals from the configuration pins of the integrated circuit during the power-on process. Therefore, the use of this technical solution is beneficial to further improve the reliability of the integrated circuit.
  • the integrated circuit may further include a power control pin; the control unit may also output a power-on signal through the power control pin, and the power-on signal can conduct a path for powering on the target chip.
  • the integrated circuit can also calculate the target time point according to the time point when the power-on signal is output and the time delay for the power-on voltage of the target chip to reach the target voltage.
  • the integrated circuit can output a control signal to the target chip through the configuration pin.
  • the integrated circuit may further include a pull-down switch resistance, the first end of the pull-down switch resistance is connected to the configuration pin, the second end of the pull-down switch resistance is grounded, and the control end of the pull-down switch resistance is connected to the control unit.
  • the control unit can control the pull-up switch resistance to be in the on or off state, and control the pull-down switch to be in the on or off state to generate a control signal;
  • the control signal can be output to the target chip through the configuration pin.
  • the integrated circuit provided in the embodiment of the present application may include a plurality of pull-up switch resistors connected in parallel.
  • the control unit When the control unit generates the control signal, it can determine one or more target pull-up switch resistances among the multiple pull-up switch resistances; the control unit can then control one or more target pull-up switch resistances to be in the on state or the off state .
  • the target pull-up switch resistance can adjust the high-level voltage of the control signal.
  • the parallel resistance of the multiple target pull-up switch resistances can adjust the high-level voltage of the control signal.
  • the pull-down switch resistance may include a pull-down switch and a pull-down resistor;
  • the pull-down switch includes a first terminal, a second terminal, and a control terminal; wherein, the first terminal of the pull-down switch and the configuration The pins are connected, the second end of the pull-down switch is connected to one end of the pull-down resistor, the control end of the pull-down switch is connected to the control unit, and the other end of the pull-down resistor is grounded.
  • the control end of the pull-down switch is also the control end of the pull-down switch resistance, and the control unit can turn on the pull-down switch, thereby controlling the pull-down switch resistance to be in an on state.
  • the control unit can also disconnect the pull-down switch, thereby controlling the resistance of the pull-down switch to be in an off state.
  • the pull-up switch resistance may include a pull-up switch and a pull-up resistor; the pull-up switch includes a first terminal, a second terminal, and a control terminal; the first terminal of the pull-up switch The second end of the pull-up switch is connected with one end of the pull-up resistor, the control end of the pull-up switch is connected with the control unit, and the other end of the pull-up resistor is connected with the power pin.
  • the control end of the pull-up switch is also the control end of the pull-up switch resistance, and the control unit can turn on the pull-up switch, thereby controlling the pull-up switch resistance to be in an on state.
  • the control unit can also disconnect the pull-up switch, thereby controlling the resistance of the pull-up switch to be in an off state.
  • the resistance value of the pull-up switch resistor can be adapted to the target chip.
  • the resistance value of the pull-up switch resistance may include any value from 4.7K ⁇ to 10K ⁇ .
  • the embodiments of the present application provide a control method that can be applied to integrated circuits.
  • the technical effects of the corresponding solutions in the second aspect can refer to the technical effects that can be obtained by the corresponding solutions in the first aspect, and repetitions are not allowed.
  • the integrated circuit to which the embodiment of the present application is applied may include a pull-up switch resistor, a power supply pin, and a configuration pin. The first end of the pull-up switch resistor is connected to the power supply pin, and the first end of the pull-up switch resistor is connected to the power supply pin.
  • the two ends are connected to the configuration pins, and the integrated circuit can provide control signals to the target chip through the configuration pins; in the method provided in the embodiment of the present application, the integrated circuit can receive the supply voltage through the power pin; the integrated circuit is powered on the target chip Previously, the control pull-up switch resistance was in an off state.
  • the integrated circuit can determine whether it is necessary to continue to control the pull-up switch resistance to be in the off state according to the target time point.
  • the target time point is no earlier than the time point when the power-on voltage of the target chip reaches the target voltage.
  • the integrated circuit may control the pull-up switch resistance to be in an off state before the target time point.
  • the integrated circuit can also output a power-on signal through the power control pin of the integrated circuit, and the power-on signal can turn on the path for powering on the target chip; the integrated circuit can output the power-on signal according to the time point and The time delay for the power-on voltage of the target chip to reach the target voltage is calculated to obtain the above-mentioned target time point.
  • the integrated circuit may further include a pull-down switch resistor, the first end of the pull-down switch resistor is connected to the configuration pin, and the second end of the pull-down switch resistor is grounded.
  • the integrated circuit can control the pull-up switch resistance to be on or off after the target chip is powered on, and control the pull-down switch resistance to be on or off to generate a control signal; In turn, control signals can be output to the target chip through the configuration pins.
  • the integrated circuit provided in the embodiments of the present application may include multiple pull-up switch resistors connected in parallel.
  • the integrated circuit when the integrated circuit generates the control signal, it can determine one or more target pull-up switch resistances among the multiple pull-up switch resistances.
  • the integrated circuit can further control the above-mentioned one or more target pull-up switch resistances to be in an on state or an off state.
  • the resistance value of the pull-up switch resistor can be adapted to the target chip.
  • the resistance value of the pull-up switch resistance may include any value from 4.7K ⁇ to 10K ⁇ .
  • an embodiment of the present application provides a system, which may be an electronic device.
  • the technical effects of the corresponding solutions in the third aspect can refer to the technical effects that can be obtained by the corresponding solutions in the first aspect, and the repetitions are not described in detail.
  • the system provided in the embodiments of the present application may include a target chip and an integrated circuit as provided in any one of the above-mentioned first aspects.
  • Figure 1 is a schematic diagram of the structure of an electronic device
  • FIG. 2 is a schematic diagram of a system structure of an electronic device provided by an embodiment of the application.
  • FIG. 3 is an enlarged schematic diagram of a partial structure of an integrated circuit provided by an embodiment of the application.
  • FIG. 4 is an enlarged schematic diagram of a partial structure in another integrated circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic flowchart of a control method provided by an embodiment of this application.
  • FIG. 6 is a schematic flowchart of a specific control method provided by an embodiment of the application.
  • connection in the embodiments of the present application refers to an electrical connection, and the connection of two electrical components may be a direct or indirect connection between two electrical components.
  • connection between A and B can be either directly connected between A and B, or indirectly connected between A and B through one or more other electrical components, for example, A and B are connected, or A and C can be directly connected, C and B are directly connected, and A and B are connected through C.
  • Integrated circuit is a kind of miniature electronic device or component, which can be understood as the integration of a certain number of commonly used electronic components, such as resistors, capacitors, transistors, etc., and the connections between these components through semiconductor technology. Circuits with specific functions together. For example, SoC, central processing unit (CPU) and other chips can all be implemented by integrated circuits.
  • SoC can also be called system-level chip, or system-on-chip.
  • SoC is an integrated circuit used to achieve special purpose. Most of the core components of electronic equipment can be integrated in SoC to form a miniature system.
  • a smart TV is also provided with a screen driver chip, and the screen driver chip may also be called a timing control (TCON) chip.
  • the TCON chip is a processing chip in smart TVs that is responsible for receiving image signals and converting the image signals into timing signals that control the LCD screen.
  • the smart terminal is also provided with a baseband chip.
  • the baseband chip is a chip used in the smart terminal to synthesize the baseband signal for external transmission or decode the received baseband signal.
  • the type of the functional chip may also be different, which will not be listed in the embodiment of the present application.
  • FIG. 1 exemplarily shows a schematic structural diagram of an electronic device.
  • the electronic device 100 mainly includes a SoC101, a TCON chip 102 and a power module 103.
  • SoC101 may include a power pin P1, a power control pin P2, a data pin P3, a configuration pin P4, and a configuration pin P5.
  • the power pin P1 is connected to the power module 103
  • the power control pin P2 is connected to the power switch MOS
  • the data pin P3, configuration pin P4, and configuration pin P5 are respectively connected to the corresponding pins in the TCON chip 102 .
  • the power switch MOS is set on the SoC board where the SoC is located.
  • the power switch MOS mainly includes a control terminal, a first terminal and a second terminal. Wherein, the control end of the power switch MOS is connected to the power control pin P2 of the SoC, the first end of the power switch MOS is connected to the power module 103, and the second end of the power switch MOS is connected to the TCON chip.
  • the power module 103 may include a battery, a power management unit (PMU), a direct-current conversion circuit (direct-current conversion circuit), and the like.
  • the power module 103 is respectively connected to the SoC101 and the first end of the power switch MOS.
  • the power module 103 can provide a power supply voltage to the SoC101.
  • the power supply voltage provided by the power module 103 to the SoC can be 3V3, that is, the power supply voltage is 3.3V. Of course, it can also be other voltages, for example, the power supply voltage can also be 1.8V.
  • the SoC101 can receive the supply voltage through the power pin P1 to complete the power-on.
  • SoC101 After SoC101 is powered on, operations such as initialization can be completed. After that, SoC101 can continue to control the power-on of the TCON chip. Specifically, the SoC101 can send a power-on signal to the power switch MOS through the power control pin P2. The power-on signal can turn on the power switch MOS, thereby turning on the path between the power module 103 and the TCON chip 102.
  • the power module 103 outputs a power-on voltage VCC to the power switch MOS, and the power-on voltage VCC is transmitted to the TCON chip through the power switch MOS.
  • the TCON chip receives the power-on voltage VCC, and then completes the power-on.
  • SoC101 can continue to send control signal 1 to the TCON chip through the configuration pin P4, and send control signal 2 to the TCON chip through the configuration pin P5, so that the TCON chip can be controlled by the control signal 1 and control signal 2.
  • the SoC101 may configure the TCON chip through the control signal 1 and the control signal 2, for example, configure parameters such as the display partition and the number of bits of the TCON chip.
  • the control signal 1 can be a high-level signal, corresponding to a number 1, or it can be a low-level signal, corresponding to a number 0, and the same is true for the control signal 2. Therefore, four configuration types can be preset in the TCON chip, and the four configuration types correspond to 00, 01, 10, and 11 respectively.
  • the SoC101 can indicate the specific configuration type of the TOCN chip through the control signal 1 and the control signal 2.
  • the specific configuration type is any one of the four configuration types, so that the TCON chip 102 can complete the configuration according to the specific configuration type indicated by the SoC101.
  • the SoC101 can transmit the data signal Data to the TCON chip 102 through the data pin P3, so that the TCON chip 102 can control the display panel to display images according to the data signal Data.
  • the pull-up resistor R1 Take the pull-up resistor R1 as an example.
  • One end of the pull-up resistor R1 is connected to the power module 103, and the other end is connected to the configuration pin P4.
  • the pull-up resistor R1 can receive the pull-up voltage from the power module 103.
  • the control signal 1 output by the configuration pin P4 is a high-level signal
  • the pull-up resistor R1 can divide the received pull-up voltage. Therefore, the voltage of the control signal 1 is suppressed to protect the TCON chip 102.
  • the resistance of the pull-up resistor R1 is set according to the TCON chip 102, so that when the control signal 1 is a high-level signal, the voltage of the control signal 1 can be recognized by the TCON chip 102 without being too current due to excessive current. The TCON chip 102 is damaged.
  • the pull-up voltage of the pull-up resistor R1 is the same as the supply voltage of SoC101. Therefore, when the SoC101 is powered on, the pull-up resistor R1 will also receive the pull-up voltage, which may cause the pull-up resistor R1 to provide a high-level signal to the TCON chip 102.
  • SoC101 usually does not turn on the power switch MOS immediately after power-on, for example, SoC101 needs to complete initialization first, and then turn on the power switch MOS. Therefore, when the TCON chip 102 receives the high-level signal provided by the pull-up resistor R1, the TCON chip 102 has not yet been powered on. After the TCON chip 102 receives the high-level signal provided by the pull-up resistor R1, it may generate Misjudgment.
  • an embodiment of the present application provides an integrated circuit.
  • the integrated circuit may be an SoC, or an integrated circuit with control functions such as a CPU, a microcontroller unit (MCU), etc.
  • the embodiment of the present application does not No restrictions. For ease of presentation, the embodiments of the present application will continue to take SoC as an example for description.
  • Fig. 2 exemplarily shows a schematic diagram of a system structure of an electronic device to which an embodiment of the present application is applicable.
  • the electronic device 200 includes an SoC201 and a target chip 202.
  • the target chip 202 may be a functional chip controlled by the SoC201, such as a baseband chip, a TCON chip, a sensor chip, etc., a functional chip in a different power domain from the SoC201.
  • the electronic device 200 may further include a power module 203, and the power module 203 may provide power for the SoC201 and the target chip 202.
  • the implementation of the power module 203 can refer to the above-mentioned power module 103, which will not be repeated here.
  • SoC201 mainly includes power supply pin P1, configuration pins P4 and P5, pull-up switch resistors (KR1 and KR2) and control unit 2011. It should be understood that SoC201 may include one or more configuration pins, and each configuration pin corresponds to a pull-up switch resistance. As shown in Figure 2, the configuration pin P4 corresponds to the pull-up switch resistance KR1, and the configuration pin P5 corresponds to the pull-up switch resistance KR2. SoC201 can provide control signals for the target chip through configuration pins P4 and P5.
  • the pull-up switch resistor KR1 includes a first terminal, a second terminal and a control terminal.
  • the first end of the pull-up switch resistor KR1 is connected to the power pin P1. Therefore, after the SoC201 receives the power supply voltage through the power pin P1, the power supply voltage can also be used as the pull-up voltage of the pull-up switch resistor KR1.
  • the second end of the pull-up switch resistance KR1 is connected to the configuration pin P4, and the control end of the pull-up switch resistance KR1 is connected to the control unit 2011.
  • the control unit 2011 may control the pull-up switch resistor KR1 to be in a disconnected state before the target chip 202 is powered on.
  • SoC201 may include only one configuration pin, such as configuration pin P4, and SoC201 may also include multiple configuration pins, such as configuration pins P4 and P5.
  • the multiple configuration pins also correspond to pull-up switch resistors, and the connection between each configuration pin and the corresponding pull-up switch resistor is similar to the configuration pin P4.
  • the configuration pin P5 corresponds to the pull-up switch resistor KR2.
  • the pull-up switch resistor KR2 includes a first terminal, a second terminal and a control terminal.
  • the first end of the pull-up switch resistor KR2 is connected to the power pin P1. Therefore, after the SoC201 receives the power supply voltage through the power pin P1, the power supply voltage can also be used as the pull-up voltage of the pull-up switch resistor KR2.
  • the second end of the pull-up switch resistance KR2 is connected to the configuration pin P5, and the control end of the pull-up switch resistance KR2 is connected to the control unit 2011.
  • the control unit 2011 may control the pull-up switch resistor KR2 to be in a disconnected state before the target chip 202 is powered on.
  • configuration pin P4 and the pull-up switch resistor KR1 are taken as an example for description.
  • Other configuration pins (such as P5) and other pull-up switch resistors (such as KR2) in SoC201 can have similar implementations, which will not be repeated here.
  • the pull-up switch resistance KR1 is a controllable switch resistance
  • the control unit 2011 keeps the pull-up switch resistance KR1 off before the target chip 202 is powered on, so that the pull-up voltage received by the pull-up switch resistance KR1 ( The power supply voltage of SoC201) will not be transmitted to the configuration pin P4, and therefore will not be transmitted to the target chip 202. Therefore, the embodiment of the present application is beneficial to prevent the target chip 202 from receiving an error signal from the configuration pin P4 before being powered on, thereby helping to improve the reliability of the SoC201.
  • the pull-up switch resistor KR1 is built in the SoC201, and the power supply voltage of the SoC itself is used to provide the pull-up switch resistor KR1 with a pull-up voltage. Adopting this implementation method is beneficial to simplify the structure of the SoC peripheral circuit and reduce the board area and production cost of the peripheral circuit.
  • the SoC201 can send a control signal 1 through the configuration pin P4.
  • the specific implementation of the control signal 1 is mainly determined according to the type of the target chip 202.
  • the control signal 1 may be a high-level signal or a low-level signal to indicate the configuration type to the target chip 202, such as the configuration of the TCON chip 102 described above.
  • the control signal 1 may also carry configuration information of the target chip 202. For example, if the value of each parameter configured by the target chip 202 is required, the target chip 202 may complete the configuration according to the configuration information.
  • the SoC201 may further include a pull-down switch resistance KR3 corresponding to the configuration pin P4.
  • the pull-down switch resistance KR3 includes a first terminal, a second terminal and a control terminal.
  • the first end of the pull-down switch resistor KR3 is connected to the configuration pin P4, and the second end of the pull-down switch resistor KR3 is grounded.
  • the control unit 2011 may control the pull-up switch resistor KR1 to be in the on state or the off state, and control the pull-down switch resistor KR3 to be in the on state or the off state to generate the control signal 1.
  • the control signal 1 is output to the target chip through the configuration pin P4.
  • the control unit 2011 can generate the control signal 1 by controlling the pull-up switch resistor KR1 to be in the on state or the off state, and controlling the pull-down switch resistor KR3 to be in the on state or the off state.
  • the pull-up switch resistance KR1, the pull-down switch resistance KR3, and the control unit 2011 are further exemplified.
  • the resistance value of the pull-up switch resistor KR1 can be adapted to the target chip. Therefore, when the control signal 1 is at a high level, the control signal 1 can be recognized by the target chip 202, and the target chip 202 will not be damaged due to excessive current.
  • the resistance value of the pull-up switch resistance may include any resistance value from 4.7K ⁇ to 10K ⁇ .
  • the pull-up switch resistor KR1 includes a pull-up switch Ku and a pull-up resistor Ru.
  • the pull-up switch Ku includes a first terminal, a second terminal and a control terminal.
  • the first terminal of the pull-up switch Ku is connected to the configuration pin P4, and the second terminal of the pull-up switch Ku is connected to one end of the pull-up resistor Ru.
  • the control end of the pull-up switch Ku is connected to the control unit 2011, and the other end of the pull-up resistor Ru is connected to the power pin P1.
  • the control end of the pull-up switch Ku is also the control end of the pull-up switch resistance KR1, and the control unit 2011 can turn on the pull-up switch Ku, thereby controlling the pull-up switch resistance KR1 to be in an on state.
  • the control unit 2011 may also turn off the pull-up switch Ku, thereby controlling the pull-up switch resistor KR1 to be in a disconnected state.
  • the resistance value of the pull-up resistor Ru is also the resistance value of the pull-up switch resistor KR1.
  • the resistance value of the pull-up resistor Ru can be adapted to the target chip 202.
  • the resistance value of the pull-up resistor Ru may include any value from 4.7K ⁇ to 10K ⁇ .
  • the pull-down switch resistance KR3 may include a pull-down switch Kd and a pull-down resistance Rd.
  • the pull-down switch Kd includes a first terminal, a second terminal, and a control terminal.
  • the first terminal of the pull-down switch Kd is connected to the configuration pin P4, and the second terminal of the pull-down switch Kd is connected to one end of the pull-down resistor Rd.
  • the control end is connected to the control unit 2011, and the other end of the pull-down resistor Rd is grounded.
  • the control end of the pull-down switch Kd is also the control end of the pull-down switch resistance KR3, and the control unit 2011 can turn on the pull-down switch Kd, thereby controlling the pull-down switch resistance KR3 to be in a conducting state.
  • the control unit 2011 may also turn off the pull-down switch Kd, thereby controlling the pull-down switch resistance KR3 to be in an off state.
  • the pull-down resistor Rd has a relatively large resistance value, which can reduce the magnitude of the current passing through the pull-down switch KR3 when the pull-down switch Kd is turned on, which is beneficial to protect the pull-down switch Kd.
  • control unit 2011 may control the pull-up switch resistor KR1 to be in a disconnected state before the target chip 202 is powered on. It should be understood that before the target chip is powered on, the pull-up switch resistor KR1 is always in an off state.
  • the control unit 2011 may output a power-on signal through the power control pin P2.
  • the power-on signal can turn on a path for powering on the target chip 202.
  • the power-on signal may turn on the power switch MOS, thereby turning on the path between the power module 203 and the target chip 202, so that the power-on voltage output by the power module 203 can be transmitted to the target chip 202.
  • the power-on voltage will gradually increase from a lower initial voltage to the target voltage. After the power-on voltage stabilizes at the target voltage, the target chip 202 can be considered The power-up is complete.
  • control unit 2011 may control the pull-up switch resistor KR1 to be in the off state before the target time point.
  • the target time point is no earlier than the time point when the power-on voltage of the target chip 202 reaches the target voltage, that is, the time point when the target chip 202 is powered on.
  • control unit 2011 may calculate the aforementioned target time point according to the time point when the power-on signal is output and the time delay for the power-on voltage of the target chip 202 to reach the target voltage.
  • the time delay between the power-on voltage of the target chip 202 from the time when the power is started to the time point of the target voltage, that is, the power-on delay of the target chip 202, and the power-on delay can be preset in SoC201 .
  • control unit 2011 may also start timing after outputting the power-on signal. Before the timing of the timing reaches the first time delay, the pull-up switch resistor KR1 is controlled to be in an off state. Wherein, the time length of the first delay is not less than the power-on delay of the target chip 202.
  • control unit 2011 may include a processor and one or more registers.
  • the processor and the registers may be integrated in the same module or may be set independently, which is not limited in the embodiment of the present application.
  • the control unit 2011 includes a register 1 and a register 2, wherein the register 1 corresponds to the pull-up switch resistance KR1, that is, the register 1 is connected to the control end of the pull-up switch resistance KR1.
  • the register 2 corresponds to the pull-down switch resistance KR3, that is, the register 2 is connected to the control end of the pull-down switch resistance KR3.
  • the SoC201 may include N pull-up switch resistors (KR11 to KR1N, where N is an integer greater than 1) corresponding to the configuration pin P4.
  • the control unit 2011 includes registers 11 to 1N, and register 2.
  • the registers 11 to 1N respectively correspond to the pull-up switch resistances KR11 to KR1N
  • the register 2 corresponds to the pull-down switch resistance KR3.
  • the processor can write control information of the pull-up switch resistor KR1 to the register 1.
  • the register 1 then generates a drive signal according to the control information of the pull-up switch resistor KR1, and the drive signal can control the on or off of the pull-up switch resistor KR1.
  • the processor can write data 1 to the register 1.
  • the register 1 generates a driving signal a according to the written data 1, and provides the driving signal a to the pull-up switch resistor KR1, so that the pull-up switch resistor KR1 is turned on.
  • the processor can write data 0 to register 1.
  • the register 1 generates the driving signal b according to the written data 0, and provides the driving signal b to the pull-up switch resistance KR1, so that the pull-up switch resistance KR1 is turned off.
  • control method of the control unit 2011 on other switch resistors is similar to that of the pull-up switch resistor KR1, which will not be repeated here.
  • the N pull-up switch resistors in SoC201 are connected in parallel between the power supply pin P1 and the configuration pin P4.
  • the control unit 2011 configures the target chip 202, it can determine one or more target pull-up switch resistances among the N pull-up switch resistances, and control the one or more target pull-up switch resistances to be conductive.
  • the resistance values of the N pull-up switch resistors can be set according to the possible types of the target chip 202.
  • the resistance between different pull-up switch resistors can be the same or different.
  • the information of the target pull-up switch resistance can be set for the SoC201 according to the target chip 202.
  • the control unit 2011 configures the target chip 202, it may determine one or more target pull-up switch resistances among the N pull-up switch resistances according to the information of the target pull-up switch resistances.
  • the target pull-up switch resistance can adjust the high-level voltage of the control signal 1.
  • the parallel resistance of the multiple target pull-up switch resistances can adjust the high-level voltage of the control signal 1.
  • the embodiment of the present application also provides a control method.
  • This method can be applied to integrated circuits.
  • the integrated circuit may be an integrated circuit (SoC) as provided in any of the above-mentioned embodiments, which will not be repeated in the embodiment of the present application.
  • SoC integrated circuit
  • Fig. 5 exemplarily shows a schematic flow chart of a control method provided by an embodiment of the present application. As shown in Figure 5, the method mainly includes the following steps:
  • S501 Receive the power supply voltage through the power supply pin.
  • the pull-up switch resistance is a controllable switch resistance
  • the integrated circuit keeps the pull-up switch resistance off before the target chip is powered on, so that the pull-up voltage received by the pull-up switch resistance (that is, the integrated circuit The power supply voltage) will not be transmitted to the configuration pins, and thus will not be transmitted to the target chip. Therefore, the embodiments of the present application help prevent the target chip from receiving an error signal from the configuration pin before being powered on, thereby helping to improve the reliability of the integrated circuit.
  • the pull-up switch resistance in the present application is built into the integrated circuit, and the power supply voltage of the integrated circuit is used to provide the pull-up voltage for the pull-up switch resistance. Adopting this implementation mode is beneficial to simplify the structure of the peripheral circuit of the integrated circuit, and reduce the board area and production cost of the peripheral circuit.
  • the integrated circuit can determine whether it is necessary to continue to control the pull-up switch resistance to be in the off state according to the target time point.
  • the target time point is no earlier than the time point when the power-on voltage of the target chip reaches the target voltage.
  • the integrated circuit may control the pull-up switch resistance to be in an off state before the target time point.
  • the integrated circuit can also output a power-on signal through the power control pin of the integrated circuit, and the power-on signal can turn on the path for powering on the target chip; the integrated circuit can output the power-on signal according to the time point and The time delay for the power-on voltage of the target chip to reach the target voltage is calculated to obtain the above-mentioned target time point.
  • the integrated circuit may further include a pull-down switch resistor, the first end of the pull-down switch resistor is connected to the configuration pin, and the second end of the pull-down switch resistor is grounded.
  • the integrated circuit can control the pull-up switch resistance to be on or off after the target chip is powered on, and control the pull-down switch resistance to be on or off to generate a control signal; In turn, control signals can be output to the target chip through the configuration pins.
  • the integrated circuit provided in the embodiments of the present application may include multiple pull-up switch resistors connected in parallel.
  • the integrated circuit when the integrated circuit generates the control signal, it can determine one or more target pull-up switch resistances among the multiple pull-up switch resistances.
  • the integrated circuit can further control the above-mentioned one or more target pull-up switch resistances to be in an on state or an off state.
  • FIG. 6 is a schematic flowchart of a control method provided by an embodiment of the application. As shown in FIG. 6, it mainly includes the following steps:
  • SoC201 is powered on. Specifically, the SoC 201 can receive the power supply voltage provided by the power module 203 through the power pin P1 to complete power-on. Generally speaking, after the SoC201 is powered on, it can also perform operations such as initialization. During the execution of S601, the SoC201 controls the pull-up switch resistors KR1 and KR2 to be in a disconnected state.
  • SoC201 outputs a power-on signal. Specifically, the SoC201 can output a power-on signal to the power switch MOS through the power control pin P2. The power-on signal can turn on the power switch MOS, thereby turning on the path between the power module 203 and the target chip 202, so that the power-on voltage output by the power module 203 can be transmitted to the target chip 202.
  • the SoC201 controls the pull-up switch resistors KR1 and KR2 to be in a disconnected state.
  • SoC201 waits for the first time delay.
  • the time length of the first delay is not less than the power-on delay of the target chip 202.
  • the SoC201 After the SoC201 outputs the power-on signal, it can be considered that the target chip 202 starts to be powered on. After waiting for the first time delay, it can be considered that the target chip 202 has completed power-on.
  • the SoC201 controls the pull-up switch resistors KR1 and KR2 to be in a disconnected state.
  • SoC201 outputs a control signal. During this period, the SoC201 can control the pull-up switch resistor KR1 to be on or off to generate the control signal 1. And, the SoC201 can control the pull-up switch resistor KR2 to be in the on state or the off state to generate the control signal 2. The SoC201 can thus achieve control of the target chip 202 through the control signal 1 and the control signal 2.
  • this application can be provided as methods, systems, or computer program products. Therefore, this application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device.
  • the device implements the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.
  • These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment.
  • the instructions provide steps for implementing the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

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Abstract

一种集成电路、控制方法及系统，用以提高集成电路的可靠性。其中，集成电路主要包括电源管脚（P1）、配置管脚（P4，P5）、上拉开关电阻（KR1，KR2）和控制单元（2011），该集成电路能够通过其配置管脚（P4，P5）为目标芯片（202）提供控制信号。在集成电路中，上拉开关电阻（KR1，KR2）的第一端与电源管脚（P1）连接，上拉开关电阻（KR1，KR2）的第二端与配置管脚（P4，P5）连接，上拉开关电阻（KR1，KR2）的控制端与控制单元（2011）连接；电源管脚（P1）可以接收集成电路的供电电压；控制单元（2011）可以在目标芯片（202）上电之前，控制上拉开关电阻（KR1，KR2）处于断开状态。有利于防止目标芯片（202）在上电之前从集成电路的配置管脚（P4，P5）接收到误差信号，从而有利于提高集成电路的可靠性。此外，还有利于简化集成电路的外围电路的结构。

Description

一种集成电路、控制方法及系统 技术领域
本申请涉及集成电路技术领域，尤其涉及一种集成电路、控制方法及系统。
背景技术
目前，电子设备中常设置有集成电路，如片上系统(system on chip，SoC)，便是一种用于实现专用目标的集成电路。SoC中可以集成电子设备的大部分核心元件，能够控制电子设备中的其它芯片的工作状态。
例如，SoC在上电后，可以通过电源控制管脚控制目标芯片上电。在控制目标芯片上电后，SoC还可以通过配置管脚配置目标芯片中的参数。目前，为了适配目标芯片，往往需要在SoC的外围电路中往往为每个配置管脚设置有对应的上拉电阻，该上拉电阻的一端与对应的配置管脚连接，另一端与上拉电源连接。
然而，在目前的电子设备中，上拉电阻的上拉电源和SoC的供电电源通常为同一电源。也就是说，在SoC上电后，上拉电阻的上拉电源便会开始放电，致使配置管脚的电压被上拉，进而导致目标芯片在上电之前便会从SoC的配置管脚接收到信号，引起目标芯片工作异常。
因此。目前的SoC芯片的可靠性还有待进一步提高。
发明内容
本申请实施例提供一种集成电路、控制方法及系统，用以提高集成电路的可靠性。
第一方面，本申请实施例提供一种集成电路，其主要包括电源管脚、配置管脚、上拉开关电阻和控制单元，本申请实施例所提供的集成电路能够通过其配置管脚为目标芯片提供控制信号。在集成电路中，上拉开关电阻的第一端与电源管脚连接，上拉开关电阻的第二端与配置管脚连接，上拉开关电阻的控制端与控制单元连接；电源管脚可以接收集成电路的供电电压；控制单元可以在目标芯片上电之前，控制上拉开关电阻处于断开状态。
在本申请实施例所提供的集成电路中，上拉开关电阻为可控的开关电阻，控制单元在目标芯片上电之前控制上拉开关电阻处于断开状态，使得上拉开关电阻接收到的上拉电压(集成电路的供电电压)并不会被传输至配置管脚，进而也不会被传输至目标芯片。因此，本申请实施例有利于防止目标芯片在上电之前从集成电路的配置管脚接收到误差信号，从而有利于提高集成电路的可靠性。此外，上拉开关电阻内置于集成电路中，利用集成电路本身的供电电压为上拉开关电阻提供上拉电压。采用该实现方式，有利于简化集成电路的外围电路的结构，降低外围电路的占板面积和生产成本。
示例性的，控制单元在目标芯片上电之前，控制上拉开关电阻处于断开状态，具体可以是控制单元在目标时间点之前，控制上拉开关电阻处于断开状态，其中，目标时间点不早于目标芯片的上电电压到达目标电压的时间点。可以理解，在目标芯片的上电过程中，提供给目标芯片的上电电压可以是由较低的初始电压逐渐增大至目标电压，本申请实施例中控制单元在目标时间点之前，控制上拉开关电阻处于断开状态，也就是在目标芯片的上电电压到达目标电压之前，控制上拉开关电阻处于断开状态。有利于防止目标芯片在上电 过程中，从集成电路的配置管脚接收到误差信号。因此，采用本技术方案有利于进一步提高集成电路的可靠性。
在本申请实施例中，集成电路还可以包括电源控制管脚；控制单元还可以通过电源控制管脚输出上电信号，该上电信号可以导通对目标芯片进行上电的通路。在此情况下，集成电路还可以根据输出上电信号的时间点和目标芯片的上电电压到达目标电压的时延，计算得到上述目标时间点。
在本申请实施例中，集成电路能够通过配置管脚向目标芯片输出控制信号。示例性的，集成电路还可以包括下拉开关电阻，该下拉开关电阻的第一端与配置管脚连接，下拉开关电阻的第二端接地，下拉开关电阻的控制端与控制单元连接。在此情况下，控制单元还可以在目标芯片上电之后，控制上拉开关电阻处于导通状态或断开状态，以及控制下拉开关电阻处于导通状态或断开状态，以生成控制信号；进而可以通过配置管脚向目标芯片输出控制信号。
为了增加集成电路能够适用的目标芯片的类型，本申请实施例所提供的集成电路可以包括多个并联的上拉开关电阻。控制单元在生成控制信号时，可以确定多个上拉开关电阻中的一个或多个目标上拉开关电阻；控制单元进而可以控制一个或多个目标上拉开关电阻处于导通状态或断开状态。在确定一个目标上拉开关电阻时，该目标上拉开关电阻可以调节控制信号的高电平电压。在确定多个目标上拉开关电阻时，多个目标上拉开关电阻的并联电阻可以调节控制信号的高电平电压。采用该实现方式，通过调节控制单元所确定的一个或多个目标上拉开关电阻，便可以使集成电路能够适用不同类型的目标芯片。
示例性的，本申请实施例所提供的集成电路中，下拉开关电阻可以包括下拉开关和下拉电阻；下拉开关包括第一端、第二端和控制端；其中，下拉开关的第一端与配置管脚连接，下拉开关的第二端与下拉电阻的一端连接，下拉开关的控制端与控制单元连接，下拉电阻的另一端接地。下拉开关的控制端也就是下拉开关电阻的控制端，控制单元可以导通下拉开关，从而控制下拉开关电阻处于导通状态。控制单元也可以断开下拉开关，从而控制下拉开关电阻处于断开状态。
示例性的，本申请实施例所提供的集成电路中，上拉开关电阻可以包括上拉开关和上拉电阻；上拉开关包括第一端、第二端和控制端；上拉开关的第一端与配置管脚连接，上拉开关的第二端与上拉电阻的一端连接，上拉开关的控制端与控制单元连接，上拉电阻的另一端与电源管脚连接。上拉开关的控制端也就是上拉开关电阻的控制端，控制单元可以导通上拉开关，从而控制上拉开关电阻处于导通状态。控制单元也可以断开上拉开关，从而控制上拉开关电阻处于断开状态。
在本申请实施例中，上拉开关电阻的阻值能够适配于目标芯片。示例性的，上拉开关电阻的阻值可以包括4.7KΩ至10KΩ中的任一取值。
第二方面，本申请实施例提供一种控制方法，该方法可以应用于集成电路，第二方面中相应方案的技术效果可以参照第一方面中对应方案可以得到的技术效果，重复之处不予详述。示例性的，本申请实施例所适用的集成电路可以包括上拉开关电阻、电源管脚和配置管脚，其中，上拉开关电阻的第一端与电源管脚连接，上拉开关电阻的第二端与配置管脚连接，集成电路能够通过配置管脚为目标芯片提供控制信号；本申请实施例所提供的方法中，集成电路可以通过电源管脚接收供电电压；集成电路在目标芯片上电之前，控制上拉开关电阻处于断开状态。
为了进一步提高集成电路的可靠性，在一种可能的实现方式中，集成电路可以根据目标时间点判断是否需要继续控制上拉开关电阻处于断开状态。其中，目标时间点不早于所述目标芯片的上电电压到达目标电压的时间点。示例性的，集成电路在目标时间点之前，可以控制上拉开关电阻处于断开状态。
本申请实施例中，集成电路还可以通过集成电路的电源控制管脚输出上电信号，上电信号可以导通对目标芯片进行上电的通路；集成电路可以根据输出上电信号的时间点和目标芯片的上电电压到达目标电压的时延，计算得到上述目标时间点。
在本申请实施例中，集成电路还可以包括下拉开关电阻，该下拉开关电阻的第一端与配置管脚连接，该下拉开关电阻的第二端接地。在此情况下，集成电路可以在目标芯片上电之后，控制上拉开关电阻处于导通状态或断开状态，以及控制下拉开关电阻处于导通状态或断开状态，以生成控制信号；集成电路进而可以通过配置管脚向目标芯片输出控制信号。
为了增加集成电路能够适用的目标芯片的类型，本申请实施例所提供的集成电路中可以包括多个并联的上拉开关电阻。在此情况下，集成电路在生成控制信号时，可以确定多个上拉开关电阻中的一个或多个目标上拉开关电阻。集成电路进而可以控制上述一个或多个目标上拉开关电阻处于导通状态或断开状态。
在本申请实施例中，上拉开关电阻的阻值能够适配于目标芯片。示例性的，上拉开关电阻的阻值可以包括4.7KΩ至10KΩ中的任一取值。
第三方面，本申请实施例提供一种系统，该系统可以是电子设备。第三方面中相应方案的技术效果可以参照第一方面中对应方案可以得到的技术效果，重复之处不予详述。示例性的，本申请实施例所提供的系统可以包括目标芯片和如上述第一方面中任一项所提供的集成电路。
本申请的这些方面或其它方面在以下实施例的描述中会更加简明易懂。
附图说明
图1为一种电子设备结构示意图；
图2为本申请实施例提供的一种电子设备的系统结构示意图；
图3为本申请实施例提供的一种集成电路中局部结构放大示意图；
图4为本申请实施例提供的另一种集成电路中局部结构放大示意图；
图5为本申请实施例提供的一种控制方法流程示意图；
图6为本申请实施例提供的一种具体的控制方法流程示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。需要说明的是，在本申请实施例的描述中“至少一个”是指一个或多个，其中，多个是指两个或两个以上。鉴于此，本发明实施例中也可以将“多个”理解为“至少两个”。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示 相对重要性，也不能理解为指示或暗示顺序。
需要指出的是，本申请实施例中“连接”指的是电连接，两个电学元件连接可以是两个电学元件之间的直接或间接连接。例如，A与B连接，既可以是A与B直接连接，也可以是A与B之间通过一个或多个其它电学元件间接连接，例如A与B连接，也可以是A与C直接连接，C与B直接连接，A与B之间通过C实现了连接。
集成电路(integrated circuit，IC)是一种微型电子器件或部件，可以理解为，把一定数量的常用电子元件，如电阻、电容、晶体管等，以及这些元件之间的连线，通过半导体工艺集成在一起的具有特定功能的电路。例如，SoC、中央处理器(central processing unit，CPU)等芯片皆可以通过集成电路实现。
以SoC为例，SoC又可以称为系统级芯片，或系统芯片。SoC是一个用于实现专用目的集成电路。SoC中可以集成电子设备的大部分核心元件，从而构成一个微小型系统。
可以理解，SoC中往往无法集成电子设备的整个电子系统。因此，电子设备中，除SoC之外，还可能存在其它特定功能的功能芯片。例如，智能电视中除SoC之外，还设置有屏驱动芯片，屏驱动芯片又可以称为时间控制(timing control，TCON)芯片。TCON芯片是智能电视中，负责接收图像信号，并将图像信号转换成控制液晶屏的时序信号的处理芯片。
又例如，智能终端中除SoC之外，还设置有基带芯片。基带芯片是智能终端中，用来合成用于向外发射的基带信号，或对接收到的基带信号进行解码的芯片。根据电子设备类型的不同，功能芯片的类型也可以有所差异，本申请实施例对此不再一一列举。
作为电子设备核心的SoC可以控制其它功能芯片的工作。接下来，以TCON芯片为例进行说明。图1示例性示出了一种电子设备结构示意图，如图1所示，电子设备100主要包括SoC101、TCON芯片102和电源模组103。
如图1所示，SoC101可以包括电源管脚P1、电源控制管脚P2、数据管脚P3、配置管脚P4和配置管脚P5。其中，电源管脚P1与电源模组103连接，电源控制管脚P2与电源开关MOS连接，数据管脚P3、配置管脚P4和配置管脚P5则分别与TCON芯片102中对应的管脚连接。
电源开关MOS设置在SoC所在的SoC板上。电源开关MOS主要包括控制端、第一端和第二端。其中，电源开关MOS的控制端与SoC的电源控制管脚P2连接，电源开关MOS的第一端与电源模组103连接，电源开关MOS的第二端与TCON芯片连接。
电源模组103可以包括电池、电源管理单元(power management unit，PMU)、直流变换电路(direct-current converting circuit)等。电源模组103分别与SoC101和电源开关MOS的第一端连接。电源模组103能够向SoC101提供供电电压。一般来说，电源模组103向SoC提供的供电电压可以是3V3电压，即供电电压为3.3V。当然，也可以是其它电压，例如供电电压也可以是1.8V电压。SoC101可以通过电源管脚P1接收供电电压，从而完成上电。
SoC101上电之后，可以完成初始化等操作。之后，SoC101可以继续控制TCON芯片上电。具体来说，SoC101可以通过电源控制管脚P2向电源开关MOS发送上电信号。该上电信号可以导通电源开关MOS，进而导通电源模组103与TCON芯片102之间的通路。电源模组103向电源开关MOS输出上电电压VCC，上电电压VCC经电源开关MOS，传输至TCON芯片。TCON芯片接收上电电压VCC，进而完成上电。
TCON芯片上电之后，SoC101可以继续通过配置管脚P4向TCON芯片发送控制信号 1，以及通过配置管脚P5向TCON芯片发送控制信号2，从而可以通过控制信号1和控制信号2控制TCON芯片。
示例性的，SoC101可以通过控制信号1和控制信号2对TCON芯片进行配置，例如，配置TCON芯片的显示分区、比特数等参数。具体来说，控制信号1可以是高电平信号，对应数字1，也可以是低电平信号，对应数字0，控制信号2同理。因此TCON芯片中可以预先设置有4种配置类型，该4种配置类型分别对应00、01、10和11。SoC101可以通过控制信号1和控制信号2指示TOCN芯片具体的配置类型，该具体配置类型为4种配置类型中的任一种，使得TCON芯片102可以按照SoC101指示的具体配置类型完成配置。
对TCON芯片102完成配置之后，SoC101便可以通过数据管脚P3向TCON芯片102传输数据信号Data，使得TCON芯片102可以根据数据信号Data控制显示面板显示图像。
一般来说，为了提高配置管脚P4和配置管脚P5的稳定性，如图1所示，还可以在SoC101的外围电路中，设置与配置管脚P4对应的上拉电阻R1，以及与配置管脚P5对应的上拉电阻R2。
以上拉电阻R1为例，上拉电阻R1的一端与电源模组103连接，另一端与配置管脚P4连接。上拉电阻R1可以从电源模组103接收上拉电压，当配置管脚P4输出的控制信号1为高电平信号时，上拉电阻R1可以对其所接收到的上拉电压进行分压，从而抑制控制信号1的电压，以保护TCON芯片102。
一般来说，上拉电阻R1的阻值是根据TCON芯片102设置的，使得控制信号1为高电平信号时，控制信号1的电压既可以被TCON芯片102识别，又不至于因电流过大而损坏TCON芯片102。
如图1所示，上拉电阻R1的上拉电压和SoC101的供电电压同源。因此，当SoC101上电时，上拉电阻R1也会接收到上拉电压进而导致上拉电阻R1有可能向TCON芯片102提供一高电平信号。然而，由于SoC101在上电后通常不会立即导通电源开关MOS，例如SoC101需要先完成初始化，再导通电源开关MOS。因此，TCON芯片102在接收到上拉电阻R1提供的高电平信号时，TCON芯片102尚未完成上电，TCON芯片102在接收到上拉电阻R1提供的高电平信号后，有可能会产生误判。
有鉴于此，本申请实施例提供一种集成电路，该集成电路可以是SoC，也可以是CPU、微控制单元(microcontroller unit，MCU)等具备控制功能的集成电路，本申请实施例对此并不多作限制。为了便于表述，本申请实施例接下来继续以SoC为例进行说明。
图2示例性示出了本申请实施例适用的一种电子设备的系统结构示意图。如图2所示，电子设备200包括SoC201和目标芯片202。其中，目标芯片202可以是受SoC201控制的功能芯片，如基带芯片、TCON芯片、传感器芯片等与SoC201处于不同的电源域的功能芯片。
在一种可能的实现方式中，电子设备200还可以包括电源模组203，电源模组203可以为SoC201和目标芯片202供电。电源模组203的实现方式可以参考上述电源模组103，对此不再赘述。
如图2所示，SoC201主要包括电源管脚P1、配置管脚P4和P5、上拉开关电阻(KR1和KR2)和控制单元2011。应理解，SoC201可以包括一个或多个配置管脚，每个配置管脚皆对应有上拉开关电阻。如图2中，配置管脚P4对应有上拉开关电阻KR1，配置管脚P5对应有上拉开关电阻KR2。SoC201能够通过配置管脚P4和P5为目标芯片提供控制信 号。
如图2所示，上拉开关电阻KR1包括第一端、第二端和控制端。其中，上拉开关电阻KR1的第一端与电源管脚P1连接，因此，当SoC201通过电源管脚P1接收到供电电压后，供电电压也可以作为上拉开关电阻KR1的上拉电压。
上拉开关电阻KR1的第二端与配置管脚P4连接，上拉开关电阻KR1的控制端与控制单元2011连接。控制单元2011可以在目标芯片202上电之前，控制上拉开关电阻KR1处于断开状态。
应理解，配置管脚的数量并不影响本申请实施例的具体实现。例如，SoC201中可以只包括一个配置管脚，如只包括配置管脚P4，SoC201中也可以包括多个配置管脚，如包括配置管脚P4和P5。SoC201中包括多个配置管脚的情况下，多个配置管脚也对应有上拉开关电阻，且每个配置管脚与对应的上拉开关电阻之间的连接方式与配置管脚P4类似。
例如图2中，配置管脚P5对应有上拉开关电阻KR2。上拉开关电阻KR2包括第一端、第二端和控制端。其中，上拉开关电阻KR2的第一端与电源管脚P1连接，因此，当SoC201通过电源管脚P1接收到供电电压后，供电电压也可以作为上拉开关电阻KR2的上拉电压。上拉开关电阻KR2的第二端与配置管脚P5连接，上拉开关电阻KR2的控制端与控制单元2011连接。控制单元2011可以在目标芯片202上电之前，控制上拉开关电阻KR2处于断开状态。
接下来，在未特别说明的情况下，皆以配置管脚P4和上拉开关电阻KR1为例进行说明。SoC201中的其它配置管脚(如P5)和其它上拉开关电阻(如KR2)可以具有类似的实现方式，对此不再赘述。
本申请实施例中，上拉开关电阻KR1为可控的开关电阻，控制单元2011在目标芯片202上电之前保持上拉开关电阻KR1断开，使得上拉开关电阻KR1接收到的上拉电压(SoC201的供电电压)并不会被传输至配置管脚P4，进而也不会被传输至目标芯片202。因此，本申请实施例有利于防止目标芯片202在上电之前从配置管脚P4接收到误差信号，从而有利于提高SoC201的可靠性。
此外，本申请实施例中上拉开关电阻KR1内置于SoC201中，利用SoC本身的供电电压为上拉开关电阻KR1提供上拉电压。采用该实现方式，有利于简化SoC外围电路的结构，降低外围电路的占板面积和生产成本。
在目标芯片202上电之后，SoC201便可以通过配置管脚P4发送控制信号1。在本申请实施例中，控制信号1的具体实现方式主要根据目标芯片202的类型确定。例如，控制信号1可以是一高电平信号或低电平信号，以向目标芯片202指示配置类型，如上述对TCON芯片102的配置。又例如，控制信号1也可以携带目标芯片202的配置信息，如需要目标芯片202配置的各个参数的取值，目标芯片202可以根据配置信息完成配置。
示例性的，如图3所示，SoC201中还可以包括与配置管脚P4对应的下拉开关电阻KR3。下拉开关电阻KR3包括第一端、第二端和控制端。其中，下拉开关电阻KR3的第一端与配置管脚P4连接，下拉开关电阻KR3的第二端接地。控制单元2011可以在目标芯片202上电之后，控制上拉开关电阻KR1处于导通状态或断开状态，以及控制下拉开关电阻KR3处于导通状态或断开状态，以生成控制信号1。进而，通过配置管脚P4向目标芯片输出控制信号1。
具体来说，当上拉开关电阻KR1处于导通状态，下拉开关电阻KR3处于断开状态， 则控制信号1为高电平。当上拉开关电阻KR1处于断开状态，下拉开关电阻KR3处于导通状态，则控制信号1为低电平。因此，控制单元2011可以通过控制上拉开关电阻KR1处于导通状态或断开状态，以及控制下拉开关电阻KR3处于导通状态或断开状态生成控制信号1。
接下来，分别对上拉开关电阻KR1、下拉开关电阻KR3和控制单元2011作进一步的示例性说明。
上拉开关电阻KR1
在本申请实施例中，上拉开关电阻KR1的阻值可以与目标芯片适配。使得，在控制信号1为高电平时，控制信号1既可以被目标芯片202识别到，又不至于因电流过大而损坏目标芯片202。一般来说，上拉开关电阻的阻值可以包括4.7KΩ至10KΩ中的任一个阻值。
如图3所示，上拉开关电阻KR1包括上拉开关Ku和上拉电阻Ru。上拉开关Ku包括第一端、第二端和控制端，其中，上拉开关Ku的第一端与配置管脚P4连接，上拉开关Ku的第二端与上拉电阻Ru的一端连接，上拉开关Ku的控制端与控制单元2011连接，上拉电阻Ru的另一端与电源管脚P1连接。
上拉开关Ku的控制端也就是上拉开关电阻KR1的控制端，控制单元2011可以导通上拉开关Ku，从而控制上拉开关电阻KR1处于导通状态。控制单元2011也可以断开上拉开关Ku，从而控制上拉开关电阻KR1处于断开状态。
在此情况下，上拉电阻Ru的阻值也就是上拉开关电阻KR1的阻值。也就是说，上拉电阻Ru的阻值可以适配于目标芯片202。一般来说，上拉电阻Ru的阻值可以包括4.7KΩ至10KΩ中的任一取值。
下拉开关电阻KR3
如图3所示，下拉开关电阻KR3可以包括下拉开关Kd和下拉电阻Rd。下拉开关Kd包括第一端、第二端和控制端，其中，下拉开关Kd的第一端与配置管脚P4连接，下拉开关Kd的第二端与下拉电阻Rd的一端连接，下拉开关Kd的控制端与控制单元2011连接，下拉电阻Rd的另一端接地。
下拉开关Kd的控制端也就是下拉开关电阻KR3的控制端，控制单元2011可以导通下拉开关Kd，从而控制下拉开关电阻KR3处于导通状态。控制单元2011也可以断开下拉开关Kd，从而控制下拉开关电阻KR3处于断开状态。
一般来说，下拉电阻Rd具有较大的阻值，可以降低在下拉开关Kd导通时，经过下拉开关电阻KR3的电流大小，有利于保护下拉开关Kd。
控制单元2011
在本申请实施例中，控制单元2011可以在目标芯片202上电之前，控制上拉开关电阻KR1处于断开状态。应当理解，在目标芯片上电之前，上拉开关电阻KR1是始终处于断开状态的。
对于如TCON芯片这种需要较大工作电压的功能芯片，其需要一定的上电时延，才能完成上电。具体来说，控制单元2011可以通过电源控制管脚P2输出上电信号。上电信号可以导通对目标芯片202进行上电的通路。例如图2中，上电信号可以导通电源开关MOS， 从而导通电源模组203与目标芯片202之间的通路，使得电源模组203输出的上电电压可以被传输至目标芯片202。
由于目标芯片202的工作电压较大，为了保护目标芯片202，上电电压将会由较低的初始电压逐渐增大至目标电压，待上电电压稳定在目标电压后，才可以认为目标芯片202完成了上电。
有鉴于此，在一种可能的实现方式中，控制单元2011可以在目标时间点之前，控制上拉开关电阻KR1处于断开状态。其中，目标时间点不早于目标芯片202的上电电压到达目标电压的时间点，也就是目标芯片202完成上电的时间点。
示例性的，控制单元2011可以根据输出上电信号的时间点和目标芯片202的上电电压到达目标电压的时延，计算得到上述目标时间点。其中，目标芯片202的上电电压从开始上电的时间点到达目标电压的时间点之间的时延，也就是目标芯片202的上电时延，该上电时延可以预先设置于SoC201中。
在另一种可能的实现方式中，控制单元2011也可以在输出上电信号后开始计时。在计时的时常达到第一时延之前，控制上拉开关电阻KR1处于断开状态。其中，第一时延的时间长度不小于目标芯片202的上电时延。
接下来，对控制单元2011的结构作进一步的示例性说明。如图3所示，控制单元2011可以包括处理器和一个或多个寄存器，处理器和寄存器可以集成在同一个模块中，也可以独立设置，本申请实施例对此并不多作限制。
控制单元2011中的一个或多个寄存器，与受控制单元2011控制的开关电阻一一对应。例如图3中，控制单元2011包括寄存器1和寄存器2，其中寄存器1与上拉开关电阻KR1对应，即寄存器1与上拉开关电阻KR1的控制端连接。寄存器2与下拉开关电阻KR3对应，即寄存器2与下拉开关电阻KR3的控制端连接。
又例如图4中，SoC201可以包括N个与配置管脚P4对应的上拉开关电阻(KR11至KR1N，N为大于1的整数)。在此情况下，控制单元2011包括寄存器11至1N，以及寄存器2。其中，寄存器11至1N分别与上拉开关电阻KR11至KR1N对应，寄存器2与下拉开关电阻KR3对应。
以图3中的处理器与寄存器1为例，处理器可以向寄存器1写入上拉开关电阻KR1的控制信息。寄存器1继而根据上拉开关电阻KR1的控制信息生成驱动信号，该驱动信号可以控制上拉开关电阻KR 1的导通或断开。
以一具体示例说明。在需要导通上拉开关电阻KR 1时，处理器可以向寄存器1写入数据1。寄存器1根据被写入的数据1生成驱动信号a，并将驱动信号a提供给上拉开关电阻KR1，使上拉开关电阻KR1导通。在需要断开上拉开关电阻KR1时，处理器可以向寄存器1写入数据0。寄存器1根据被写入的数据0生成驱动信号b，并将驱动信号b提供给上拉开关电阻KR1，使上拉开关电阻KR1断开。
控制单元2011对其它开关电阻的控制方式与上拉开关电阻KR1类似，对此不再赘述。
如图4所示，SoC201中的N个上拉开关电阻并联于电源管脚P1和配置管脚P4之间。在此情况下，控制单元2011在对目标芯片202进行配置时，可以确定N个上拉开关电阻中的一个或多个目标上拉开关电阻，控制该一个或多个目标上拉开关电阻处于导通状态或断开状态，以及控制下拉开关电阻KR3处于导通状态或断开状态，以生成控制信号1。
在本申请实施例中，可以根据目标芯片202可能的类型设置N个上拉开关电阻的阻值。 不同的上拉开关电阻之间的阻值可以相同，也可以不同。
具体来说，可以根据目标芯片202为SoC201设置目标上拉开关电阻的信息。控制单元2011在对目标芯片202进行配置时，可以根据目标上拉开关电阻的信息确定N个上拉开关电阻中的一个或多个目标上拉开关电阻。
在确定一个目标上拉开关电阻时，该目标上拉开关电阻可以调节控制信号1的高电平电压。在确定多个目标上拉开关电阻时，多个目标上拉开关电阻的并联电阻可以调节控制信号1的高电平电压。
可以理解，在对目标芯片202进行配置时，N个上拉开关电阻中，除目标上拉开关电阻之外的其它上拉开关电阻处于断开状态，以免对控制信号1造成干扰。
基于相同的技术构思，本申请实施例还提供一种控制方法。该方法可以应用于集成电路。示例性的，该集成电路可以是如上述任一实施例所提供的集成电路(SoC)，本申请实施例对此不再赘述。
图5示例性示出了本申请实施例所提供的一种控制方法流程示意图。如图5所示，该方法主要包括以下步骤：
S501：通过电源管脚接收供电电压。
S502：在目标芯片上电之前，控制上拉开关电阻处于断开状态。
在本申请实施例中，上拉开关电阻为可控的开关电阻，集成电路在目标芯片上电之前保持上拉开关电阻断开，使得上拉开关电阻接收到的上拉电压(也就是集成电路的供电电压)并不会被传输至配置管脚，进而也不会被传输至目标芯片。因此，本申请实施例有利于防止目标芯片在上电之前从配置管脚接收到误差信号，从而有利于提高集成电路的可靠性。
此外，本申请中的上拉开关电阻内置于集成电路中，利用集成电路本身的供电电压为上拉开关电阻提供上拉电压。采用该实现方式，有利于简化集成电路外围电路的结构，降低外围电路的占板面积和生产成本。
为了进一步提高集成电路的可靠性，在一种可能的实现方式中，集成电路可以根据目标时间点判断是否需要继续控制上拉开关电阻处于断开状态。其中，目标时间点不早于所述目标芯片的上电电压到达目标电压的时间点。示例性的，集成电路在目标时间点之前，可以控制上拉开关电阻处于断开状态。
本申请实施例中，集成电路还可以通过集成电路的电源控制管脚输出上电信号，上电信号可以导通对目标芯片进行上电的通路；集成电路可以根据输出上电信号的时间点和目标芯片的上电电压到达目标电压的时延，计算得到上述目标时间点。
在本申请实施例中，集成电路还可以包括下拉开关电阻，该下拉开关电阻的第一端与配置管脚连接，该下拉开关电阻的第二端接地。在此情况下，集成电路可以在目标芯片上电之后，控制上拉开关电阻处于导通状态或断开状态，以及控制下拉开关电阻处于导通状态或断开状态，以生成控制信号；集成电路进而可以通过配置管脚向目标芯片输出控制信号。
为了增加集成电路能够适用的目标芯片的类型，本申请实施例所提供的集成电路中可以包括多个并联的上拉开关电阻。在此情况下，集成电路在生成控制信号时，可以确定多个上拉开关电阻中的一个或多个目标上拉开关电阻。集成电路进而可以控制上述一个或多 个目标上拉开关电阻处于导通状态或断开状态。
接下来，以图2所示的SoC201为例，通过一具体示例进行说明。图6为本申请实施例提供的一种控制方法流程示意图，如图6所示，主要包括以下步骤：
S601：SoC201上电。具体来说，SoC201可以通过电源管脚P1接收电源模组203提供的供电电压，从而完成上电。一般来说，SoC201在上电之后，还可以执行初始化等操作。SoC201在执行S601期间，控制上拉开关电阻KR1和KR2处于断开状态。
S602：SoC201输出上电信号。具体来说，SoC201可以通过电源控制管脚P2，向电源开关MOS输出上电信号。上电信号能够导通电源开关MOS，从而可以导通电源模组203与目标芯片202之间的通路，使电源模组203输出的上电电压可以被传输至目标芯片202。SoC201在执行S602期间，控制上拉开关电阻KR1和KR2处于断开状态。
S603：SoC201等待第一时延。其中，第一时延的时间长度不小于目标芯片202的上电时延。SoC201在输出上电信号之后，可以认为目标芯片202开始上电。在等待第一时延之后，可以认为目标芯片202完成了上电。SoC201在执行S603期间，控制上拉开关电阻KR1和KR2处于断开状态。
S604：SoC201输出控制信号。在此期间，SoC201可以控制上拉开关电阻KR1处于导通状态或断开状态，以生成控制信号1。以及，SoC201可以控制上拉开关电阻KR2处于导通状态或断开状态，以生成控制信号2。SoC201从而可以通过控制信号1和控制信号2实现对目标芯片202的控制。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内， 则本申请也意图包含这些改动和变型在内。

Claims (17)

  1. 一种集成电路，其特征在于，包括：电源管脚、配置管脚、上拉开关电阻和控制单元，所述集成电路能够通过所述配置管脚为目标芯片提供控制信号；
    所述上拉开关电阻的第一端与所述电源管脚连接，所述上拉开关电阻的第二端与所述配置管脚连接，所述上拉开关电阻的控制端与所述控制单元连接；
    所述电源管脚，用于接收所述集成电路的供电电压；
    所述控制单元，用于在所述目标芯片上电之前，控制所述上拉开关电阻处于断开状态。
  2. 根据权利要求1所述的集成电路，其特征在于，所述控制单元，具体用于：
    在目标时间点之前，控制所述上拉开关电阻处于断开状态，所述目标时间点不早于所述目标芯片的上电电压到达目标电压的时间点。
  3. 根据权利要求2所述的集成电路，其特征在于，所述集成电路还包括电源控制管脚；
    所述控制单元，还用于：
    通过所述电源控制管脚输出上电信号，所述上电信号用于导通对所述目标芯片进行上电的通路；
    根据输出上电信号的时间点和所述目标芯片的上电电压到达目标电压的时延，计算得到所述目标时间点。
  4. 根据权利要求1至3中任一项所述的集成电路，其特征在于，所述集成电路还包括下拉开关电阻，所述下拉开关电阻的第一端与所述配置管脚连接，所述下拉开关电阻的第二端接地，所述下拉开关电阻的控制端与所述控制单元连接；
    所述控制单元还用于：
    在所述目标芯片上电之后，控制所述上拉开关电阻处于导通状态或断开状态，以及控制所述下拉开关电阻处于导通状态或断开状态，以生成所述控制信号；
    通过所述配置管脚向所述目标芯片输出所述控制信号。
  5. 根据权利要求4所述的集成电路，其特征在于，所述集成电路包括多个并联的上拉开关电阻；
    所述控制单元具体用于：
    确定所述多个上拉开关电阻中的一个或多个目标上拉开关电阻；
    控制所述一个或多个目标上拉开关电阻处于导通状态或断开状态。
  6. 根据权利要求4或5所述的集成电路，其特征在于，所述下拉开关电阻包括下拉开关和下拉电阻；
    所述下拉开关包括第一端、第二端和控制端；
    其中，所述下拉开关的第一端与所述配置管脚连接，所述下拉开关的第二端与所述下拉电阻的一端连接，所述下拉开关的控制端与所述控制单元连接，所述下拉电阻的另一端接地。
  7. 根据权利要求1至6中任一项所述的集成电路，其特征在于，所述上拉开关电阻包括上拉开关和上拉电阻；
    所述上拉开关包括第一端、第二端和控制端；
    所述上拉开关的第一端与所述配置管脚连接，所述上拉开关的第二端与所述上拉电阻 的一端连接，所述上拉开关的控制端与所述控制单元连接，所述上拉电阻的另一端与所述电源管脚连接。
  8. 根据权利要求1至7中任一项所述的集成电路，其特征在于，所述上拉开关电阻的阻值适配于所述目标芯片。
  9. 根据权利要求1至8中任一项所述的集成电路，其特征在于，所述上拉开关电阻的阻值包括4.7KΩ至10KΩ中的任一阻值。
  10. 一种控制方法，其特征在于，应用于集成电路，所述集成电路包括上拉开关电阻、电源管脚和配置管脚，所述上拉开关电阻的第一端与所述电源管脚连接，所述上拉开关电阻的第二端与所述配置管脚连接，所述集成电路能够通过所述配置管脚为目标芯片提供控制信号；
    所述方法包括：
    通过所述电源管脚接收供电电压；
    在所述目标芯片上电之前，控制所述上拉开关电阻处于断开状态。
  11. 根据权利要求10所述的控制方法，其特征在于，所述在目标芯片上电之前，控制所述上拉开关电阻处于断开状态，具体包括：
    在目标时间点之前，控制所述上拉开关电阻处于断开状态，所述目标时间点不早于所述目标芯片的上电电压到达目标电压的时间点。
  12. 根据权利要求11所述的控制方法，其特征在于，通过所述电源管脚接收供电电压之后，还包括：
    通过所述集成电路的电源控制管脚输出上电信号，所述上电信号用于导通对所述目标芯片进行上电的通路；
    根据输出上电信号的时间点和所述目标芯片的上电电压到达目标电压的时延，计算得到所述目标时间点。
  13. 根据权利要求10至12中任一项所述的控制方法，其特征在于，所述集成电路还包括下拉开关电阻，所述下拉开关电阻的第一端与所述配置管脚连接，所述下拉开关电阻的第二端接地，所述方法还包括：
    在所述目标芯片上电之后，控制所述上拉开关电阻处于导通状态或断开状态，以及控制所述下拉开关电阻处于导通状态或断开状态，以生成控制信号；
    通过所述配置管脚向所述目标芯片输出所述控制信号。
  14. 根据权利要求13所述的控制方法，其特征在于，所述集成电路包括多个并联的上拉开关电阻；
    控制所述上拉开关电阻处于导通状态或断开状态，具体包括：
    确定所述多个上拉开关电阻中的一个或多个目标上拉开关电阻；
    控制所述一个或多个目标上拉开关电阻处于导通状态或断开状态。
  15. 根据权利要求10至14中任一项所述的控制方法，其特征在于，所述上拉开关电阻的阻值适配于所述目标芯片。
  16. 根据权利要求10至15中任一项所述的控制方法，所述上拉开关电阻的阻值包括4.7KΩ至10KΩ中的任一阻值。
  17. 一种系统，其特征在于，包括目标芯片和如权利要求1至9中任一项所述的集成电路。
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