WO2020133246A1 - 一种分时复用的复位装置、方法、及终端 - Google Patents

一种分时复用的复位装置、方法、及终端 Download PDF

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Publication number
WO2020133246A1
WO2020133246A1 PCT/CN2018/124971 CN2018124971W WO2020133246A1 WO 2020133246 A1 WO2020133246 A1 WO 2020133246A1 CN 2018124971 W CN2018124971 W CN 2018124971W WO 2020133246 A1 WO2020133246 A1 WO 2020133246A1
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Prior art keywords
reset
slave controller
interface
serial port
controller
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PCT/CN2018/124971
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English (en)
French (fr)
Inventor
张良钿
Original Assignee
福建联迪商用设备有限公司
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Application filed by 福建联迪商用设备有限公司 filed Critical 福建联迪商用设备有限公司
Priority to CN201880002683.0A priority Critical patent/CN109844685A/zh
Priority to PCT/CN2018/124971 priority patent/WO2020133246A1/zh
Publication of WO2020133246A1 publication Critical patent/WO2020133246A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Definitions

  • the invention relates to the technical field of resetting, in particular to a time-division multiplexing resetting device, method and terminal.
  • the existing reset technology includes two types, one is power-off reset, and the other is to generate a reset by generating a reset signal input to the reset pin of the controller chip.
  • the reset signal is usually generated by the IO pin of the master controller to the slave controller. This method requires the use of valuable resources such as the pins of the master controller, communication cables, and connector ports.
  • the present invention provides a time-multiplexed reset device, method and terminal, which solves the problem that when the IO pin of the master controller sends a reset signal to the slave controller, it needs to occupy a dedicated Problems with precious resources such as IO pins, communication cables, and connector ports.
  • the present invention provides a time-multiplexed reset device, including a reset circuit, a master controller, and a slave controller connected to the master controller through a serial port;
  • the reset circuit includes a first MOS transistor Q1, a second MOS transistor Q2, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a power supply, a ground wire, an input terminal and an output terminal;
  • the RX interface of the slave controller is connected to the input terminal, the input terminal is connected to the gate of Q1, the source of Q1 and one end of C1 are respectively connected to the ground; the drain of Q1 and the other end of C1 are respectively Connected to one end of R1; the drain of Q1 and the other end of C1 are respectively connected to the gate of Q2, the source of Q2 and one end of C2 are respectively connected to the ground; the drain of Q2 and C2 The other end is connected to one end of R2; the other end of R1 and the other end of R2 are connected to the power supply; the drain of Q2 and the other end of C2 are connected to the output end; the output end is connected to the slave controller The reset terminal is connected.
  • the present invention provides a reset device for time-sharing.
  • the serial port baud rate of the master controller is set to the first value (such as 50bps), the data is sent 0x00, and a continuous 10 is generated.
  • Low level signal, low level duration is 200ms, at this time Q1 is cut off, C1 is charged, when the potential at the upper end of C1 is higher than the turn-on voltage threshold of Q2, Q2 is turned on, C2 quickly discharges, and the output end outputs low level 0V makes the slave controller reset.
  • the main controller sends a high-level (3.3V) stop bit, Q1 turns on, C1 quickly discharges to 0V, Q2 ends, VCC slowly charges C2 through R2, and after a certain period of time, the voltage at the output rises to a certain voltage value , The reset ends.
  • the present invention connects the input terminal of the above reset circuit to the RX interface of the slave controller, and the output terminal is connected to the reset terminal. There is no need to pass a dedicated IO pin, which solves the problem that the IO pin of the master controller sends a reset signal to the slave control. The problem of using valuable resources such as dedicated IO pins, communication cables, and connector ports is required when using the device.
  • the present invention provides a reset method using the above time-division multiplexing reset device, including the following steps:
  • S2 The master controller sends preset data to the slave controller through the serial port;
  • the slave controller's RX interface is connected to the reset terminal of the slave controller through a reset circuit; after receiving a continuous low-level signal from the slave controller's RX interface, it is transmitted to the reset terminal through the reset circuit to complete the process Reset operation from the controller.
  • the invention also provides a time-multiplexed reset terminal, which includes a master controller, a slave controller and the reset circuit;
  • the master controller is connected to the slave controller through a serial port, and the RX interface of the slave controller Connected to the reset terminal of the slave controller through a reset circuit;
  • the master controller includes a first memory, a first processor, and a first computer program stored on the first memory and executable on the first processor;
  • the slave controller includes a second memory, a second processor, and a second computer program stored on the second memory and executable on the second processor; when the first processor executes the first computer program, the following step:
  • S2 Send preset data to the slave controller through the serial port
  • the invention provides a time-division multiplexing reset method and terminal.
  • the master controller is connected to the slave controller through a serial port; when the master controller receives a reset command, the baud rate of the serial port is adjusted to the first value; the master controller Send data to the slave controller through the serial port, and receive a continuous low-level signal from the RX interface of the slave controller, and transmit it to the reset terminal through the reset circuit to complete the reset operation of the slave controller.
  • the present invention can realize the function of time-division multiplexing through the above serial port. When the master controller needs to transmit data to the slave controller, it can be realized through the above serial port.
  • the baud rate of the serial port is adjusted The first value enables the master controller to send a low-level signal for a long time, and connects the RX interface to the reset terminal of the slave controller through a reset circuit to complete the reset operation of the slave controller.
  • the IO pin of the master controller sends a reset signal to the slave controller, it needs to occupy dedicated IO pins, communication cables, connector port lines and other precious resources.
  • FIG. 1 is a schematic structural diagram of a time-division multiplexing reset device according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of main steps of a time-division multiplexing reset method according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a time-multiplexed reset terminal according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a connection between a master controller and a slave controller according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of data transmitted by a master controller and a slave controller according to an embodiment of the present invention
  • the first memory 2. The first processor; 3. The second memory; 4. The second processor.
  • the master controller is connected to the slave controller through the serial port; when the master controller receives the reset command, the baud rate of the serial port is adjusted to the first value; the master controller sends data to the slave controller through the serial port After receiving a continuous low-level signal from the RX interface of the controller, it is transmitted to the reset terminal through the reset circuit to complete the reset operation of the slave controller.
  • the present invention provides a time-division multiplexing reset device, including a reset circuit, a master controller, and a slave controller connected to the master controller through a serial port;
  • the reset circuit includes a first MOS transistor Q1, a second MOS transistor Q2, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a power supply, a ground wire, an input terminal and an output terminal;
  • the RX interface of the slave controller is connected to the input terminal, the input terminal is connected to the gate of Q1, the source of Q1 and one end of C1 are respectively connected to the ground; the drain of Q1 and the other end of C1 are respectively Connected to one end of R1; the drain of Q1 and the other end of C1 are respectively connected to the gate of Q2, the source of Q2 and one end of C2 are respectively connected to the ground; the drain of Q2 and C2 The other end is connected to one end of R2; the other end of R1 and the other end of R2 are connected to the power supply; the drain of Q2 and the other end of C2 are connected to the output end; the output end is connected to the slave controller The reset terminal is connected.
  • the present invention provides a reset device for time-sharing, when the slave controller needs to be reset, set the serial port baud rate of the master controller to the first value (such as 50bps), and send data 0x00 , A continuous 10-bit low-level signal is generated, and the low-level duration is 200ms.
  • Q1 is turned off and C1 is charged.
  • Q2 is turned on, and C2 is quickly discharged
  • the terminal outputs low level 0V, making the slave controller reset.
  • the main controller sends a high-level (3.3V) stop bit, Q1 turns on, C1 quickly discharges to 0V, Q2 ends, VCC slowly charges C2 through R2, and after a certain period of time, the voltage at the output rises to a certain voltage value , The reset ends.
  • the present invention connects the input terminal of the above reset circuit to the RX interface of the slave controller, and the output terminal is connected to the reset terminal. There is no need to pass a dedicated IO pin, which solves the problem that the IO pin of the master controller sends a reset signal to the slave control. The problem of using valuable resources such as dedicated IO pins, communication cables, and connector ports is required when using the device.
  • both Q1 and Q2 are N-type MOS transistors.
  • the voltage of the power supply is a preset voltage value.
  • the master controller includes a first TX interface, a first RX interface, and a first ground interface;
  • the slave controller includes a TX interface, the RX interface, and a ground interface;
  • the first TX interface and the RX interface are connected through a UART serial port; the first RX interface and the TX interface are connected through a UART serial port; and the first ground wire interface is connected to the ground wire interface.
  • the above-mentioned first TX interface is an interface used by the master controller to send serial data to the slave controller;
  • the above-mentioned first RX interface is an interface used by the master controller to receive serial data sent from the controller;
  • the above-mentioned TX interface is The slave controller is used to send serial data to the interface of the master controller;
  • the above-mentioned RX interface is an interface used by the slave controller to receive serial data sent by the master controller.
  • the C1 capacitance is a preset first capacitance value
  • the C2 is a preset second capacitance value
  • the R1 is a preset first resistance value
  • the R2 is a preset second resistance value.
  • the present invention provides a reset method using the time-division multiplexing reset device, including the following steps:
  • S2 The master controller sends preset data to the slave controller through the serial port;
  • the slave controller's RX interface is connected to the reset terminal of the slave controller through a reset circuit; after receiving a continuous low-level signal from the slave controller's RX interface, it is transmitted to the reset terminal through the reset circuit to complete the process Reset operation from the controller.
  • the present invention provides a time-multiplexed reset method.
  • the master controller is connected to the slave controller through a serial port; when the master controller receives a reset command, the baud rate of the serial port is adjusted to the first value;
  • the master controller sends data to the slave controller through the serial port, the slave controller receives a continuous low-level signal from the RX interface, and transmits it to the reset terminal through the reset circuit to complete the reset operation of the slave controller.
  • the present invention can realize the function of time-division multiplexing through the above serial port. When the master controller needs to transmit data to the slave controller, it can be realized through the above serial port.
  • the baud rate of the serial port is adjusted The first value enables the master controller to send a low-level signal for a long time, and connects the RX interface to the reset terminal of the slave controller through a reset circuit to complete the reset operation of the slave controller.
  • the IO pin of the master controller sends a reset signal to the slave controller, it needs to occupy dedicated IO pins, communication cables, connector port lines and other precious resources.
  • the above-mentioned RX interface is an interface for receiving serial port data sent by the main controller; the above-mentioned preset first value is less than the baud rate of the serial port during normal communication (non-reset).
  • the method further includes: the master controller setting the serial port The baud rate is the preset second value.
  • the above second value is the baud rate during normal serial communication.
  • the S3 is replaced with:
  • the slave controller's RX interface is connected to the reset terminal of the slave controller through a bus expander GPIO; the slave controller's RX interface receives continuous low-level signals and transmits to the reset terminal through GPIO to complete the slave control The reset operation of the device.
  • the reset terminal can also receive continuous low-level signals through the above-mentioned different methods to ensure normal reset of the slave controller.
  • the master controller sending preset data to the slave controller through the serial port is specifically:
  • the main controller generates the first data according to the pre-stored preset data; the preset data is 0x00 data;
  • the first data includes a start bit, eight data bits, and a check bit; the first data start bit, data bit, and check bit are all zero;
  • the master controller sends the first data to the slave controller.
  • the slave controller can receive a continuous low level during reset to complete the reset of the slave controller; at the same time, the serial data communication between the master and slave controllers transmits the data
  • the format is the same as the format of the first data above, that is, the invention realizes the time-division multiplexing function, and does not change the data format between the master and slave controllers.
  • the serial port is a UART serial port, an SPI serial port, or an I2C serial port.
  • UART is a universal asynchronous transceiver (Universal The abbreviation of Asynchronous Receiver/Transmitter, usually referred to as "serial port", which is composed of two signal lines: TX (transmit data) and RX (receive data);
  • SPI is a serial peripheral interface (Serial The abbreviation of Peripheral Interface is a high-speed, full-duplex, synchronous communication bus; I2C is the abbreviation of Inter-Integrated Circuit, which is composed of serial data line SDA and serial clock line SCL.
  • the present invention provides a time-multiplexed reset terminal, including a master controller, a slave controller, and the reset circuit;
  • the master controller is connected to the slave controller through a serial port, and the slave control
  • the RX interface of the controller is connected to the reset end of the slave controller through a reset circuit;
  • the master controller includes a first memory 1, a first processor 2 and stored on the first memory 1 and can run on the first processor 2
  • the slave controller includes a second memory 3, a second processor 4 and a second computer program stored on the second memory 3 and executable on the second processor 4;
  • the first The processor 2 implements the following steps when executing the first computer program:
  • S2 Send preset data to the slave controller through the serial port
  • the present invention provides a time-multiplexed reset terminal.
  • the master controller is connected to the slave controller through a serial port; when the master controller receives a reset command, the baud rate of the serial port is adjusted to the first value;
  • the master controller sends data to the slave controller through the serial port, the slave controller receives a continuous low-level signal from the RX interface, and transmits it to the reset terminal through the reset circuit to complete the reset operation of the slave controller.
  • the present invention can realize the function of time-division multiplexing through the above serial port. When the master controller needs to transmit data to the slave controller, it can be realized through the above serial port.
  • the baud rate of the serial port is adjusted The first value enables the master controller to send a low-level signal for a long time, and connects the RX interface to the reset terminal of the slave controller through a reset circuit to complete the reset operation of the slave controller.
  • the IO pin of the master controller sends a reset signal to the slave controller, it needs to occupy dedicated IO pins, communication cables, connector port lines and other precious resources.
  • the above-mentioned RX interface is an interface for receiving serial port data sent by the main controller; the above-mentioned preset first value is less than the baud rate of the serial port during normal communication (non-reset).
  • the first processor executes The steps implemented by the first computer program further include: setting the serial port baud rate to a preset second value.
  • the above second value is the baud rate during normal communication of the serial port.
  • the "RX interface of the slave controller is connected to the reset terminal of the slave controller through a reset circuit" is replaced by "the RX interface of the slave controller passes The bus expander GPIO is connected to the reset end of the slave controller"; and replace the S3 with:
  • the RX interface receives continuous low-level signals and transmits them to the reset terminal through GPIO to complete the reset operation of the slave controller.
  • the reset terminal can also receive continuous low-level signals through the above-mentioned different methods to ensure normal reset of the slave controller.
  • sending preset data to the slave controller through the serial port is specifically:
  • the preset data is 0x00 data
  • the first data includes a start bit, eight data bits, and a check bit; the first data start bit, data bit, and check bit are all zero;
  • the slave controller can receive a continuous low level during reset to complete the reset of the slave controller; at the same time, the serial data communication between the master and slave controllers transmits the data
  • the format is the same as the format of the first data above, that is, the invention realizes the time-division multiplexing function, and does not change the data format between the master and slave controllers.
  • the serial port is a UART serial port, an SPI serial port or an I2C serial port.
  • the first embodiment of the present invention is:
  • the invention provides a time-division multiplexing reset device, including a reset circuit, a master controller and a slave controller connected with the master controller through a serial port;
  • the reset circuit includes a first MOS transistor Q1, a second MOS transistor Q2, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a power supply, a ground wire, an input terminal and an output terminal;
  • the RX interface of the slave controller is connected to the input terminal, the input terminal is connected to the gate of Q1, the source of Q1 and one end of C1 are respectively connected to the ground; the drain of Q1 and the other end of C1 are respectively Connected to one end of R1; the drain of Q1 and the other end of C1 are respectively connected to the gate of Q2, the source of Q2 and one end of C2 are respectively connected to the ground; the drain of Q2 and C2 The other end is connected to one end of R2; the other end of R1 and the other end of R2 are connected to the power supply; the drain of Q2 and the other end of C2 are connected to the output end; the output end is connected to the slave controller The reset terminal connection;
  • the input end is UART_RX in Figure 1;
  • the output end is /Reset_out in Figure 1;
  • Both Q1 and Q2 are N-type MOS transistors; the voltage of the power supply is a preset voltage value.
  • the master controller includes a first TX interface, a first RX interface, and a first ground interface;
  • the slave controller includes a TX interface, the RX interface, and a ground interface;
  • the first TX interface and the RX interface pass UART serial port connection;
  • the first RX interface and the TX interface are connected through a UART serial port;
  • the first ground wire interface is connected to the ground wire interface;
  • the C1 capacitor is a preset first capacitance value, and the C2 is a pre- Set a second capacitance value, the R1 is a preset first resistance value, and the R2 is a preset second resistance value;
  • the preset voltage value is 3.3V
  • the first resistance and the second resistance are both 20K ⁇
  • the first capacitance value and the second capacitance value are both 10uF.
  • Embodiment 2 is replaced with an SPI serial port or an I2C serial port.
  • the third embodiment of the present invention is:
  • the present invention provides a reset method using the time-division multiplexing reset device in Embodiment 1, including the following steps:
  • the master controller is connected to the slave controller through the serial port; when the master controller receives the reset command, the baud rate of the serial port is adjusted to the preset first value;
  • the first value is 50bps
  • the first value is less than the serial port baud rate value (9600 bps) when the master controller and the slave controller communicate normally; that is, by reducing the baud rate of the above serial port, the transmission time of the low-level signal is increased;
  • S2 The master controller sends preset data to the slave controller through the serial port;
  • the master controller sending preset data to the slave controller through the serial port is specifically:
  • the main controller generates the first data according to the pre-stored preset data; the preset data is 0x00 data;
  • the first data includes a start bit, eight data bits, and a check bit; the first data start bit, data bit, and check bit are all zero;
  • the master controller sends the first data to the slave controller.
  • the slave controller's RX interface is connected to the reset terminal of the slave controller through a reset circuit; after receiving a continuous low-level signal (zero voltage signal) from the slave controller's RX interface, it is transmitted to the reset terminal through the reset circuit
  • the master controller sets the serial port baud rate to a preset second value, thereby completing the reset restart operation of the slave controller;
  • the second value is 9600 bps; through the above method, the low-level duration input by the reset terminal can be made 200 ms to complete the reset operation of the slave controller.
  • the serial port is a UART serial port, an SPI serial port or an I2C serial port.
  • the slave controller's RX interface is connected to the reset terminal of the slave controller through a bus expander GPIO; the slave controller's RX interface receives continuous low-level signals and transmits to the reset terminal through GPIO to complete the slave control The reset operation of the device.
  • the fifth embodiment of the present invention is:
  • the invention provides a time-multiplexed reset terminal, including a master controller, a slave controller and the reset circuit; the master controller is connected to the slave controller through a serial port, and the RX interface of the slave controller is passed
  • the reset circuit is connected to the reset terminal of the slave controller;
  • the master controller includes a first memory 1, a first processor 2, and a first computer program stored on the first memory 1 and executable on the first processor 2
  • the slave controller includes a second memory 3, a second processor 4, and a second computer program stored on the second memory 3 and executable on the second processor 4; the first processor 2 executes the The following steps are realized when describing the first computer program:
  • the first value is 50bps
  • the first value is less than the serial port baud rate value (9600 bps) when the master controller and the slave controller communicate normally; that is, by reducing the baud rate of the above serial port, the transmission time of the low-level signal is increased;
  • S2 Send preset data to the slave controller through the serial port
  • sending the preset data to the slave controller through the serial port is specifically:
  • the preset data is 0x00 data
  • the first data includes a start bit, eight data bits, and a check bit; the first data start bit, data bit, and check bit are all zero;
  • the steps implemented by the first processor 2 when executing the first computer program further include:
  • S4 The master controller sets the serial port baud rate to a preset second value, thereby completing the reset restart operation of the slave controller;
  • the second value is 9600 bps; through the above method, the low-level duration input by the reset terminal can be made 200 ms to complete the reset operation of the slave controller.
  • the serial port is a UART serial port, an SPI serial port or an I2C serial port.
  • the RX interface receives continuous low-level signals and transmits them to the reset terminal through GPIO to complete the reset operation of the slave controller.
  • the seventh embodiment of the present invention is:
  • UART_TX is sent from the controller to the master control
  • UART_RX is the cable that the master controller sends to the slave controller.
  • the timing of the UART serial port signal is shown in Figure 5.
  • the RX interface of the slave controller will maintain a high level when it is idle. From high level to low level, a start bit is generated, followed by 8 data bits. And an optional stop bit, after which it becomes a high level to generate a stop bit to complete a communication.
  • the transmission characteristic of UART is to maintain a low level of up to 10 consecutive bits.
  • the invention uses the RX interface in the UART communication serial port to generate a reset signal through a specially designed circuit, and then resets the controller chip.
  • the circuit shown in Figure 1 includes two N-type MOS tubes: Q1 and Q2, two resistors: R1 and R2, and two capacitors: C1 and C2.
  • the signal from the RX interface of the controller has high and low levels alternately generated.
  • Q1 When the high level, Q1 is turned on, C1 voltage is equal to 0V, Q2 is turned off, and C2 voltage is equal to VCC; when the level is low, Q1 is turned off , VCC slowly charges C1 through R1, but because UART_RX maintains a low level of up to 10 consecutive bits, as long as UART_RX generates a high level, Q1 will turn on and C1 will immediately discharge to 0V, so the voltage of C1 is always low , Q2 cannot be turned on, and the voltage of the /Reset_out signal is equal to VCC.
  • the master controller When the master controller needs to reset the slave controller, the master controller only needs to set the baud rate of the UART to a very small value (such as 50bps), and then send 0x00 data to generate 9 consecutive low-level data, low Level duration is tens to hundreds of ms, or directly configure the RX interface as GPIO and output a long low level.
  • Q1 is turned off, VCC charges C1 through R1, so that the voltage of C1 is higher than the opening threshold of Q2, Q2 is turned on to quickly discharge C2, the /Reset_out signal quickly drops to 0V, and a reset signal is generated.
  • the main controller sets the UART baud rate to the normal value (9600bps), or reconfigures the UART_RX port line back to the UART function, UART_RX outputs high level, Q1 is turned on, C1 is discharged quickly, Q2 is turned off , VCC slowly charges C2 through R2, /Reset_out voltage rises slowly beyond the threshold of the reset pin of the slave controller, the reset ends, and the slave controller starts to work.
  • the communication baud rate of the UART serial port is 9600bps, VCC is 3.3V, Q1 and Q2 are optional BSS138 (conduction threshold is 0.9V), R1 and R2 are optional 20K ⁇ , C1 and C2 are optional 10uF, the reset from the controller is high
  • the level threshold is 2V.
  • the worst case is to send 0x00 data, resulting in a continuous 10-bit low level, the low level duration is 1ms, at this time Q1 is cut off, C1 is charged to 0.015V, far lower than the Q2 guide
  • the turn-on voltage threshold is not enough to turn on Q2, after which a high level (3.3V) stop bit is generated, Q1 turns on, and C1 quickly discharges to 0V. Therefore, in the serial communication process, Q2 is always cut off, and any communication data will not affect the reset.
  • /Reset_out rises above 2V, and the reset ends.
  • Another method is when the reset is required, the main controller configures the UART_RX port line as GPIO, and outputs a low level of 0V for more than a certain time (such as 200ms), and then configures the UART_RX as the normal baud rate UART serial port function to work
  • a certain time such as 200ms

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Abstract

本发明提供了一种分时复用的复位装置、方法及终端，主控制器通过串口与从控制器连接；当主控制器接到复位指令时，调节串口的波特率为预设的第一值；主控制器通过所述串口发送预设数据至从控制器；所述从控制器的RX接口通过复位电路与从控制器的复位端连接；从控制器的RX接口接收到连续的低电平信号后，通过复位电路传输至复位端，以完成所述从控制器的复位操作。本发明解决了由主控制器的IO管脚发送复位信号给从控制器时，需要占用专用的IO管脚和通讯线缆、连接器口线等宝贵资源的问题。

Description

一种分时复用的复位装置、方法、及终端 技术领域
本发明涉及复位技术领域，尤其涉及一种分时复用的复位装置、方法及终端。
 背景技术
目前的电子产品，在使用过程中经常会由于其系统软件的程序跑飞、电磁干扰或者操作不当等原因而导致产品出现死机、宕机等问题，必须进行重启或复位等操作。
现有的复位技术包括两种，一种是断电复位，另一种是通过产生复位信号输入给控制器芯片的复位管脚产生复位。在多个控制器的系统中，通常由主控制器的IO管脚产生复位信号给从控制器，这种方法需要占用主控器的管脚和通讯线缆、连接器口线等宝贵资源。
 技术问题
本发明所要解决的技术问题是：本发明提供了一种分时复用的复位装置、方法及终端，解决了由主控制器的IO管脚发送复位信号给从控制器时，需要占用专用的IO管脚和通讯线缆、连接器口线等宝贵资源的问题。
 技术解决方案
为了解决上述技术问题，本发明提供了一种分时复用的复位装置，包括复位电路、主控制器和与主控制器通过串口连接的从控制器；
所述复位电路包括第一MOS管Q1、第二MOS管Q2、第一电容C1、第二电容C2、第一电阻R1、第二电阻R2、电源、地线、输入端和输出端；所述从控制器的RX接口与输入端连接，所述输入端与Q1的栅极连接，所述Q1的源极和C1的一端分别与地线连接；所述Q1的漏极和C1的另一端分别与R1的一端连接；所述Q1的漏极和C1的另一端分别与Q2的栅极连接，所述Q2的源极和C2的一端分别与地线连接；所述Q2的漏极和C2的另一端分别与R2的一端连接；所述R1的另一端和R2的另一端分别与电源连接；所述Q2的漏极和C2的另一端分别与输出端连接；所述输出端与从控制器的复位端连接。
上述复位装置的有益效果为：
本发明提供了一种分时利用的复位装置，当需要对从控制器进行复位时，将主控制器的串口波特率设置成第一值（如50bps），发送数据0x00，产生连续的10位低电平信号，低电平持续时间为200ms，此时Q1截止，C1充电，当C1上端的电势高于Q2的导通电压门限，Q2导通，C2迅速放电，输出端输出低电平0V，使得从控制器复位。之后使主控制器发送高电平（3.3V）的停止位，Q1导通，C1迅速放电到0V，Q2截止，VCC通过R2缓慢给C2充电，一定时间后，输出端的电压上升到一定电压值时，复位结束。本发明通过上述复位电路的输入端与从控制器的RX接口连接，输出端与复位端连接，无需要通过专用的IO管脚，解决了由主控制器的IO管脚发送复位信号给从控制器时，需要占用专用的IO管脚和通讯线缆、连接器口线等宝贵资源的问题。
本发明提供了采用上述分时复用的复位装置的复位方法，包括以下步骤：
S1：当主控制器接到复位指令时，调节串口的波特率为预设的第一值；
S2：主控制器通过所述串口发送预设数据至从控制器；
S3：所述从控制器的RX接口通过复位电路与从控制器的复位端连接；从控制器的RX接口接收到连续的低电平信号后，通过复位电路传输至复位端，以完成所述从控制器的复位操作。
本发明还提供了一种分时复用的复位终端，包括主控制器、从控制器和所述复位电路；所述主控制器通过串口与从控制器连接，所述从控制器的RX接口通过复位电路与从控制器的复位端连接；所述主控制器包括第一存储器、第一处理器及存储在第一存储器上并可在第一处理器上运行的第一计算机程序；所述从控制器包括第二存储器、第二处理器及存储在第二存储器上并可在第二处理器上运行的第二计算机程序；所述第一处理器执行所述第一计算机程序时实现以下步骤：
S1：当接到复位指令时，调节串口的波特率为预设的第一值；
S2：通过所述串口发送预设数据至从控制器；
所述第二处理器执行所述第二计算机程序时实现以下步骤：
S3：RX接口接收到连续的低电平信号后，通过复位电路传输至复位端，以完成所述从控制器的复位操作。
 有益效果
上述方法和终端的有益效果为：
本发明提供了一种分时复用的复位方法及终端，主控制器通过串口与从控制器连接；当主控制器接到复位指令时，调节串口的波特率为第一值；主控制器通过串口发送数据至从控制器，从控制器的RX接口接收到连续的低电平信号，通过复位电路传输至复位端，以完成所述从控制器的复位操作。本发明通过上述的串口能够实现分时复用的功能，当主控制器需要向从控制器传输数据时通过上述串口能够实现，当需要对从控制器进行复位时，通过调节串口的波特率为第一值，能够使主控制器长时间发送低电平信号，并通过将RX接口通过复位电路与从控制器的复位端连接，以完成所述从控制器的复位操作，本发明解决了由主控制器的IO管脚发送复位信号给从控制器时，需要占用专用的IO管脚和通讯线缆、连接器口线等宝贵资源的问题。
 附图说明
图1为根据本发明实施例的一种分时复用的复位装置的结构示意图；
图2为根据本发明实施例的一种分时复用的复位方法的主要步骤示意图；
图3为根据本发明实施例的一种分时复用的复位终端的结构示意图；
图4为根据本发明实施例的主控制器和从控制器连接的结构示意图；
图5为根据本发明实施例的主控制器和从控制器传输的数据的示意图；
标号说明：
1、第一存储器；2、第一处理器；3、第二存储器；4、第二处理器。
 本发明的实施方式
为详细说明本发明的技术内容、所实现目的及效果，以下结合实施方式并配合附图详予说明。
本发明最关键的构思为：主控制器通过串口与从控制器连接；当主控制器接到复位指令时，调节串口的波特率为第一值；主控制器通过串口发送数据至从控制器，从控制器的RX接口接收到连续的低电平信号，通过复位电路传输至复位端，以完成所述从控制器的复位操作。
请参照图1，本发明提供了一种分时复用的复位装置，包括复位电路、主控制器和与主控制器通过串口连接的从控制器；
所述复位电路包括第一MOS管Q1、第二MOS管Q2、第一电容C1、第二电容C2、第一电阻R1、第二电阻R2、电源、地线、输入端和输出端；所述从控制器的RX接口与输入端连接，所述输入端与Q1的栅极连接，所述Q1的源极和C1的一端分别与地线连接；所述Q1的漏极和C1的另一端分别与R1的一端连接；所述Q1的漏极和C1的另一端分别与Q2的栅极连接，所述Q2的源极和C2的一端分别与地线连接；所述Q2的漏极和C2的另一端分别与R2的一端连接；所述R1的另一端和R2的另一端分别与电源连接；所述Q2的漏极和C2的另一端分别与输出端连接；所述输出端与从控制器的复位端连接。
从上述描述可知，本发明提供了一种分时利用的复位装置，当需要对从控制器进行复位时，将主控制器的串口波特率设置成第一值（如50bps），发送数据0x00，产生连续的10位低电平信号，低电平持续时间为200ms，此时Q1截止，C1充电，当C1上端的电势高于Q2的导通电压门限，Q2导通，C2迅速放电，输出端输出低电平0V，使得从控制器复位。之后使主控制器发送高电平（3.3V）的停止位，Q1导通，C1迅速放电到0V，Q2截止，VCC通过R2缓慢给C2充电，一定时间后，输出端的电压上升到一定电压值时，复位结束。本发明通过上述复位电路的输入端与从控制器的RX接口连接，输出端与复位端连接，无需要通过专用的IO管脚，解决了由主控制器的IO管脚发送复位信号给从控制器时，需要占用专用的IO管脚和通讯线缆、连接器口线等宝贵资源的问题。
进一步的，所述Q1和Q2均为N型MOS管。
从上述描述可知，通过上述结构，能够有效实现从控制器的复位。
进一步的，所述电源的电压为预设电压值。
进一步的，所述主控制器包括第一TX接口、第一RX接口和第一地线接口；所述从控制器包括TX接口、所述RX接口和地线接口；
所述第一TX接口和RX接口通过UART串口连接；所述第一RX接口和TX接口通过UART串口连接；所述第一地线接口与所述地线接口连接。
其中，上述的第一TX接口是主控制器用于发送串口数据至从控制器的接口；上述的第一RX接口是主控制器用于接收从控制器发送的串口数据的接口；上述的TX接口是从控制器用于发送串口数据至主控制器的接口；上述的RX接口是从控制器用于接收主控制器发送的串口数据的接口。
从上述描述可知，通过上述结构，能够实现主控制器与从控制器两者之间正常的数据传输。
进一步的，将UART串口替换为SPI串口或I2C串口。
从上述描述可知，通过上述的串口，能够有效实现数据通讯，以及从控制器的复位。
进一步的，所述C1电容为预设第一电容值，所述C2为预设第二电容值，所述R1为预设第一电阻值，所述R2为预设第二电阻值。
从上述可知，通过上述电容值及电阻值，能够保证主控制器与从控制器正常通讯时，并不能使得输出端输出低电平信号。
请参照图2，本发明提供了一种采用所述的分时复用的复位装置的复位方法，包括以下步骤：
S1：当主控制器接到复位指令时，调节串口的波特率为预设的第一值；
S2：主控制器通过所述串口发送预设数据至从控制器；
S3：所述从控制器的RX接口通过复位电路与从控制器的复位端连接；从控制器的RX接口接收到连续的低电平信号后，通过复位电路传输至复位端，以完成所述从控制器的复位操作。
从上述描述可知，本发明提供了一种分时复用的复位方法，主控制器通过串口与从控制器连接；当主控制器接到复位指令时，调节串口的波特率为第一值；主控制器通过串口发送数据至从控制器，从控制器的RX接口接收到连续的低电平信号，通过复位电路传输至复位端，以完成所述从控制器的复位操作。本发明通过上述的串口能够实现分时复用的功能，当主控制器需要向从控制器传输数据时通过上述串口能够实现，当需要对从控制器进行复位时，通过调节串口的波特率为第一值，能够使主控制器长时间发送低电平信号，并通过将RX接口通过复位电路与从控制器的复位端连接，以完成所述从控制器的复位操作，本发明解决了由主控制器的IO管脚发送复位信号给从控制器时，需要占用专用的IO管脚和通讯线缆、连接器口线等宝贵资源的问题。
其中，上述的RX接口是用于接收主控制器发送的串口数据的接口；上述的预设的第一值小于串口在正常通讯（非复位时）时的波特率。
进一步的，所述的分时复用的复位方法，所述从控制器的RX接口接收到连续的低电平信号后，通过复位电路传输至复位端之后还包括：主控制器设置所述串口波特率为预设的第二值。
从上述描述可知，上述第二值为串口正常通讯时的波特率，通过上述方法，能够快速完成从控制器的复位重启，提高了复位效率，以保证主控制器与从控制器之间的正常通讯功能。
进一步的，所述的分时复用的复位方法，将所述S3替换为：
所述从控制器的RX接口通过总线扩展器GPIO与从控制器的复位端连接；从控制器的RX接口接收到连续的低电平信号，通过GPIO传输至复位端，以完成所述从控制器的复位操作。
从上述描述可知，通过上述不同的方式，也能够使复位端接收连续的低电平信号，保证从控制器复位的正常进行。
进一步的，所述的分时复用的复位方法，所述主控制器通过所述串口发送预设数据至从控制器具体为：
主控制器根据预存的预设数据，生成第一数据；所述预设数据为0x00数据；
所述第一数据包括一位起始位、八位数据位和一位检验位；所述第一数据起始位、数据位和检验位均为零；
主控制器发送第一数据至从控制器。
从上述描述可知，通过上述方法，使得在复位时，从控制器能够接收到连续的低电平，以完成从控制器的复位；同时主、从控制器之间进行串口通讯时，传输的数据格式与上述第一数据的格式相同，即本发明实现了分时复用功能，且不改变主、从控制器之间传输数据格式，通过改变串口的皮特率及使传输的数据中的每一位均为零，即可实现上述功能。
进一步的，所述的分时复用的复位方法，所述串口为UART串口、SPI串口或I2C串口。
其中，UART：是通用异步收发传输器（Universal Asynchronous Receiver/Transmitter）的缩写，通常简称为“串口”，由TX（发送数据）和RX(接收数据)两根信号线组成；SPI：是串行外设接口（Serial Peripheral Interface）的缩写，是一种高速的，全双工，同步的通信总线；I2C是集成电路总线（Inter-Integrated Circuit）的缩写，由串行数据线SDA和串行时钟线SCL组成。
从上述描述可知，通过上述串口均能够实现上述复位功能。
请参照图3，本发明提供了一种分时复用的复位终端，包括主控制器、从控制器和所述复位电路；所述主控制器通过串口与从控制器连接，所述从控制器的RX接口通过复位电路与从控制器的复位端连接；所述主控制器包括第一存储器1、第一处理器2及存储在第一存储器1上并可在第一处理器2上运行的第一计算机程序；所述从控制器包括第二存储器3、第二处理器4及存储在第二存储器3上并可在第二处理器4上运行的第二计算机程序；所述第一处理器2执行所述第一计算机程序时实现以下步骤：
S1：当接到复位指令时，调节串口的波特率为预设的第一值；
S2：通过所述串口发送预设数据至从控制器；
所述第二处理器4执行所述第二计算机程序时实现以下步骤：
S3：RX接口接收到连续的低电平信号后，通过复位电路传输至复位端，以完成所述从控制器的复位操作。
从上述描述可知，本发明提供了一种分时复用的复位终端，主控制器通过串口与从控制器连接；当主控制器接到复位指令时，调节串口的波特率为第一值；主控制器通过串口发送数据至从控制器，从控制器的RX接口接收到连续的低电平信号，通过复位电路传输至复位端，以完成所述从控制器的复位操作。本发明通过上述的串口能够实现分时复用的功能，当主控制器需要向从控制器传输数据时通过上述串口能够实现，当需要对从控制器进行复位时，通过调节串口的波特率为第一值，能够使主控制器长时间发送低电平信号，并通过将RX接口通过复位电路与从控制器的复位端连接，以完成所述从控制器的复位操作，本发明解决了由主控制器的IO管脚发送复位信号给从控制器时，需要占用专用的IO管脚和通讯线缆、连接器口线等宝贵资源的问题。
其中，上述的RX接口是用于接收主控制器发送的串口数据的接口；上述的预设的第一值小于串口在正常通讯（非复位时）时的波特率。
进一步的，所述的一种分时复用的复位终端，所述从控制器的RX接口接收到连续的低电平信号后，通过复位电路传输至复位端之后，所述第一处理器执行第一计算机程序实现的步骤还包括：设置所述串口波特率为预设的第二值。
从上述描述可知，上述第二值为串口正常通讯时的波特率，通过上述终端，能够快速完成从控制器的复位重启，提高了复位效率，以保证主控制器与从控制器之间的正常通讯功能。
进一步的，所述的一种分时复用的复位终端，将“所述从控制器的RX接口通过复位电路与从控制器的复位端连接”替换为“所述从控制器的RX接口通过总线扩展器GPIO与从控制器的复位端连接”；并将所述S3替换为：
RX接口接收到连续的低电平信号，通过GPIO传输至复位端，以完成所述从控制器的复位操作。
从上述描述可知，通过上述不同的方式，也能够使复位端接收连续的低电平信号，保证从控制器复位的正常进行。
进一步的，所述的一种分时复用的复位终端，通过所述串口发送预设数据至从控制器具体为：
根据预存的预设数据，生成第一数据；所述预设数据为0x00数据；
所述第一数据包括一位起始位、八位数据位和一位检验位；所述第一数据起始位、数据位和检验位均为零；
发送第一数据至从控制器。
从上述描述可知，通过上述方法，使得在复位时，从控制器能够接收到连续的低电平，以完成从控制器的复位；同时主、从控制器之间进行串口通讯时，传输的数据格式与上述第一数据的格式相同，即本发明实现了分时复用功能，且不改变主、从控制器之间传输数据格式，通过改变串口的皮特率及使传输的数据中的每一位均为零，即可实现上述功能。
进一步的，所述的一种分时复用的复位终端，所述串口为UART串口、SPI串口或I2C串口。
从上述描述可知，通过上述串口均能够实现上述复位功能。
请参照图1，本发明的实施例一为：
本发明提供了一种分时复用的复位装置，包括复位电路、主控制器和与主控制器通过串口连接的从控制器；
所述复位电路包括第一MOS管Q1、第二MOS管Q2、第一电容C1、第二电容C2、第一电阻R1、第二电阻R2、电源、地线、输入端和输出端；所述从控制器的RX接口与输入端连接，所述输入端与Q1的栅极连接，所述Q1的源极和C1的一端分别与地线连接；所述Q1的漏极和C1的另一端分别与R1的一端连接；所述Q1的漏极和C1的另一端分别与Q2的栅极连接，所述Q2的源极和C2的一端分别与地线连接；所述Q2的漏极和C2的另一端分别与R2的一端连接；所述R1的另一端和R2的另一端分别与电源连接；所述Q2的漏极和C2的另一端分别与输出端连接；所述输出端与从控制器的复位端连接；
其中，输入端为图1中的UART_RX；输出端为图1中的/Reset_out；
所述Q1和Q2均为N型MOS管；所述电源的电压为预设电压值。所述主控制器包括第一TX接口、第一RX接口和第一地线接口；所述从控制器包括TX接口、所述RX接口和地线接口；所述第一TX接口和RX接口通过UART串口连接；所述第一RX接口和TX接口通过UART串口连接；所述第一地线接口与所述地线接口连接；所述C1电容为预设第一电容值，所述C2为预设第二电容值，所述R1为预设第一电阻值，所述R2为预设第二电阻值；
其中，预设电压值为3.3V，第一电阻和第二电阻值均为20KΩ，所述第一电容值和第二电容值匀为10uF。
本发明的实施例二为：
本发明的实施例二与实施例一的区别在于，将UART串口替换为SPI串口或I2C串口。
请参照图2，本发明的实施例三为：
本发明提供了一种采用实施例一中的分时复用的复位装置的复位方法，包括以下步骤：
S1：主控制器通过串口与从控制器连接；当主控制器接到复位指令时，调节串口的波特率为预设的第一值；
优选的，第一值为50bps；
其中，第一值小于主控制器与从控制器正常通讯时串口的波特率值（9600 bps）；即通过减少上述串口的波特率，增大低电平信号的传输时间；
S2：主控制器通过所述串口发送预设数据至从控制器；
其中，所述主控制器通过所述串口发送预设数据至从控制器具体为：
主控制器根据预存的预设数据，生成第一数据；所述预设数据为0x00数据；
所述第一数据包括一位起始位、八位数据位和一位检验位；所述第一数据起始位、数据位和检验位均为零；
主控制器发送第一数据至从控制器。
S2：所述从控制器的RX接口通过复位电路与从控制器的复位端连接；从控制器的RX接口接收到连续的低电平信号（零电压信号）后，通过复位电路传输至复位端；主控制器设置所述串口波特率为预设的第二值，从而完成所述从控制器的复位重启操作；
其中，优选的，第二值为9600bps；通过上述方法，能够使得复位端输入的低电平持续时间为200ms，完成从控制器的复位操作。
其中，所述串口为UART串口、SPI串口或I2C串口。
本发明的实施例四为：
本实施例四与实施例三的区别在于，将所述S3替换为：
所述从控制器的RX接口通过总线扩展器GPIO与从控制器的复位端连接；从控制器的RX接口接收到连续的低电平信号，通过GPIO传输至复位端，以完成所述从控制器的复位操作。
请参照图3，本发明的实施例五为：
本发明提供了一种分时复用的复位终端，包括主控制器、从控制器和所述复位电路；所述主控制器通过串口与从控制器连接，所述从控制器的RX接口通过复位电路与从控制器的复位端连接；所述主控制器包括第一存储器1、第一处理器2及存储在第一存储器1上并可在第一处理器2上运行的第一计算机程序；所述从控制器包括第二存储器3、第二处理器4及存储在第二存储器3上并可在第二处理器4上运行的第二计算机程序；所述第一处理器2执行所述第一计算机程序时实现以下步骤：
S1：当接到复位指令时，调节串口的波特率为预设的第一值；
优选的，第一值为50bps；
其中，第一值小于主控制器与从控制器正常通讯时串口的波特率值（9600 bps）；即通过减少上述串口的波特率，增大低电平信号的传输时间；
S2：通过所述串口发送预设数据至从控制器；
其中，通过所述串口发送预设数据至从控制器具体为：
根据预存的预设数据，生成第一数据；所述预设数据为0x00数据；
所述第一数据包括一位起始位、八位数据位和一位检验位；所述第一数据起始位、数据位和检验位均为零；
发送第一数据至从控制器。
所述第二处理器4执行所述第二计算机程序时实现以下步骤：
S3：RX接口接收到连续的低电平信号（零电压信号）后，通过复位电路传输至复位端；
所述第一处理器2执行所述第一计算机程序时实现的步骤还包括：
S4：主控制器设置所述串口波特率为预设的第二值，从而完成所述从控制器的复位重启操作；
其中，优选的，第二值为9600bps；通过上述方法，能够使得复位端输入的低电平持续时间为200ms，完成从控制器的复位操作。
其中，所述串口为UART串口、SPI串口或I2C串口。
本发明的实施例六为：
本实施例六与实施例五的区别在于，将“所述从控制器的RX接口通过复位电路与从控制器的复位端连接”替换为“所述从控制器的RX接口通过总线扩展器GPIO与从控制器的复位端连接”；并将所述S3替换为：
RX接口接收到连续的低电平信号，通过GPIO传输至复位端，以完成所述从控制器的复位操作。
请参照图1、图4和图5，本发明的实施例七为：
在使用UART串口进行通信的多控制器系统中，如图4所示，主控制器和从控制器之间使用UART_TX、UART_RX、GND三根线缆进行连接，其中UART_TX是从控制器发送给主控制器的线缆，UART_RX是主控制器发送给从控制器的线缆。UART串口信号时序如图5所示，从控制器的RX接口在空闲时会保持高电平，由高电平变为低电平则产生1个起始位，紧跟着是8个数据位和1个可选的停止位，之后变为高电平产生停止位完成一次通信。UART的传输特点是最多保持连续10个位的低电平。
本发明使用UART通信串口中的RX接口，通过特殊设计的电路，产生复位信号，进而复位控制器芯片。电路如图1所示，包括两颗N型MOS管：Q1和Q2、两颗电阻：R1和R2、两颗电容：C1和C2。
当串口处于空闲状态时，从控制器的RX接口的信号保持高电平，Q1导通，C1电压等于0V，Q2关断，/Reset_out信号的电压等于VCC。
当串口处于通信状态时，从控制器的RX接口的信号有高低电平交替产生，高电平时，Q1导通，C1电压等于0V，Q2关断，C2电压等于VCC；低电平时，Q1截止，VCC通过R1给C1缓慢充电，但由于UART_RX最多保持连续10个位的低电平，只要UART_RX一产生高电平，Q1就会导通，C1马上会放电到0V，因此C1电压始终较低，无法开启Q2，/Reset_out信号的电压等于VCC。
当主控制器需要对从控制器进行复位时，主控制器只要把UART的波特率设置成非常小的值（如50bps），然后发送0x00数据，产生连续9个位的低电平数据，低电平持续时间几十到几百个ms，或者直接把RX接口配置成GPIO并输出长时间的低电平。此时，Q1截止，VCC通过R1给C1充电，使得C1电压高于Q2的开启门限值，Q2导通使C2快速放电，/Reset_out信号迅速降低为0V，产生复位信号。当复位结束后，主控器再将UART的波特率设置为正常值（9600bps），或者重新将UART_RX口线配置回UART功能，UART_RX输出高电平，Q1导通，C1快速放电，Q2截止，VCC通过R2给C2缓慢充电，/Reset_out电压缓慢上升超过从控制器复位管脚的门限值，复位结束，从控制器开始工作。
此外，刚开机时，VCC上电后，/Reset_out电压缓慢上升，R2和C2也可以实现从控制器的上电复位。
本发明的实施例七为：
UART串口的通信波特率为9600bps，VCC为3.3V，Q1和Q2可选BSS138（导通门限为0.9V），R1和R2可选20KΩ，C1和C2可选10uF，从控制器的复位高电平门限为2V。
当串口处于空闲状态下，UART_RX为高电平3.3V，Q1导通，C1为0V，Q2截止，/Reset_out为3.3V，从控制器正常工作。
当串口处于通信状态下，最恶劣的情况是发送0x00数据，产生连续的10位低电平，低电平持续时间为1ms，此时Q1截止，C1充电到0.015V，远低于Q2的导通电压门限，不足以使Q2导通，之后产生高电平（3.3V）的停止位，Q1导通，C1迅速放电到0V。因此在串口通信过程中，Q2始终截止，任何通信数据对复位都不产生影响。
当需要对从控制器进行复位时，将主控制器的串口波特率设置成非常小的值（如50bps），发送数据0x00，产生连续的10位低电平，低电平持续时间为200ms，此时Q1截止，C1充电到2V，远高于Q2的导通电压门限，Q2导通，C2迅速放电，/Reset_out输出低电平0V，使得从控制器复位。之后产生高电平（3.3V）的停止位，Q1导通，C1迅速放电到0V，Q2截止，VCC通过R2缓慢给C2充电，约210ms后，/Reset_out上升到高于2V，复位结束。另一种方法是需要复位时，主控制器将UART_RX口线配置为GPIO，并输出低电平0V超过一定时间（如200ms），然后再将UART_RX配置为正常波特率的UART串口功能，工作过程同实施六，不再赘述。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等同变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种分时复用的复位装置，其特征在于，包括复位电路、主控制器和与主控制器通过串口连接的从控制器；
    所述复位电路包括第一MOS管Q1、第二MOS管Q2、第一电容C1、第二电容C2、第一电阻R1、第二电阻R2、电源、地线、输入端和输出端；所述从控制器的RX接口与输入端连接，所述输入端与Q1的栅极连接，所述Q1的源极和C1的一端分别与地线连接；所述Q1的漏极和C1的另一端分别与R1的一端连接；所述Q1的漏极和C1的另一端分别与Q2的栅极连接，所述Q2的源极和C2的一端分别与地线连接；所述Q2的漏极和C2的另一端分别与R2的一端连接；所述R1的另一端和R2的另一端分别与电源连接；所述Q2的漏极和C2的另一端分别与输出端连接；所述输出端与从控制器的复位端连接。
  2. 根据权利要求1所述的分时复用的复位装置，其特征在于，所述Q1和Q2均为N型MOS管。
  3. 根据权利要求1所述的分时复用的复位装置，其特征在于，所述电源的电压为预设电压值。
  4. 根据权利要求1所述的分时复用的复位装置，其特征在于，所述主控制器包括第一TX接口、第一RX接口和第一地线接口；所述从控制器包括TX接口、所述RX接口和地线接口；
    所述第一TX接口和RX接口通过UART串口连接；所述第一RX接口和TX接口通过UART串口连接；所述第一地线接口与所述地线接口连接。
  5. 根据权利要求4所述的分时复用的复位装置，其特征在于，将UART串口替换为SPI串口或I2C串口。
  6. 根据权利要求5所述的分时复用的复位装置，其特征在于，所述C1电容为预设第一电容值，所述C2为预设第二电容值，所述R1为预设第一电阻值，所述R2为预设第二电阻值。
  7. 一种采用权利要求1-6任意一项所述的分时复用的复位装置的复位方法，其特征在于，包括以下步骤：
    S1：当主控制器接到复位指令时，调节串口的波特率为预设的第一值；
    S2：主控制器通过所述串口发送预设数据至从控制器；
    S3：所述从控制器的RX接口通过复位电路与从控制器的复位端连接；从控制器的RX接口接收到连续的低电平信号后，通过复位电路传输至复位端，以完成所述从控制器的复位操作。
  8. 根据权利要求7所述的分时复用的复位方法，其特征在于，所述从控制器的RX接口接收到连续的低电平信号后，通过复位电路传输至复位端之后还包括：主控制器设置所述串口波特率为预设的第二值。
  9. 根据权利要求7所述的分时复用的复位方法，其特征在于，将所述S3替换为：
    所述从控制器的RX接口通过总线扩展器GPIO与从控制器的复位端连接；从控制器的RX接口接收到连续的低电平信号，通过GPIO传输至复位端，以完成所述从控制器的复位操作。
  10. 根据权利要求7所述的分时复用的复位方法，其特征在于，所述主控制器通过所述串口发送预设数据至从控制器具体为：
    主控制器根据预存的预设数据，生成第一数据；所述预设数据为0x00数据；
    所述第一数据包括一位起始位、八位数据位和一位检验位；所述第一数据起始位、数据位和检验位均为零；
    主控制器发送第一数据至从控制器。
  11. 根据权利要求7所述的分时复用的复位方法，其特征在于，所述串口为UART串口、SPI串口或I2C串口。
  12. 一种分时复用的复位终端，其特征在于，包括主控制器、从控制器和如权利要求1-6任意一项的所述复位电路；所述主控制器通过串口与从控制器连接，所述从控制器的RX接口通过复位电路与从控制器的复位端连接；所述主控制器包括第一存储器、第一处理器及存储在第一存储器上并可在第一处理器上运行的第一计算机程序；所述从控制器包括第二存储器、第二处理器及存储在第二存储器上并可在第二处理器上运行的第二计算机程序；所述第一处理器执行所述第一计算机程序时实现以下步骤：
    S1：当接到复位指令时，调节串口的波特率为预设的第一值；
    S2：通过所述串口发送预设数据至从控制器；
    所述第二处理器执行所述第二计算机程序时实现以下步骤：
    S3：RX接口接收到连续的低电平信号后，通过复位电路传输至复位端，以完成所述从控制器的复位操作。
  13. 根据权利要求12所述的分时复用的复位终端，其特征在于，所述从控制器的RX接口接收到连续的低电平信号后，通过复位电路传输至复位端之后，所述第一处理器执行第一计算机程序实现的步骤还包括：设置所述串口波特率为预设的第二值。
  14. 根据权利要求12所述的分时复用的复位终端，其特征在于，将“所述从控制器的RX接口通过复位电路与从控制器的复位端连接”替换为“所述从控制器的RX接口通过总线扩展器GPIO与从控制器的复位端连接”；并将所述S3替换为：
    RX接口接收到连续的低电平信号，通过GPIO传输至复位端，以完成所述从控制器的复位操作。
  15. 根据权利要求12所述的分时复用的复位终端，其特征在于，通过所述串口发送预设数据至从控制器具体为：
    根据预存的预设数据，生成第一数据；所述预设数据为0x00数据；
    所述第一数据包括一位起始位、八位数据位和一位检验位；所述第一数据起始位、数据位和检验位均为零；
    发送第一数据至从控制器。
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