WO2021145250A1 - Semiconductor device and power conversion device - Google Patents

Semiconductor device and power conversion device Download PDF

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Publication number
WO2021145250A1
WO2021145250A1 PCT/JP2021/000189 JP2021000189W WO2021145250A1 WO 2021145250 A1 WO2021145250 A1 WO 2021145250A1 JP 2021000189 W JP2021000189 W JP 2021000189W WO 2021145250 A1 WO2021145250 A1 WO 2021145250A1
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WO
WIPO (PCT)
Prior art keywords
metal layer
layer
semiconductor device
conductor layer
solder
Prior art date
Application number
PCT/JP2021/000189
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French (fr)
Japanese (ja)
Inventor
藤野　純司
道雄 小川
智香 川添
井本　裕児
翔平 小川
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2021571155A priority Critical patent/JP7418474B2/en
Priority to CN202180008642.4A priority patent/CN114930528A/en
Publication of WO2021145250A1 publication Critical patent/WO2021145250A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present disclosure relates to semiconductor devices and power conversion devices.
  • a semiconductor device including an insulating substrate, a circuit layer, solder arranged in the circuit layer, and a semiconductor element bonded to the circuit layer by solder.
  • the circuit layer includes an aluminum layer.
  • Aluminum has low wettability to solder. Therefore, in order to bond the semiconductor element to the circuit layer by soldering, it is necessary to provide a metal layer made of a metal having high wettability to the solder on the aluminum layer.
  • an oxide film is likely to be formed on the surface of the aluminum layer, it is difficult to provide a metal layer on the aluminum layer by plating.
  • the circuit layer includes a first aluminum layer (aluminum layer) and a first copper layer (metal layer).
  • the first copper layer (metal layer) is bonded to the first aluminum layer (aluminum layer) by solid phase diffusion bonding.
  • the first copper layer (metal layer) has higher wettability to solder than the first aluminum layer (aluminum layer).
  • the metal layer (first copper layer) is bonded to the conductor layer (first aluminum layer) by solid phase diffusion bonding.
  • the solid-phase diffusion bonding no liquid phase is generated on the contact surfaces of the metal layer (first copper layer) and the conductor layer (first aluminum layer). Therefore, when the contact surfaces of the metal layer (first copper layer) and the conductor layer (first aluminum layer) are provided with irregularities, the metal layer (first copper layer) becomes the conductor layer (first aluminum layer). Not enough contact. Therefore, the contact surface needs to be smoothed before the metal layer (first copper layer) is joined to the conductor layer (first aluminum layer) by solid phase diffusion bonding. That is, the conductor layer (first aluminum layer) of the substrate needs to be smoothed.
  • the present disclosure has been made in view of the above problems, and an object thereof is a semiconductor capable of bonding a semiconductor element to a metal layer having a higher wettability to solder than aluminum without the need for smoothing the conductor layer of the substrate. It is to provide an apparatus and a power conversion apparatus.
  • the semiconductor device of the present disclosure includes a substrate, a brazing material, a laminated material, a solder, and a semiconductor element.
  • the substrate includes a ceramic layer and a first conductor layer.
  • the first conductor layer is laminated on the ceramic layer.
  • the brazing material is arranged on the side opposite to the ceramic layer with respect to the first conductor layer.
  • the laminated material includes a first metal layer and a second metal layer.
  • the first metal layer is joined to the first conductor layer by a brazing material on the side opposite to the ceramic layer with respect to the first conductor layer.
  • the second metal layer is laminated on the first metal layer on the opposite side of the first metal layer from the first conductor layer.
  • the solder is arranged on the second metal layer.
  • the semiconductor element is bonded to the second metal layer by soldering.
  • the semiconductor element is electrically connected to the substrate via a laminated material.
  • the material of the first conductor layer and the first metal layer contains aluminum.
  • the second metal layer has higher wettability to solder than the first metal layer.
  • the first metal layer is joined to the first conductor layer by a brazing material on the side opposite to the ceramic layer with respect to the first conductor layer. Therefore, it is not necessary for the first conductor layer of the substrate to be smoothed.
  • the semiconductor element is bonded to the second metal layer by soldering.
  • the second metal layer has higher wettability to solder than the first metal layer. Therefore, the semiconductor element can be bonded to a metal layer having a higher wettability to solder than aluminum.
  • FIG. 5 is a cross-sectional view schematically showing a state of the semiconductor device in the step of joining the first metal layer to the first conductor layer by a brazing material in the method for manufacturing a semiconductor device according to the first embodiment.
  • FIG. 5 is a cross-sectional view schematically showing a state of the semiconductor device in the step of joining the semiconductor element to the second metal layer by solder in the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 5 is a cross-sectional view schematically showing a state of the semiconductor device in the step of joining the semiconductor element to the second metal layer by solder in the method for manufacturing the semiconductor device according to the first modification of the first embodiment.
  • FIG. 5 is a cross-sectional view schematically showing another state of the semiconductor device in the step of joining the semiconductor element to the second metal layer by solder in the method for manufacturing the semiconductor device according to the first modification of the first embodiment.
  • FIG. 5 is a cross-sectional view schematically showing a state of the semiconductor device in the step of joining the first metal layer to the first conductor layer by a brazing material in the method for manufacturing a semiconductor device according to the second embodiment. It is a block diagram which shows schematic structure of the power conversion apparatus which concerns on Embodiment 4.
  • FIG. FIG. 5 is a cross-sectional view schematically showing a state in which a plurality of substrate portions are mounted in the method for manufacturing a semiconductor device according to a second modification of the first embodiment.
  • FIG. 5 is a cross-sectional view schematically showing a state in which a second metal layer of a clad material is divided by a plurality of slits in the method for manufacturing a semiconductor device according to the fifth embodiment.
  • FIG. 5 is a cross-sectional view schematically showing a state in which a first metal layer and a second metal layer of a laminated material and a brazing material are integrated in the method for manufacturing a semiconductor device according to the sixth embodiment.
  • Embodiment 1 The configuration of the semiconductor device 100 according to the first embodiment will be described with reference to FIG.
  • the semiconductor device 100 includes a substrate 1, a laminate 2, a semiconductor element 3, a solder 4, a brazing material 5, a back surface brazing material 50, a heat sink 6, a case 7, and the like.
  • the wiring member 8 and the sealing material SR are included.
  • the semiconductor device 100 is a power semiconductor device for electric power.
  • the substrate 1 includes a ceramic layer 11, a first conductor layer 12, and a second conductor layer 13.
  • the substrate 1 extends in the in-plane direction.
  • the material of the ceramic layer 11 is, for example, aluminum nitride (AlN), alumina (aluminum oxide), silicon carbide (SiC), silicon nitride (SiN), or the like.
  • the material of the ceramic layer 11 is aluminum nitride (AlN).
  • the width of the ceramic layer 11 in the in-plane direction is, for example, 65 mm.
  • the length of the ceramic layer 11 in the in-plane direction is, for example, 65 mm.
  • the thickness of the ceramic layer 11 in the first direction is, for example, 0.64 mm.
  • the first direction is orthogonal to the in-plane direction.
  • the first conductor layer 12 is laminated on the ceramic layer 11.
  • the first conductor layer 12 is directly laminated on the ceramic layer 11 in the first direction.
  • the first conductor layer 12 is configured as a circuit pattern.
  • the second conductor layer 13 is laminated on the ceramic layer 11 on the opposite side of the first conductor layer 12.
  • the second conductor layer 13 is directly laminated on the ceramic layer 11 in the first direction.
  • the second conductor layer 13 sandwiches the ceramic layer 11 with the first conductor layer 12 in the first direction.
  • the second conductor layer 13 may be configured as a circuit pattern.
  • Each of the first conductor layer 12 and the second conductor layer 13 is attached to both sides of the ceramic layer 11.
  • the material of the first conductor layer 12 and the second conductor layer 13 contains aluminum (Al).
  • the material of the first conductor layer 12 and the second conductor layer 13 may be, for example, aluminum (Al) or an aluminum alloy such as A6063. In the present embodiment, the material of the first conductor layer 12 and the second conductor layer 13 is aluminum (Al).
  • the width of the first conductor layer 12 and the second conductor layer 13 in the in-plane direction is, for example, 61 mm.
  • the length of the first conductor layer 12 and the second conductor layer 13 in the in-plane direction is, for example, 61 mm.
  • the thickness of the first conductor layer 12 and the second conductor layer 13 in the first direction is, for example, 0.4 mm.
  • the laminated material 2 is laminated on the substrate 1 in the first direction. As shown in FIG. 1, the laminated material 2 includes a first metal layer 21 and a second metal layer 22.
  • the first metal layer 21 is joined to the first conductor layer 12 on the opposite side of the ceramic layer 11 with respect to the first conductor layer 12.
  • the thickness of the first metal layer 21 is, for example, 0.2 mm.
  • the brazing material 5 is arranged on the side opposite to the ceramic layer 11 with respect to the first conductor layer 12.
  • the first metal layer 21 is joined to the first conductor layer 12 by a brazing material 5.
  • the first metal layer 21 sandwiches the brazing material 5 with the first conductor layer 12.
  • the brazing material 5 is directly laminated on the substrate 1 and the laminated material 2 in the first direction.
  • the brazing material 5 is, for example, an aluminum-silicon brazing material.
  • the thickness of the brazing filler metal 5 is, for example, 0.1 mm.
  • the material of the first metal layer 21 contains aluminum.
  • the material of the first metal layer 21 may be, for example, aluminum (Al) or an aluminum alloy such as A6063. In the present embodiment, the material of the first metal layer 21 is aluminum (Al).
  • the second metal layer 22 is laminated on the first metal layer 21 on the opposite side of the first metal layer 21 from the first conductor layer 12.
  • the second metal layer 22 is directly laminated on the first metal layer 21.
  • the second metal layer 22 is arranged on the outermost surface side of the laminated material 2.
  • the thickness of the second metal layer 22 is, for example, 0.1 mm.
  • the second metal layer 22 has higher wettability to the solder 4 than the first metal layer 21.
  • the second metal layer 22 has higher wettability with respect to the solder 4 than aluminum (Al).
  • the material of the second metal layer 22 contains any of nickel (Ni), silver (Ag) and 42 alloy. 42 Alloy is an alloy containing iron (Fe) and nickel (Ni). In the present embodiment, the material of the second metal layer 22 contains nickel (Ni).
  • the laminated material 2 is a clad material including the first metal layer 21 and the second metal layer 22. Therefore, the first metal layer 21 is in close contact with the second metal layer 22 without any gap.
  • the first metal layer 21 and the second metal layer 22 may be pressure-bonded and integrated.
  • the clad material may be formed by laminating the first metal layer 21 and the second metal layer 22 by cold pressing, hot pressing, laser welding, friction stir welding, or the like. In the present embodiment, the first metal layer 21 and the second metal layer 22 are pressure-bonded and integrated by cold pressure welding.
  • the laminated material 2 may be formed by laminating the first metal layer 21 and the second metal layer 22 by vapor deposition, sputtering, or the like.
  • the minimum value of the thickness of the laminated lumber 2 is, for example, 30 ⁇ m or more and 50 ⁇ m or less.
  • the maximum thickness of the laminated lumber 2 is, for example, 10 mm.
  • the solder 4 is arranged on the second metal layer 22.
  • the solder 4 is arranged on the second metal layer 22 on the side opposite to the first metal layer 21 with respect to the second metal layer 22.
  • the material of the solder 4 is, for example, Sn-Ag-Cu (tin-silver-copper) -based solder, Sn-Sb-Ag (tin-antimon-silver) -based solder, and the like.
  • the materials of the solder 4 are, for example, Sn965.5Ag3-Cu0.5 (mass%) solder, Sn98.5-Ag1-Cu0.5 (mass%) solder and Sn96-Sb3-Ag1 (mass%). %) Solder, etc.
  • the material of the solder 4 in this embodiment is Sn96.5-Ag3-Cu0.5 (mass%) solder.
  • the material of the solder 4 may be copper (Cu) -tin (Sn) paste, nano-silver (Ag) paste, or the like. Bonding with copper (Cu) -tin (Sn) paste has high heat resistance because the dispersed copper powder is isothermally solidified. Bonding with nano-silver (Ag) paste is joined by low-temperature firing with nano-silver (Ag) particles.
  • the semiconductor element 3 is bonded to the second metal layer 22 by the solder 4.
  • the semiconductor element 3 is electrically connected to the substrate 1 via the laminated material 2.
  • the semiconductor element 3 is, for example, an insulated gate type bipolar transistor (IGBT: Insulated Gate Bipolar Transistor), a diode and a metal oxide semiconductor field effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor).
  • the semiconductor device 100 may include a plurality of semiconductor elements 3. In the present embodiment, the semiconductor device 100 includes a plurality of semiconductor elements 3.
  • One semiconductor element 3 is electrically connected to at least one of the terminal 9 and the other semiconductor element 3 via a wiring member 8.
  • the substrate 1, the laminated material 2, the semiconductor element 3, the wiring member 8, and the terminal 9 form an electric circuit.
  • the terminal 9 is insert-formed in the case 7.
  • the terminal 9 includes a signal terminal 91 and a main terminal 92.
  • the signal terminal 91 and the main terminal 92 are electrically connected to the semiconductor element 3.
  • the wiring member 8 is, for example, a bonding wire, a bonding ribbon, a plate-shaped electrode, or the like.
  • the wiring member 8 is wire-bonded to the semiconductor element 3.
  • the material of the bonding wire is, for example, aluminum (Al), copper (Cu), gold (Au), and the like.
  • the bonding wire may be a copper wire coated with aluminum (Al).
  • the wiring member 8 is a bonding wire made of aluminum (Al).
  • the diameter of the wiring member 8 connected to the signal terminal 91 is, for example, 0.15 mm.
  • the diameter of the wiring member 8 connected to the main terminal 92 is, for example, 0.3 mm.
  • the wiring member 8 is a bonding ribbon
  • the wiring member 8 is ribbon-bonded to the semiconductor element 3.
  • the wiring member 8 is directly soldered to the semiconductor element 3.
  • the heat sink 6 is joined to the second conductor layer 13 on the opposite side of the second conductor layer 13 from the first conductor layer 12.
  • the heat sink 6 is joined to the second conductor layer 13 by the back surface brazing material 50.
  • the back surface brazing material 50 is, for example, an aluminum-silicon brazing material.
  • the heat sink 6 includes a base plate 61 and a plurality of fin portions 62.
  • the base plate 61 is joined to the second conductor layer 13 by the back surface brazing material 50.
  • the plurality of fin portions 62 project from the base plate 61 toward the side opposite to the substrate 1 with respect to the base plate 61.
  • the case 7 surrounds the substrate 1, the laminated material 2, the semiconductor element 3, the solder 4, the brazing material 5, the back surface brazing material 50, the heat sink 6, and the wiring member 8.
  • the case 7 has a frame shape.
  • the material of Case 7 is, for example, PPS (PolyPhenylene Sulfide) resin and liquid crystal polymer (LCP: Liquid Crystal Polymer).
  • the material of the case 7 is a PPS resin.
  • the sealing material SR is injected into the internal space of the case 7.
  • the encapsulant SR is a liquid encapsulant.
  • the encapsulant SR may be, for example, an epoxy resin containing a silica filler, a silicone gel, or the like.
  • the semiconductor device 100 includes a transfer mold resin TR and a lead frame LF.
  • the lead frame LF includes an electrode 90.
  • the electrode 90 includes a signal electrode 93 and a main electrode 94.
  • the signal electrode 93 and the main electrode 94 are electrically connected to the semiconductor element 3.
  • the dimensions of the lead frame LF in the in-plane direction are, for example, 150 mm ⁇ 50 mm.
  • the thickness of the lead frame LF is, for example, 0.6 mm.
  • the transfer mold resin TR seals the substrate 1, the laminated material 2, the semiconductor element 3, the solder 4, the brazing material 5, the back surface brazing material 50, and the wiring member 8.
  • the transfer mold resin TR partially seals the electrode 90.
  • the substrate 1 includes a plurality of substrate portions 19. That is, the substrate 1 according to the present embodiment is individualized.
  • the substrate 1 is divided into, for example, two or six substrate portions 19.
  • the ceramic layer 11 includes a ceramic portion included in each of the plurality of substrate portions 19.
  • the conductor layer includes a conductor portion included in each of the plurality of substrate portions 19.
  • the manufacturing method of the semiconductor device 100 includes a step S101 in which the substrate 1, the laminated material 2, the solder 4, the semiconductor element 3 and the brazing material 5 are prepared, and the brazing material 5 in which the first metal layer 21 is formed. It includes a step S102 in which the semiconductor element 3 is bonded to the first conductor layer 12 and a step S103 in which the semiconductor element 3 is bonded to the second metal layer 22 by the solder 4.
  • step S101 in which the substrate 1, the laminate 2, the solder 4 (see FIG. 5), the semiconductor element 3 (see FIG. 5), and the brazing material 5 are prepared, the substrate 1 , Laminated material 2, solder 4 (see FIG. 5), semiconductor element 3 (see FIG. 5), and brazing material 5 are prepared.
  • the laminated lumber 2 in which the first metal layer 21 and the second metal layer 22 are laminated is prepared.
  • step S101 in which the substrate 1, the laminated material 2, the solder 4, the semiconductor element 3 and the brazing material 5 are prepared, the back surface brazing material 50, the heat sink 6, the case 7, and the terminal 9 are prepared.
  • the wiring member 8 and the sealing material SR are further prepared.
  • the terminal 9 is insert-molded into the case 7.
  • step S102 in which the first metal layer 21 is joined to the first conductor layer 12 by the brazing material 5, the first conductor layer 12 is opposite to the ceramic layer 11.
  • the brazing filler metal 5 is arranged on the side, the first metal layer 21 is joined to the first conductor layer 12 by the brazing filler metal 5.
  • step S102 in which the first metal layer 21 is joined to the first conductor layer 12 by the brazing material 5, the back surface brazing material 50 is sandwiched between the second conductor layer 13 and the heat sink 6, and then the second metal layer 22 Is joined to the heat sink 6 by the back surface brazing material 50.
  • the substrate 1, the laminated material 2, the brazing material 5, the back surface brazing material 50, and the heat sink 6 are sandwiched while being loaded by a jig (not shown).
  • the substrate 1, the laminated material 2, the brazing material 5, the back surface brazing material 50, and the heat sink 6 sandwiched by a jig (not shown) are joined by being heated at 580 ° C. for 3 minutes, for example.
  • the semiconductor element 3 is bonded to the second metal layer 22 by the solder 4.
  • the substrate 1 is positioned in the case 7 by an adhesive (not shown).
  • the semiconductor element 3 is electrically connected to the terminal 9 by the wiring member 8.
  • the sealing material SR (see FIG. 1) is injected into the case 7.
  • the encapsulant SR (see FIG. 1) is cured, for example, by heating at 150 ° C. for 1.5 hours. As a result, the case 7 is insulated and sealed.
  • the substrate 1 is positioned with respect to the lead frame LF.
  • the lead frame LF is positioned with respect to the mold M.
  • the substrate 1, the laminated material 2, the semiconductor element 3, the solder 4, and the brazing material 5 are arranged in the internal space of the mold M.
  • the mold M includes an upper mold M1 and a lower mold M2.
  • the dimensions of the upper die M1 and the lower die M2 in the in-plane direction are, for example, 100 mm ⁇ 80 mm.
  • the dimension of the upper mold M1 in the first direction is, for example, 70 mm.
  • the dimension of the lower mold M2 in the first direction is, for example, 100 mm.
  • the transfer mold resin TR (see FIG. 2) is poured into the internal space of the mold M while being pressurized and heated.
  • the transfer mold resin TR (see FIG. 2) is temporarily cured by heating at 170 ° C. for 5 minutes, for example.
  • the temporarily cured transfer mold resin TR (see FIG. 2) is removed from the mold M and then finally cured.
  • the transfer mold resin TR (see FIG. 2) is finally cured by heating at 170 ° C. for 2 hours in an oven (not shown), for example.
  • the first metal layer 21 is first formed by a brazing material 5 on the side opposite to the ceramic layer 11 with respect to the first conductor layer 12. It is joined to the conductor layer 12. Therefore, it is not necessary for the contact surface between the first conductor layer 12 and the first metal layer 21 to be smoothed. Therefore, it is not necessary for the first conductor layer 12 of the substrate 1 to be smoothed.
  • the semiconductor element 3 is bonded to the second metal layer 22 by the solder 4.
  • the second metal layer 22 has higher wettability with respect to the solder 4 than the first metal layer 21.
  • the material of the first metal layer 21 contains aluminum (Al). Therefore, the semiconductor element 3 can be bonded to the metal layer (second metal layer 22) having a higher wettability to the solder 4 than the aluminum (Al). Therefore, the semiconductor element 3 can be bonded more firmly by the solder 4 than when it is bonded to aluminum (Al).
  • the materials of the first conductor layer 12 and the first metal layer 21 contain aluminum (Al).
  • Al aluminum
  • the specific gravity of aluminum (Al) is smaller than that of copper (Cu), and the thermal conductivity of aluminum (Al) is high. Therefore, the dimensions and weight of the semiconductor device 100 can be reduced, and the heat dissipation of the semiconductor device 100 can be increased.
  • the first conductor layer 12 is bonded to the first conductor layer 12 by solid phase diffusion bonding and the material of the first metal layer 21 contains copper (Cu)
  • the first conductor layer 12 (aluminum). (Al)) and the first metal layer 21 (copper (Cu)) cause a eutectic reaction. Since the melting points of the first conductor layer 12 and the first metal layer 21 are lowered by the eutectic reaction, the first conductor layer 12 and the first metal layer 21 can be liquefied. Specifically, the first conductor layer 12 (aluminum (Al)) and the first metal layer 21 (copper (Cu)) are liquefied at, for example, 540 ° C.
  • the heat resistant temperature of the semiconductor device 100 Is 540 ° C. or lower. Further, the first conductor layer 12 and the first metal layer 21 need to be heated at a temperature lower than 540 ° C. for a long time.
  • the first metal layer 21 is joined to the first conductor layer 12 by the brazing material 5.
  • the materials of both the first metal layer 21 and the first conductor layer 12 contain aluminum (Al).
  • the first metal layer 21 is bonded to the first conductor layer 12 by the brazing material 5 at, for example, 570 ° C. or higher and 600 ° C. or lower. Therefore, the liquefaction of the first metal layer 21 and the first conductor layer 12 by the eutectic reaction can be suppressed. Therefore, the heat resistant temperature of the semiconductor device 100 is higher than that when the first metal layer 21 is bonded to the first conductor layer 12 by solid phase diffusion bonding and the material of the first metal layer 21 contains copper (Cu). Also expensive. As a result, the heat resistance of the semiconductor device 100 is improved. Further, the time required for joining the first conductor layer 12 and the first metal layer 21 is shorter than when the first metal layer 21 is joined to the first conductor layer 12 by solid phase diffusion bonding.
  • the laminated material 2 is a clad material including a first metal layer 21 and a second metal layer 22.
  • the laminated lumber 2 made of a clad material is cheaper than the laminated lumber 2 made of thin film or sputter. Therefore, the manufacturing cost of the semiconductor device 100 can be reduced. Further, the laminated material 2 made of a clad material has higher productivity than the laminated material 2 made by vapor deposition, sputtering, or the like. Therefore, the productivity of the semiconductor device 100 can be increased.
  • the laminated material 2 is a clad material including a first metal layer 21 and a second metal layer 22. Therefore, the first metal layer 21 is pressure-bonded and integrated with the second metal layer 22. Therefore, it is not necessary to smooth the surface of the first metal layer 21.
  • the material of the second metal layer 22 contains nickel (Ni). Nickel (Ni) has higher wettability with respect to the solder 4 than aluminum (Al). Therefore, the second metal layer 22 has higher wettability to the solder 4 than aluminum (Al). Therefore, the semiconductor element 3 can be bonded to the second metal layer 22 which has higher wettability to the solder 4 than aluminum (Al).
  • the semiconductor device 100 includes a heat sink 6. Therefore, the heat dissipation of the semiconductor device 100 is higher than that in the case where the semiconductor device 100 does not include the heat sink 6.
  • the substrate 1 includes a first conductor layer 12 and a second conductor layer 13. Therefore, when the heat sink 6 is bonded to the second conductor layer 13, the laminated lumber 2 can be bonded to the first conductor layer 12. As a result, the manufacturing cost of the semiconductor device 100 can be reduced.
  • the material of the first metal layer 21 may be an aluminum alloy. Therefore, the surface hardness of the first metal layer 21 is higher than that when the material of the first metal layer 21 is aluminum (Al). Further, the recrystallization temperature of the first metal layer 21 is higher than that when the material of the first metal layer 21 is aluminum (Al). Thereby, the quality and reliability of the first metal layer 21 can be improved.
  • the semiconductor device 100 includes a transfer mold resin TR.
  • the transfer mold resin TR is molded by a resin molding pressure higher than that of the sealing material SR. Therefore, the semiconductor device 100 has higher insulating property and heat dissipation than the case where the semiconductor device 100 contains the sealing material SR.
  • the substrate 1 includes a plurality of substrate portions.
  • the substrate 1 including the plurality of substrate portions is more easily deformed than the case where the substrate 1 is integrated due to the gaps between the plurality of substrate portions. Therefore, the substrate 1 is easily deformed by the warp due to the difference between the coefficient of thermal expansion of the ceramic layer 11 and the coefficient of thermal expansion of the first conductor layer 12, and the deformation due to the temperature cycle of the semiconductor device 100. Therefore, damage to the substrate 1 including the plurality of substrate portions due to a temperature change is suppressed as compared with the case where the substrate 1 is integrated.
  • the step S102 (see FIG. 3) in which the first metal layer 21 is joined to the first conductor layer 12 by the brazing material 5.
  • the brazing material 5 is arranged on the side opposite to the ceramic layer 11 with respect to the first conductor layer 12, and then the first metal layer 21 is joined to the first conductor layer 12 by the brazing material 5. Therefore, it is not necessary for the first conductor layer 12 of the substrate 1 to be smoothed.
  • the step S101 in which the semiconductor element 3 (see FIG. 5) and the brazing material 5 are prepared, the laminated material 2 in which the first metal layer 21 and the second metal layer 22 are laminated is prepared. Will be done. Therefore, the first metal layer 21 does not need to be smoothed.
  • the semiconductor element 3 is bonded to the second metal layer 22 by the solder 4.
  • the second metal layer 22 has higher wettability with respect to the solder 4 than aluminum (Al). Therefore, the semiconductor element 3 can be bonded to the second metal layer 22 which has higher wettability to the solder 4 than aluminum (Al). Therefore, the semiconductor element 3 can be bonded more firmly by the solder 4 than when it is bonded to aluminum (Al).
  • Embodiment 2 the configuration of the semiconductor device 100 according to the second embodiment will be described with reference to FIG. Unless otherwise specified, the second embodiment has the same configuration, manufacturing method, and action and effect as those of the first embodiment. Therefore, the same components as those in the first embodiment are designated by the same reference numerals, and the description will not be repeated.
  • the laminated material 2 further includes a third metal layer 23.
  • the third metal layer 23 is arranged between the first metal layer 21 and the second metal layer 22.
  • the material of the third metal layer 23 contains titanium (Ti).
  • the material of the third metal layer 23 may include a material that does not cause a low temperature eutectic reaction with aluminum (Al) such as stainless steel or steel.
  • the first metal layer 21, the second metal layer 22, and the third metal layer 23 are laminated in the first direction.
  • the third metal layer 23 is directly laminated on the first metal layer 21 and the second metal layer 22.
  • the thickness of the third metal layer 23 is, for example, 0.05 mm.
  • the material of the second metal layer 22 contains any of copper (Cu), nickel (Ni), silver (Ag) and 42 alloy. In the present embodiment, the material of the second metal layer 22 contains copper (Cu).
  • the third metal layer 23 is arranged between the first metal layer 21 and the second metal layer 22. Therefore, it is possible to prevent the surface roughness of the second metal layer 22 from changing due to the diffusion of the first metal layer 21 and the second metal layer 22. As a result, it is possible to prevent the second metal layer 22 from being less wetted with respect to the solder 4 due to the change in the surface roughness of the second metal layer 22.
  • the material of the third metal layer 23 contains titanium (Ti). Titanium (Ti) has higher heat resistance than nickel (Ni) and copper (Cu). Therefore, it is possible to suppress the eutectic reaction between the first metal layer 21 and the third metal layer 23.
  • the third metal layer 23 is arranged between the first metal layer 21 and the second metal layer 22, the first metal layer 21 and the second metal layer 22 are not directly laminated. Therefore, it is possible to suppress the eutectic reaction between the first metal layer 21 and the second metal layer 22. Therefore, the material of the second metal layer 22 can be appropriately selected.
  • the material of the second metal layer 22 contains copper (Cu). Copper (Cu) has higher wettability with respect to the solder 4 than nickel (Ni). Therefore, the semiconductor element 3 can be bonded to the second metal layer 22 more firmly than when the material of the second metal layer 22 contains nickel (Ni). Further, the semiconductor element 3 can be bonded to the second metal layer 22 by a silver sintering agent. Further, copper (Cu) has a higher thermal conductivity than nickel (Ni). Therefore, the semiconductor device 100 has higher heat dissipation than the case where the material of the second metal layer 22 contains nickel (Ni).
  • Embodiment 3 the configuration of the semiconductor device 100 according to the third embodiment will be described with reference to FIG. Unless otherwise specified, the third embodiment has the same configuration, manufacturing method, and action and effect as those of the first embodiment. Therefore, the same components as those in the first embodiment are designated by the same reference numerals, and the description will not be repeated. Note that in FIG. 9, for convenience of explanation, the semiconductor element 3 and the like are not shown.
  • the semiconductor device 100 further includes the back surface laminated material 20.
  • the back surface laminated material 20 is bonded to the substrate 1 on the side opposite to the laminated material 2 with respect to the substrate 1.
  • the back surface laminated material 20 may have the same structure as the laminated material 2.
  • the back surface laminated material 20 includes a back surface first metal layer 210 and a back surface second metal layer 220.
  • the back surface first metal layer 210 is joined to the second conductor layer 13 on the side opposite to the ceramic layer 11 with respect to the second conductor layer 13.
  • the back surface first metal layer 210 is joined to the second conductor layer 13 by the back surface brazing material 50.
  • the material of the back surface first metal layer 210 contains aluminum (Al).
  • the back surface second metal layer 220 is laminated on the back surface first metal layer 210 on the side opposite to the second conductor layer 13 with respect to the back surface first metal layer 210.
  • the back surface second metal layer 220 is directly bonded to the back surface first metal layer 210.
  • the back surface second metal layer 220 has higher wettability to the solder 4 than aluminum (Al).
  • the back surface second metal layer 220 sandwiches the substrate 1 with the second metal layer 22.
  • the semiconductor device 100 in the step S102 (see FIG. 3) in which the first metal layer 21 is joined to the first conductor layer 12 by the brazing material 5, the back surface first metal layer 210 is the second conductor layer by the back surface brazing material 50. It is joined to 13.
  • the semiconductor device 100 further includes a back surface laminated material 20. Therefore, each of the second metal layer 22 and the back surface second metal layer 220 is joined to each of the first conductor layer 12 and the second conductor layer 13 of the substrate 1. Therefore, the semiconductor element 3 (see FIG. 1) is placed on at least one of the first conductor layer 12 and the second conductor layer 13 of the substrate 1 via at least one of the second metal layer 22 and the back surface second metal layer 220. Can be electrically connected. Therefore, the design of the semiconductor device 100 is easier than in the case where the semiconductor element 3 (see FIG. 1) is electrically connected to the substrate 1 only by the second metal layer 22.
  • Embodiment 4 the semiconductor devices according to the above-described first to third embodiments and the fifth and sixth embodiments described later are applied to a power conversion device.
  • the present disclosure is not limited to a specific power conversion device, the case where the present disclosure is applied to a three-phase inverter will be described below as a fourth embodiment.
  • FIG. 11 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.
  • the power conversion system shown in FIG. 11 includes a power supply 101, a power conversion device 200, and a load 300.
  • the power supply 101 is a DC power supply, and supplies DC power to the power converter 200.
  • the power supply 101 can be composed of various things, for example, a DC system, a solar cell, a storage battery, a rectifier circuit connected to an AC system, or an AC / DC converter. May be good. Further, the power supply 101 may be configured by a DC / DC converter that converts the DC power output from the DC system into a predetermined power.
  • the power conversion device 200 is a three-phase inverter connected between the power supply 101 and the load 300, converts the DC power supplied from the power supply 101 into AC power, and supplies the AC power to the load 300. As shown in FIG. 11, the power conversion device 200 has a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. And have.
  • the load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200.
  • the load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices.
  • the load 300 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an air conditioner.
  • the main conversion circuit 201 includes a switching element and a freewheeling diode (not shown), and when the switching element switches, the DC power supplied from the power supply 101 is converted into AC power and supplied to the load 300.
  • the main conversion circuit 201 is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It can consist of six anti-parallel freewheeling diodes.
  • each switching element and each freewheeling diode of the main conversion circuit 201 is a switching element or freewheeling diode included in the semiconductor device 202 corresponding to any of the semiconductor devices of the above-described first to third embodiments.
  • the six switching elements are connected in series for each of the two switching elements to form an upper and lower arm, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. Then, the output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.
  • the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element
  • the drive circuit may be built in the semiconductor device 202, or a drive circuit may be provided separately from the semiconductor device 202. It may be provided.
  • the drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201.
  • a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of each switching element.
  • the drive signal When the switching element is kept on, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is kept off, the drive signal is a voltage equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).
  • the control circuit 203 controls the switching element of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the time (on time) at which each switching element of the main conversion circuit 201 should be in the on state is calculated based on the power to be supplied to the load 300.
  • the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit included in the main conversion circuit 201 so that an on signal is output to the switching element that should be turned on at each time point and an off signal is output to the switching element that should be turned off. Is output.
  • the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.
  • the power conversion device in order to apply the semiconductor devices according to the first to third embodiments as the semiconductor device 202 constituting the main conversion circuit 201, it is necessary to pretreat the conductor layer of the substrate. It is possible to realize a power conversion device capable of bonding a semiconductor element to a metal layer having a higher wettability to solder than aluminum.
  • the present disclosure is not limited to this, and can be applied to various power conversion devices.
  • a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used, and when power is supplied to a single-phase load, the present disclosure is provided to a single-phase inverter. You may apply it.
  • the present disclosure can be applied to a DC / DC converter or an AC / DC converter.
  • the power conversion device to which the present disclosure is applied is not limited to the case where the above-mentioned load is an electric motor, and is, for example, a power supply device for an electric discharge machine, a laser machine, an induction heating cooker, or a non-contact power supply system. It can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.
  • Embodiment 5 Next, the configuration of the semiconductor device 100 according to the fifth embodiment will be described with reference to FIGS. 13 and 14.
  • the laminated lumber 2 may be provided with a plurality of slits 22s. Either the first metal layer 21 or the second metal layer 22 is divided into a plurality of portions by a plurality of slits 22s. In FIG. 13, the second metal layer 22 is divided into a plurality of portions 229 by the plurality of slits 22s.
  • the warp of the laminated material 2 at a high temperature due to the difference between the coefficient of thermal expansion of the first metal layer 21 and the coefficient of thermal expansion of the second metal layer 22 can be suppressed. Since the warp of the laminated material 2 is suppressed, it is possible to suppress the formation of voids in the brazing material 5.
  • the bondability of the brazing material 5 is improved.
  • the first metal layer 21 may be divided into a plurality of portions by a plurality of slits. Even in this case, the warp due to the difference in the coefficient of thermal expansion is suppressed.
  • either the first metal layer 21 or the second metal layer 22 is divided into a plurality of portions according to the shape and dimensions of the semiconductor element 3 by the plurality of slits 22s.
  • the solder 4 it is possible to prevent the solder 4 from spreading too much on the upper surface of the second metal layer 22 when the semiconductor element 3 is mounted on the upper surface of the second metal layer 22. Therefore, it is possible to suppress problems such as the solder 4 flowing out to the soldered portion adjacent to the solder 4.
  • Embodiment 6 Next, the configuration of the semiconductor device 100 according to the sixth embodiment will be described with reference to FIG.
  • the first metal layer 21, the second metal layer 22, and the brazing material 5 of the laminated material 2 constitute a clad material. That is, the first metal layer 21, the second metal layer 22, and the brazing material 5 of the laminated material 2 may be integrated in advance. This further improves productivity and bondability.
  • the laminated material 2 may be provided with a plurality of slits 22s.
  • the plurality of slits 22s divide any one of the first metal layer 21, the second metal layer 22, and the brazing material 5 into a plurality of portions.

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Abstract

A semiconductor device (100) is provided with: a base plate (1); a brazing material (5); a laminated material (2); solder (4); and semiconductor elements (3). A first metal layer (21) is bonded to a first conductor layer (12) by the brazing material (5) at the opposite side of the first conductor layer (12) from a ceramic layer (11). A second metal layer (22) is layered on the first metal layer (21) at the opposite side of the first metal layer (21) from the first conductor layer (12). The semiconductor elements (3) are bonded to the second metal layer (22) by the solder (4). The materials of the first conductor layer (12) and the first metal layer (21) contain aluminum. The second metal layer (22) has higher wettability to the solder (4) than the first metal layer (21) does.

Description

半導体装置および電力変換装置Semiconductor devices and power converters
　本開示は、半導体装置および電力変換装置に関するものである。 The present disclosure relates to semiconductor devices and power conversion devices.
　従来、絶縁基板と、回路層と、回路層に配置されたはんだと、はんだによって回路層に接合された半導体素子とを備える半導体装置がある。回路層は、アルミニウム層を含んでいる。アルミニウムは、はんだに対する濡れ性が低い。このため、はんだによって半導体素子を回路層に接合するためには、アルミニウム層上にはんだに対する濡れ性が高い金属からなる金属層を設ける必要がある。しかしながら、アルミニウム層の表面には酸化膜が生じやすいため、めっきによってアルミニウム層上に金属層を設けることは困難である。 Conventionally, there is a semiconductor device including an insulating substrate, a circuit layer, solder arranged in the circuit layer, and a semiconductor element bonded to the circuit layer by solder. The circuit layer includes an aluminum layer. Aluminum has low wettability to solder. Therefore, in order to bond the semiconductor element to the circuit layer by soldering, it is necessary to provide a metal layer made of a metal having high wettability to the solder on the aluminum layer. However, since an oxide film is likely to be formed on the surface of the aluminum layer, it is difficult to provide a metal layer on the aluminum layer by plating.
　例えば、特開２０１４－２０９５３９号公報（特許文献１）に記載された半導体装置では、回路層は、第１アルミニウム層（アルミニウム層）と、第１銅層（金属層）とを含んでいる。第１銅層（金属層）は、第１アルミニウム層（アルミニウム層）に固相拡散接合によって接合されている。第１銅層（金属層）は、第１アルミニウム層（アルミニウム層）よりもはんだに対する濡れ性が高い。 For example, in the semiconductor device described in Japanese Patent Application Laid-Open No. 2014-209039 (Patent Document 1), the circuit layer includes a first aluminum layer (aluminum layer) and a first copper layer (metal layer). The first copper layer (metal layer) is bonded to the first aluminum layer (aluminum layer) by solid phase diffusion bonding. The first copper layer (metal layer) has higher wettability to solder than the first aluminum layer (aluminum layer).
特開２０１４－２０９５３９号公報Japanese Unexamined Patent Publication No. 2014-209039
　上記公報に記載された半導体装置では、金属層（第１銅層）は、導体層（第１アルミニウム層）に固相拡散接合によって接合されている。固相拡散接合では金属層（第１銅層）および導体層（第１アルミニウム層）の接触面に液相が発生しない。このため、金属層（第１銅層）および導体層（第１アルミニウム層）の接触面に凹凸が設けられている場合、金属層（第１銅層）が導体層（第１アルミニウム層）に十分に接触しない。したがって、金属層（第１銅層）が導体層（第１アルミニウム層）に固相拡散接合によって接合される前に、接触面が平滑にされる必要がある。すなわち、基板の導体層（第１アルミニウム層）が平滑にされる必要がある。 In the semiconductor device described in the above publication, the metal layer (first copper layer) is bonded to the conductor layer (first aluminum layer) by solid phase diffusion bonding. In the solid-phase diffusion bonding, no liquid phase is generated on the contact surfaces of the metal layer (first copper layer) and the conductor layer (first aluminum layer). Therefore, when the contact surfaces of the metal layer (first copper layer) and the conductor layer (first aluminum layer) are provided with irregularities, the metal layer (first copper layer) becomes the conductor layer (first aluminum layer). Not enough contact. Therefore, the contact surface needs to be smoothed before the metal layer (first copper layer) is joined to the conductor layer (first aluminum layer) by solid phase diffusion bonding. That is, the conductor layer (first aluminum layer) of the substrate needs to be smoothed.
　本開示は上記課題に鑑みてなされたものであり、その目的は、基板の導体層が平滑にされる必要がなく、かつ半導体素子をアルミニウムよりもはんだに対する濡れ性が高い金属層に接合できる半導体装置および電力変換装置を提供することである。 The present disclosure has been made in view of the above problems, and an object thereof is a semiconductor capable of bonding a semiconductor element to a metal layer having a higher wettability to solder than aluminum without the need for smoothing the conductor layer of the substrate. It is to provide an apparatus and a power conversion apparatus.
　本開示の半導体装置は、基板と、ろう材と、積層材と、はんだと、半導体素子とを備えている。基板は、セラミック層と、第１導体層とを含んでいる。第１導体層は、セラミック層に積層されている。ろう材は、第１導体層に対してセラミック層とは反対側に配置されている。積層材は、第１金属層と、第２金属層とを含んでいる。第１金属層は、第１導体層に対してセラミック層とは反対側でろう材によって第１導体層に接合されている。第２金属層は、第１金属層に対して第１導体層とは反対側で第１金属層に積層されている。はんだは、第２金属層に配置されている。半導体素子は、はんだによって第２金属層に接合されている。半導体素子は、積層材を介して基板に電気的に接続されている。第１導体層および第１金属層の材料は、アルミニウムを含んでいる。第２金属層は、第１金属層よりもはんだに対する濡れ性が高い。 The semiconductor device of the present disclosure includes a substrate, a brazing material, a laminated material, a solder, and a semiconductor element. The substrate includes a ceramic layer and a first conductor layer. The first conductor layer is laminated on the ceramic layer. The brazing material is arranged on the side opposite to the ceramic layer with respect to the first conductor layer. The laminated material includes a first metal layer and a second metal layer. The first metal layer is joined to the first conductor layer by a brazing material on the side opposite to the ceramic layer with respect to the first conductor layer. The second metal layer is laminated on the first metal layer on the opposite side of the first metal layer from the first conductor layer. The solder is arranged on the second metal layer. The semiconductor element is bonded to the second metal layer by soldering. The semiconductor element is electrically connected to the substrate via a laminated material. The material of the first conductor layer and the first metal layer contains aluminum. The second metal layer has higher wettability to solder than the first metal layer.
　本開示の半導体装置によれば、第１金属層は、第１導体層に対してセラミック層とは反対側でろう材によって第１導体層に接合されている。このため、基板の第１導体層が平滑にされる必要がない。また、半導体素子は、はんだによって第２金属層に接合されている。第２金属層は、第１金属層よりもはんだに対する濡れ性が高い。このため、半導体素子をアルミニウムよりもはんだに対する濡れ性が高い金属層に接合できる。 According to the semiconductor device of the present disclosure, the first metal layer is joined to the first conductor layer by a brazing material on the side opposite to the ceramic layer with respect to the first conductor layer. Therefore, it is not necessary for the first conductor layer of the substrate to be smoothed. Further, the semiconductor element is bonded to the second metal layer by soldering. The second metal layer has higher wettability to solder than the first metal layer. Therefore, the semiconductor element can be bonded to a metal layer having a higher wettability to solder than aluminum.
実施の形態１に係る半導体装置の構成を概略的に示す断面図である。It is sectional drawing which shows schematic the structure of the semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１の第１の変形例に係る半導体装置の構成を概略的に示す断面図である。It is sectional drawing which shows schematic the structure of the semiconductor device which concerns on 1st modification of Embodiment 1. FIG. 実施の形態１に係る半導体装置の製造方法を概略的に示すフローチャートである。It is a flowchart which shows roughly the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１に係る半導体装置の製造方法において、第１金属層がろう材によって第１導体層に接合される工程における半導体装置の状態を概略的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing a state of the semiconductor device in the step of joining the first metal layer to the first conductor layer by a brazing material in the method for manufacturing a semiconductor device according to the first embodiment. 実施の形態１に係る半導体装置の製造方法において、半導体素子がはんだによって第２金属層に接合される工程における半導体装置の状態を概略的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing a state of the semiconductor device in the step of joining the semiconductor element to the second metal layer by solder in the method for manufacturing the semiconductor device according to the first embodiment. 実施の形態１の第１の変形例に係る半導体装置の製造方法において、半導体素子がはんだによって第２金属層に接合される工程における半導体装置の状態を概略的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing a state of the semiconductor device in the step of joining the semiconductor element to the second metal layer by solder in the method for manufacturing the semiconductor device according to the first modification of the first embodiment. 実施の形態１の第１の変形例に係る半導体装置の製造方法において、半導体素子がはんだによって第２金属層に接合される工程における半導体装置の他の状態を概略的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing another state of the semiconductor device in the step of joining the semiconductor element to the second metal layer by solder in the method for manufacturing the semiconductor device according to the first modification of the first embodiment. 実施の形態２に係る半導体装置の構成を概略的に示す断面図である。It is sectional drawing which shows schematic the structure of the semiconductor device which concerns on Embodiment 2. FIG. 実施の形態３に係る半導体装置の構成を概略的に示す断面図である。It is sectional drawing which shows schematic the structure of the semiconductor device which concerns on Embodiment 3. FIG. 実施の形態２に係る半導体装置の製造方法において、第１金属層がろう材によって第１導体層に接合される工程における半導体装置の状態を概略的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing a state of the semiconductor device in the step of joining the first metal layer to the first conductor layer by a brazing material in the method for manufacturing a semiconductor device according to the second embodiment. 実施の形態４に係る電力変換装置の構成を概略的に示すブロック図である。It is a block diagram which shows schematic structure of the power conversion apparatus which concerns on Embodiment 4. FIG. 実施の形態１の第２の変形例に係る半導体装置の製造方法において、複数の基板部が搭載される状態を概略的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing a state in which a plurality of substrate portions are mounted in the method for manufacturing a semiconductor device according to a second modification of the first embodiment. 実施の形態５に係る半導体装置の製造方法において、クラッド材の第２金属層が複数のスリットによって分割された状態を概略的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing a state in which a second metal layer of a clad material is divided by a plurality of slits in the method for manufacturing a semiconductor device according to the fifth embodiment. 実施の形態５の半導体装置の構成を概略的に示す断面図である。It is sectional drawing which shows schematic the structure of the semiconductor device of Embodiment 5. 実施の形態６に係る半導体装置の製造方法において、積層材の第１金属層および第２金属層ならびにろう材が一体化された状態を概略的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing a state in which a first metal layer and a second metal layer of a laminated material and a brazing material are integrated in the method for manufacturing a semiconductor device according to the sixth embodiment.
　以下、実施の形態について図に基づいて説明する。なお、以下では、同一または相当する部分に同一の符号を付すものとし、重複する説明は繰り返さない。 Hereinafter, the embodiment will be described with reference to the figure. In the following, the same or corresponding parts will be designated by the same reference numerals, and duplicate description will not be repeated.
　実施の形態１．
　図１を用いて、実施の形態１に係る半導体装置１００の構成を説明する。図１に示されるように、半導体装置１００は、基板１と、積層材２と、半導体素子３と、はんだ４と、ろう材５と、裏面ろう材５０と、ヒートシンク６と、ケース７と、配線部材８と、封止材ＳＲとを含んでいる。半導体装置１００は、電力用のパワー半導体装置である。 Embodiment 1.
The configuration of the semiconductor device 100 according to the first embodiment will be described with reference to FIG. As shown in FIG. 1, the semiconductor device 100 includes a substrate 1, a laminate 2, a semiconductor element 3, a solder 4, a brazing material 5, a back surface brazing material 50, a heat sink 6, a case 7, and the like. The wiring member 8 and the sealing material SR are included. The semiconductor device 100 is a power semiconductor device for electric power.
　図１に示されるように、基板１は、セラミック層１１と、第１導体層１２と、第２導体層１３とを含んでいる。基板１は、面内方向に延びている。 As shown in FIG. 1, the substrate 1 includes a ceramic layer 11, a first conductor layer 12, and a second conductor layer 13. The substrate 1 extends in the in-plane direction.
　セラミック層１１の材料は、例えば、窒化アルミニウム（ＡｌＮ）、アルミナ（酸化アルミニウム）、炭化珪素（ＳｉＣ）窒化珪素（ＳｉＮ）などである。本実施の形態において、セラミック層１１の材料は、窒化アルミニウム（ＡｌＮ）である。 The material of the ceramic layer 11 is, for example, aluminum nitride (AlN), alumina (aluminum oxide), silicon carbide (SiC), silicon nitride (SiN), or the like. In this embodiment, the material of the ceramic layer 11 is aluminum nitride (AlN).
　セラミック層１１の面内方向における幅は、例えば、６５ｍｍである。セラミック層１１の面内方向における長さは、例えば、６５ｍｍである。セラミック層１１の第１方向における厚みは、例えば、０．６４ｍｍである。本実施の形態において、第１方向は、面内方向に直交している。 The width of the ceramic layer 11 in the in-plane direction is, for example, 65 mm. The length of the ceramic layer 11 in the in-plane direction is, for example, 65 mm. The thickness of the ceramic layer 11 in the first direction is, for example, 0.64 mm. In this embodiment, the first direction is orthogonal to the in-plane direction.
　図１に示されるように、第１導体層１２は、セラミック層１１に積層されている。第１導体層１２は、第１方向においてセラミック層１１に直接積層されている。第１導体層１２は、回路パターンとして構成されている。第２導体層１３は、セラミック層１１に対して第１導体層１２とは反対側に積層されている。第２導体層１３は、第１方向においてセラミック層１１に直接積層されている。第２導体層１３は、第１方向において第１導体層１２とでセラミック層１１を挟み込んでいる。第２導体層１３は、回路パターンとして構成されていてもよい。第１導体層１２および第２導体層１３の各々は、セラミック層１１の両面にそれぞれ貼り付けられている。 As shown in FIG. 1, the first conductor layer 12 is laminated on the ceramic layer 11. The first conductor layer 12 is directly laminated on the ceramic layer 11 in the first direction. The first conductor layer 12 is configured as a circuit pattern. The second conductor layer 13 is laminated on the ceramic layer 11 on the opposite side of the first conductor layer 12. The second conductor layer 13 is directly laminated on the ceramic layer 11 in the first direction. The second conductor layer 13 sandwiches the ceramic layer 11 with the first conductor layer 12 in the first direction. The second conductor layer 13 may be configured as a circuit pattern. Each of the first conductor layer 12 and the second conductor layer 13 is attached to both sides of the ceramic layer 11.
　第１導体層１２および第２導体層１３の材料は、アルミニウム（Ａｌ）を含んでいる。第１導体層１２および第２導体層１３の材料は、例えば、アルミニウム（Ａｌ）であってもよいし、Ａ６０６３などのアルミニウム合金であってもよい。本実施の形態において、第１導体層１２および第２導体層１３の材料は、アルミニウム（Ａｌ）である。 The material of the first conductor layer 12 and the second conductor layer 13 contains aluminum (Al). The material of the first conductor layer 12 and the second conductor layer 13 may be, for example, aluminum (Al) or an aluminum alloy such as A6063. In the present embodiment, the material of the first conductor layer 12 and the second conductor layer 13 is aluminum (Al).
　第１導体層１２および第２導体層１３の面内方向における幅は、例えば、６１ｍｍである。第１導体層１２および第２導体層１３の面内方向における長さは、例えば、６１ｍｍである。第１導体層１２および第２導体層１３の第１方向における厚みは、例えば、０．４ｍｍである。 The width of the first conductor layer 12 and the second conductor layer 13 in the in-plane direction is, for example, 61 mm. The length of the first conductor layer 12 and the second conductor layer 13 in the in-plane direction is, for example, 61 mm. The thickness of the first conductor layer 12 and the second conductor layer 13 in the first direction is, for example, 0.4 mm.
　積層材２は、基板１に第１方向に積層されている。図１に示されるように、積層材２は、第１金属層２１と、第２金属層２２とを含んでいる。 The laminated material 2 is laminated on the substrate 1 in the first direction. As shown in FIG. 1, the laminated material 2 includes a first metal layer 21 and a second metal layer 22.
　図１に示されるように、第１金属層２１は、第１導体層１２に対してセラミック層１１とは反対側で第１導体層１２に接合されている。第１金属層２１の厚みは、例えば、０．２ｍｍである。ろう材５は、第１導体層１２に対してセラミック層１１とは反対側に配置されている。第１金属層２１は、ろう材５によって第１導体層１２に接合されている。第１金属層２１は、第１導体層１２とでろう材５を挟み込んでいる。ろう材５は、基板１および積層材２に第１方向に直接積層されている。ろう材５は、例えば、アルミニウム－シリコンろう材である。ろう材５の厚みは、例えば、０．１ｍｍである。 As shown in FIG. 1, the first metal layer 21 is joined to the first conductor layer 12 on the opposite side of the ceramic layer 11 with respect to the first conductor layer 12. The thickness of the first metal layer 21 is, for example, 0.2 mm. The brazing material 5 is arranged on the side opposite to the ceramic layer 11 with respect to the first conductor layer 12. The first metal layer 21 is joined to the first conductor layer 12 by a brazing material 5. The first metal layer 21 sandwiches the brazing material 5 with the first conductor layer 12. The brazing material 5 is directly laminated on the substrate 1 and the laminated material 2 in the first direction. The brazing material 5 is, for example, an aluminum-silicon brazing material. The thickness of the brazing filler metal 5 is, for example, 0.1 mm.
　第１金属層２１の材料は、アルミニウムを含んでいる。第１金属層２１の材料は、例えば、アルミニウム（Ａｌ）であってもよいし、Ａ６０６３などのアルミニウム合金であってもよい。本実施の形態において、第１金属層２１の材料は、アルミニウム（Ａｌ）である。 The material of the first metal layer 21 contains aluminum. The material of the first metal layer 21 may be, for example, aluminum (Al) or an aluminum alloy such as A6063. In the present embodiment, the material of the first metal layer 21 is aluminum (Al).
　図１に示されるように、第２金属層２２は、第１金属層２１に対して第１導体層１２とは反対側で第１金属層２１に積層されている。本実施の形態において、第２金属層２２は、第１金属層２１に直接積層されている。第２金属層２２は、積層材２の最表面側に配置されている。第２金属層２２の厚みは、例えば、０．１ｍｍである。 As shown in FIG. 1, the second metal layer 22 is laminated on the first metal layer 21 on the opposite side of the first metal layer 21 from the first conductor layer 12. In the present embodiment, the second metal layer 22 is directly laminated on the first metal layer 21. The second metal layer 22 is arranged on the outermost surface side of the laminated material 2. The thickness of the second metal layer 22 is, for example, 0.1 mm.
　第２金属層２２は、第１金属層２１よりもはんだ４に対する濡れ性が高い。第２金属層２２は、アルミニウム（Ａｌ）よりもはんだ４に対する濡れ性が高い。第２金属層２２の材料は、ニッケル（Ｎｉ）、銀（Ａｇ）および４２アロイのいずれかを含んでいる。４２アロイは、鉄（Ｆｅ）とニッケル（Ｎｉ）とを含む合金である。本実施の形態において、第２金属層２２の材料は、ニッケル（Ｎｉ）を含んでいる。 The second metal layer 22 has higher wettability to the solder 4 than the first metal layer 21. The second metal layer 22 has higher wettability with respect to the solder 4 than aluminum (Al). The material of the second metal layer 22 contains any of nickel (Ni), silver (Ag) and 42 alloy. 42 Alloy is an alloy containing iron (Fe) and nickel (Ni). In the present embodiment, the material of the second metal layer 22 contains nickel (Ni).
　本実施の形態において、積層材２は、第１金属層２１と第２金属層２２とを含むクラッド材である。このため、第１金属層２１は、第２金属層２２に隙間なく密着している。第１金属層２１と第２金属層２２とは、圧着一体化されていてもよい。クラッド材は、第１金属層２１と第２金属層２２とが冷間圧接、熱間圧接、レーザ溶接および摩擦攪拌接合などによって積層されることによって、形成されていてもよい。本実施の形態において、第１金属層２１と第２金属層２２とは、冷間圧接によって圧着一体化されている。 In the present embodiment, the laminated material 2 is a clad material including the first metal layer 21 and the second metal layer 22. Therefore, the first metal layer 21 is in close contact with the second metal layer 22 without any gap. The first metal layer 21 and the second metal layer 22 may be pressure-bonded and integrated. The clad material may be formed by laminating the first metal layer 21 and the second metal layer 22 by cold pressing, hot pressing, laser welding, friction stir welding, or the like. In the present embodiment, the first metal layer 21 and the second metal layer 22 are pressure-bonded and integrated by cold pressure welding.
　積層材２は、第１金属層２１と第２金属層２２とが蒸着またはスパッタなどによって積層されることによって形成されていてもよい。積層材２の厚みの最小値は、例えば、３０μｍ以上５０μｍ以下である。積層材２の厚みの最大値は、例えば、１０ｍｍである。 The laminated material 2 may be formed by laminating the first metal layer 21 and the second metal layer 22 by vapor deposition, sputtering, or the like. The minimum value of the thickness of the laminated lumber 2 is, for example, 30 μm or more and 50 μm or less. The maximum thickness of the laminated lumber 2 is, for example, 10 mm.
　図１に示されるように、はんだ４は、第２金属層２２に配置されている。はんだ４は、第２金属層２２に対して第１金属層２１とは反対側で第２金属層２２上に配置されている。はんだ４の材料は、例えば、Ｓｎ－Ａｇ－Ｃｕ（スズ－銀－銅）系はんだおよびＳｎ－Ｓｂ－Ａｇ（スズ－アンチモン－銀）系はんだなどである。はんだ４の材料は、具体的には、例えば、Ｓｎ９６．５－Ａｇ３－Ｃｕ０．５（質量％）はんだ、Ｓｎ９８．５－Ａｇ１－Ｃｕ０．５（質量％）はんだおよびＳｎ９６－Ｓｂ３－Ａｇ１（質量％）はんだなどである。本実施の形態におけるはんだ４の材料は、Ｓｎ９６．５－Ａｇ３－Ｃｕ０．５（質量％）はんだである。 As shown in FIG. 1, the solder 4 is arranged on the second metal layer 22. The solder 4 is arranged on the second metal layer 22 on the side opposite to the first metal layer 21 with respect to the second metal layer 22. The material of the solder 4 is, for example, Sn-Ag-Cu (tin-silver-copper) -based solder, Sn-Sb-Ag (tin-antimon-silver) -based solder, and the like. Specifically, the materials of the solder 4 are, for example, Sn965.5Ag3-Cu0.5 (mass%) solder, Sn98.5-Ag1-Cu0.5 (mass%) solder and Sn96-Sb3-Ag1 (mass%). %) Solder, etc. The material of the solder 4 in this embodiment is Sn96.5-Ag3-Cu0.5 (mass%) solder.
　はんだ４の材料は、銅（Ｃｕ）－スズ（Ｓｎ）ペーストおよびナノ銀（Ａｇ）ペーストなどであってもよい。銅（Ｃｕ）－スズ（Ｓｎ）ペーストによる接合は、分散された銅粉が等温凝固するため、高い耐熱性を有している。ナノ銀（Ａｇ）ペーストによる接合は、ナノ銀（Ａｇ）粒子による低温焼成によって接合される。 The material of the solder 4 may be copper (Cu) -tin (Sn) paste, nano-silver (Ag) paste, or the like. Bonding with copper (Cu) -tin (Sn) paste has high heat resistance because the dispersed copper powder is isothermally solidified. Bonding with nano-silver (Ag) paste is joined by low-temperature firing with nano-silver (Ag) particles.
　図１に示されるように、半導体素子３は、はんだ４によって第２金属層２２に接合されている。半導体素子３は、積層材２を介して基板１に電気的に接続されている。半導体素子３は、例えば、絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ：Insulated　Gate　Bipolar　Transistor）、ダイオードおよび金属酸化物半導体電界効果トランジスタ（ＭＯＳＦＥＴ：Metal　Oxide　Semiconductor　Field　Effect　Transistor）などである。半導体装置１００は、複数の半導体素子３を含んでいてもよい。本実施の形態において、半導体装置１００は、複数の半導体素子３を含んでいる。 As shown in FIG. 1, the semiconductor element 3 is bonded to the second metal layer 22 by the solder 4. The semiconductor element 3 is electrically connected to the substrate 1 via the laminated material 2. The semiconductor element 3 is, for example, an insulated gate type bipolar transistor (IGBT: Insulated Gate Bipolar Transistor), a diode and a metal oxide semiconductor field effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device 100 may include a plurality of semiconductor elements 3. In the present embodiment, the semiconductor device 100 includes a plurality of semiconductor elements 3.
　１つの半導体素子３は、配線部材８を介して端子９と他の半導体素子３との少なくともいずれか一方に電気的に接続されている。これにより、基板１、積層材２、半導体素子３、配線部材８および端子９は、電気回路を構成している。端子９は、ケース７内にインサート形成されている。端子９は、信号端子９１と、主端子９２とを含んでいる。信号端子９１および主端子９２は、半導体素子３に電気的に接続されている。 One semiconductor element 3 is electrically connected to at least one of the terminal 9 and the other semiconductor element 3 via a wiring member 8. As a result, the substrate 1, the laminated material 2, the semiconductor element 3, the wiring member 8, and the terminal 9 form an electric circuit. The terminal 9 is insert-formed in the case 7. The terminal 9 includes a signal terminal 91 and a main terminal 92. The signal terminal 91 and the main terminal 92 are electrically connected to the semiconductor element 3.
　配線部材８は、例えば、ボンディングワイヤ、ボンディングリボンまたは板状電極などである。配線部材８がボンディングワイヤである場合、配線部材８は半導体素子３にワイヤボンディングされる。ボンディングワイヤの材料は、例えば、アルミニウム（Ａｌ）、銅（Ｃｕ）および金（Ａｕ）などである。ボンディングワイヤは、アルミニウム（Ａｌ）が被覆された銅線であってもよい。本実施の形態において、配線部材８は、アルミニウム（Ａｌ）製のボンディングワイヤである。信号端子９１に接続された配線部材８の直径は、例えば、０．１５ｍｍである。主端子９２に接続された配線部材８の直径は、例えば、０．３ｍｍである。配線部材８がボンディングリボンである場合、配線部材８は半導体素子３にリボンボンディングされる。配線部材８が板状電極である場合、配線部材８は半導体素子３に直接にはんだ付けされる。 The wiring member 8 is, for example, a bonding wire, a bonding ribbon, a plate-shaped electrode, or the like. When the wiring member 8 is a bonding wire, the wiring member 8 is wire-bonded to the semiconductor element 3. The material of the bonding wire is, for example, aluminum (Al), copper (Cu), gold (Au), and the like. The bonding wire may be a copper wire coated with aluminum (Al). In the present embodiment, the wiring member 8 is a bonding wire made of aluminum (Al). The diameter of the wiring member 8 connected to the signal terminal 91 is, for example, 0.15 mm. The diameter of the wiring member 8 connected to the main terminal 92 is, for example, 0.3 mm. When the wiring member 8 is a bonding ribbon, the wiring member 8 is ribbon-bonded to the semiconductor element 3. When the wiring member 8 is a plate-shaped electrode, the wiring member 8 is directly soldered to the semiconductor element 3.
　図１に示されるように、ヒートシンク６は、第２導体層１３に対して第１導体層１２とは反対側で第２導体層１３に接合されている。ヒートシンク６は、裏面ろう材５０によって第２導体層１３に接合されている。裏面ろう材５０は、例えば、アルミニウム－シリコンろう材である。ヒートシンク６は、ベース板６１と、複数のフィン部６２とを含んでいる。ベース板６１は、裏面ろう材５０によって第２導体層１３に接合されている。複数のフィン部６２は、ベース板６１に対して基板１とは反対側に向かってベース板６１から突出している。 As shown in FIG. 1, the heat sink 6 is joined to the second conductor layer 13 on the opposite side of the second conductor layer 13 from the first conductor layer 12. The heat sink 6 is joined to the second conductor layer 13 by the back surface brazing material 50. The back surface brazing material 50 is, for example, an aluminum-silicon brazing material. The heat sink 6 includes a base plate 61 and a plurality of fin portions 62. The base plate 61 is joined to the second conductor layer 13 by the back surface brazing material 50. The plurality of fin portions 62 project from the base plate 61 toward the side opposite to the substrate 1 with respect to the base plate 61.
　ケース７は、基板１と、積層材２と、半導体素子３と、はんだ４と、ろう材５と、裏面ろう材５０と、ヒートシンク６と、配線部材８とを取り囲んでいる。ケース７は、枠形状を有している。ケース７の材料は、例えば、ＰＰＳ（PolyPhenylene　Sulfide）樹脂および液晶ポリマー（ＬＣＰ：Liquid　Crystal　Polymer）などである。本実施の形態において、ケース７の材料は、ＰＰＳ樹脂である。 The case 7 surrounds the substrate 1, the laminated material 2, the semiconductor element 3, the solder 4, the brazing material 5, the back surface brazing material 50, the heat sink 6, and the wiring member 8. The case 7 has a frame shape. The material of Case 7 is, for example, PPS (PolyPhenylene Sulfide) resin and liquid crystal polymer (LCP: Liquid Crystal Polymer). In this embodiment, the material of the case 7 is a PPS resin.
　封止材ＳＲは、ケース７の内部空間に注入されている。封止材ＳＲは、液状の封止材である。封止材ＳＲは、例えば、シリカフィラーを含むエポキシ樹脂であってもよいし、シリコーンゲルなどであってもよい。 The sealing material SR is injected into the internal space of the case 7. The encapsulant SR is a liquid encapsulant. The encapsulant SR may be, for example, an epoxy resin containing a silica filler, a silicone gel, or the like.
　次に、図２を用いて、実施の形態１の第１の変形例に係る半導体装置１００の構成を説明する。図２に示されるように、実施の形態１の第１の変形例において、半導体装置１００は、トランスファーモールド樹脂ＴＲと、リードフレームＬＦを含んでいる。 Next, the configuration of the semiconductor device 100 according to the first modification of the first embodiment will be described with reference to FIG. As shown in FIG. 2, in the first modification of the first embodiment, the semiconductor device 100 includes a transfer mold resin TR and a lead frame LF.
　リードフレームＬＦは、電極９０を含んでいる。電極９０は、信号電極９３および主電極９４を含んでいる。信号電極９３および主電極９４は、半導体素子３に電気的に接続されている。リードフレームＬＦの面内方向における寸法は、例えば、１５０ｍｍ×５０ｍｍである。リードフレームＬＦの厚みは、例えば、０．６ｍｍである。トランスファーモールド樹脂ＴＲは、基板１、積層材２、半導体素子３、はんだ４、ろう材５、裏面ろう材５０および配線部材８を封止している。トランスファーモールド樹脂ＴＲは、電極９０を部分的に封止している。 The lead frame LF includes an electrode 90. The electrode 90 includes a signal electrode 93 and a main electrode 94. The signal electrode 93 and the main electrode 94 are electrically connected to the semiconductor element 3. The dimensions of the lead frame LF in the in-plane direction are, for example, 150 mm × 50 mm. The thickness of the lead frame LF is, for example, 0.6 mm. The transfer mold resin TR seals the substrate 1, the laminated material 2, the semiconductor element 3, the solder 4, the brazing material 5, the back surface brazing material 50, and the wiring member 8. The transfer mold resin TR partially seals the electrode 90.
　次に、実施の形態１の第２の変形例に係る半導体装置１００の構成を説明する。図１２に示されるように、実施の形態１の第２の変形例において、基板１は、複数の基板部１９を含んでいる。すなわち、本実施の形態に係る基板１は、個片化されている。基板１は、例えば、２つまたは６つの基板部１９に分割されている。セラミック層１１は、複数の基板部１９の各々に含まれるセラミック部を含んでいる。導体層は、複数の基板部１９の各々に含まれる導体部を含んでいる。 Next, the configuration of the semiconductor device 100 according to the second modification of the first embodiment will be described. As shown in FIG. 12, in the second modification of the first embodiment, the substrate 1 includes a plurality of substrate portions 19. That is, the substrate 1 according to the present embodiment is individualized. The substrate 1 is divided into, for example, two or six substrate portions 19. The ceramic layer 11 includes a ceramic portion included in each of the plurality of substrate portions 19. The conductor layer includes a conductor portion included in each of the plurality of substrate portions 19.
　次に、図３～図５を用いて、実施の形態１に係る半導体装置１００の製造方法を説明する。図３に示されるように、半導体装置１００の製造方法は、基板１、積層材２、はんだ４、半導体素子３およびろう材５が準備される工程Ｓ１０１と、第１金属層２１がろう材５によって第１導体層１２に接合される工程Ｓ１０２と、半導体素子３がはんだ４によって第２金属層２２に接合される工程Ｓ１０３とを含んでいる。 Next, a method of manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to FIGS. 3 to 5. As shown in FIG. 3, the manufacturing method of the semiconductor device 100 includes a step S101 in which the substrate 1, the laminated material 2, the solder 4, the semiconductor element 3 and the brazing material 5 are prepared, and the brazing material 5 in which the first metal layer 21 is formed. It includes a step S102 in which the semiconductor element 3 is bonded to the first conductor layer 12 and a step S103 in which the semiconductor element 3 is bonded to the second metal layer 22 by the solder 4.
　図４に示されるように、基板１、積層材２、はんだ４（図５参照）、半導体素子３（図５参照）およびろう材５が準備される工程Ｓ１０１（図３参照）において、基板１、積層材２、はんだ４（図５参照）、半導体素子３（図５参照）およびろう材５が準備される。第１金属層２１および第２金属層２２が積層されている状態の積層材２が準備される。図４および図５に示されるように、基板１、積層材２、はんだ４、半導体素子３およびろう材５が準備される工程Ｓ１０１において、裏面ろう材５０、ヒートシンク６、ケース７、端子９、配線部材８および封止材ＳＲがさらに準備される。端子９は、ケース７にインサート成形されている。 As shown in FIG. 4, in the step S101 (see FIG. 3) in which the substrate 1, the laminate 2, the solder 4 (see FIG. 5), the semiconductor element 3 (see FIG. 5), and the brazing material 5 are prepared, the substrate 1 , Laminated material 2, solder 4 (see FIG. 5), semiconductor element 3 (see FIG. 5), and brazing material 5 are prepared. The laminated lumber 2 in which the first metal layer 21 and the second metal layer 22 are laminated is prepared. As shown in FIGS. 4 and 5, in step S101 in which the substrate 1, the laminated material 2, the solder 4, the semiconductor element 3 and the brazing material 5 are prepared, the back surface brazing material 50, the heat sink 6, the case 7, and the terminal 9 are prepared. The wiring member 8 and the sealing material SR are further prepared. The terminal 9 is insert-molded into the case 7.
　図４に示されるように、第１金属層２１がろう材５によって第１導体層１２に接合される工程Ｓ１０２（図３参照）において、第１導体層１２に対してセラミック層１１とは反対側にろう材５が配置されてから、第１金属層２１がろう材５によって第１導体層１２に接合される。第１金属層２１がろう材５によって第１導体層１２に接合される工程Ｓ１０２において、第２導体層１３とヒートシンク６との間に裏面ろう材５０が挟み込まれてから、第２金属層２２が裏面ろう材５０によってヒートシンク６に接合される。 As shown in FIG. 4, in the step S102 (see FIG. 3) in which the first metal layer 21 is joined to the first conductor layer 12 by the brazing material 5, the first conductor layer 12 is opposite to the ceramic layer 11. After the brazing filler metal 5 is arranged on the side, the first metal layer 21 is joined to the first conductor layer 12 by the brazing filler metal 5. In step S102 in which the first metal layer 21 is joined to the first conductor layer 12 by the brazing material 5, the back surface brazing material 50 is sandwiched between the second conductor layer 13 and the heat sink 6, and then the second metal layer 22 Is joined to the heat sink 6 by the back surface brazing material 50.
　具体的には、基板１、積層材２、ろう材５、裏面ろう材５０およびヒートシンク６は、図示されない治具によって荷重が加えられながら挟み込まれる。図示されない治具によって挟み込まれた基板１、積層材２、ろう材５、裏面ろう材５０およびヒートシンク６は、例えば、５８０℃で３分間加熱されることで接合される。 Specifically, the substrate 1, the laminated material 2, the brazing material 5, the back surface brazing material 50, and the heat sink 6 are sandwiched while being loaded by a jig (not shown). The substrate 1, the laminated material 2, the brazing material 5, the back surface brazing material 50, and the heat sink 6 sandwiched by a jig (not shown) are joined by being heated at 580 ° C. for 3 minutes, for example.
　図５に示されるように、半導体素子３がはんだ４によって第２金属層２２に接合される工程Ｓ１０３において、半導体素子３がはんだ４によって第２金属層２２に接合される。基板１は、図示されない接着剤によってケース７内に位置決めされる。半導体素子３は、配線部材８によって端子９に電気的に接続される。ケース７内に封止材ＳＲ（図１参照）が注入される。封止材ＳＲ（図１参照）は、例えば、１５０℃で１．５時間加熱されることによって硬化される。これにより、ケース７は絶縁封止される。 As shown in FIG. 5, in the step S103 in which the semiconductor element 3 is bonded to the second metal layer 22 by the solder 4, the semiconductor element 3 is bonded to the second metal layer 22 by the solder 4. The substrate 1 is positioned in the case 7 by an adhesive (not shown). The semiconductor element 3 is electrically connected to the terminal 9 by the wiring member 8. The sealing material SR (see FIG. 1) is injected into the case 7. The encapsulant SR (see FIG. 1) is cured, for example, by heating at 150 ° C. for 1.5 hours. As a result, the case 7 is insulated and sealed.
　次に、図６および図７を用いて、実施の形態１の第１の変形例に係る半導体装置１００の製造方法を説明する。 Next, a method of manufacturing the semiconductor device 100 according to the first modification of the first embodiment will be described with reference to FIGS. 6 and 7.
　図６に示されるように、半導体素子３がはんだ４によって第２金属層２２に接合される工程Ｓ１０３において、基板１は、リードフレームＬＦに対して位置決めされる。続いて、図７に示されるように、リードフレームＬＦは、金型Ｍに対して位置決めされる。基板１、積層材２、半導体素子３、はんだ４およびろう材５は、金型Ｍの内部空間に配置される。金型Ｍは、上型Ｍ１と下型Ｍ２とを含んでいる。上型Ｍ１および下型Ｍ２の面内方向における寸法は、例えば、１００ｍｍ×８０ｍｍである。上型Ｍ１の第１方向における寸法は、例えば、７０ｍｍである。下型Ｍ２の第１方向における寸法は、例えば、１００ｍｍである。 As shown in FIG. 6, in the step S103 in which the semiconductor element 3 is joined to the second metal layer 22 by the solder 4, the substrate 1 is positioned with respect to the lead frame LF. Subsequently, as shown in FIG. 7, the lead frame LF is positioned with respect to the mold M. The substrate 1, the laminated material 2, the semiconductor element 3, the solder 4, and the brazing material 5 are arranged in the internal space of the mold M. The mold M includes an upper mold M1 and a lower mold M2. The dimensions of the upper die M1 and the lower die M2 in the in-plane direction are, for example, 100 mm × 80 mm. The dimension of the upper mold M1 in the first direction is, for example, 70 mm. The dimension of the lower mold M2 in the first direction is, for example, 100 mm.
　図７に示されるように、トランスファーモールド樹脂ＴＲ（図２参照）が加圧および加熱されつつ、金型Ｍの内部空間に流し込まれる。トランスファーモールド樹脂ＴＲ（図２参照）は、例えば、１７０℃で５分間加熱されることによって、仮硬化される。仮硬化されたトランスファーモールド樹脂ＴＲ（図２参照）は、金型Ｍから外されてから、本硬化される。トランスファーモールド樹脂ＴＲ（図２参照）は、例えば、図示されないオーブンによって１７０℃で２時間加熱されることによって、本硬化される。 As shown in FIG. 7, the transfer mold resin TR (see FIG. 2) is poured into the internal space of the mold M while being pressurized and heated. The transfer mold resin TR (see FIG. 2) is temporarily cured by heating at 170 ° C. for 5 minutes, for example. The temporarily cured transfer mold resin TR (see FIG. 2) is removed from the mold M and then finally cured. The transfer mold resin TR (see FIG. 2) is finally cured by heating at 170 ° C. for 2 hours in an oven (not shown), for example.
　続いて、本実施の形態の作用効果を説明する。
　実施の形態１に係る半導体装置１００によれば、図１に示されるように、第１金属層２１は、第１導体層１２に対してセラミック層１１とは反対側でろう材５によって第１導体層１２に接合されている。このため、第１導体層１２と第１金属層２１との接触面が平滑にされる必要がない。よって、基板１の第１導体層１２が平滑にされる必要がない。 Subsequently, the action and effect of the present embodiment will be described.
According to the semiconductor device 100 according to the first embodiment, as shown in FIG. 1, the first metal layer 21 is first formed by a brazing material 5 on the side opposite to the ceramic layer 11 with respect to the first conductor layer 12. It is joined to the conductor layer 12. Therefore, it is not necessary for the contact surface between the first conductor layer 12 and the first metal layer 21 to be smoothed. Therefore, it is not necessary for the first conductor layer 12 of the substrate 1 to be smoothed.
　図１に示されるように、半導体素子３は、はんだ４によって第２金属層２２に接合されている。第２金属層２２は、第１金属層２１よりもはんだ４に対する濡れ性が高い。第１金属層２１の材料は、アルミニウム（Ａｌ）を含んでいる。このため、半導体素子３をアルミニウム（Ａｌ）よりもはんだ４に対する濡れ性が高い金属層（第２金属層２２）に接合できる。よって、半導体素子３は、アルミニウム（Ａｌ）に接合される場合よりも、はんだ４によって強固に接合され得る。 As shown in FIG. 1, the semiconductor element 3 is bonded to the second metal layer 22 by the solder 4. The second metal layer 22 has higher wettability with respect to the solder 4 than the first metal layer 21. The material of the first metal layer 21 contains aluminum (Al). Therefore, the semiconductor element 3 can be bonded to the metal layer (second metal layer 22) having a higher wettability to the solder 4 than the aluminum (Al). Therefore, the semiconductor element 3 can be bonded more firmly by the solder 4 than when it is bonded to aluminum (Al).
　図１に示されるように、第１導体層１２および第１金属層２１の材料は、アルミニウム（Ａｌ）を含んでいる。例えば、銅（Ｃｕ）よりもアルミニウム（Ａｌ）の比重は小さく、かつアルミニウム（Ａｌ）の熱伝導率は高い。このため、半導体装置１００の寸法および重量を小さくし、かつ半導体装置１００の放熱性を高くすることができる。 As shown in FIG. 1, the materials of the first conductor layer 12 and the first metal layer 21 contain aluminum (Al). For example, the specific gravity of aluminum (Al) is smaller than that of copper (Cu), and the thermal conductivity of aluminum (Al) is high. Therefore, the dimensions and weight of the semiconductor device 100 can be reduced, and the heat dissipation of the semiconductor device 100 can be increased.
　仮に、第１金属層２１が固相拡散接合によって第１導体層１２に接合されており、かつ第１金属層２１の材料が銅（Ｃｕ）を含んでいる場合、第１導体層１２（アルミニウム（Ａｌ））および第１金属層２１（銅（Ｃｕ））は、共晶反応を起こす。共晶反応によって第１導体層１２および第１金属層２１の融点が低下するため、第１導体層１２および第１金属層２１は、液体化し得る。第１導体層１２（アルミニウム（Ａｌ））と第１金属層２１（銅（Ｃｕ））は、具体的には、例えば、５４０℃で液体化する。このため、第１金属層２１が固相拡散接合によって第１導体層１２に接合されており、かつ第１金属層２１の材料が銅（Ｃｕ）を含んでいる場合、半導体装置１００の耐熱温度は、５４０℃以下である。また、第１導体層１２と第１金属層２１とは、５４０℃よりも低い温度で長時間加熱される必要がある。 If the first metal layer 21 is bonded to the first conductor layer 12 by solid phase diffusion bonding and the material of the first metal layer 21 contains copper (Cu), the first conductor layer 12 (aluminum). (Al)) and the first metal layer 21 (copper (Cu)) cause a eutectic reaction. Since the melting points of the first conductor layer 12 and the first metal layer 21 are lowered by the eutectic reaction, the first conductor layer 12 and the first metal layer 21 can be liquefied. Specifically, the first conductor layer 12 (aluminum (Al)) and the first metal layer 21 (copper (Cu)) are liquefied at, for example, 540 ° C. Therefore, when the first metal layer 21 is bonded to the first conductor layer 12 by solid phase diffusion bonding and the material of the first metal layer 21 contains copper (Cu), the heat resistant temperature of the semiconductor device 100 Is 540 ° C. or lower. Further, the first conductor layer 12 and the first metal layer 21 need to be heated at a temperature lower than 540 ° C. for a long time.
　本実施の形態に係る半導体装置１００によれば、図１に示されるように、第１金属層２１は、ろう材５によって第１導体層１２に接合されている。第１金属層２１および第１導体層１２の両方の材料は、アルミニウム（Ａｌ）を含んでいる。また、第１金属層２１は、第１導体層１２にろう材５によって、例えば、５７０℃以上６００℃以下で接合される。よって、第１金属層２１および第１導体層１２が共晶反応によって液体化することが抑制され得る。したがって、半導体装置１００の耐熱温度は、第１金属層２１が固相拡散接合によって第１導体層１２に接合されておりかつ第１金属層２１の材料が銅（Ｃｕ）を含んでいる場合よりも、高い。これにより、半導体装置１００の耐熱性は、向上する。また、第１導体層１２と第１金属層２１との接合に必要な時間は、第１金属層２１が固相拡散接合によって第１導体層１２に接合される場合よりも、短い。 According to the semiconductor device 100 according to the present embodiment, as shown in FIG. 1, the first metal layer 21 is joined to the first conductor layer 12 by the brazing material 5. The materials of both the first metal layer 21 and the first conductor layer 12 contain aluminum (Al). Further, the first metal layer 21 is bonded to the first conductor layer 12 by the brazing material 5 at, for example, 570 ° C. or higher and 600 ° C. or lower. Therefore, the liquefaction of the first metal layer 21 and the first conductor layer 12 by the eutectic reaction can be suppressed. Therefore, the heat resistant temperature of the semiconductor device 100 is higher than that when the first metal layer 21 is bonded to the first conductor layer 12 by solid phase diffusion bonding and the material of the first metal layer 21 contains copper (Cu). Also expensive. As a result, the heat resistance of the semiconductor device 100 is improved. Further, the time required for joining the first conductor layer 12 and the first metal layer 21 is shorter than when the first metal layer 21 is joined to the first conductor layer 12 by solid phase diffusion bonding.
　図１に示されるように、積層材２は、第１金属層２１と第２金属層２２とを含むクラッド材である。クラッド材による積層材２は、蒸着およびスパッタなどによる積層材２よりも安価である。このため、半導体装置１００の製造コストを小さくすることができる。また、クラッド材による積層材２は、蒸着およびスパッタなどによる積層材２よりも高い生産性を有している。このため、半導体装置１００の生産性を高くすることができる。 As shown in FIG. 1, the laminated material 2 is a clad material including a first metal layer 21 and a second metal layer 22. The laminated lumber 2 made of a clad material is cheaper than the laminated lumber 2 made of thin film or sputter. Therefore, the manufacturing cost of the semiconductor device 100 can be reduced. Further, the laminated material 2 made of a clad material has higher productivity than the laminated material 2 made by vapor deposition, sputtering, or the like. Therefore, the productivity of the semiconductor device 100 can be increased.
　図１に示されるように、積層材２は、第１金属層２１と第２金属層２２とを含むクラッド材である。このため、第１金属層２１は、第２金属層２２に圧着一体化されている。よって、第１金属層２１の表面が平滑にされる必要がない。 As shown in FIG. 1, the laminated material 2 is a clad material including a first metal layer 21 and a second metal layer 22. Therefore, the first metal layer 21 is pressure-bonded and integrated with the second metal layer 22. Therefore, it is not necessary to smooth the surface of the first metal layer 21.
　第２金属層２２の材料は、ニッケル（Ｎｉ）を含んでいる。ニッケル（Ｎｉ）は、アルミニウム（Ａｌ）よりもはんだ４に対する濡れ性が高い。このため、第２金属層２２は、アルミニウム（Ａｌ）よりもはんだ４に対する濡れ性が高い。よって、半導体素子３をアルミニウム（Ａｌ）よりもはんだ４に対する濡れ性が高い第２金属層２２に接合できる。 The material of the second metal layer 22 contains nickel (Ni). Nickel (Ni) has higher wettability with respect to the solder 4 than aluminum (Al). Therefore, the second metal layer 22 has higher wettability to the solder 4 than aluminum (Al). Therefore, the semiconductor element 3 can be bonded to the second metal layer 22 which has higher wettability to the solder 4 than aluminum (Al).
　図１に示されるように、半導体装置１００は、ヒートシンク６を含んでいる。よって、半導体装置１００の放熱性は、半導体装置１００がヒートシンク６を含んでいない場合よりも高い。 As shown in FIG. 1, the semiconductor device 100 includes a heat sink 6. Therefore, the heat dissipation of the semiconductor device 100 is higher than that in the case where the semiconductor device 100 does not include the heat sink 6.
　図１に示されるように、基板１は、第１導体層１２および第２導体層１３を含んでいる。このため、ヒートシンク６を第２導体層１３に接合するときに、積層材２を第１導体層１２に接合することができる。これにより、半導体装置１００の製造コストを小さくすることができる。 As shown in FIG. 1, the substrate 1 includes a first conductor layer 12 and a second conductor layer 13. Therefore, when the heat sink 6 is bonded to the second conductor layer 13, the laminated lumber 2 can be bonded to the first conductor layer 12. As a result, the manufacturing cost of the semiconductor device 100 can be reduced.
　第１金属層２１の材料は、アルミニウム合金であってもよい。このため、第１金属層２１の表面硬度は、第１金属層２１の材料がアルミニウム（Ａｌ）である場合よりも、高くなる。また、第１金属層２１の再結晶温度は、第１金属層２１の材料がアルミニウム（Ａｌ）である場合よりも、高くなる。これにより、第１金属層２１の品質および信頼性は、向上し得る。 The material of the first metal layer 21 may be an aluminum alloy. Therefore, the surface hardness of the first metal layer 21 is higher than that when the material of the first metal layer 21 is aluminum (Al). Further, the recrystallization temperature of the first metal layer 21 is higher than that when the material of the first metal layer 21 is aluminum (Al). Thereby, the quality and reliability of the first metal layer 21 can be improved.
　実施の形態１の第１の変形例に係る半導体装置１００によれば、図２に示されるように、半導体装置１００は、トランスファーモールド樹脂ＴＲを含んでいる。トランスファーモールド樹脂ＴＲは、封止材ＳＲよりも高い樹脂成形圧力によって成形されている。このため、半導体装置１００は、半導体装置１００が封止材ＳＲを含んでいる場合よりも高い絶縁性および放熱性を有している。 According to the semiconductor device 100 according to the first modification of the first embodiment, as shown in FIG. 2, the semiconductor device 100 includes a transfer mold resin TR. The transfer mold resin TR is molded by a resin molding pressure higher than that of the sealing material SR. Therefore, the semiconductor device 100 has higher insulating property and heat dissipation than the case where the semiconductor device 100 contains the sealing material SR.
　実施の形態１の第２の変形例に係る半導体装置１００によれば、基板１は、複数の基板部を含んでいる。複数の基板部を含む基板１は、複数の基板部同士の隙間によって基板１が一体的である場合よりも変形しやすい。このため、基板１は、セラミック層１１の熱膨張係数と第１導体層１２の熱膨張係数との差による反り、および半導体装置１００の温度サイクルによる変形によって変形しやすい。このため、複数の基板部を含む基板１が温度変化によって破損することは、基板１が一体的である場合よりも抑制される。 According to the semiconductor device 100 according to the second modification of the first embodiment, the substrate 1 includes a plurality of substrate portions. The substrate 1 including the plurality of substrate portions is more easily deformed than the case where the substrate 1 is integrated due to the gaps between the plurality of substrate portions. Therefore, the substrate 1 is easily deformed by the warp due to the difference between the coefficient of thermal expansion of the ceramic layer 11 and the coefficient of thermal expansion of the first conductor layer 12, and the deformation due to the temperature cycle of the semiconductor device 100. Therefore, damage to the substrate 1 including the plurality of substrate portions due to a temperature change is suppressed as compared with the case where the substrate 1 is integrated.
　実施の形態１に係る半導体装置１００の製造方法によれば、図４に示されるように、第１金属層２１がろう材５によって第１導体層１２に接合される工程Ｓ１０２（図３参照）において、第１導体層１２に対してセラミック層１１とは反対側にろう材５が配置されてから、第１金属層２１がろう材５によって第１導体層１２に接合される。このため、基板１の第１導体層１２が平滑にされる必要がない。また、半導体素子３（図５参照）およびろう材５が準備される工程Ｓ１０１（図３参照）において、第１金属層２１および第２金属層２２が積層されている状態の積層材２が準備される。このため、第１金属層２１が平滑にされる必要がない。 According to the manufacturing method of the semiconductor device 100 according to the first embodiment, as shown in FIG. 4, the step S102 (see FIG. 3) in which the first metal layer 21 is joined to the first conductor layer 12 by the brazing material 5. The brazing material 5 is arranged on the side opposite to the ceramic layer 11 with respect to the first conductor layer 12, and then the first metal layer 21 is joined to the first conductor layer 12 by the brazing material 5. Therefore, it is not necessary for the first conductor layer 12 of the substrate 1 to be smoothed. Further, in the step S101 (see FIG. 3) in which the semiconductor element 3 (see FIG. 5) and the brazing material 5 are prepared, the laminated material 2 in which the first metal layer 21 and the second metal layer 22 are laminated is prepared. Will be done. Therefore, the first metal layer 21 does not need to be smoothed.
　図５に示されるように、半導体素子３がはんだ４によって第２金属層２２に接合される工程Ｓ１０３において、半導体素子３がはんだ４によって第２金属層２２に接合される。第２金属層２２は、アルミニウム（Ａｌ）よりもはんだ４に対する濡れ性が高い。よって、半導体素子３をアルミニウム（Ａｌ）よりもはんだ４に対する濡れ性が高い第２金属層２２に接合できる。したがって、半導体素子３は、アルミニウム（Ａｌ）に接合される場合よりも、はんだ４によって強固に接合され得る。 As shown in FIG. 5, in the step S103 in which the semiconductor element 3 is bonded to the second metal layer 22 by the solder 4, the semiconductor element 3 is bonded to the second metal layer 22 by the solder 4. The second metal layer 22 has higher wettability with respect to the solder 4 than aluminum (Al). Therefore, the semiconductor element 3 can be bonded to the second metal layer 22 which has higher wettability to the solder 4 than aluminum (Al). Therefore, the semiconductor element 3 can be bonded more firmly by the solder 4 than when it is bonded to aluminum (Al).
　実施の形態２．
　次に、図８を用いて、実施の形態２に係る半導体装置１００の構成を説明する。実施の形態２は、特に説明しない限り、上記の実施の形態１と同一の構成、製造方法および作用効果を有している。したがって、上記の実施の形態１と同一の構成には同一の符号を付し、説明を繰り返さない。 Embodiment 2.
Next, the configuration of the semiconductor device 100 according to the second embodiment will be described with reference to FIG. Unless otherwise specified, the second embodiment has the same configuration, manufacturing method, and action and effect as those of the first embodiment. Therefore, the same components as those in the first embodiment are designated by the same reference numerals, and the description will not be repeated.
　図８に示されるように、本実施の形態において、積層材２は、第３金属層２３をさらに含んでいる。第３金属層２３は、第１金属層２１と第２金属層２２との間に配置されている。第３金属層２３の材料は、チタン（Ｔｉ）を含んでいる。第３金属層２３の材料は、ステンレスまたは鋼などのアルミニウム（Ａｌ）と低温共晶反応を起こさない材料を含んでいてもよい。 As shown in FIG. 8, in the present embodiment, the laminated material 2 further includes a third metal layer 23. The third metal layer 23 is arranged between the first metal layer 21 and the second metal layer 22. The material of the third metal layer 23 contains titanium (Ti). The material of the third metal layer 23 may include a material that does not cause a low temperature eutectic reaction with aluminum (Al) such as stainless steel or steel.
　第１金属層２１、第２金属層２２および第３金属層２３は、第１方向に積層されている。第３金属層２３は、第１金属層２１および第２金属層２２に直接積層されている。第３金属層２３の厚みは、例えば、０．０５ｍｍである。第２金属層２２の材料は、銅（Ｃｕ）、ニッケル（Ｎｉ）、銀（Ａｇ）および４２アロイのいずれかを含んでいる。本実施の形態において、第２金属層２２の材料は、銅（Ｃｕ）を含んでいる。 The first metal layer 21, the second metal layer 22, and the third metal layer 23 are laminated in the first direction. The third metal layer 23 is directly laminated on the first metal layer 21 and the second metal layer 22. The thickness of the third metal layer 23 is, for example, 0.05 mm. The material of the second metal layer 22 contains any of copper (Cu), nickel (Ni), silver (Ag) and 42 alloy. In the present embodiment, the material of the second metal layer 22 contains copper (Cu).
　続いて、本実施の形態の作用効果を説明する。
　実施の形態２に係る半導体装置１００によれば、図８に示されるように、第３金属層２３は、第１金属層２１と第２金属層２２との間に配置されている。このため、第１金属層２１と第２金属層２２とが拡散することによって第２金属層２２の表面粗さが変化することを抑制できる。これにより、第２金属層２２の表面粗さが変化することによって第２金属層２２のはんだ４に対する濡れ性が低下することを抑制できる。 Subsequently, the action and effect of the present embodiment will be described.
According to the semiconductor device 100 according to the second embodiment, as shown in FIG. 8, the third metal layer 23 is arranged between the first metal layer 21 and the second metal layer 22. Therefore, it is possible to prevent the surface roughness of the second metal layer 22 from changing due to the diffusion of the first metal layer 21 and the second metal layer 22. As a result, it is possible to prevent the second metal layer 22 from being less wetted with respect to the solder 4 due to the change in the surface roughness of the second metal layer 22.
　第３金属層２３の材料は、チタン（Ｔｉ）を含んでいる。チタン（Ｔｉ）は、ニッケル（Ｎｉ）および銅（Ｃｕ）よりも耐熱性が高い。このため、第１金属層２１と第３金属層２３とが共晶反応を起こすことを抑制できる。 The material of the third metal layer 23 contains titanium (Ti). Titanium (Ti) has higher heat resistance than nickel (Ni) and copper (Cu). Therefore, it is possible to suppress the eutectic reaction between the first metal layer 21 and the third metal layer 23.
　第３金属層２３が第１金属層２１と第２金属層２２との間に配置されているため、第１金属層２１と第２金属層２２とは直接積層されていない。このため、第１金属層２１と第２金属層２２とが共晶反応を起こすことを抑制できる。よって、第２金属層２２の材料を適宜に選ぶことができる。 Since the third metal layer 23 is arranged between the first metal layer 21 and the second metal layer 22, the first metal layer 21 and the second metal layer 22 are not directly laminated. Therefore, it is possible to suppress the eutectic reaction between the first metal layer 21 and the second metal layer 22. Therefore, the material of the second metal layer 22 can be appropriately selected.
　第２金属層２２の材料は、銅（Ｃｕ）を含んでいる。銅（Ｃｕ）は、ニッケル（Ｎｉ）よりもはんだ４に対する濡れ性が高い。このため、半導体素子３は、第２金属層２２の材料がニッケル（Ｎｉ）を含んでいる場合よりも強固に第２金属層２２に接合され得る。また、半導体素子３は、銀焼結剤によって第２金属層２２に接合され得る。また、銅（Ｃｕ）は、ニッケル（Ｎｉ）よりも熱伝導率が高い。このため、半導体装置１００は、第２金属層２２の材料がニッケル（Ｎｉ）を含んでいる場合よりも、高い放熱性を有している。 The material of the second metal layer 22 contains copper (Cu). Copper (Cu) has higher wettability with respect to the solder 4 than nickel (Ni). Therefore, the semiconductor element 3 can be bonded to the second metal layer 22 more firmly than when the material of the second metal layer 22 contains nickel (Ni). Further, the semiconductor element 3 can be bonded to the second metal layer 22 by a silver sintering agent. Further, copper (Cu) has a higher thermal conductivity than nickel (Ni). Therefore, the semiconductor device 100 has higher heat dissipation than the case where the material of the second metal layer 22 contains nickel (Ni).
　実施の形態３．
　次に、図９を用いて、実施の形態３に係る半導体装置１００の構成を説明する。実施の形態３は、特に説明しない限り、上記の実施の形態１と同一の構成、製造方法および作用効果を有している。したがって、上記の実施の形態１と同一の構成には同一の符号を付し、説明を繰り返さない。なお、図９では、説明の便宜のため、半導体素子３などは図示されていない。 Embodiment 3.
Next, the configuration of the semiconductor device 100 according to the third embodiment will be described with reference to FIG. Unless otherwise specified, the third embodiment has the same configuration, manufacturing method, and action and effect as those of the first embodiment. Therefore, the same components as those in the first embodiment are designated by the same reference numerals, and the description will not be repeated. Note that in FIG. 9, for convenience of explanation, the semiconductor element 3 and the like are not shown.
　図９に示されるように、本実施の形態において、半導体装置１００は、裏面積層材２０をさらに含んでいる。裏面積層材２０は、基板１に対して積層材２とは反対側で基板１に接合されている。裏面積層材２０は、積層材２と同じ構成を有していてもよい。 As shown in FIG. 9, in the present embodiment, the semiconductor device 100 further includes the back surface laminated material 20. The back surface laminated material 20 is bonded to the substrate 1 on the side opposite to the laminated material 2 with respect to the substrate 1. The back surface laminated material 20 may have the same structure as the laminated material 2.
　裏面積層材２０は、裏面第１金属層２１０と、裏面第２金属層２２０とを含んでいる。裏面第１金属層２１０は、第２導体層１３に対してセラミック層１１とは反対側で第２導体層１３に接合されている。裏面第１金属層２１０は、裏面ろう材５０によって第２導体層１３に接合されている。裏面第１金属層２１０の材料は、アルミニウム（Ａｌ）を含んでいる。 The back surface laminated material 20 includes a back surface first metal layer 210 and a back surface second metal layer 220. The back surface first metal layer 210 is joined to the second conductor layer 13 on the side opposite to the ceramic layer 11 with respect to the second conductor layer 13. The back surface first metal layer 210 is joined to the second conductor layer 13 by the back surface brazing material 50. The material of the back surface first metal layer 210 contains aluminum (Al).
　裏面第２金属層２２０は、裏面第１金属層２１０に対して第２導体層１３とは反対側で裏面第１金属層２１０に積層されている。裏面第２金属層２２０は、裏面第１金属層２１０に直接接合されている。裏面第２金属層２２０は、アルミニウム（Ａｌ）よりもはんだ４に対する濡れ性が高い。裏面第２金属層２２０は、第２金属層２２とで基板１を挟み込んでいる。 The back surface second metal layer 220 is laminated on the back surface first metal layer 210 on the side opposite to the second conductor layer 13 with respect to the back surface first metal layer 210. The back surface second metal layer 220 is directly bonded to the back surface first metal layer 210. The back surface second metal layer 220 has higher wettability to the solder 4 than aluminum (Al). The back surface second metal layer 220 sandwiches the substrate 1 with the second metal layer 22.
　次に、図１０を用いて、実施の形態３に係る半導体装置１００の製造方法を説明する。なお、図１０では、説明の便宜のため、半導体素子３などは図示されていない。本実施の形態では、第１金属層２１がろう材５によって第１導体層１２に接合される工程Ｓ１０２（図３参照）において、裏面第１金属層２１０が裏面ろう材５０によって第２導体層１３に接合される。 Next, a method of manufacturing the semiconductor device 100 according to the third embodiment will be described with reference to FIG. Note that in FIG. 10, for convenience of explanation, the semiconductor element 3 and the like are not shown. In the present embodiment, in the step S102 (see FIG. 3) in which the first metal layer 21 is joined to the first conductor layer 12 by the brazing material 5, the back surface first metal layer 210 is the second conductor layer by the back surface brazing material 50. It is joined to 13.
　続いて、本実施の形態の作用効果を説明する。
　実施の形態３に係る半導体装置１００によれば、図９に示されるように、半導体装置１００は、裏面積層材２０をさらに含んでいる。このため、第２金属層２２および裏面第２金属層２２０の各々は、基板１の第１導体層１２および第２導体層１３のそれぞれに接合されている。よって、半導体素子３（図１参照）は、第２金属層２２および裏面第２金属層２２０の少なくともいずれかを介して基板１の第１導体層１２および第２導体層１３の少なくともいずれかに電気的に接続されることができる。したがって、半導体素子３（図１参照）が第２金属層２２のみによって基板１に電気的に接続されている場合に比べて半導体装置１００の設計が容易である。 Subsequently, the action and effect of the present embodiment will be described.
According to the semiconductor device 100 according to the third embodiment, as shown in FIG. 9, the semiconductor device 100 further includes a back surface laminated material 20. Therefore, each of the second metal layer 22 and the back surface second metal layer 220 is joined to each of the first conductor layer 12 and the second conductor layer 13 of the substrate 1. Therefore, the semiconductor element 3 (see FIG. 1) is placed on at least one of the first conductor layer 12 and the second conductor layer 13 of the substrate 1 via at least one of the second metal layer 22 and the back surface second metal layer 220. Can be electrically connected. Therefore, the design of the semiconductor device 100 is easier than in the case where the semiconductor element 3 (see FIG. 1) is electrically connected to the substrate 1 only by the second metal layer 22.
　実施の形態４．
　本実施の形態は、上述した実施の形態１～３および後述される実施の形態５および６にかかる半導体装置を電力変換装置に適用したものである。本開示は特定の電力変換装置に限定されるものではないが、以下、実施の形態４として、三相のインバータに本開示を適用した場合について説明する。 Embodiment 4.
In this embodiment, the semiconductor devices according to the above-described first to third embodiments and the fifth and sixth embodiments described later are applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, the case where the present disclosure is applied to a three-phase inverter will be described below as a fourth embodiment.
　図１１は、本実施の形態にかかる電力変換装置を適用した電力変換システムの構成を示すブロック図である。 FIG. 11 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.
　図１１に示す電力変換システムは、電源１０１、電力変換装置２００、負荷３００から構成される。電源１０１は、直流電源であり、電力変換装置２００に直流電力を供給する。電源１０１は種々のもので構成することが可能であり、例えば、直流系統、太陽電池、蓄電池で構成することができるし、交流系統に接続された整流回路やＡＣ／ＤＣコンバータで構成することとしてもよい。また、電源１０１を、直流系統から出力される直流電力を所定の電力に変換するＤＣ／ＤＣコンバータによって構成することとしてもよい。 The power conversion system shown in FIG. 11 includes a power supply 101, a power conversion device 200, and a load 300. The power supply 101 is a DC power supply, and supplies DC power to the power converter 200. The power supply 101 can be composed of various things, for example, a DC system, a solar cell, a storage battery, a rectifier circuit connected to an AC system, or an AC / DC converter. May be good. Further, the power supply 101 may be configured by a DC / DC converter that converts the DC power output from the DC system into a predetermined power.
　電力変換装置２００は、電源１０１と負荷３００の間に接続された三相のインバータであり、電源１０１から供給された直流電力を交流電力に変換し、負荷３００に交流電力を供給する。電力変換装置２００は、図１１に示すように、直流電力を交流電力に変換して出力する主変換回路２０１と、主変換回路２０１を制御する制御信号を主変換回路２０１に出力する制御回路２０３とを備えている。 The power conversion device 200 is a three-phase inverter connected between the power supply 101 and the load 300, converts the DC power supplied from the power supply 101 into AC power, and supplies the AC power to the load 300. As shown in FIG. 11, the power conversion device 200 has a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. And have.
　負荷３００は、電力変換装置２００から供給された交流電力によって駆動される三相の電動機である。なお、負荷３００は特定の用途に限られるものではなく、各種電気機器に搭載された電動機であり、例えば、ハイブリッド自動車や電気自動車、鉄道車両、エレベーター、もしくは、空調機器向けの電動機として用いられる。 The load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200. The load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices. For example, the load 300 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an air conditioner.
　以下、電力変換装置２００の詳細を説明する。主変換回路２０１は、スイッチング素子と還流ダイオードを備えており（図示せず）、スイッチング素子がスイッチングすることによって、電源１０１から供給される直流電力を交流電力に変換し、負荷３００に供給する。主変換回路２０１の具体的な回路構成は種々のものがあるが、本実施の形態にかかる主変換回路２０１は２レベルの三相フルブリッジ回路であり、６つのスイッチング素子とそれぞれのスイッチング素子に逆並列された６つの還流ダイオードから構成することができる。主変換回路２０１の各スイッチング素子および各還流ダイオードの少なくともいずれかは、上述した実施の形態１～３のいずれかの半導体装置に相当する半導体装置２０２が有するスイッチング素子又は還流ダイオードである。６つのスイッチング素子は２つのスイッチング素子ごとに直列接続され上下アームを構成し、各上下アームはフルブリッジ回路の各相（Ｕ相、Ｖ相、Ｗ相）を構成する。そして、各上下アームの出力端子、すなわち主変換回路２０１の３つの出力端子は、負荷３００に接続される。 The details of the power conversion device 200 will be described below. The main conversion circuit 201 includes a switching element and a freewheeling diode (not shown), and when the switching element switches, the DC power supplied from the power supply 101 is converted into AC power and supplied to the load 300. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It can consist of six anti-parallel freewheeling diodes. At least one of each switching element and each freewheeling diode of the main conversion circuit 201 is a switching element or freewheeling diode included in the semiconductor device 202 corresponding to any of the semiconductor devices of the above-described first to third embodiments. The six switching elements are connected in series for each of the two switching elements to form an upper and lower arm, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. Then, the output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.
　また、主変換回路２０１は、各スイッチング素子を駆動する駆動回路（図示なし）を備えているが、駆動回路は半導体装置２０２に内蔵されていてもよいし、半導体装置２０２とは別に駆動回路を備える構成であってもよい。駆動回路は、主変換回路２０１のスイッチング素子を駆動する駆動信号を生成し、主変換回路２０１のスイッチング素子の制御電極に供給する。具体的には、後述する制御回路２０３からの制御信号に従い、スイッチング素子をオン状態にする駆動信号とスイッチング素子をオフ状態にする駆動信号とを各スイッチング素子の制御電極に出力する。スイッチング素子をオン状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以上の電圧信号（オン信号）であり、スイッチング素子をオフ状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以下の電圧信号（オフ信号）となる。 Further, although the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element, the drive circuit may be built in the semiconductor device 202, or a drive circuit may be provided separately from the semiconductor device 202. It may be provided. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of each switching element. When the switching element is kept on, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is kept off, the drive signal is a voltage equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).
　制御回路２０３は、負荷３００に所望の電力が供給されるよう主変換回路２０１のスイッチング素子を制御する。具体的には、負荷３００に供給すべき電力に基づいて主変換回路２０１の各スイッチング素子がオン状態となるべき時間（オン時間）を算出する。例えば、出力すべき電圧に応じてスイッチング素子のオン時間を変調するＰＷＭ制御によって主変換回路２０１を制御することができる。そして、各時点においてオン状態となるべきスイッチング素子にはオン信号を、オフ状態となるべきスイッチング素子にはオフ信号が出力されるよう、主変換回路２０１が備える駆動回路に制御指令（制御信号）を出力する。駆動回路は、この制御信号に従い、各スイッチング素子の制御電極にオン信号又はオフ信号を駆動信号として出力する。 The control circuit 203 controls the switching element of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the time (on time) at which each switching element of the main conversion circuit 201 should be in the on state is calculated based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit included in the main conversion circuit 201 so that an on signal is output to the switching element that should be turned on at each time point and an off signal is output to the switching element that should be turned off. Is output. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.
　本実施の形態に係る電力変換装置では、主変換回路２０１を構成する半導体装置２０２として実施の形態１～３にかかる半導体装置を適用するため、基板の導体層に前処理が施される必要がなく、かつ半導体素子をアルミニウムよりもはんだに対する濡れ性が高い金属層に接合できる電力変換装置を実現することができる。 In the power conversion device according to the present embodiment, in order to apply the semiconductor devices according to the first to third embodiments as the semiconductor device 202 constituting the main conversion circuit 201, it is necessary to pretreat the conductor layer of the substrate. It is possible to realize a power conversion device capable of bonding a semiconductor element to a metal layer having a higher wettability to solder than aluminum.
　本実施の形態では、２レベルの三相インバータに本開示を適用する例を説明したが、本開示は、これに限られるものではなく、種々の電力変換装置に適用することができる。本実施の形態では、２レベルの電力変換装置としたが３レベルやマルチレベルの電力変換装置であっても構わないし、単相負荷に電力を供給する場合には単相のインバータに本開示を適用しても構わない。また、直流負荷等に電力を供給する場合にはＤＣ／ＤＣコンバータやＡＣ／ＤＣコンバータに本開示を適用することも可能である。 In the present embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described, but the present disclosure is not limited to this, and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used, and when power is supplied to a single-phase load, the present disclosure is provided to a single-phase inverter. You may apply it. Further, when supplying electric power to a DC load or the like, the present disclosure can be applied to a DC / DC converter or an AC / DC converter.
　また、本開示を適用した電力変換装置は、上述した負荷が電動機の場合に限定されるものではなく、例えば、放電加工機やレーザー加工機、又は誘導加熱調理器や非接触給電システムの電源装置として用いることもでき、さらには太陽光発電システムや蓄電システム等のパワーコンディショナーとして用いることも可能である。 Further, the power conversion device to which the present disclosure is applied is not limited to the case where the above-mentioned load is an electric motor, and is, for example, a power supply device for an electric discharge machine, a laser machine, an induction heating cooker, or a non-contact power supply system. It can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.
　実施の形態５．
　次に、図１３および図１４を用いて、実施の形態５に係る半導体装置１００の構成を説明する。 Embodiment 5.
Next, the configuration of the semiconductor device 100 according to the fifth embodiment will be described with reference to FIGS. 13 and 14.
　実施の形態５では、図１３に示されるように、積層材２には、複数のスリット２２ｓが設けられていてもよい。第１金属層２１および第２金属層２２のいずれかは、複数のスリット２２ｓによって複数の部分に分割されている。図１３では、第２金属層２２は、複数のスリット２２ｓによって複数の部分２２９に分割されている。これにより、第１金属層２１の熱膨張係数と第２金属層２２の熱膨張係数との差による高温での積層材２の反りを抑制することができる。積層材２の反りが抑制されるため、ろう材５にボイドが生じることを抑制することができる。よって、ろう材５による接合性が向上する。なお、図示されないが、第１金属層２１は、複数のスリットによって複数の部分に分割されていてもよい。この場合でも、熱膨張係数の差による反りが抑制される。 In the fifth embodiment, as shown in FIG. 13, the laminated lumber 2 may be provided with a plurality of slits 22s. Either the first metal layer 21 or the second metal layer 22 is divided into a plurality of portions by a plurality of slits 22s. In FIG. 13, the second metal layer 22 is divided into a plurality of portions 229 by the plurality of slits 22s. Thereby, the warp of the laminated material 2 at a high temperature due to the difference between the coefficient of thermal expansion of the first metal layer 21 and the coefficient of thermal expansion of the second metal layer 22 can be suppressed. Since the warp of the laminated material 2 is suppressed, it is possible to suppress the formation of voids in the brazing material 5. Therefore, the bondability of the brazing material 5 is improved. Although not shown, the first metal layer 21 may be divided into a plurality of portions by a plurality of slits. Even in this case, the warp due to the difference in the coefficient of thermal expansion is suppressed.
　図１４に示されるように、第１金属層２１および第２金属層２２のいずれかは、複数のスリット２２ｓによって、半導体素子３の形状および寸法に応じて複数の部分に分割されている。これにより、第２金属層２２の上面に半導体素子３が搭載される際に第２金属層２２の上面においてはんだ４が広がりすぎることを抑制することができる。よって、はんだ４がはんだ４に隣接するはんだ付け部に流出する等の不具合を抑制することができる。 As shown in FIG. 14, either the first metal layer 21 or the second metal layer 22 is divided into a plurality of portions according to the shape and dimensions of the semiconductor element 3 by the plurality of slits 22s. As a result, it is possible to prevent the solder 4 from spreading too much on the upper surface of the second metal layer 22 when the semiconductor element 3 is mounted on the upper surface of the second metal layer 22. Therefore, it is possible to suppress problems such as the solder 4 flowing out to the soldered portion adjacent to the solder 4.
　実施の形態６．
　次に、図１５を用いて、実施の形態６に係る半導体装置１００の構成を説明する。 Embodiment 6.
Next, the configuration of the semiconductor device 100 according to the sixth embodiment will be described with reference to FIG.
　実施の形態６では、図１５に示されるように、積層材２の第１金属層２１および第２金属層２２ならびにろう材５がクラッド材を構成している。すなわち、積層材２の第１金属層２１および第２金属層２２ならびにろう材５は、あらかじめ一体化されていてもよい。これにより、生産性および接合性がさらに向上する。 In the sixth embodiment, as shown in FIG. 15, the first metal layer 21, the second metal layer 22, and the brazing material 5 of the laminated material 2 constitute a clad material. That is, the first metal layer 21, the second metal layer 22, and the brazing material 5 of the laminated material 2 may be integrated in advance. This further improves productivity and bondability.
　積層材２およびろう材５がクラッド材を構成している場合でも、積層材２に複数のスリット２２ｓが設けられていてもよい。この場合、複数のスリット２２ｓは、第１金属層２１、第２金属層２２およびろう材５のいずれかを複数の部分に分割している。これにより、高温において積層材２が反ることを抑制することができる。よって、積層材２の接合性が向上する。 Even when the laminated material 2 and the brazing material 5 constitute a clad material, the laminated material 2 may be provided with a plurality of slits 22s. In this case, the plurality of slits 22s divide any one of the first metal layer 21, the second metal layer 22, and the brazing material 5 into a plurality of portions. As a result, it is possible to prevent the laminated lumber 2 from warping at a high temperature. Therefore, the bondability of the laminated lumber 2 is improved.
　今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本開示の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiments disclosed this time should be considered to be exemplary in all respects and not restrictive. The scope of the present disclosure is indicated by the scope of claims rather than the above description, and is intended to include all modifications within the meaning and scope of the claims.
　１　基板、２　積層材、３　半導体素子、４　はんだ、５　ろう材、６　ヒートシンク、１１　セラミック層、１２　第１導体層、１３　第２導体層、２１　第１金属層、２２　第２金属層、２３　第３金属層、１００　半導体装置、１０１　電源、２００　電力変換装置、２０１　主変換回路、２０２　半導体装置、２０３　制御回路、３００　負荷。 1 substrate, 2 laminated material, 3 semiconductor element, 4 solder, 5 brazing material, 6 heat sink, 11 ceramic layer, 12 1st conductor layer, 13 2nd conductor layer, 21 1st metal layer, 22 2nd metal layer, 23 Third metal layer, 100 semiconductor device, 101 power supply, 200 power conversion device, 201 main conversion circuit, 202 semiconductor device, 203 control circuit, 300 load.

Claims (10)

  1. 　セラミック層と、前記セラミック層に積層された第１導体層とを含む基板と、
    　前記第１導体層に対して前記セラミック層とは反対側に配置されたろう材と、
    　前記第１導体層に対して前記セラミック層とは反対側で前記ろう材によって前記第１導体層に接合された第１金属層と、前記第１金属層に対して前記第１導体層とは反対側で前記第１金属層に積層された第２金属層とを含む積層材と、
    　前記第２金属層に配置されたはんだと、
    　前記はんだによって前記第２金属層に接合された半導体素子とを備え、
    　前記半導体素子は、前記積層材を介して前記基板に電気的に接続されており、
    　前記第１導体層および前記第１金属層の材料は、アルミニウムを含み、
    　前記第２金属層は、前記第１金属層よりも前記はんだに対する濡れ性が高い、半導体装置。     A substrate including a ceramic layer and a first conductor layer laminated on the ceramic layer,
    A brazing material arranged on the side opposite to the ceramic layer with respect to the first conductor layer,
    The first metal layer bonded to the first conductor layer by the brazing material on the side opposite to the ceramic layer with respect to the first conductor layer, and the first conductor layer with respect to the first metal layer A laminated material containing a second metal layer laminated on the first metal layer on the opposite side, and
    With the solder arranged on the second metal layer,
    A semiconductor element bonded to the second metal layer by the solder is provided.
    The semiconductor element is electrically connected to the substrate via the laminated material.
    The material of the first conductor layer and the first metal layer contains aluminum and contains aluminum.
    The second metal layer is a semiconductor device having a higher wettability to the solder than the first metal layer.
  2. 　前記積層材は、前記第１金属層と前記第２金属層とを含むクラッド材である、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the laminated material is a clad material including the first metal layer and the second metal layer.
  3. 　前記積層材の前記第１金属層および前記第２金属層ならびに前記ろう材がクラッド材を構成している、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the first metal layer, the second metal layer, and the brazing material of the laminated material constitute a clad material.
  4. 　前記積層材は、前記第１金属層と前記第２金属層との間に配置された第３金属層をさらに含み、
    　前記第３金属層の材料は、チタンを含む、請求項１～３のいずれか１項に記載の半導体装置。     The laminated material further includes a third metal layer arranged between the first metal layer and the second metal layer.
    The semiconductor device according to any one of claims 1 to 3, wherein the material of the third metal layer contains titanium.
  5. 　前記第２金属層の材料は、ニッケルを含む、請求項１～４のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 4, wherein the material of the second metal layer contains nickel.
  6. 　前記第２金属層の材料は、銅を含む、請求項５に記載の半導体装置。 The semiconductor device according to claim 5, wherein the material of the second metal layer contains copper.
  7. 　前記基板は、前記セラミック層に対して前記第１導体層とは反対側に積層された第２導体層をさらに含み、
    　前記第２導体層に対して前記第１導体層とは反対側で前記第２導体層に接合されたヒートシンクをさらに備えた、請求項１～６のいずれか１項に記載の半導体装置。     The substrate further includes a second conductor layer laminated on the side opposite to the first conductor layer with respect to the ceramic layer.
    The semiconductor device according to any one of claims 1 to 6, further comprising a heat sink bonded to the second conductor layer on the side opposite to the first conductor layer with respect to the second conductor layer.
  8. 　前記基板は、複数の基板部を含んでいる、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the substrate includes a plurality of substrate portions.
  9. 　前記第１金属層および前記第２金属層のいずれかは、複数のスリットによって複数の部分に分割されている、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein either the first metal layer or the second metal layer is divided into a plurality of portions by a plurality of slits.
  10. 　請求項１～９のいずれか１項に記載の前記半導体装置を有し、入力される電力を変換して出力する主変換回路と、
    　前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路とを備えた電力変換装置。     A main conversion circuit having the semiconductor device according to any one of claims 1 to 9 and converting and outputting input power.
    A power conversion device including a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit.
PCT/JP2021/000189 2020-01-16 2021-01-06 Semiconductor device and power conversion device WO2021145250A1 (en)

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JP2011029323A (en) * 2009-07-23 2011-02-10 Mitsubishi Materials Corp Substrate for power module, power module, and method of manufacturing substrate for power module
JP2012004534A (en) * 2010-05-18 2012-01-05 Showa Denko Kk Heat radiation insulating substrate and method of manufacturing the same
JP2013222758A (en) * 2012-04-13 2013-10-28 Showa Denko Kk Method of manufacturing insulation board
JP2013222909A (en) * 2012-04-19 2013-10-28 Showa Denko Kk Method of manufacturing insulation board
JP2015023128A (en) * 2013-07-18 2015-02-02 三菱電機株式会社 Semiconductor module and manufacturing method of the same

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JP2011029323A (en) * 2009-07-23 2011-02-10 Mitsubishi Materials Corp Substrate for power module, power module, and method of manufacturing substrate for power module
JP2012004534A (en) * 2010-05-18 2012-01-05 Showa Denko Kk Heat radiation insulating substrate and method of manufacturing the same
JP2013222758A (en) * 2012-04-13 2013-10-28 Showa Denko Kk Method of manufacturing insulation board
JP2013222909A (en) * 2012-04-19 2013-10-28 Showa Denko Kk Method of manufacturing insulation board
JP2015023128A (en) * 2013-07-18 2015-02-02 三菱電機株式会社 Semiconductor module and manufacturing method of the same

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