CN114930528A - Semiconductor device and power conversion device - Google Patents

Semiconductor device and power conversion device Download PDF

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Publication number
CN114930528A
CN114930528A CN202180008642.4A CN202180008642A CN114930528A CN 114930528 A CN114930528 A CN 114930528A CN 202180008642 A CN202180008642 A CN 202180008642A CN 114930528 A CN114930528 A CN 114930528A
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metal layer
layer
semiconductor device
metal
conductor layer
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CN202180008642.4A
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Inventor
藤野纯司
小川道雄
川添智香
井本裕児
小川翔平
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor device (100) is provided with a substrate (1), a brazing filler metal (5), a laminate (2), a solder (4), and a semiconductor element (3). The 1 st metal layer (21) is joined to the 1 st conductor layer (12) by brazing filler metal (5) on the side opposite to the ceramic layer (11) with respect to the 1 st conductor layer (12). The 2 nd metal layer (22) is laminated on the 1 st metal layer (21) on the side opposite to the 1 st conductor layer (12) with respect to the 1 st metal layer (21). The semiconductor element (3) is bonded to the 2 nd metal layer (22) by a solder (4). The material of the 1 st conductor layer (12) and the 1 st metal layer (21) includes aluminum. The wettability of the 2 nd metal layer (22) with respect to the solder (4) is higher than that of the 1 st metal layer (21).

Description

Semiconductor device and power conversion device
Technical Field
The present disclosure relates to a semiconductor device and a power conversion device.
Background
Conventionally, there is a semiconductor device including an insulating substrate, a circuit layer, a solder disposed on the circuit layer, and a semiconductor element bonded to the circuit layer by the solder. The circuit layer includes an aluminum layer. Aluminum has low wettability to solder. Therefore, in order to bond the semiconductor element to the circuit layer by solder, it is necessary to provide a metal layer containing a metal having high wettability with respect to solder on the aluminum layer. However, since an oxide film is easily generated on the surface of the aluminum layer, it is difficult to provide a metal layer on the aluminum layer by plating.
For example, in a semiconductor device described in japanese patent application laid-open No. 2014-209539 (patent document 1), a circuit layer includes a 1 st aluminum layer (aluminum layer) and a 1 st copper layer (metal layer). The 1 st copper layer (metal layer) is bonded to the 1 st aluminum layer (aluminum layer) by solid-phase diffusion bonding. The 1 st copper layer (metal layer) has higher wettability to solder than the 1 st aluminum layer (aluminum layer).
Documents of the prior art
Patent literature
Patent document 1: japanese patent laid-open publication No. 2014-209539
Disclosure of Invention
In the semiconductor device described in the above publication, the metal layer (1 st copper layer) is bonded to the conductor layer (1 st aluminum layer) by solid phase diffusion bonding. In the solid-phase diffusion bonding, no liquid phase is generated at the contact surface between the metal layer (1 st copper layer) and the conductor layer (1 st aluminum layer). Therefore, when the contact surface between the metal layer (1 st copper layer) and the conductor layer (1 st aluminum layer) is provided with irregularities, the metal layer (1 st copper layer) and the conductor layer (1 st aluminum layer) are not sufficiently in contact with each other. Therefore, it is necessary to smooth the contact surface before the metal layer (1 st copper layer) is joined to the conductor layer (1 st aluminum layer) by solid phase diffusion bonding. That is, the conductor layer (1 st aluminum layer) of the substrate needs to be smoothed.
The present disclosure has been made in view of the above problems, and an object thereof is to provide a semiconductor device and a power conversion device capable of bonding a semiconductor element to a metal layer having higher wettability with respect to solder than aluminum without smoothing a conductor layer of a substrate.
The semiconductor device of the present disclosure includes a substrate, a brazing filler metal, a laminate, a solder, and a semiconductor element. The substrate includes a ceramic layer and a 1 st conductor layer. The 1 st conductor layer is laminated on the ceramic layer. The brazing filler metal is disposed on the opposite side of the ceramic layer from the 1 st conductor layer. The laminate material includes a 1 st metal layer and a 2 nd metal layer. The 1 st metal layer is joined to the 1 st conductor layer by brazing filler metal on the side opposite to the ceramic layer with respect to the 1 st conductor layer. The 2 nd metal layer is laminated on the 1 st metal layer on the opposite side of the 1 st conductor layer with respect to the 1 st metal layer. The solder is disposed on the 2 nd metal layer. The semiconductor element is joined to the 2 nd metal layer by solder. The semiconductor element is electrically connected to the substrate via the laminate material. The material of the 1 st conductor layer and the 1 st metal layer includes aluminum. The 2 nd metal layer has higher wettability for solder than the 1 st metal layer.
According to the semiconductor device of the present disclosure, the 1 st metal layer is joined to the 1 st conductor layer with the brazing filler metal on the side opposite to the ceramic layer with respect to the 1 st conductor layer. Therefore, it is not necessary to smooth the 1 st conductor layer of the substrate. The semiconductor element is bonded to the 2 nd metal layer with solder. The 2 nd metal layer has higher wettability for solder than the 1 st metal layer. Therefore, the semiconductor element can be bonded to the metal layer having higher wettability with solder than aluminum.
Drawings
Fig. 1 is a sectional view schematically showing the structure of a semiconductor device according to embodiment 1.
Fig. 2 is a cross-sectional view schematically showing the structure of a semiconductor device according to modification 1 of embodiment 1.
Fig. 3 is a flowchart schematically showing a method for manufacturing a semiconductor device according to embodiment 1.
Fig. 4 is a cross-sectional view schematically showing a state of the semiconductor device in the step of joining the 1 st metal layer to the 1 st conductor layer with a brazing material in the method for manufacturing a semiconductor device according to embodiment 1.
Fig. 5 is a cross-sectional view schematically showing a state of the semiconductor device in the step of bonding the semiconductor element to the 2 nd metal layer with solder in the method of manufacturing a semiconductor device according to embodiment 1.
Fig. 6 is a cross-sectional view schematically showing a state of the semiconductor device in the step of bonding the semiconductor element to the 2 nd metal layer with solder in the method of manufacturing the semiconductor device according to the 1 st modification of embodiment 1.
Fig. 7 is a cross-sectional view schematically showing another state of the semiconductor device in the step of bonding the semiconductor element to the 2 nd metal layer with solder in the method of manufacturing a semiconductor device according to variation 1 of embodiment 1.
Fig. 8 is a cross-sectional view schematically showing the structure of the semiconductor device of embodiment 2.
Fig. 9 is a cross-sectional view schematically showing the structure of the semiconductor device of embodiment 3.
Fig. 10 is a cross-sectional view schematically showing a state of the semiconductor device in the step of joining the 1 st metal layer to the 1 st conductor layer with a brazing filler metal in the method for manufacturing a semiconductor device according to embodiment 2.
Fig. 11 is a block diagram schematically showing the configuration of a power conversion device according to embodiment 4.
Fig. 12 is a cross-sectional view schematically showing a state where a plurality of substrate portions are mounted in the method for manufacturing a semiconductor device according to modification 2 of embodiment 1.
Fig. 13 is a cross-sectional view schematically showing a state where the 2 nd metal layer of the cladding material is divided by a plurality of slits in the method for manufacturing a semiconductor device according to embodiment 5.
Fig. 14 is a cross-sectional view schematically showing the structure of the semiconductor device according to embodiment 5.
Fig. 15 is a cross-sectional view schematically showing a state in which the 1 st metal layer and the 2 nd metal layer of the laminate and the brazing filler metal are integrated in the method for manufacturing a semiconductor device according to embodiment 6.
Description of the symbols
1: a substrate; 2: a laminate material; 3: a semiconductor element; 4: soft solder; 5: brazing filler metal; 6: a heat sink; 11: a ceramic layer; 12: 1 st conductor layer; 13: a 2 nd conductor layer; 21: a 1 st metal layer; 22: a 2 nd metal layer; 23: a 3 rd metal layer; 100: a semiconductor device; 101: a power source; 200: a power conversion device; 201: a main conversion circuit; 202: a semiconductor device; 203: a control circuit; 300: and (4) loading.
Detailed Description
Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same or corresponding portions are denoted by the same reference numerals, and redundant description thereof will not be repeated.
Embodiment 1.
The structure of a semiconductor device 100 according to embodiment 1 will be described with reference to fig. 1. As shown in fig. 1, the semiconductor device 100 includes a substrate 1, a laminate 2, a semiconductor element 3, a solder 4, a brazing material 5, a back surface brazing material 50, a heat sink 6, a case 7, a wiring member 8, and a sealing material SR. The semiconductor device 100 is a power semiconductor device for electric power.
As shown in fig. 1, the substrate 1 includes a ceramic layer 11, a 1 st conductor layer 12, and a 2 nd conductor layer 13. The substrate 1 extends in an in-plane direction.
The material of the ceramic layer 11 is, for example, aluminum nitride (AlN), alumina (alumina), silicon carbide (SiC), silicon nitride (SiN), or the like. In the present embodiment, the material of the ceramic layer 11 is aluminum nitride (AlN).
The width of the ceramic layer 11 in the in-plane direction is, for example, 65 mm. The length of the ceramic layer 11 in the in-plane direction is, for example, 65 mm. The thickness of the ceramic layer 11 in the 1 st direction is, for example, 0.64 mm. In the present embodiment, the 1 st direction is orthogonal to the in-plane direction.
As shown in fig. 1, the 1 st conductor layer 12 is laminated on the ceramic layer 11. The 1 st conductor layer 12 is directly laminated on the ceramic layer 11 in the 1 st direction. The 1 st conductor layer 12 is formed as a circuit pattern. The 2 nd conductor layer 13 is laminated on the opposite side of the ceramic layer 11 from the 1 st conductor layer 12. The 2 nd conductor layer 13 is directly laminated on the ceramic layer 11 in the 1 st direction. The 2 nd conductor layer 13 sandwiches the ceramic layer 11 with the 1 st conductor layer 12 in the 1 st direction. The 2 nd conductor layer 13 may be formed as a circuit pattern. The 1 st conductor layer 12 and the 2 nd conductor layer 13 are respectively bonded to both surfaces of the ceramic layer 11.
The material of the 1 st conductor layer 12 and the 2 nd conductor layer 13 includes aluminum (Al). The material of the 1 st conductor layer 12 and the 2 nd conductor layer 13 may be, for example, aluminum (Al) or an aluminum alloy such as a 6063. In the present embodiment, the material of the 1 st conductor layer 12 and the 2 nd conductor layer 13 is aluminum (Al).
The width in the in-plane direction of the 1 st conductor layer 12 and the 2 nd conductor layer 13 is, for example, 61 mm. The lengths of the 1 st conductor layer 12 and the 2 nd conductor layer 13 in the in-plane direction are, for example, 61 mm. The thickness of the 1 st conductor layer 12 and the 2 nd conductor layer 13 in the 1 st direction is, for example, 0.4 mm.
The laminate 2 is laminated on the substrate 1 in the 1 st direction. As shown in fig. 1, the laminated material 2 includes a 1 st metal layer 21 and a 2 nd metal layer 22.
As shown in fig. 1, the 1 st metal layer 21 is bonded to the 1 st conductor layer 12 on the opposite side of the 1 st conductor layer 12 from the ceramic layer 11. The thickness of the 1 st metal layer 21 is, for example, 0.2 mm. The brazing filler metal 5 is disposed on the opposite side of the ceramic layer 11 with respect to the 1 st conductor layer 12. The 1 st metal layer 21 is bonded to the 1 st conductor layer 12 with brazing filler metal 5. The brazing filler metal 5 is sandwiched between the 1 st metal layer 21 and the 1 st conductor layer 12. The brazing filler metal 5 is directly laminated on the substrate 1 and the laminated material 2 in the 1 st direction. The brazing filler 5 is, for example, an aluminum-silicon brazing filler. The thickness of the brazing filler metal 5 is, for example, 0.1 mm.
The material of the 1 st metal layer 21 includes aluminum. The material of the 1 st metal layer 21 may be, for example, aluminum (Al) or an aluminum alloy such as a 6063. In the present embodiment, the material of the 1 st metal layer 21 is aluminum (Al).
As shown in fig. 1, the 2 nd metal layer 22 is laminated on the 1 st metal layer 21 on the side opposite to the 1 st conductor layer 12 with respect to the 1 st metal layer 21. In the present embodiment, the 2 nd metal layer 22 is directly laminated on the 1 st metal layer 21. The 2 nd metal layer 22 is disposed on the outermost surface side of the laminate 2. The thickness of the 2 nd metal layer 22 is, for example, 0.1 mm.
The wettability of the 2 nd metal layer 22 with respect to the solder 4 is higher than that of the 1 st metal layer 21. The 2 nd metal layer 22 has higher wettability to the solder 4 than aluminum (Al). The material of the 2 nd metal layer 22 includes any of nickel (Ni), silver (Ag), and 42 alloy. The 42 alloy is an alloy containing iron (Fe) and nickel (Ni). In the present embodiment, the material of the 2 nd metal layer 22 includes nickel (Ni).
In the present embodiment, the laminate 2 is a clad material including the 1 st metal layer 21 and the 2 nd metal layer 22. Therefore, the 1 st metal layer 21 is closely attached to the 2 nd metal layer 22 without a gap. The 1 st metal layer 21 and the 2 nd metal layer 22 may be bonded and integrated. The clad material may be formed by laminating the 1 st metal layer 21 and the 2 nd metal layer 22 by cold pressure welding, hot pressure welding, laser welding, friction stir bonding, or the like. In the present embodiment, the 1 st metal layer 21 and the 2 nd metal layer 22 are pressure-welded and integrated by cold pressure welding.
The laminate 2 may be formed by laminating the 1 st metal layer 21 and the 2 nd metal layer 22 by vapor deposition, sputtering, or the like. The minimum value of the thickness of the laminate 2 is, for example, 30 μm or more and 50 μm or less. The maximum value of the thickness of the laminate 2 is, for example, 10 mm.
As shown in fig. 1, solder 4 is disposed on metal layer 2 22. The solder 4 is disposed on the 2 nd metal layer 22 on the side opposite to the 1 st metal layer 21 with respect to the 2 nd metal layer 22. The material of the solder 4 is, for example, Sn-Ag-Cu (tin-silver-copper) solder, Sn-Sb-Ag (tin-antimony-silver) solder, or the like. Specific examples of the material of the solder 4 include Sn96.5-Ag 3-Cu0.5 (mass%) solder, Sn98.5-Ag 1-Cu0.5 (mass%) solder, and Sn 96-Sb 3-Ag 1 (mass%) solder. The material of the solder 4 in the present embodiment is Sn96.5-Ag 3-Cu0.5 (mass%) solder.
The material of solder 4 may be copper (Cu) -tin (Sn) paste, nano silver (Ag) paste, or the like. In the joining with the copper (Cu) -tin (Sn) paste, the copper powder after dispersion is solidified isothermally, and therefore has high heat resistance. The bonding based on the nano silver (Ag) paste is performed by low-temperature firing based on nano silver (Ag) particles.
As shown in fig. 1, semiconductor element 3 is bonded to metal 2 layer 22 with solder 4. The semiconductor element 3 is electrically connected to the substrate 1 via the laminate 2. Examples of the Semiconductor element 3 include an Insulated Gate Bipolar Transistor (IGBT), a diode, and a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The semiconductor device 100 may include a plurality of semiconductor elements 3. In this embodiment, the semiconductor device 100 includes a plurality of semiconductor elements 3.
The 1 semiconductor element 3 is electrically connected to at least one of the terminal 9 and the other semiconductor elements 3 via the wiring member 8. Thus, the substrate 1, the laminate 2, the semiconductor element 3, the wiring member 8, and the terminal 9 constitute a circuit. The terminals 9 are insert-formed in the housing 7. The terminals 9 include signal terminals 91 and main terminals 92. The signal terminal 91 and the main terminal 92 are electrically connected to the semiconductor element 3.
The wiring member 8 is, for example, a bonding wire, a bonding tape, a plate electrode, or the like. In the case where the wiring member 8 is a bonding wire, the wiring member 8 is wire-bonded to the semiconductor element 3. The material of the bonding wire is, for example, aluminum (Al), copper (Cu), gold (Au), or the like. The bonding wire may also be a copper wire coated with aluminum (Al). In the present embodiment, the wiring member 8 is a bonding wire made of aluminum (Al). The diameter of the wiring member 8 connected to the signal terminal 91 is, for example, 0.15 mm. The diameter of the wiring member 8 connected to the main terminal 92 is, for example, 0.3 mm. In the case where the wiring member 8 is a bonding tape, the wiring member 8 is tape-bonded to the semiconductor element 3. When wiring member 8 is a plate electrode, wiring member 8 is directly soldered to semiconductor element 3.
As shown in fig. 1, the heat spreader 6 is joined to the 2 nd conductor layer 13 on the side opposite to the 1 st conductor layer 12 with respect to the 2 nd conductor layer 13. The heat spreader 6 is bonded to the 2 nd conductor layer 13 with a back brazing filler metal 50. The back braze 50 is, for example, an aluminum-silicon braze. The heat sink 6 includes a base plate 61 and a plurality of fin portions 62. The base plate 61 is bonded to the 2 nd conductor layer 13 with the back brazing filler metal 50. The plurality of fin portions 62 protrude from the base plate 61 toward the opposite side of the base plate 61 from the base plate 1.
The case 7 surrounds the substrate 1, the laminate 2, the semiconductor element 3, the solder 4, the brazing filler metal 5, the back brazing filler metal 50, the heat sink 6, and the wiring member 8. The housing 7 has a frame shape. The material of the case 7 is, for example, PPS (PolyPhenylene Sulfide) resin, Liquid Crystal Polymer (LCP) or the like. In the present embodiment, the material of the case 7 is PPS resin.
The sealing material SR is injected into the inner space of the case 7. The sealing material SR is a liquid sealing material. The sealing material SR may be, for example, an epoxy resin containing a silica filler, or may be a silicone rubber.
Next, the structure of a semiconductor device 100 according to modification 1 of embodiment 1 will be described with reference to fig. 2. As shown in fig. 2, in modification 1 of embodiment 1, the semiconductor device 100 includes a transfer molding resin TR and a lead frame LF.
The lead frame LF includes an electrode 90. The electrode 90 includes a signal electrode 93 and a main electrode 94. The signal electrode 93 and the main electrode 94 are electrically connected to the semiconductor element 3. The dimension in the in-plane direction of the lead frame LF is, for example, 150mm × 50 mm. The thickness of the lead frame LF is, for example, 0.6 mm. The transfer molding resin TR seals the substrate 1, the laminate 2, the semiconductor element 3, the solder 4, the brazing filler metal 5, the back brazing filler metal 50, and the wiring member 8. The transfer molding resin TR partially seals the electrode 90.
Next, the structure of the semiconductor device 100 according to modification 2 of embodiment 1 will be described. As shown in fig. 12, in modification 2 of embodiment 1, the substrate 1 includes a plurality of substrate portions 19. That is, the substrate 1 of the present embodiment is singulated. The substrate 1 is divided into two or 6 substrate portions 19, for example. The ceramic layer 11 includes ceramic portions included in the plurality of substrate portions 19. The conductor layer includes conductor portions included in the plurality of substrate portions 19.
Next, a method for manufacturing the semiconductor device 100 according to embodiment 1 will be described with reference to fig. 3 to 5. As shown in fig. 3, the method of manufacturing the semiconductor device 100 includes: step S101 of preparing substrate 1, laminate 2, solder 4, semiconductor element 3, and brazing filler metal 5; a step S102 of bonding the 1 st metal layer 21 to the 1 st conductor layer 12 with a brazing material 5; and step S103 of bonding the semiconductor element 3 to the 2 nd metal layer 22 with the solder 4.
As shown in fig. 4, in step S101 (see fig. 3) of preparing substrate 1, laminate 2, solder 4 (see fig. 5), semiconductor element 3 (see fig. 5), and brazing filler metal 5, substrate 1, laminate 2, solder 4 (see fig. 5), semiconductor element 3 (see fig. 5), and brazing filler metal 5 are prepared. A laminate 2 in which the 1 st metal layer 21 and the 2 nd metal layer 22 are laminated is prepared. As shown in fig. 4 and 5, in step S101 of preparing substrate 1, laminate 2, solder 4, semiconductor element 3, and brazing filler metal 5, back side brazing filler metal 50, heat sink 6, case 7, terminal 9, wiring member 8, and sealing material SR are also prepared. The terminal 9 is insert-molded to the housing 7.
As shown in fig. 4, in step S102 (see fig. 3) of bonding the 1 st metal layer 21 to the 1 st conductor layer 12 with the brazing filler metal 5, the brazing filler metal 5 is disposed on the opposite side of the ceramic layer 11 with respect to the 1 st conductor layer 12, and then the 1 st metal layer 21 is bonded to the 1 st conductor layer 12 with the brazing filler metal 5. In step S102 of bonding the 1 st metal layer 21 to the 1 st conductor layer 12 with the brazing filler metal 5, the back brazing filler metal 50 is sandwiched between the 2 nd conductor layer 13 and the heat sink 6, and then the 2 nd metal layer 22 is bonded to the heat sink 6 with the back brazing filler metal 50.
Specifically, the substrate 1, the laminate 2, the brazing filler metal 5, the back surface brazing filler metal 50, and the heat sink 6 are sandwiched by a jig, not shown, while applying a load. The substrate 1, the laminate 2, the brazing filler metal 5, the back brazing filler metal 50, and the heat sink 6, which are sandwiched by a jig not shown, are joined by heating at 580 ℃ for 3 minutes, for example.
As shown in fig. 5, in step S103 of bonding the semiconductor element 3 to the 2 nd metal layer 22 with the solder 4, the semiconductor element 3 is bonded to the 2 nd metal layer 22 with the solder 4. The substrate 1 is positioned in the case 7 by an adhesive agent not shown. The semiconductor element 3 is electrically connected to the terminal 9 by the wiring member 8. The sealing material SR (see fig. 1) is injected into the case 7. The sealing material SR (see fig. 1) is hardened by being heated at 150 ℃ for 1.5 hours, for example. Thereby, the case 7 is insulation-sealed.
Next, a method for manufacturing the semiconductor device 100 according to modification 1 of embodiment 1 will be described with reference to fig. 6 and 7.
As shown in fig. 6, in step S103 of bonding semiconductor element 3 to metal 2 layer 22 with solder 4, substrate 1 is positioned with respect to lead frame LF. Next, as shown in fig. 7, the lead frame LF is positioned with respect to the mold M. The substrate 1, the laminate 2, the semiconductor element 3, the solder 4, and the brazing filler metal 5 are disposed in the internal space of the mold M. The mold M includes an upper mold M1 and a lower mold M2. The dimensions of the upper mold M1 and the lower mold M2 in the in-plane direction are, for example, 100mm × 80 mm. The dimension of the upper die M1 in the 1 st direction is, for example, 70 mm. The dimension of the lower mold M2 in the 1 st direction is, for example, 100 mm.
As shown in fig. 7, the transfer molding resin TR (see fig. 2) is pressurized and heated, and flows into the internal space of the mold M. The transfer molding resin TR (refer to fig. 2) is temporarily hardened by being heated at 170 ℃ for 5 minutes, for example. The transfer molding resin TR (see fig. 2) after the temporary curing is completely cured after being released from the mold M. The transfer molding resin TR (see fig. 2) is formally hardened by heating at 170 ℃ for 2 hours by an oven, not shown, for example.
Next, the operation and effects of the present embodiment will be described.
According to the semiconductor device 100 of embodiment 1, as shown in fig. 1, the 1 st metal layer 21 is bonded to the 1 st conductor layer 12 with the brazing material 5 on the side opposite to the ceramic layer 11 with respect to the 1 st conductor layer 12. Therefore, it is not necessary to smooth the contact surface between the 1 st conductor layer 12 and the 1 st metal layer 21. Therefore, it is not necessary to smooth the 1 st conductor layer 12 of the substrate 1.
As shown in fig. 1, semiconductor element 3 is bonded to metal 2 layer 22 with solder 4. The 2 nd metal layer 22 has higher wettability with respect to the solder 4 than the 1 st metal layer 21. The material of the 1 st metal layer 21 includes aluminum (Al). Therefore, the semiconductor element 3 can be bonded to the metal layer (the 2 nd metal layer 22) having higher wettability with respect to the solder 4 than aluminum (Al). Therefore, compared to the case where semiconductor element 3 is bonded to aluminum (Al), it can be firmly bonded by solder 4.
As shown in fig. 1, the material of the 1 st conductor layer 12 and the 1 st metal layer 21 includes aluminum (Al). For example, aluminum (Al) has a small specific gravity and a high thermal conductivity as compared with copper (Cu). Therefore, the size and weight of the semiconductor device 100 can be reduced, and the heat dissipation performance of the semiconductor device 100 can be increased.
If the 1 st metal layer 21 is bonded to the 1 st conductor layer 12 by solid-phase diffusion bonding and the material of the 1 st metal layer 21 includes copper (Cu), eutectic reaction occurs between the 1 st conductor layer 12 (aluminum (Al)) and the 1 st metal layer 21 (copper (Cu)). The eutectic reaction lowers the melting point of the 1 st conductor layer 12 and the 1 st metal layer 21, and therefore the 1 st conductor layer 12 and the 1 st metal layer 21 can be liquefied. The 1 st conductor layer 12 (aluminum (Al)) and the 1 st metal layer 21 (copper (Cu)) are liquefied at 540 ℃. Therefore, when the 1 st metal layer 21 is bonded to the 1 st conductor layer 12 by solid-phase diffusion bonding and the material of the 1 st metal layer 21 includes copper (Cu), the heat-resistant temperature of the semiconductor device 100 is 540 ℃. In addition, the 1 st conductor layer 12 and the 1 st metal layer 21 need to be heated at a temperature lower than 540 ℃ for a long time.
According to the semiconductor device 100 of the present embodiment, as shown in fig. 1, the 1 st metal layer 21 is bonded to the 1 st conductor layer 12 with the brazing filler metal 5. The material of both the 1 st metal layer 21 and the 1 st conductor layer 12 includes aluminum (Al). The 1 st metal layer 21 is bonded to the 1 st conductor layer 12 with the brazing filler metal 5 at, for example, 570 ℃ to 600 ℃. Therefore, the liquefaction of the 1 st metal layer 21 and the 1 st conductor layer 12 due to the eutectic reaction can be suppressed. Therefore, the heat resistant temperature of the semiconductor device 100 is higher than that in the case where the 1 st metal layer 21 is bonded to the 1 st conductor layer 12 by solid phase diffusion bonding and the material of the 1 st metal layer 21 includes copper (Cu). This improves the heat resistance of the semiconductor device 100. The time required for bonding the 1 st conductor layer 12 and the 1 st metal layer 21 is shorter than that in the case where the 1 st metal layer 21 is bonded to the 1 st conductor layer 12 by solid-phase diffusion bonding.
As shown in fig. 1, the laminated material 2 is a clad material including a 1 st metal layer 21 and a 2 nd metal layer 22. The clad material-based laminate 2 is less expensive than the clad material-based laminate 2, such as those based on vapor deposition and sputtering. Therefore, the manufacturing cost of the semiconductor device 100 can be reduced. The clad material-based laminate 2 has higher productivity than the clad material-based laminate 2 by vapor deposition, sputtering, or the like. Therefore, the productivity of the semiconductor device 100 can be increased.
As shown in fig. 1, the laminated material 2 is a clad material including a 1 st metal layer 21 and a 2 nd metal layer 22. Therefore, the 1 st metal layer 21 and the 2 nd metal layer 22 are pressure-welded integrally. Therefore, the surface of the 1 st metal layer 21 does not need to be smoothed.
The material of the 2 nd metal layer 22 includes nickel (Ni). Nickel (Ni) has higher wettability with respect to solder 4 than aluminum (Al). Therefore, the wettability of the 2 nd metal layer 22 with respect to the solder 4 is higher than that of aluminum (Al). Therefore, the semiconductor element 3 can be bonded to the 2 nd metal layer 22 having higher wettability with respect to the solder 4 than aluminum (Al).
As shown in fig. 1, the semiconductor device 100 includes a heat spreader 6. Thus, the heat dissipation of the semiconductor device 100 is higher than the case where the semiconductor device 100 does not include the heat sink 6.
As shown in fig. 1, the substrate 1 includes a 1 st conductor layer 12 and a 2 nd conductor layer 13. Therefore, when the heat sink 6 is bonded to the 2 nd conductor layer 13, the laminate 2 can be bonded to the 1 st conductor layer 12. This can reduce the manufacturing cost of the semiconductor device 100.
The material of the 1 st metal layer 21 may be an aluminum alloy. Therefore, the surface hardness of the 1 st metal layer 21 is higher than that in the case where the material of the 1 st metal layer 21 is aluminum (Al). The recrystallization temperature of the 1 st metal layer 21 is higher than that in the case where the material of the 1 st metal layer 21 is aluminum (Al). This improves the quality and reliability of the 1 st metal layer 21.
According to the semiconductor device 100 of modification 1 of embodiment 1, as shown in fig. 2, the semiconductor device 100 includes a transfer molding resin TR. The transfer molding resin TR is molded by a resin molding pressure higher than the sealing material SR. Therefore, the semiconductor device 100 has higher insulation and heat dissipation than the case where the semiconductor device 100 includes the sealing material SR.
According to the semiconductor device 100 of modification 2 of embodiment 1, the substrate 1 includes a plurality of substrate portions. The substrate 1 including the plurality of substrate portions is more easily deformed than the case where the substrate 1 is integrated due to the gaps between the plurality of substrate portions. Therefore, the substrate 1 is easily deformed by warpage due to the difference between the thermal expansion coefficient of the ceramic layer 11 and the thermal expansion coefficient of the first conductor layer 12 and deformation due to temperature cycles of the semiconductor device 100. Therefore, compared to the case where the substrate 1 is integrated, the substrate 1 including a plurality of substrate portions is suppressed from being damaged by a temperature change.
According to the method of manufacturing the semiconductor device 100 of embodiment 1, as shown in fig. 4, in step S102 (see fig. 3) of bonding the 1 st metal layer 21 to the 1 st conductor layer 12 with the brazing filler metal 5, the brazing filler metal 5 is disposed on the opposite side of the ceramic layer 11 with respect to the 1 st conductor layer 12, and then the 1 st metal layer 21 is bonded to the 1 st conductor layer 12 with the brazing filler metal 5. Therefore, it is not necessary to smooth the 1 st conductor layer 12 of the substrate 1. In step S101 (see fig. 3) of preparing the semiconductor element 3 (see fig. 5) and the brazing filler metal 5, the laminated material 2 in which the 1 st metal layer 21 and the 2 nd metal layer 22 are laminated is prepared. Therefore, it is not necessary to smooth the 1 st metal layer 21.
As shown in fig. 5, in step S103 of bonding the semiconductor element 3 to the 2 nd metal layer 22 with the solder 4, the semiconductor element 3 is bonded to the 2 nd metal layer 22 with the solder 4. The 2 nd metal layer 22 has higher wettability with respect to the solder 4 than aluminum (Al). Therefore, the semiconductor element 3 can be bonded to the 2 nd metal layer 22 having higher wettability with respect to the solder 4 than aluminum (Al). Therefore, the semiconductor element 3 can be firmly bonded with the solder 4, compared with the case of bonding to aluminum (Al).
Embodiment 2.
Next, the structure of the semiconductor device 100 according to embodiment 2 will be described with reference to fig. 8. Embodiment 2 has the same configuration, manufacturing method, and operational effects as those of embodiment 1 described above, unless otherwise specified. Therefore, the same components as those in embodiment 1 are denoted by the same reference numerals, and description thereof will not be repeated.
As shown in fig. 8, in the present embodiment, the laminated material 2 further includes a 3 rd metal layer 23. The 3 rd metal layer 23 is disposed between the 1 st metal layer 21 and the 2 nd metal layer 22. The material of the 3 rd metal layer 23 includes titanium (Ti). The material of the 3 rd metal layer 23 may include stainless steel, or other materials that do not undergo a low-temperature eutectic reaction with aluminum (Al).
The 1 st metal layer 21, the 2 nd metal layer 22, and the 3 rd metal layer 23 are stacked in the 1 st direction. The 3 rd metal layer 23 is directly laminated on the 1 st metal layer 21 and the 2 nd metal layer 22. The thickness of the 3 rd metal layer 23 is, for example, 0.05 mm. The material of the 2 nd metal layer 22 includes any of copper (Cu), nickel (Ni), silver (Ag), and 42 alloy. In the present embodiment, the material of the 2 nd metal layer 22 includes copper (Cu).
Next, the operation and effects of the present embodiment will be described.
According to semiconductor device 100 of embodiment 2, as shown in fig. 8, 3 rd metal layer 23 is disposed between 1 st metal layer 21 and 2 nd metal layer 22. Therefore, it is possible to suppress the surface roughness of the 2 nd metal layer 22 from being changed due to the diffusion of the 1 st metal layer 21 and the 2 nd metal layer 22. This can suppress a decrease in wettability of the 2 nd metal layer 22 with respect to the solder 4 due to a change in surface roughness of the 2 nd metal layer 22.
The material of the 3 rd metal layer 23 includes titanium (Ti). Titanium (Ti) has higher heat resistance than nickel (Ni) and copper (Cu). Therefore, eutectic reaction between the 1 st metal layer 21 and the 3 rd metal layer 23 can be suppressed.
The 3 rd metal layer 23 is disposed between the 1 st metal layer 21 and the 2 nd metal layer 22, and therefore the 1 st metal layer 21 and the 2 nd metal layer 22 are not directly stacked. Therefore, eutectic reaction between the 1 st metal layer 21 and the 2 nd metal layer 22 can be suppressed. Thus, the material of the 2 nd metal layer 22 can be appropriately selected.
The material of the 2 nd metal layer 22 includes copper (Cu). Copper (Cu) has higher wettability with respect to solder 4 than nickel (Ni). Therefore, the semiconductor element 3 can be firmly bonded to the 2 nd metal layer 22, as compared with the case where the material of the 2 nd metal layer 22 includes nickel (Ni). The semiconductor element 3 can be bonded to the 2 nd metal layer 22 with a silver sintering agent. In addition, copper (Cu) has higher thermal conductivity than nickel (Ni). Therefore, the semiconductor device 100 has higher heat dissipation than the case where the material of the 2 nd metal layer 22 includes nickel (Ni).
Embodiment 3.
Next, the structure of a semiconductor device 100 according to embodiment 3 will be described with reference to fig. 9. Embodiment 3 has the same configuration, manufacturing method, and operational effects as those of embodiment 1 described above, unless otherwise specified. Therefore, the same components as those in embodiment 1 are denoted by the same reference numerals, and description thereof will not be repeated. In fig. 9, the semiconductor element 3 and the like are not shown for convenience of explanation.
As shown in fig. 9, in this embodiment, the semiconductor device 100 further includes a back surface laminate 20. The back laminate 20 is joined to the substrate 1 on the side opposite to the laminate 2 with respect to the substrate 1. The back laminate 20 may have the same structure as the laminate 2.
The back laminate 20 includes a back metal layer 1 210 and a back metal layer 2 220. The back surface 1 st metal layer 210 is bonded to the 2 nd conductor layer 13 on the side opposite to the ceramic layer 11 with respect to the 2 nd conductor layer 13. The back side 1 st metal layer 210 is bonded to the 2 nd conductor layer 13 with a back side brazing material 50. The material of the back side 1 st metal layer 210 includes aluminum (Al).
The back-side metal layer 2 220 is laminated on the back-side metal layer 1 210 on the side opposite to the 2 nd conductor layer 13 with respect to the back-side metal layer 1 210. The back side metal 2 layer 220 is directly bonded to the back side metal 1 layer 210. The back side 2 nd metal layer 220 has higher wettability with respect to solder 4 than aluminum (Al). The back surface 2 nd metal layer 220 and the 2 nd metal layer 22 sandwich the substrate 1.
Next, a method for manufacturing the semiconductor device 100 according to embodiment 3 will be described with reference to fig. 10. In fig. 10, the semiconductor element 3 and the like are not shown for convenience of explanation. In the present embodiment, in step S102 (see fig. 3) of bonding the 1 st metal layer 21 to the 1 st conductor layer 12 with the brazing filler metal 5, the back surface 1 st metal layer 210 is bonded to the 2 nd conductor layer 13 with the back surface brazing filler metal 50.
Next, the operation and effects of the present embodiment will be described.
According to the semiconductor device 100 of embodiment 3, as shown in fig. 9, the semiconductor device 100 further includes the back surface laminate 20. Therefore, the metal layer 2 22 and the back surface metal layer 2 220 are bonded to the conductor layers 1 and 2 of the conductor layer 12 and 13 of the substrate 1, respectively. Therefore, the semiconductor element 3 (see fig. 1) can be electrically connected to at least one of the 1 st conductor layer 12 and the 2 nd conductor layer 13 of the substrate 1 via at least one of the 2 nd metal layer 22 and the back surface 2 nd metal layer 220. Therefore, the semiconductor device 100 can be designed more easily than the case where the semiconductor element 3 (see fig. 1) is electrically connected to the substrate 1 only by the 2 nd metal layer 22.
Embodiment 4.
In this embodiment, the semiconductor devices of embodiments 1 to 3 described above and embodiments 5 and 6 described later are applied to a power conversion device. The present disclosure is not limited to a specific power conversion device, but a case where the present disclosure is applied to a three-phase inverter as embodiment 4 will be described below.
Fig. 11 is a block diagram showing a configuration of a power conversion system to which the power conversion device of the present embodiment is applied.
The power conversion system shown in fig. 11 includes a power source 101, a power conversion device 200, and a load 300. The power supply 101 is a dc power supply and supplies dc power to the power conversion device 200. The power supply 101 may have various configurations, and may be composed of a DC system, a solar cell, or a storage battery, or may be composed of a rectifier circuit or an AC/DC converter connected to an AC system. The power supply 101 may be configured by a DC/DC converter that converts DC power output from the DC system into predetermined power.
The power converter 200 is a three-phase inverter connected between the power source 101 and the load 300, and converts dc power supplied from the power source 101 into ac power to supply ac power to the load 300. As shown in fig. 11, the power conversion device 200 includes: a main converter circuit 201 that converts dc power into ac power and outputs the ac power; and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201.
The load 300 is a three-phase motor driven by ac power supplied from the power conversion device 200. The load 300 is not limited to a specific application, and is a motor mounted on various electric devices, and is used as a motor for a hybrid car, an electric car, a railway vehicle, an elevator, or an air conditioner, for example.
The details of the power conversion device 200 will be described below. The main converter circuit 201 includes a switching element and a flywheel diode (not shown), and the switching element switches to convert dc power supplied from the power supply 101 into ac power and supply the ac power to the load 300. The main conversion circuit 201 has various specific circuit configurations, but the main conversion circuit 201 of the present embodiment is a 2-level three-phase full bridge circuit and may include 6 switching elements and 6 freewheeling diodes connected in anti-parallel to the switching elements. At least one of the switching elements and the free wheel diodes of the main converter 201 is a switching element or a free wheel diode included in the semiconductor device 202 corresponding to the semiconductor device of any of embodiments 1 to 3. For 6 switching elements, two switching elements are connected in series to form upper and lower arms, and each upper and lower arm forms each phase (U-phase, V-phase, W-phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, 3 output terminals of the main converter circuit 201 are connected to the load 300.
The main converter circuit 201 includes a drive circuit (not shown) for driving each switching element, but the drive circuit may be incorporated in the semiconductor device 202 or may be provided separately from the semiconductor device 202. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201, and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, a drive signal for turning the switching element on and a drive signal for turning the switching element off are output to the control electrode of each switching element in accordance with a control signal from the control circuit 203 to be described later. When the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.
The control circuit 203 controls the switching elements of the main converter 201 so as to supply desired power to the load 300. Specifically, the time (on time) for which each switching element of the main converter circuit 201 should be brought into an on state is calculated based on the power to be supplied to the load 300. For example, the main converter circuit 201 can be controlled by PWM control in which the on time of the switching element is modulated in accordance with a voltage to be output. Then, a control command (control signal) is output to the drive circuit provided in the main conversion circuit 201 so that the switching element that is turned on at each time point outputs an on signal and the switching element that is turned off outputs an off signal. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element in accordance with the control signal.
In the power converter of the present embodiment, the semiconductor devices of embodiments 1 to 3 are applied as the semiconductor device 202 constituting the main converter 201, and therefore, it is possible to realize a power converter in which the semiconductor element can be bonded to the metal layer having higher wettability with respect to the solder than aluminum without performing pretreatment on the conductor layer of the substrate.
In the present embodiment, an example in which the present disclosure is applied to a 2-level three-phase inverter is described, but the present disclosure is not limited thereto, and can be applied to various power conversion devices. In the present embodiment, the power conversion device of 2 level is used, but the power conversion device may be a 3 level or multilevel power conversion device, and the present disclosure may be applied to a single-phase inverter when power is supplied to a single-phase load. In addition, the present disclosure can be applied to a DC/DC converter and an AC/DC converter when power is supplied to a DC load or the like.
The power conversion device to which the present disclosure is applied is not limited to the case where the load is a motor, and may be used as a power supply device for an electric discharge machine, a laser machine, an induction heating cooker, or a non-contact power supply system, or may be used as a power conditioner for a solar power generation system, a power storage system, or the like.
Embodiment 5.
Next, the structure of a semiconductor device 100 according to embodiment 5 will be described with reference to fig. 13 and 14.
In embodiment 5, as shown in fig. 13, a plurality of slits 22s may be provided in the laminate 2. Any of the 1 st metal layer 21 and the 2 nd metal layer 22 is divided into a plurality of portions by the plurality of slits 22 s. In fig. 13, the 2 nd metal layer 22 is divided into a plurality of portions 229 by a plurality of slits 22 s. This can suppress warpage of the laminate 2 at high temperature due to the difference between the thermal expansion coefficient of the 1 st metal layer 21 and the thermal expansion coefficient of the 2 nd metal layer 22. Since the warping of the laminated material 2 is suppressed, the generation of voids in the brazing filler metal 5 can be suppressed. Therefore, the bondability by the brazing filler metal 5 is improved. Although not shown, the 1 st metal layer 21 may be divided into a plurality of portions by a plurality of slits. In this case, too, warping due to the difference in thermal expansion coefficient can be suppressed.
As shown in fig. 14, any of the 1 st metal layer 21 and the 2 nd metal layer 22 is divided into a plurality of portions by a plurality of slits 22s according to the shape and size of the semiconductor element 3. This can suppress the solder 4 from spreading excessively on the upper surface of the 2 nd metal layer 22 when the semiconductor element 3 is mounted on the upper surface of the 2 nd metal layer 22. Therefore, troubles such as the solder 4 flowing out to the soldered portion adjacent to the solder 4 can be suppressed.
Embodiment 6.
Next, the structure of a semiconductor device 100 according to embodiment 6 will be described with reference to fig. 15.
In embodiment 6, as shown in fig. 15, the 1 st metal layer 21 and the 2 nd metal layer 22 of the layered material 2 and the brazing filler metal 5 constitute a clad material. That is, the 1 st metal layer 21 and the 2 nd metal layer 22 of the laminate 2 and the brazing filler metal 5 may be integrated in advance. This further improves productivity and bondability.
Even when the laminated material 2 and the brazing filler metal 5 constitute a clad material, a plurality of slits 22s may be provided in the laminated material 2. In this case, the plurality of slits 22s divide any one of the 1 st metal layer 21, the 2 nd metal layer 22, and the brazing filler metal 5 into a plurality of portions. This can suppress the occurrence of warpage in the laminate 2 at high temperatures. Thus, the bondability of the laminate 2 is improved.
The embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive. The scope of the present disclosure is shown not by the above description but by the claims, and is intended to include all modifications within the scope and meaning equivalent to the claims.

Claims (10)

1. A semiconductor device includes:
a substrate including a ceramic layer and a 1 st conductor layer laminated on the ceramic layer;
a brazing filler metal disposed on the opposite side of the ceramic layer with respect to the 1 st conductor layer;
a laminate including a 1 st metal layer and a 2 nd metal layer, the 1 st metal layer being joined to the 1 st conductor layer by the brazing material on a side opposite to the ceramic layer with respect to the 1 st conductor layer, the 2 nd metal layer being laminated on the 1 st metal layer on a side opposite to the 1 st conductor layer with respect to the 1 st metal layer;
a solder disposed on the 2 nd metal layer; and
a semiconductor element bonded to the 2 nd metal layer with the solder,
the semiconductor element is electrically connected to the substrate via the laminate material,
the material of the 1 st conductor layer and the 1 st metal layer comprises aluminum,
the 2 nd metal layer has a higher wettability for the solder than the 1 st metal layer.
2. The semiconductor device according to claim 1,
the laminate material is a clad material including the 1 st metal layer and the 2 nd metal layer.
3. The semiconductor device according to claim 1,
the 1 st metal layer and the 2 nd metal layer of the laminate material and the brazing filler metal constitute a clad material.
4. The semiconductor device according to any one of claims 1 to 3,
the laminated material further includes a 3 rd metal layer, the 3 rd metal layer being disposed between the 1 st metal layer and the 2 nd metal layer,
the material of the 3 rd metal layer comprises titanium.
5. The semiconductor device according to any one of claims 1 to 4,
the material of the 2 nd metal layer includes nickel.
6. The semiconductor device according to claim 5,
the material of the 2 nd metal layer comprises copper.
7. The semiconductor device according to any one of claims 1 to 6,
the substrate further includes a 2 nd conductor layer laminated on a side opposite to the 1 st conductor layer with respect to the ceramic layer,
the semiconductor device further includes a heat sink bonded to the 2 nd conductor layer on a side opposite to the 1 st conductor layer with respect to the 2 nd conductor layer.
8. The semiconductor device according to claim 1,
the substrate includes a plurality of substrate portions.
9. The semiconductor device according to claim 1,
any one of the 1 st metal layer and the 2 nd metal layer is divided into a plurality of portions by a plurality of slits.
10. A power conversion device is provided with:
a main conversion circuit having the semiconductor device according to any one of claims 1 to 9, the main conversion circuit converting input electric power and outputting the converted electric power; and
and a control circuit which outputs a control signal for controlling the main conversion circuit to the main conversion circuit.
CN202180008642.4A 2020-01-16 2021-01-06 Semiconductor device and power conversion device Pending CN114930528A (en)

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