WO2021139445A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

Info

Publication number
WO2021139445A1
WO2021139445A1 PCT/CN2020/132461 CN2020132461W WO2021139445A1 WO 2021139445 A1 WO2021139445 A1 WO 2021139445A1 CN 2020132461 W CN2020132461 W CN 2020132461W WO 2021139445 A1 WO2021139445 A1 WO 2021139445A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
area
array substrate
winding
shielding
Prior art date
Application number
PCT/CN2020/132461
Other languages
English (en)
French (fr)
Inventor
朱雪婧
姚远
贾溪洋
朱修剑
朱正勇
张九占
Original Assignee
昆山国显光电有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Publication of WO2021139445A1 publication Critical patent/WO2021139445A1/zh
Priority to US17/592,114 priority Critical patent/US12034012B2/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane

Definitions

  • This application belongs to the field of display technology, and in particular relates to an array substrate, a display panel, and a display device.
  • the first winding section of the wire area is arranged around a portion of the perforated area;
  • the shielding component includes at least a first shielding layer arranged on the side of the first wiring layer away from the substrate and insulated from the first signal line,
  • the first shielding layer is electrically connected to the first fixed potential terminal, and the orthographic projection of the first shielding layer on the substrate covers the orthographic projection of the first winding segment on the substrate.
  • a first shielding layer is provided on the side of the first wiring layer away from the substrate, and the first shielding layer is connected to the first fixed potential terminal, which can reduce the coupling capacitance between adjacent first winding segments. In order to reduce the crosstalk caused by the coupling capacitance in the pixel circuit, the display effect is improved.
  • FIG. 1 is a perspective view of a top structure of an array substrate according to an embodiment of the present application
  • Fig. 2 is an enlarged schematic diagram of part P of Fig. 1;
  • Figure 3 is a cross-sectional view of A-A in Figure 2;
  • Fig. 5 is an enlarged schematic diagram of part Q in Fig. 4;
  • Figure 6 is a B-B cross-sectional view in Figure 5;
  • FIG. 7 is a schematic structural diagram of a first shielding layer according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a first shielding layer according to another embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a second shielding layer according to an embodiment of the present application.
  • Figure 13 is another cross-sectional view of C-C in Figure 5;
  • FIG. 14 is a schematic structural diagram of a second shielding layer according to another embodiment of the present application.
  • FIG. 16 is a schematic top view of the structure of a display panel according to an embodiment of the present application.
  • FIG. 17 is a schematic top view of the structure of a display device according to an embodiment of the present application.
  • Fig. 18 is a D-D cross-sectional view of Fig. 17.
  • FIG. 1 is a perspective view of a top structure of an array substrate according to an embodiment of the present application, and FIG. 2 is an enlarged schematic view of the P portion in FIG. 1; FIG. 3 is an AA cross-sectional view in FIG. .
  • the array substrate 100 has a perforated area NA1, a wiring area AA1 at least partially surrounding the perforated area NA1, and a winding area DA1 located between the perforated area NA1 and the wiring area AA1.
  • the perforated area NA1 of the array substrate 100 is used to accommodate functional devices, such as image collectors, infrared sensors, proximity sensors, infrared lenses, flood light sensing elements, ambient light sensors, dot matrix projectors and other photosensitive components. It is a handset, speaker and other devices.
  • the array substrate 100 of this embodiment includes a substrate 10, a first wiring layer 30, and a shielding member 40 that are stacked in sequence.
  • the first wiring layer 30 is disposed on one side of the substrate 10, and the first wiring layer 30 includes a plurality of first signal lines 31. At least part of the first signal lines 31 of the plurality of first signal lines 31 include a first straight line segment 311 located in the wiring area AA1 and a first winding segment 312 located in the winding area DA1. The first winding segment 312 surrounds the perforation area DA1. Partial settings.
  • the shielding assembly 40 at least includes a first shielding layer 41 arranged on the side of the first wiring layer 30 away from the substrate 10 and insulated from the first signal line 31.
  • the first shielding layer 41 is electrically connected to a first fixed potential terminal.
  • the orthographic projection of the shielding layer 41 on the substrate 10 covers the orthographic projection of the first winding segment 312 on the substrate 10.
  • the fixed potential terminal in this article refers to the potential terminal on which the electrical signal does not change.
  • the first shielding layer 41 is provided on the side of the first wiring layer 30 away from the substrate 10, and the first shielding layer 41 is connected to the first fixed potential terminal, which can reduce the adjacent first windings.
  • the coupling capacitance between the line segments 312 can reduce the crosstalk caused by the coupling capacitance in the pixel circuit and improve the display effect.
  • FIG. 4 is a perspective view of a top structure of an array substrate according to another embodiment of the present application;
  • FIG. 5 is an enlarged schematic view of part Q in FIG. 4;
  • FIG. 6 is a BB cross-sectional view of FIG. .
  • the array substrate 100 further includes a second wiring layer 20, the second wiring layer 20 is disposed between the substrate 10 and the first wiring layer 30, and the second wiring layer 20 includes a plurality of second wiring layers.
  • the signal line 21. At least part of the second signal line 21 among the plurality of second signal lines 21 includes a second straight line segment 211 located in the wiring area AA1 and a second winding segment 212 located in the winding area DA1.
  • the second winding segment 212 surrounds Part of the perforated area NA1 is provided, wherein the second winding wire 212 and the first winding wire segment 312 at least partially overlap.
  • the first shielding layer 41 can further reduce the coupling capacitance generated by the overlap of the first signal line 31 and the second signal line 21 in the winding area DA1.
  • the second signal line 21 may be at least one of a scan line (scan line) or a light emission control signal line (emit line), and the first signal line 31 may be a data line (data line).
  • the scan line, the emit line, and the data line overlap with a coupling capacitor in the winding area DA1, and there is also a coupling capacitor between adjacent data lines.
  • the first shielding layer 41 is arranged on the side of the first signal line 31 away from the substrate 10 and insulated from the first signal line 31.
  • the projection of the first shielding layer 41 on the substrate 10 covers the first winding section 312 on the substrate 10
  • the orthographic projection on the bottom 10, that is, the first shielding layer 41 is located directly above the first signal line 31 in the winding area DA1 and covers the first winding section 312.
  • the first shielding layer 41 is connected to a fixed potential terminal, which can effectively weaken The coupling capacitance between the data line and the coupling capacitance in the overlap area between the data line and the scan line and the emit line.
  • the distance L between adjacent first winding segments 312 is ⁇ 3 ⁇ m. Properly increasing the adjacent distance can reduce the coupling capacitance between the adjacent first winding segments 312.
  • the second signal line 21 is a scan line and/or an emit line
  • the first signal line 31 is a data line as an example for description.
  • FIG. 7 is a schematic structural diagram of a first shielding layer provided by an embodiment of the present application
  • FIG. 8 is a C-C cross-sectional view in FIG. 5.
  • the first shielding layer 41 is arranged in the winding area DA1, and the first shielding layer 41 is a ring-shaped layer structure arranged around the perforated area NA1.
  • the first shielding layer 41 has a ring-shaped layer structure, which can effectively cover each first winding section 312 and simplify the manufacturing process.
  • Figure 9 is a schematic structural diagram of the first shielding layer provided by another embodiment of the present application;
  • Figure 10 is another CC in Figure 5 Sectional view.
  • the first shielding layer 41 is disposed in the winding area DA1.
  • the first shielding layer 41 includes a plurality of first shielding wires 411.
  • the orthographic projection of each first shielding wire 411 on the substrate 10 covers the first winding segment 312 on the substrate 10 Orthographic projection on. Further, the orthographic projection of the first shielding wire 411 on the substrate 10 coincides with the orthographic projection of the first winding segment 312 on the substrate 10.
  • the patterned first shielding layer 41 is used, and the first shielding wire 411 is only provided above the first winding section 312, which can save cost.
  • each of the first shielding wires 411 can be directly connected to the first fixed potential terminal, or after each first shielding wire 411 is short-circuited through the first short-circuit wire, then connected to the first fixed potential terminal through the first short-circuit wire. Potential terminal.
  • FIG. 11 is another B-B cross-sectional view in FIG. 5.
  • the shielding assembly 40 further includes a second shielding layer 42 arranged between the second wiring layer 20 and the first wiring layer 30.
  • the second shielding layer 42 is insulated from the second signal line 21 and the first signal line 31.
  • the second shielding layer 42 is connected to the second fixed potential terminal.
  • the orthographic projection of the second shielding layer 42 on the substrate 10 covers the orthographic projection of the second winding segment 212 on the substrate.
  • a second shielding layer 42 is provided between the second signal line 21 and the first signal line 31.
  • the second shielding layer 42 is connected to the second fixed potential terminal, which can reduce the relationship between the second signal line 21 and the first signal line.
  • the coupling capacitance generated by the overlapping of the wire 31 in the winding area DA1 can reduce the crosstalk caused by the coupling capacitance in the pixel circuit and improve the display effect.
  • the second shielding layer 42 is disposed in the wiring area AA1 and the winding area DA1, and the orthographic projection of the second shielding layer 42 on the substrate 10 also covers the second straight section 211 on the substrate 10. Orthographic projection.
  • the second shielding layer 42 covers the second signal line 21 of the wiring area AA1 and the winding area DA1, which can further improve the shielding effect and reduce the coupling capacitance between the second signal line 21 and the first signal line 31.
  • FIG. 12 is a schematic structural diagram of the second shielding layer according to an embodiment of the present application; FIG. 13 is another cross-sectional view of C-C in FIG. 5.
  • the second shielding layer 42 is arranged in the winding area DA1, and the second shielding layer 42 may be a ring-shaped layer structure arranged around the perforated area NA1.
  • the second shielding layer 42 has a ring-shaped layer structure, which can effectively cover each second winding section 212 and simplify the manufacturing process.
  • the first shielding layer 41 has a ring structure as an example for description. It can be understood that the first shielding layer 41 may also be the one that includes a plurality of first shielding lines 411 in the above-mentioned embodiment. structure.
  • FIG. 14 is a schematic structural diagram of the second shielding layer according to another embodiment of the present application; FIG. 15 is another cross-sectional view of C-C in FIG. 5.
  • the second shielding layer 42 is disposed in the winding area DA1.
  • the second shielding layer 42 includes a plurality of second shielding wires 421.
  • the orthographic projection of each second shielding wire 421 on the substrate 10 covers the second winding section 421 on the substrate 10. Orthographic projection on. Further, the orthographic projection of the second shielding wire 421 on the substrate 10 coincides with the orthographic projection of the second winding segment 212 on the substrate 10.
  • the patterned second shielding layer 42 is used, and the second shielding wire 421 is only provided directly above the second winding section 212, which can save cost.
  • each second shielding wire 421 can be directly connected to the second fixed potential terminal, or after each second shielding wire 421 is short-circuited through a second short-circuit wire, it is connected to the second fixed potential terminal through a second short-circuit wire. Potential terminal.
  • the first shielding layer 41 has a ring structure as an example for description. It can be understood that the first shielding layer 41 may also be the one that includes a plurality of first shielding lines 411 in the above-mentioned embodiment. structure.
  • the array substrate 100 further includes a power voltage signal line, a reference voltage signal line, and a low-level signal line.
  • the first shielding layer 41 and the second shielding layer 42 are electrically connected to one of a power voltage signal line, a reference voltage signal line, and a low-level signal line.
  • both the first shielding layer 41 and the second shielding layer 42 are electrically connected to the power supply voltage signal line.
  • the first shielding layer 41 and the second shielding layer 42 are electrically connected to one of the power supply voltage signal line, the reference voltage signal line, and the low-level signal line, which can also reduce the corresponding power supply voltage signal.
  • the impedance of the signal line, reference voltage signal line and low-level signal line improves the signal transmission effect.
  • the second straight section 211 and the second winding section 212 of the second signal line 21 may be arranged in the same layer, or may be arranged in different layers.
  • the first straight section 311 and the first winding section 312 of the first signal line 31 may be arranged in the same layer, or may be arranged in different layers.
  • the second winding section 212 and the first winding section 312 exactly overlapped in the direction perpendicular to the array substrate 100 are taken as an example for description in FIGS. 8, 10, 14, and 15. It can be understood that the second The winding segment 212 and the first winding segment 312 may partially overlap in the direction perpendicular to the array substrate 100.
  • the wiring area AA1 of the array substrate 100 of this embodiment has multiple pixel circuits, and the pixel circuits may include multiple thin film transistors, capacitors, and other structures.
  • the pixel circuit may specifically include a 7T1C or 2T1C circuit structure, where "T” refers to a thin film transistor, "C” refers to a capacitor, and the number refers to the number of thin film transistors or capacitors.
  • T refers to a thin film transistor
  • C refers to a capacitor
  • the number refers to the number of thin film transistors or capacitors.
  • other circuit structures can also be used, which is not limited in this application.
  • the array substrate 100 in the embodiment of the present application may include a plurality of pixel circuits distributed in an array.
  • the wiring area AA1 includes a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, and a second insulating layer stacked on the substrate 10 in sequence.
  • Three metal layers are used to form structures such as thin film transistors and capacitors.
  • a first electrode layer is also provided on the third metal layer.
  • the second signal lines 21 of this embodiment may be provided in the same layer as the first metal layer, and the first signal lines 31 may be provided in the same layer as the third metal layer, and the second shielding layer 42 may be provided in the same layer as the second metal layer.
  • the first shielding layer 41 and the first electrode layer are provided in the same layer. In this embodiment, the first shielding layer 41 and the second shielding layer 42 are both arranged in the same layer as the existing film layer of the array substrate 100, and there is no need to add a new film layer, which does not increase the manufacturing process difficulty of the array substrate 100.
  • a fourth metal layer may be provided between the third metal layer and the first electrode layer, wherein the power supply voltage signal line may be provided on the third metal layer and the fourth metal layer, To reduce the impedance of the voltage power signal line.
  • part of the plurality of second signal lines 21 may be arranged in the same layer as the first metal layer, and another part may be arranged in the same layer as the second metal layer.
  • one of the scan line and the emit line may be arranged in the same layer as the first metal layer.
  • the layer is arranged in the same layer, and the other is arranged in the same layer as the second metal layer.
  • the second shielding layer 42 can be provided in the same layer as the third metal layer, and in the winding area DA1, the first winding segment 312 can be provided in the same layer as the fourth metal layer.
  • the first shielding layer 41 is provided in the same layer as the first electrode layer.
  • both the first shielding layer 41 and the second shielding layer 42 are arranged in the same layer as the existing film layer of the array substrate 100, and there is no need to add a new film layer, which does not increase the manufacturing process difficulty of the array substrate 100.
  • FIG. 16 is a schematic structural diagram of a display panel according to an embodiment of the application.
  • the display panel 200 has a display area AA2 and a non-display area NA2.
  • the display panel 200 includes the array substrate 100 of any of the above embodiments, wherein the wiring area AA1 and the winding area DA1 of the array substrate 100 are arranged corresponding to the display area AA2 of the display panel 200 ,
  • the perforated area NA1 of the array substrate 100 is set corresponding to the non-display area NA2 of the display panel 200.
  • the display panel 200 of this embodiment includes the array substrate 100 of any of the above embodiments, it has the beneficial effects of the array substrate 100 of any of the above embodiments, which will not be repeated here.
  • FIG. 17 is a schematic top view of a display device provided by an embodiment of the present application.
  • FIG. 18 is a DD in FIG. Sectional view.
  • the display device 300 of the embodiment of the present application includes the display panel 200 of any of the foregoing embodiments.
  • the display device 300 of this embodiment further includes a functional device 310 corresponding to the non-display area NA2 of the display panel 200.
  • the functional device 310 may be an image acquisition device for acquiring external image information.
  • the functional device 310 is a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image acquisition device.
  • the functional device 310 may also be a charge-coupled device (CCD).
  • the functional device 310 may also be an infrared sensor, a proximity sensor, an infrared lens, a flood light sensor, an ambient light sensor, and a dot matrix projection. Light sensors such as devices.
  • the display device 300 may also integrate other components in the non-display area NA2 of the display panel 200, such as a receiver, a speaker, and the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板（100）、显示面板（200）及显示装置（300）。阵列基板（100）具有打孔区（NA1）、至少部分围绕打孔区（NA1）的布线区（AA1）以及位于打孔区（NA1）和布线区（AA1）之间的绕线区（DA1），阵列基板（100）包括：衬底（10）和设置于衬底（10）上的第一布线层（30），还包括屏蔽组件（40），屏蔽组件（40）至少包括设置于第一布线层（30）背离衬底（10）一侧且与第一布线层（30）中的第一信号线（31）绝缘设置的第一屏蔽层（41），第一屏蔽层（41）电连接至第一固定电位端，第一屏蔽层（41）在衬底（10）上的正投影覆盖第一信号线（31）的第一绕线段（312）在衬底（10）上的正投影，从而能够降低相邻的第一绕线段（312）之间的耦合电容，以降低像素电路中的耦合电容引起的串扰，改善显示效果。

Description

阵列基板、显示面板及显示装置
相关申请的交叉引用
本申请要求享有于2020年01月08日提交的名称为“阵列基板、显示面板及显示装置”的中国专利申请第202010017580.0号的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请属于显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
背景技术
随着电子设备的发展，用户对屏占比的要求越来越高，通常在显示面板的显示区内的部分区域打孔以集成摄像头等感光组件，在该集成摄像头或其他感光组件的周侧的信号线需要绕行，多条绕行的信号线密集且部分交叠产生电容耦合引起串扰，影响显示效果。
发明内容
本申请实施例提供了一种阵列基板、显示面板及显示装置，旨在减小信号线之间由于电容耦合产生的串扰，提升显示效果。
第一方面，本申请提供一种阵列基板，包括：具有打孔区、至少部分围绕打孔区的布线区以及位于打孔区和布线区之间的绕线区，阵列基板包括：衬底；第一布线层，设置于衬底的一侧，第一布线层包括多条第一信号线，多条第一信号线中至少部分第一信号线包括位于布线区的第一直线段和位于绕线区的第一绕线段，第一绕线段围绕打孔区的部分设置；屏蔽组件，至少包括设置于第一布线层背离衬底一侧且与第一信号线绝缘设置的第一屏蔽层，第一屏蔽层电连接至第一固定电位端，第一屏蔽层在衬底上的正投影覆盖第一绕线段在衬底上的正投影。
第二方面，本发明提供一种显示面板，具有显示区和非显示区，显示面板包括上述任一实施例的阵列基板，其中，布线区和绕线区对应显示区设置，打孔区对应非显示区设置。
第三方面，本申请提供一种显示装置，包括上述第二方面的显示面板。
本申请实施例中，在第一布线层背离衬底的一侧设置第一屏蔽层，第一屏蔽层连接至第一固定电位端，能够降低相邻的第一绕线段之间的耦合电容，以降低像素电路中的耦合电容引起的串扰，改善显示效果。
附图说明
图1是本申请一实施例的阵列基板的俯视结构透视图；
图2是图1的P部放大示意图；
图3是图2中的A-A剖视图；
图4是本申请另一实施例的阵列基板的俯视结构透视图；
图5是图4中的Q部放大示意图；
图6是图5中的一种B-B剖视图；
图7是本申请一实施例的第一屏蔽层的结构示意图；
图8是图5中的一种C-C剖视图；
图9是本申请另一实施例的第一屏蔽层的结构示意图；
图10是图5中的另一种C-C剖视图；
图11是图5中的另一种B-B剖视图；
图12是本申请一实施例的第二屏蔽层的结构示意图；
图13是图5中的又一种C-C剖视图；
图14是本申请另一实施例的第二屏蔽层的结构示意图；
图15是图5中的再一种C-C剖视图；
图16是本申请一实施例的显示面板的俯视结构示意图；
图17是本申请一实施例的显示装置的俯视结构示意图；
图18是图17中的一种D-D剖视图。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例，为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施例，对本申请进行进一步详细描述。应理解，此处所描述的具体实施例仅意在解释本申请，而不是限定本申请。对于本领域技术人员来说，本申请可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示例来提供对本申请更好的理解。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
下面结合图1至图18对本申请实施例的阵列基板、显示面板及显示装置进行详细描述。为了清楚的示出与本申请相关的结构，图中对一些公知的结构进行了隐藏或透明绘制。请参阅图1至图3所示，图1是本申请一实施例的阵列基板的俯视结构透视图，图2是图1中的P部放大示意图；图3是图2中的一种A-A剖视图。阵列基板100具有打孔区NA1、至少部分围绕打孔区NA1的布线区AA1以及位于打孔区NA1和布线区AA1之间的绕线区DA1。阵列基板100的打孔区NA1用于容纳功能器件，功能器件例如是图像采集器、红外传感器、接近传感器、红外镜头、泛光感应元件、环境光传感器以及点阵投影器等感光组件，还可以是听筒、扬声器等器件。
本实施例的阵列基板100包括依次层叠设置的衬底10、第一布线层30和屏蔽组件40。
第一布线层30设置于衬底10的一侧，第一布线层30包括多条第一信号线31。多条第一信号线31中至少部分第一信号线31包括位于布线区AA1的第一直线段311和位于绕线区DA1的第一绕线段312，第一绕线段312围绕打孔区DA1的部分设置。
屏蔽组件40至少包括设置于第一布线层30背离衬底10一侧且与第一信号线31绝缘设置的第一屏蔽层41，第一屏蔽层41电连接至第一固定电位端，第一屏蔽层41在衬底10上的正投影覆盖第一绕线段312在衬底10上的正投影。本文中的固定电位端是指电信号不发生变化的电位端。
根据本实施例的阵列基板100，在第一布线层30背离衬底10的一侧 设置第一屏蔽层41，第一屏蔽层41连接至第一固定电位端，能够降低相邻的第一绕线段312之间的耦合电容，以降低像素电路中的耦合电容引起的串扰，改善显示效果。
请参阅图4至图6所示，图4是本申请另一实施例的阵列基板的俯视结构透视图；图5是图4中的Q部放大示意图；图6是图5的一种B-B剖视图。在另一些可选的实施例中，阵列基板100进一步包括第二布线层20，第二布线层20设置于衬底10与第一布线层30之间，第二布线层20包括多条第二信号线21，多条第二信号线21中至少部分第二信号线21包括位于布线区AA1与的第二直线段211和位于绕线区DA1的第二绕线段212，第二绕线段212围绕打孔区NA1的部分设置，其中，第二绕线212与第一绕线段312至少部分交叠。第一屏蔽层41进一步可以降低第一信号线31和第二信号线21在绕线区DA1交叠产生的耦合电容。
在一些实施例中，第二信号线21可以为扫描线(scan线)或发光控制信号线(emit线)中的至少一种，第一信号线31可以为数据线(data线)。scan线、emit线与data线在绕线区DA1交叠存在耦合电容，相邻的data线之间也会存在耦合电容。当任一信号线的电压发生变化时，会引起相邻的data线信号电压改变，从而影响显示效果。而第一屏蔽层41设置于第一信号线31背离衬底10的一侧且与第一信号线31绝缘设置，第一屏蔽层41在衬底10上的投影覆盖第一绕线段312在衬底10上的正投影，也即第一屏蔽层41在绕线区DA1位于第一信号线31正上方且覆盖第一绕线段312，第一屏蔽层41连接至固定电位端，能够有效的减弱data线之间的耦合电容以及data线与scan线、emit线交叠区的耦合电容。
在一些可选的实施例中，相邻的第一绕线段312之间的距离L≥3μm。适当的增大相邻的间距，可以减小相邻的第一绕线段312之间的耦合电容。
下述实施例中，以第二信号线21为scan线和/或emit线，第一信号线31为data线为例进行说明。
在一些可选的实施例中，请参阅图7和图8所示，图7是本申请一实施例提供的第一屏蔽层的结构示意图；图8是图5中的一种C-C剖视图。第一屏蔽层41设置于绕线区DA1，第一屏蔽层41为环绕打孔区NA1设 置的环状层结构。本实施例中，第一屏蔽层41为环状层结构，能够有效的覆盖各第一绕线段312，且简化制备工艺。
在另一些可选的实施例中，请参阅图9和图10所示，图9是本申请另一实施例提供的第一屏蔽层的结构示意图；图10是图5中的另一种C-C剖视图。第一屏蔽层41设置于绕线区DA1，第一屏蔽层41包括多条第一屏蔽线411，各第一屏蔽线411在衬底10上的正投影覆盖第一绕线段312在衬底10上的正投影。进一步的，第一屏蔽线411在衬底10上的正投影与第一绕线段312在衬底10上的正投影重合。本实施例中，采用图案化的第一屏蔽层41，仅在第一绕线段312上方设置第一屏蔽线411，能够节省成本。本实施例中，各第一屏蔽线411可以均直接连接至第一固定电位端，还可以通过第一短路线将各第一屏蔽线411短接后，通过第一短路线连接至第一固定电位端。
在一些可选的实施例中，请参阅图11所示，图11是图5中的另一种B-B剖视图。屏蔽组件40还包括设置于第二布线层20与第一布线层30之间的第二屏蔽层42，第二屏蔽层42与第二信号线21、第一信号线31绝缘设置。第二屏蔽层42连接至第二固定电位端。第二屏蔽层42在衬底10上的正投影覆盖第二绕线段212在衬底上的正投影。本实施例中，在第二信号线21与第一信号线31之间设置第二屏蔽层42，第二屏蔽层42连接至第二固定电位端，能够降低第二信号线21与第一信号线31在绕线区DA1交叠产生的耦合电容，以降低像素电路中的耦合电容引起的串扰，改善显示效果。
进一步的，在一些实施例中，第二屏蔽层42设置于布线区AA1与绕线区DA1，第二屏蔽层42在衬底10上的正投影还覆盖第二直线段211在衬底10上的正投影。本实施例中，第二屏蔽层42覆盖布线区AA1与绕线区DA1的第二信号线21，能够进一步提升屏蔽效果，降低第二信号线21与第一信号线31之间的耦合电容。
进一步的，在另一些实施例中，请参阅图12和图13所示，图12是本申请一实施例的第二屏蔽层的结构示意图；图13是图5中的又一种C-C剖视图。第二屏蔽层42设置于绕线区DA1，第二屏蔽层42可以为绕打孔 区NA1设置的环状层结构。本实施例中，第二屏蔽层42为环状层结构，能够有效的覆盖各第二绕线段212，且简化制备工艺。本实施例中，图13中以第一屏蔽层41为环状结构为例进行说明，可以理解的是，第一屏蔽层41还可以为上述实施例中的包括多条第一屏蔽线411的结构。
进一步的，在一些实施例中，请参阅图14和图15所示，图14是本申请另一实施例的第二屏蔽层的结构示意图；图15是图5中的再一种C-C剖视图。第二屏蔽层42设置于绕线区DA1，第二屏蔽层42包括多条第二屏蔽线421，各第二屏蔽线421在衬底10上的正投影覆盖第二绕线段421在衬底10上的正投影。进一步的，第二屏蔽线421在衬底10上的正投影与第二绕线段212在衬底10上的正投影重合。本实施例中，采用图案化的第二屏蔽层42，仅在第二绕线段212正上方设置第二屏蔽线421，能够节省成本。本实施例中，各第二屏蔽线421可以均直接连接至第二固定电位端，还可以通过第二短路线将各第二屏蔽线421短接后，通过第二短路线连接至第二固定电位端。本实施例中，图15中以第一屏蔽层41为环状结构为例进行说明，可以理解的是，第一屏蔽层41还可以为上述实施例中的包括多条第一屏蔽线411的结构。
在一些可选的实施例中，阵列基板100还包括电源电压信号线、参考电压信号线和低电平信号线。第一屏蔽层41与第二屏蔽层42电连接至电源电压信号线、参考电压信号线和低电平信号线中的其中一者。在一具体实施例中，第一屏蔽层41和第二屏蔽层42均电连接至电源电压信号线。本实施例中，将第一屏蔽层41、第二屏蔽层42电连接至电源电压信号线、参考电压信号线和低电平信号线中的其中一者，还可以减小对应的电源电压信号线、参考电压信号线和低电平信号线的阻抗，提高信号传输效果。
在一些可选的实施例中，第二信号线21的第二直线段211与第二绕线段212可以同层设置，也可以异层设置。第一信号线31的第一直线段311与第一绕线段312可以同层设置，也可以异层设置。
上述实施例中，图8、10、14、15中以第二绕线段212与第一绕线段312在垂直于阵列基板100方向上恰好交叠设置为例进行说明，可以理解的是，第二绕线段212与第一绕线段312在垂直于阵列基板100方向上可 以部分交叠。
以下以一具体实施例对第二信号线21、第一信号线31、第一屏蔽层41、第二屏蔽层42与像素电路各层的结构关系进行说明。本实施例的阵列基板100的布线区AA1具有多个像素电路，像素电路可以包括多个薄膜晶体管、电容等结构。像素电路具体可以包括7T1C或2T1C的电路结构，此处“T”是指薄膜晶体管，“C”是指电容，数字是指薄膜晶体管或电容的数量。当然，也可以采用其他电路结构，对此本申请不做限制。
因此，可以理解的是，本申请实施例中的阵列基板100可包含呈阵列分布的多个像素电路。
本申请实施例的阵列基板100，布线区AA1包括依次层叠设置于衬底10上半导体层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层、第三金属层，以用于形成薄膜晶体管与电容等结构。在第三金属层上还设置有第一电极层。本实施例的第二信号线21可以均与第一金属层同层设置，第一信号线31可以均与第三金属层同层设置，则第二屏蔽层42可以与第二金属层同层设置，第一屏蔽层41与第一电极层同层设置。则本实施例中，第一屏蔽层41与第二屏蔽层42均与阵列基板100的现有膜层同层设置，不用新增膜层，不会增加阵列基板100制作的工艺难度。
在另一些可选的实施例中，在第三金属层与第一电极层之间还可以设置有第四金属层，其中，电源电压信号线可以设置于第三金属层和第四金属层，以减小电压电源信号线的阻抗。则本实施例中，多条第二信号线21中可以部分与第一金属层同层设置，另一部分与第二金属层同层设置，例如，scan线和emit线其中一者与第一金属层同层设置，另一者与第二金属层同层设置。第二屏蔽层42可以与第三金属层同层设置，而在绕线区DA1，第一绕线段312可以与第四金属层同层设置。第一屏蔽层41与第一电极层同层设置。同样的，本实施例中，第一屏蔽层41与第二屏蔽层42均与阵列基板100的现有膜层同层设置，不用新增膜层，不会增加阵列基板100制作的工艺难度。
本申请还提供了一种显示面板，请参阅图16所示，图16是申请一实 施例的显示面板的结构示意图。显示面板200具有显示区AA2和非显示区NA2，显示面板200包括上述任一实施例的阵列基板100，其中，阵列基板100的布线区AA1和绕线区DA1对应显示面板200的显示区AA2设置，阵列基板100的打孔区NA1对应显示面板200的非显示区NA2设置。
由于本实施例的显示面板200包括上述任一实施例的阵列基板100，因此，具有上述任一实施例的阵列基板100的有益效果，在此不再赘述。
本申请实施例还提供了一种显示装置300，请参阅图17和图18所示，图17是本申请一实施例提供的显示装置的俯视结构示意图，图18是图17中的一种D-D剖视图。本申请实施例的显示装置300包括上述任一实施例的显示面板200。本实施例的显示装置300还包括功能器件310，功能器件310与显示面板200的非显示区NA2对应。
功能器件310可以是图像采集装置，用于采集外部图像信息。本实施例中，功能器件310为互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)图像采集装置，在其它一些实施例中，功能器件310也可以是电荷耦合器件(Charge-coupled Device，CCD)图像采集装置等其它形式的图像采集装置。可以理解的是，功能器件310可以不限于是图像采集装置，例如在一些实施例中，功能器件310也可以是红外传感器、接近传感器、红外镜头、泛光感应元件、环境光传感器以及点阵投影器等光传感器。此外，显示装置300在显示面板200的非显示区NA2还可以集成其它部件，例如是听筒、扬声器等。
依照本申请如上文所述的实施例，这些实施例并没有详尽叙述所有的细节，也不限制该申请仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本申请的原理和实际应用，从而使所属技术领域技术人员能很好地利用本申请以及在本申请基础上的修改使用。本申请仅受权利要求书及其全部范围和等效物的限制。

Claims (20)

  1. 一种阵列基板，具有打孔区、至少部分围绕所述打孔区的布线区以及位于所述打孔区和所述布线区之间的绕线区，所述阵列基板包括：
    衬底；
    第一布线层，设置于所述衬底的一侧，所述第一布线层包括多条第一信号线，多条所述第一信号线中至少部分所述第一信号线包括位于所述布线区的第一直线段和位于所述绕线区的第一绕线段，所述第一绕线段围绕所述打孔区的部分设置；
    屏蔽组件，至少包括设置于所述第一布线层背离所述衬底一侧且与所述第一信号线绝缘设置的第一屏蔽层，所述第一屏蔽层电连接至第一固定电位端，所述第一屏蔽层在所述衬底上的正投影覆盖所述第一绕线段在所述衬底上的正投影。
  2. 根据权利要求1所述的阵列基板，其中，所述第一屏蔽层设置于所述绕线区，所述第一屏蔽层为环绕所述打孔区设置的环状层结构。
  3. 根据权利要求1所述的阵列基板，其中，所述第一屏蔽层设置于所述绕线区，所述第一屏蔽层包括多条第一屏蔽线，所述第一屏蔽线在所述衬底上的正投影与所述第一绕线段在所述衬底上的正投影重合。
  4. 根据权利要求1所述的阵列基板，其中，所述阵列基板进一步包括第二布线层，所述第二布线层设置于所述衬底与所述第一布线层之间，所述第二布线层包括多条第二信号线，多条所述第二信号线中至少部分所述第二信号线包括位于所述布线区的第二直线段和位于所述绕线区的第二绕线段，所述第二绕线段围绕所述打孔区的部分设置，其中，所述第二绕线段与所述第一绕线段至少部分交叠。
  5. 根据权利要求4所述的阵列基板，其中，所述屏蔽组件进一步包括 设置于所述第一布线层与所述第二布线层之间的第二屏蔽层，所述第一屏蔽层与所述第一信号线、第二信号线绝缘设置，所述第二屏蔽层电连接至第二固定电位端，所述第二屏蔽层在所述衬底上的正投影覆盖所述第二绕线段在所述衬底上的正投影。
  6. 根据权利要求4所述的阵列基板，其中，所述第二信号线为扫描线或发光控制信号线中的至少一种，所述第一信号线为数据线。
  7. 根据权利要求4所述的阵列基板，其中，所述第二屏蔽层设置于所述布线区与所述绕线区，所述第二屏蔽层在所述衬底上的正投影还覆盖所述第二直线段在所述衬底上的正投影。
  8. 根据权利要求4所述的阵列基板，其中，所述第二屏蔽层设置于所述绕线区，所述第二屏蔽层为绕所述打孔区设置的环状层结构。
  9. 根据权利要求4所述的阵列基板，其中，所述第二屏蔽层设置于所述绕线区，所述第二屏蔽层包括多条第二屏蔽线，所述第二屏蔽线在所述衬底上的正投影与所述第二绕线段在所述衬底上的正投影重合。
  10. 根据权利要求4所述的阵列基板，其中，所述阵列基板还包括电源电压信号线、参考电压信号线和低电平信号线；
    所述第一屏蔽层与所述第二屏蔽层电连接至所述电源电压信号线、参考电压信号线和低电平信号线中的其中一者。
  11. 根据权利要求4所述的阵列基板，其中，所述第一直线段与所述第一绕线段同层或异层设置；
  12. 根据权利要求4所述的阵列基板，其中，所述第二直线段与所述第二绕线段同层或异层设置。
  13. 根据权利要求4所述的阵列基板，其中，所述第二绕线段与所述第一绕线段在垂直于所述阵列基板的方向上至少部分交叠。
  14. 根据权利要求4所述的阵列基板，其中，所述布线区包括依次层叠设置于衬底上的半导体层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层、第一电极层、第三金属层，所述第一信号线与所述第三金属层同层设置，所述第一屏蔽层与第一电极层同层设置。
  15. 根据权利要求14所述的阵列基板，其中，所述第二信号线与所述 第一金属层同层设置，所述第二屏蔽层与第二金属层同层设置。
  16. 根据权利要求14所述的阵列基板，其中，所述阵列基板还包括电源电压信号线，所述第三金属层与所述第一电极层之间设置有第四金属层，所述电源电压信号线设置于所述第三金属层和所述第四金属层。
  17. 根据权利要求15所述的阵列基板，其中，所述第二信号线中一部分与所述第一金属层同层设置，另一部分与所述第二金属层同层设置，第二屏蔽层与第三金属层同层设置，所述第一绕线段与第四金属层同层设置。
  18. 根据权利要求1所述的阵列基板，其中，相邻的所述第一绕线段的间距L满足：L≥3μm。
  19. 一种显示面板，具有显示区和非显示区，所述显示面板包括如权利要求1至18任一项所述的阵列基板，其中，所述布线区和所述绕线区对应所述显示区设置，所述打孔区对应所述非显示区设置。
  20. 一种显示装置，包括如权利要求19所述的显示面板。
PCT/CN2020/132461 2020-01-08 2020-11-27 阵列基板、显示面板及显示装置 WO2021139445A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/592,114 US12034012B2 (en) 2020-01-08 2022-02-03 Array substrate, display panel and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010017580.0A CN111081141B (zh) 2020-01-08 2020-01-08 阵列基板、显示面板及显示装置
CN202010017580.0 2020-01-08

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/592,114 Continuation US12034012B2 (en) 2020-01-08 2022-02-03 Array substrate, display panel and display apparatus

Publications (1)

Publication Number Publication Date
WO2021139445A1 true WO2021139445A1 (zh) 2021-07-15

Family

ID=70322640

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/132461 WO2021139445A1 (zh) 2020-01-08 2020-11-27 阵列基板、显示面板及显示装置

Country Status (3)

Country Link
US (1) US12034012B2 (zh)
CN (1) CN111081141B (zh)
WO (1) WO2021139445A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111081141B (zh) 2020-01-08 2022-04-26 昆山国显光电有限公司 阵列基板、显示面板及显示装置
CN113838382B (zh) 2020-06-05 2023-01-31 京东方科技集团股份有限公司 显示基板以及显示装置
CN111951671A (zh) * 2020-08-14 2020-11-17 武汉华星光电技术有限公司 显示装置和显示装置的制作方法
CN114203759A (zh) * 2020-09-02 2022-03-18 华为技术有限公司 一种显示面板及终端设备
CN114442354B (zh) * 2020-10-30 2023-10-20 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN112599580B (zh) * 2020-12-14 2023-11-24 合肥维信诺科技有限公司 显示面板及显示装置
CN113571567B (zh) * 2021-07-26 2024-01-05 云谷（固安）科技有限公司 一种显示面板和显示装置
CN113709975B (zh) * 2021-08-26 2023-05-02 合肥京东方光电科技有限公司 电路板组件、显示模组和显示装置
CN113823642B (zh) * 2021-09-15 2024-01-19 合肥维信诺科技有限公司 阵列基板、显示面板及显示装置
WO2023065296A1 (zh) * 2021-10-22 2023-04-27 京东方科技集团股份有限公司 显示基板及电子装置
US20230133301A1 (en) * 2022-06-30 2023-05-04 Xiamen Tianma Display Technology Co., Ltd. Display panel and display device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003115912A (ja) * 2001-10-09 2003-04-18 Nec Saitama Ltd 携帯型無線通信装置
CN109119447A (zh) * 2018-08-29 2019-01-01 武汉天马微电子有限公司 一种显示面板及显示装置
CN109389907A (zh) * 2018-12-11 2019-02-26 厦门天马微电子有限公司 显示面板及显示装置
CN110299386A (zh) * 2019-06-20 2019-10-01 昆山国显光电有限公司 显示面板以及显示装置
CN110610667A (zh) * 2019-10-28 2019-12-24 武汉天马微电子有限公司 一种显示面板和显示装置
CN111081141A (zh) * 2020-01-08 2020-04-28 昆山国显光电有限公司 阵列基板、显示面板及显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6131662B2 (ja) * 2013-03-22 2017-05-24 セイコーエプソン株式会社 表示装置及び電子機器
KR102613853B1 (ko) 2016-12-19 2023-12-18 엘지디스플레이 주식회사 유기발광 다이오드 표시장치
CN108154842B (zh) * 2018-01-04 2020-05-01 武汉天马微电子有限公司 一种有机发光显示面板和电子设备
CN108459445B (zh) * 2018-03-30 2021-05-18 上海天马微电子有限公司 一种液晶显示面板、显示装置及液晶显示面板的制备方法
US11521991B2 (en) * 2019-01-28 2022-12-06 Lg Electronics Inc. Display module and mobile terminal
CN110244873B (zh) * 2019-06-05 2022-10-04 武汉天马微电子有限公司 触控显示面板和显示装置
CN110299384B (zh) * 2019-06-10 2021-09-07 昆山国显光电有限公司 一种显示面板
CN110208994B (zh) 2019-06-28 2021-08-31 厦门天马微电子有限公司 一种液晶显示面板及一种显示装置
CN113838382B (zh) * 2020-06-05 2023-01-31 京东方科技集团股份有限公司 显示基板以及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003115912A (ja) * 2001-10-09 2003-04-18 Nec Saitama Ltd 携帯型無線通信装置
CN109119447A (zh) * 2018-08-29 2019-01-01 武汉天马微电子有限公司 一种显示面板及显示装置
CN109389907A (zh) * 2018-12-11 2019-02-26 厦门天马微电子有限公司 显示面板及显示装置
CN110299386A (zh) * 2019-06-20 2019-10-01 昆山国显光电有限公司 显示面板以及显示装置
CN110610667A (zh) * 2019-10-28 2019-12-24 武汉天马微电子有限公司 一种显示面板和显示装置
CN111081141A (zh) * 2020-01-08 2020-04-28 昆山国显光电有限公司 阵列基板、显示面板及显示装置

Also Published As

Publication number Publication date
CN111081141B (zh) 2022-04-26
US20220157860A1 (en) 2022-05-19
CN111081141A (zh) 2020-04-28
US12034012B2 (en) 2024-07-09

Similar Documents

Publication Publication Date Title
WO2021139445A1 (zh) 阵列基板、显示面板及显示装置
WO2021142964A1 (zh) 一种显示面板及显示装置
CN111969027B (zh) 显示面板以及显示装置
US20210399079A1 (en) Display Substrate and Display Device
CN111785853B (zh) 一种显示面板及显示装置
US20230337492A1 (en) Array substrate, display panel and display device
US20230343794A1 (en) Array substrate, display panel, and display device
WO2022193712A1 (zh) 显示面板、显示装置
CN113410257B (zh) 阵列基板、显示面板及显示装置
CN111312152B (zh) 显示面板及显示装置
US11690256B2 (en) Organic light emitting diode display panel for improving light transmittance and organic light emitting diode display device
CN114930544A (zh) 显示面板、显示装置及终端设备
WO2023065672A1 (zh) 显示面板及显示装置
WO2020177209A1 (zh) 阵列基板的制作方法及阵列基板
CN113096550B (zh) 显示模组和显示设备
CN113488601A (zh) 透光显示模组、显示面板及透光显示模组的制备方法
CN110310572B (zh) 一种显示面板及显示装置
US20230133301A1 (en) Display panel and display device
CN111430429B (zh) 显示面板及显示装置
CN115148776B (zh) 一种显示面板及显示装置
US11798469B1 (en) Display panel and display device
US11869411B2 (en) Display substrate, manufacturing method thereof, and display device
WO2024178673A1 (zh) 像素驱动电路、显示面板及显示装置
WO2023159602A9 (zh) 显示面板、显示装置
WO2022236765A9 (zh) 显示面板、显示装置及终端设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20912985

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20912985

Country of ref document: EP

Kind code of ref document: A1