WO2023065296A1 - 显示基板及电子装置 - Google Patents

显示基板及电子装置 Download PDF

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Publication number
WO2023065296A1
WO2023065296A1 PCT/CN2021/125663 CN2021125663W WO2023065296A1 WO 2023065296 A1 WO2023065296 A1 WO 2023065296A1 CN 2021125663 W CN2021125663 W CN 2021125663W WO 2023065296 A1 WO2023065296 A1 WO 2023065296A1
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WIPO (PCT)
Prior art keywords
area
line segment
sub
signal line
line
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Application number
PCT/CN2021/125663
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English (en)
French (fr)
Inventor
田学伟
方飞
卢辉
王伟
曲峰
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/125663 priority Critical patent/WO2023065296A1/zh
Priority to CN202180003045.2A priority patent/CN117616489A/zh
Priority to EP21961044.1A priority patent/EP4339925A1/en
Publication of WO2023065296A1 publication Critical patent/WO2023065296A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure

Definitions

  • the disclosure belongs to the field of display technology, and in particular relates to a display substrate and an electronic device.
  • organic electroluminance display Organic Electroluminance Display, referred to as: OLED
  • OLED Organic Electroluminance Display
  • the present invention aims to solve at least one of the technical problems in the prior art, and provides a display substrate and an electronic device.
  • an embodiment of the present disclosure provides a display substrate, which has a display area, and the display area includes a functional area and a main display area surrounding the functional area; the functional area has at least one functional unit; the functional The unit has a blank area, a winding area and a circuit area; the display substrate includes: a base substrate, a multi-layer conductive layer arranged on the base substrate; the multi-layer conductive layer forms at least one hollow pattern, and a The blank area is formed with a hollow pattern;
  • the multi-layer conductive layer includes a first signal line, and the first signal line includes a first line segment located in the main display area, a second line segment located in the circuit area, and a line segment located in the winding area.
  • the third line segment where,
  • the extension direction of the first line segment and the second line segment are the same, the third line segment electrically connects the first line segment and the second line segment, and the third line segment includes at least two extension directions different sub-segments.
  • the winding area surrounds the blank area, and the circuit area surrounds the winding area; the first line segment, the second line segment and the third line segment of the first signal line direct electrical connection.
  • the multi-layer conductive layer includes a first conductive layer and a second conductive layer disposed on the base substrate;
  • the first conductive layer includes a first-type signal line whose main body extends along a first direction, and the first-type signal line includes a first sub-type signal line and a second sub-type signal line; the first sub-type signal line The wire is only located in the main display area; the second subtype signal line is located in the main display area and the winding area;
  • the second conductive layer includes a second-type signal line whose main body extends along the second direction, and the second-type signal line includes a third sub-type signal line and a fourth sub-type signal line; the third sub-type signal line The wire is only located in the main display area; the fourth subtype signal line is located in the main display area and the winding area;
  • the first signal line includes the second subtype signal line and/or the fourth subtype signal line.
  • the third line segment includes a first sub-line segment extending along the first direction and a second sub-line segment extending along the second direction.
  • first sub-line segment and the second sub-line segment in the third line segment are directly electrically connected.
  • the first conductive layer includes a first sub-line segment
  • the second conductive layer includes a second sub-line segment
  • the first line segment and the second sub-line segment in the third line segment pass through the interlayer Electrical connection via vias in the insulating layer.
  • each of the second sub-type signal lines takes a straight line that runs through the center of the functional area and extends along the first direction as the axis of symmetry, forming a mirror symmetry settings;
  • each of the fourth sub-type signal lines takes the line that runs through the center of the functional area and extends along the second direction as the axis of symmetry, and is mirror-symmetrical set up.
  • the first type of signal lines includes at least one of gate lines, reset signal lines, and light emission control lines.
  • the second type of signal line includes at least one of a data line, an initial signal line, and a power signal line.
  • the distance between the third signal lines is smaller than the distance between the first signal line segments.
  • the display substrate further includes pixel driving circuits located in the main display area and the circuit area; the distribution density of the pixel driving circuits in the main display area is the same as that in the circuit area.
  • the display substrate also includes middle light-emitting devices located in the main display area and the functional area; the light-emitting devices all include anodes arranged on the base substrate; The area of the anode of the light emitting device in the main display area is smaller than that of the anode of the light emitting device in the functional area.
  • the anodes of part of the light emitting device cover the empty area.
  • the embodiment of the present disclosure is an electronic device, which includes a display substrate and functional components, and the functional components are located on the side of the display substrate away from the light-emitting surface; wherein, the display substrate has a display area, and the display The area includes a functional area and a main display area surrounding the functional area; the functional area has at least one functional unit; the functional unit has a blank area, a winding area and a circuit area; the display substrate includes: a base substrate, A multi-layer conductive layer disposed on the base substrate; the multi-layer conductive layer forms at least one hollow pattern, and one hollow area is formed with one hollow pattern;
  • the multi-layer conductive layer includes a first signal line, and the first signal line includes a first line segment located in the main display area, a second line segment located in the circuit area, and a line segment located in the winding area. third line segment;
  • the extension direction of the first line segment and the second line segment are the same, the third line segment electrically connects the first line segment and the second line segment, and the third line segment includes at least two extension directions different sub-segments;
  • the functional component at least partially overlaps the hollow pattern.
  • the winding area surrounds the blank area, and the circuit area surrounds the winding area; the first line segment, the second line segment and the third line segment of the first signal line direct electrical connection.
  • the multi-layer conductive layer includes a first conductive layer and a second conductive layer disposed on the base substrate;
  • the first conductive layer includes a first-type signal line whose main body extends along a first direction, and the first-type signal line includes a first sub-type signal line and a second sub-type signal line; the first sub-type signal line The wire is only located in the main display area; the second subtype signal line is located in the main display area and the winding area;
  • the second conductive layer includes a second-type signal line whose main body extends along the second direction, and the second-type signal line includes a third sub-type signal line and a fourth sub-type signal line; the third sub-type signal line The wire is only located in the main display area; the fourth subtype signal line is located in the main display area and the winding area;
  • the first signal line includes the second subtype signal line and/or the fourth subtype signal line;
  • the third line segment includes a first sub-line segment extending along the first direction and a second sub-line segment extending along the second direction.
  • first sub-line segment and the second sub-line segment in the third line segment are directly electrically connected.
  • the first conductive layer includes a first sub-line segment
  • the second conductive layer includes a second sub-line segment
  • the first line segment and the second sub-line segment in the third line segment pass through the interlayer Electrical connection via vias in the insulating layer.
  • each of the second sub-type signal lines takes a straight line that runs through the center of the functional area and extends along the first direction as the axis of symmetry, forming a mirror symmetry settings;
  • each of the fourth sub-type signal lines takes the line that runs through the center of the functional area and extends along the second direction as the axis of symmetry, and is mirror-symmetrical set up.
  • the first type of signal lines includes at least one of gate lines, reset signal lines, and light emission control lines.
  • the second type of signal line includes at least one of a data line, an initial signal line, and a power signal line.
  • the distance between the third signal lines is smaller than the distance between the first signal line segments.
  • the display substrate further includes pixel driving circuits located in the main display area and the circuit area; the distribution density of the pixel driving circuits in the main display area is the same as that in the circuit area.
  • the display substrate further includes light-emitting devices located in the main display area and the functional area, and the distribution density of the light-emitting devices located in the main display area is greater than the distribution density of the light-emitting devices located in the functional area density.
  • the display substrate also includes middle light-emitting devices located in the main display area and the functional area; the light-emitting devices all include anodes arranged on the base substrate; The area of the anode of the light emitting device in the main display area is smaller than that of the anode of the light emitting device in the functional area.
  • the anodes of part of the light-emitting devices partially cover the blank area; the functional components do not overlap with the orthographic projection of the anode on the base substrate.
  • FIG. 1 is a schematic diagram of the distribution of various regions of a display substrate.
  • Fig. 2a is a schematic plan view of a display substrate.
  • Fig. 2b is a schematic plan view of another display substrate.
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate.
  • FIG. 4 is an equivalent circuit diagram of a pixel driving circuit.
  • FIG. 5 is a schematic diagram of the present disclosure showing a semiconductor layer pattern formed on a substrate.
  • 6a is a schematic diagram of the present disclosure showing that the substrate is patterned with a first conductive layer.
  • FIG. 6b is a schematic plan view of the first conductive layer in FIG. 6a.
  • FIG. 7 a is a schematic diagram of the present disclosure showing a substrate after forming a pattern of a fourth conductive layer.
  • FIG. 7b is a schematic plan view of the fourth conductive layer in FIG. 7a.
  • FIG. 8 a is a schematic diagram of the present disclosure showing a substrate after forming a pattern of a fourth insulating layer.
  • Fig. 8b is a schematic plan view of a plurality of via holes in Fig. 8a.
  • FIG. 9 a is a schematic diagram of the present disclosure showing a substrate after forming a third conductive layer pattern.
  • FIG. 9b is a schematic plan view of the third conductive layer in FIG. 9a.
  • FIG. 10 a is a schematic diagram of the present disclosure showing a substrate after forming a first planar layer pattern.
  • Fig. 10b is a schematic plan view of a plurality of via holes in Fig. 10a.
  • FIG. 11 a is a schematic diagram of the present disclosure showing that a second conductive layer pattern is formed on a substrate.
  • Fig. 11b is a schematic plan view of the second conductive layer in Fig. 11a.
  • FIG. 12 a is a schematic diagram of the present disclosure showing that the substrate is patterned with a second flat layer.
  • Fig. 12b is a schematic plan view of a plurality of via holes in Fig. 12a.
  • FIG. 13 a is a schematic diagram of the present disclosure showing a substrate after forming an anode pattern.
  • Fig. 13b is a schematic plan view of the anode in Fig. 13a.
  • Fig. 14a is a partial schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 14b is a schematic diagram of the first scanning signal line in FIG. 14a.
  • FIG. 15 is a partial schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 16 is a partial schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 17 is a partial schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • Fig. 18a is a partial schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • Fig. 18b is a schematic diagram of a first scanning signal line in Fig. 18a.
  • FIG. 18c is a schematic diagram of another first scanning signal line in FIG. 18a.
  • FIG. 19 is a partial schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 20 is a partial schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 21 is a schematic diagram of an electronic device according to an embodiment of the disclosure.
  • a series of functional components are integrated in the display area of the display panel, that is, the functional area is preset in the original display panel, so that the subsequent Form functional elements, as shown in Figure 1.
  • display elements such as pixel driving circuits and light emitting devices are still arranged in the functional area.
  • the display components set in the functional area cannot affect the work of the functional components. That is to say, the distance between the pixel driving circuit, the light emitting device, etc. located in the functional area will define the blank area where the functional elements are located.
  • the pixel driving circuit and the light emitting device cannot be installed at this position, which leads to the inability of the signal lines located on the two opposite sides of the blank area to connect through the blank area, which in turn causes the display elements located in the functional area can not work normally.
  • an embodiment of the present disclosure provides a display substrate structure.
  • the pixel driving circuit and the light emitting device used in the display substrate, as well as the film layer relationship between the pixel driving circuit and the light emitting device are described first.
  • FIG. 2a and FIG. 2b are schematic diagrams of a planar structure of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 that emits light of a first color, and a first sub-pixel P1 that emits light of a second color.
  • the second sub-pixel P2 and two third sub-pixels P3 and fourth sub-pixels P4 that emit light of the third color, the four sub-pixels may each include a pixel driving circuit and a light emitting device, and the pixel driving circuit may include a scanning signal line, a data signal line and the light emitting signal line, the pixel driving circuit is respectively connected to the scanning signal line, the data signal line and the light emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light emitting signal line , to output the corresponding current to the light emitting device.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel to emit light with a corresponding brightness.
  • the first sub-pixel P1 may be a red sub-pixel (R) that emits red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light
  • the four sub-pixels P4 may be green sub-pixels (G) emitting green light.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • four sub-pixels may be arranged in a square (Square) manner to form a GGRB pixel arrangement, as shown in FIG. 2 a .
  • four sub-pixels may be arranged in a diamond shape (Diamond) to form an RGBG pixel arrangement, as shown in FIG. 2b.
  • the four sub-pixels may be arranged horizontally or vertically.
  • a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged horizontally, vertically, or vertically, which is not limited in the present disclosure.
  • a plurality of sub-pixels arranged in sequence in the horizontal direction is called a pixel row
  • a plurality of sub-pixels arranged in sequence in the vertical direction are called a pixel column
  • the plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array.
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate, illustrating the structure of three sub-pixels of the display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on a base 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the base, and a light-emitting structure layer 103 disposed on the base 102.
  • Layer 103 is away from the encapsulation layer 104 on the side of the substrate.
  • the display substrate may include other film layers, such as spacer pillars, etc., which are not limited in this disclosure.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of signal lines and a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and storage capacitors. In FIG. 3 , only one driving transistor 210 and one storage capacitor 211 are taken as examples for illustration.
  • the light-emitting structure layer 103 of each sub-pixel may include multiple film layers that constitute a light-emitting device, and the multiple film layers may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 communicates with the drive transistor 210 through a via hole.
  • the drain electrode is connected, the organic light emitting layer 303 is connected to the anode 301, the cathode 304 is connected to the organic light emitting layer 303, and the organic light emitting layer 303 emits light of a corresponding color under the drive of the anode 301 and the cathode 304.
  • the encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 that are stacked.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of Organic material, the second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403 , which can ensure that external water vapor cannot enter the light emitting structure layer 103 .
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, HIL for short), a hole transport layer (Hole Transport Layer, HTL for short), an electron blocking layer (Electron Block Layer, EBL for short), Emitting Layer (EML for short), Hole Block Layer (HBL for short), Electron Transport Layer (ETL for short), and Electron Injection Layer (EIL for short) .
  • HIL Hole Injection Layer
  • HTL hole transport layer
  • EBL Electron Block Layer
  • EML Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layer and the electron injection layer of all sub-pixels may be a common layer connected together
  • the hole transport layer and the electron transport layer of all sub-pixels may be a common layer connected together
  • all The hole blocking layer of the sub-pixels can be a common layer connected together, and the light-emitting layer and the electron blocking layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 4, the pixel driving circuit may include 7 transistors (the first transistor T1 to the seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is respectively connected with 7 signal lines (data signal line D, first scan The signal line S1, the second scanning signal line S2, the light emitting signal line E, the initial signal line INIT, the first power line VDD and the second power line VSS) are connected.
  • 7 signal lines data signal line D, first scan The signal line S1, the second scanning signal line S2, the light emitting signal line E, the initial signal line INIT, the first power line VDD and the second power line VSS
  • the pixel driving circuit may include a first node N1, a second node N2 and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor T1.
  • the first pole of the second transistor T2, the control pole of the third transistor T3 and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second pole of the second transistor T2 and the second pole of the third transistor T3 It is connected with the first pole of the sixth transistor T6.
  • the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor T1 is connected to the second node N2.
  • the first transistor T1 transmits an initial voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be referred to as a switching transistor, a scanning transistor, etc., and when a turn-on level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 make the light emitting device emit light by forming a driving current path between the first power line VDD and the second power line VSS.
  • the control electrode of the seventh transistor T7 is connected to the second scanning signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits the initial voltage to the first pole of the light emitting device, so that the amount of charge accumulated in the first pole of the light emitting device is initialized or released to emit light The amount of charge accumulated in the first pole of a device.
  • the light emitting device may be an OLED comprising a stacked first pole (anode), an organic light-emitting layer, and a second pole (cathode), or may be a QLED comprising a stacked first pole (anode) , a quantum dot light-emitting layer and a second pole (cathode).
  • the second pole of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously high level signal.
  • the first scanning signal line S1 is the scanning signal line in the pixel driving circuit of this display row
  • the second scanning signal line S2 is the scanning signal line in the previous display row pixel driving circuit, that is, for the nth display row, the first scanning signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield rate of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.
  • the first transistor T1 to the seventh transistor T7 may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide (LTPO for short) display substrate can take advantage of the advantages of both to realize low-frequency drive, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the following is an exemplary description by showing the preparation process of the substrate.
  • the "patterning process” mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • “Thin film” refers to a thin film made of a certain material on a substrate by deposition, coating or other processes.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process.
  • the “layer” after the patterning process includes at least one "pattern”.
  • “A and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the orthographic projection of A , or the boundary of A's orthographic projection overlaps the boundary of B's orthographic projection.
  • the preparation process of the driving circuit layer may include the following operations.
  • Forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the base substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the base substrate, and The semiconductor layer disposed on the first insulating layer, as shown in FIG. 5 .
  • the semiconductor layer of each pixel driving circuit may include the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 17
  • the source layer 17 is an integral structure connected to each other, and the sixth active layer 16 of the Mth row of pixel driving circuits in each unit column is connected to the seventh active layer 17 of the M+1th row of pixel driving circuits, that is, each The semiconductor layers of the adjacent pixel driving circuits in the unit column are connected to each other as an integral structure.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the base substrate on which the aforementioned pattern is formed, and patterning the first conductive film through a patterning process to form The second insulating layer covering the semiconductor layer pattern, and the first conductive layer pattern disposed on the second insulating layer, the first conductive layer pattern at least includes: a first scanning signal line 21, a second scanning signal line 22, and a light emission control line 23 and the first pole plate 24, as shown in Figure 6a and Figure 6b, Figure 6b is a schematic plan view of the first conductive layer in Figure 6a.
  • the first scanning signal line 21 , the second scanning signal line 22 and the light emission control line 23 can extend along the first direction X along the main part.
  • the first scan signal line 21 and the second scan signal line 22 in the Mth row S2 pixel drive circuit are located on the side of the first plate 24 of the pixel drive circuit away from the M+1th row pixel drive circuit, and the second scan signal The line 22 is located on the side of the first scanning signal line 21 of the pixel driving circuit away from the first plate 24, and the light emission control line 23 can be located on the side of the first plate 24 of the pixel driving circuit close to the M+1th row of the pixel driving circuit. side.
  • the first pole plate 24 can be rectangular, and the corners of the rectangle can be chamfered, and the orthographic projection of the first pole plate 24 on the base substrate is in the Orthographic projections on the substrate substrate have overlapping areas.
  • the first plate 24 may serve as a plate of the storage capacitor and a gate electrode of the third transistor T3 at the same time.
  • the area where the first scanning signal line 21 overlaps with the second active layer 12 is used as the gate electrode of the second transistor T2, and the first scanning signal line 21 is provided with a protrusion protruding toward the second scanning signal line 22.
  • the gate block 21-1, the orthographic projection of the gate block 21-1 on the substrate and the orthographic projection of the second active layer 12 on the substrate have an overlapping area, forming a second transistor T2 with a double gate structure .
  • the overlapping area of the first scanning signal line 21 and the fourth active layer 14 serves as the gate electrode of the fourth transistor T4.
  • the area where the second scanning signal line 22 overlaps with the first active layer 11 is used as the gate electrode of the first transistor T1 of the double gate structure, and the area where the second scanning signal line 22 overlaps with the seventh active layer 17 is used as the seventh
  • the semiconductor layer may be subjected to conductorization treatment by using the first conductive layer as a shield, and the semiconductor layer in the area shielded by the first conductive layer forms the first transistor T1 to the seventh transistor T7 In the channel region, the semiconductor layer in the region not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer to the seventh active layer are all conductorized.
  • forming the pattern of the second conductive layer may include: sequentially depositing a third insulating film and a fourth conductive film on the base substrate on which the foregoing pattern is formed, and patterning the fourth conductive film by a patterning process , form a third insulating layer covering the first conductive layer, and a second conductive layer pattern arranged on the third insulating layer, the second conductive layer pattern at least includes: a first initial signal line 31, a second pole plate 32, a shielding
  • the electrodes 33 and the electrode plate connecting wires 35 are as described in FIG. 7a and FIG. 7b, and FIG. 7b is a schematic plan view of the fourth conductive layer in FIG. 7a.
  • the first initial signal line 31 can extend along the first direction X in the main part, and the first initial signal line 31 in the pixel driving circuit of the Mth row is located in the second scanning signal line of the pixel driving circuit. 22 is away from the side of the pixel driving circuit in the M+1th row, and the second plate 32 is used as the other plate of the storage capacitor, which is located between the first scanning signal line 21 and the light emission control line 23 of the pixel driving circuit, and the shielding electrode 33 is located between the second scanning signal line 22 and the first scanning signal line 21 (not including the main part of the gate block 21-1) of the pixel driving circuit, and the shielding electrode 33 is configured to shield the impact of the data voltage jump on key nodes. Influence, to avoid the data voltage jump from affecting the potential of the key nodes of the pixel driving circuit, and improve the display effect.
  • the outline of the second pole plate 32 can be rectangular, and the corners of the rectangle can be chamfered. There is an overlapping area in the orthographic projection on , and the first pole plate 24 and the second pole plate 32 constitute the storage capacitor of the pixel driving circuit.
  • An opening 34 is disposed on the second pole plate 32 , and the opening 34 may be located in the middle of the second pole plate 32 .
  • the opening 34 may be rectangular, so that the second pole plate 32 forms a ring structure.
  • the opening 34 exposes the third insulating layer covering the first pole plate 24 , and the orthographic projection of the first pole plate 24 on the base substrate includes the orthographic projection of the opening 34 on the base substrate.
  • the opening 34 is configured to accommodate the subsequently formed first via hole, the first via hole is located in the opening 34 and exposes the first electrode plate 24, so that the second electrode of the subsequently formed first transistor T1 Connect with the first pole plate 24.
  • the electrode plate connection line 35 is arranged between the second electrode plates 32 of adjacent pixel driving circuits in the first direction X or in the opposite direction of the first direction X, and the first end of the electrode plate connection line 35 It is connected to the second pole plate 32 of the pixel driving circuit, and the second end of the pole plate connection line 35 extends along the first direction X or the opposite direction of the first direction X, and is connected to the second pole plate of the adjacent pixel driving circuit.
  • 32 connection that is, the electrode plate connection line 35 is configured to connect the second electrode plates of adjacent pixel driving circuits on a unit row to each other.
  • the second plates of multiple pixel driving circuits in a unit row can form an interconnected integrated structure through the plate connection line 35, and the second plate of the integrated structure can be multiplexed as a power signal line , ensuring that multiple second plates in one unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • forming the pattern of the fourth insulating layer may include: depositing a fourth insulating film on the base substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film by a patterning process to form a layer covering the second conductive layer.
  • each pixel driving circuit is provided with a plurality of via holes, and the plurality of via holes at least include: a first via hole V1, a second via hole V2, a third via hole V3, and a fourth via hole V4 , the fifth via V5, the sixth via V6, the seventh via V7, the eighth via V8 and the ninth via V9, as shown in Figure 8a and Figure 8b, Figure 8b is a plurality of via holes in Figure 8a floor plan.
  • the first via hole V1 is located in the opening 34 of the second plate 32, and the orthographic projection of the first via hole V1 on the base substrate is located at the orthographic projection of the opening 34 on the base substrate.
  • the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away, exposing the surface of the first electrode plate 24 .
  • the first via hole V1 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first electrode plate 24 through the via hole.
  • the second via hole V2 is located within the range of the orthographic projection of the second polar plate 32 on the substrate, and the orthographic projection of the second via hole V2 on the substrate is located within the range of the second polar plate 32 on the substrate.
  • the fourth insulating layer in the second via hole V2 is etched away, exposing the surface of the second electrode plate 32 .
  • the second via hole V2 is configured to connect the subsequently formed first power line to the second plate 32 through the via hole.
  • the second via hole V2 used as the power supply via hole may include multiple, and the multiple second via holes V2 may be arranged in sequence along the second direction Y, so as to increase the distance between the first power line and the second plate 32. Connection reliability.
  • the orthographic projection of the third via hole V3 on the substrate is within the range of the orthographic projection of the fifth active layer on the substrate, and the fourth insulating layer, the The third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the fifth active layer.
  • the third via hole V3 is configured to connect the subsequently formed first power line to the fifth active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is within the range of the orthographic projection of the sixth active layer on the substrate, and the fourth insulating layer, the The third insulating layer and the second insulating layer are etched away, exposing the surface of the second region of the sixth active layer (also the second region of the seventh active layer).
  • the fourth via hole V4 is configured such that the second pole of the subsequently formed sixth transistor T6 is connected to the sixth active layer through the via hole, and the second pole of the subsequently formed seventh transistor T7 is connected to the sixth active layer through the via hole. Seven active layer connections.
  • the orthographic projection of the fifth via hole V5 on the substrate is within the range of the orthographic projection of the fourth active layer on the substrate, and the fourth insulating layer, the The third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the fourth active layer.
  • the fifth via hole V5 is configured to connect the subsequently formed data signal line to the fourth active layer through the via hole, and the fifth via hole V5 is called a data writing hole.
  • the orthographic projection of the sixth via hole V6 on the base substrate is within the range of the orthographic projection of the second active layer on the base substrate, and the fourth insulating layer, the sixth via hole V6
  • the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the second active layer (which is also the second region of the first active layer).
  • the sixth via hole V6 is configured to connect the second pole of the subsequently formed first transistor T1 to the first active layer through the via hole, and connect the first pole of the subsequently formed second transistor T2 to the first active layer through the via hole. Two active layer connections.
  • the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the seventh active layer on the substrate, and the fourth insulating layer, the The third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the seventh active layer (which is also the first region of the first active layer).
  • the seventh via hole V7 is configured such that the first electrode of the subsequently formed seventh transistor T7 is connected to the seventh active layer through the via hole, and the first electrode of the subsequently formed first transistor T1 is connected to the seventh active layer through the via hole.
  • An active layer connection is configured such that the first electrode of the subsequently formed seventh transistor T7 is connected to the seventh active layer through the via hole, and the first electrode of the subsequently formed first transistor T1 is connected to the seventh active layer through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is within the range of the orthographic projection of the shielding electrode 33 on the substrate, and the fourth insulating layer in the eighth via hole V8 is etched away. , exposing the surface of the shielding electrode 33 .
  • the eighth via hole V8 is configured to connect the subsequently formed first power line to the shielding electrode 33 through the via hole.
  • the orthographic projection of the ninth via hole V9 on the base substrate is within the range of the orthographic projection of the first initial signal line 31 on the base substrate, and the fourth insulating layer inside the ninth via hole V9 is covered. etched away to expose the surface of the first initial signal line 31 .
  • the ninth via hole V9 is configured such that the first pole of the subsequently formed seventh transistor T7 (also the first pole of the first transistor T1 ) is connected to the first initial signal line 31 through the via hole.
  • Forming a third conductive layer pattern may include: depositing a third conductive film on the base substrate with the aforementioned pattern, patterning the third conductive film by a patterning process, and forming a layer disposed on the fourth insulating layer.
  • the third conductive layer, the third conductive layer at least includes: a first power line 41, a data connection electrode 42, a first connection electrode 43, a second connection electrode 44 and a third connection electrode 45, as shown in Figure 9a and Figure 9b , FIG. 9b is a schematic plan view of the third conductive layer in FIG. 9a.
  • the main part of the first power line 41 extends along the second direction Y, the first power line 41 is connected to the second plate 32 through the second via hole V2 on the one hand, and connected to the second electrode plate 32 through the second via hole V2 on the other hand.
  • the third via V3 is connected to the fifth active layer, and on the other hand, is connected to the shielding electrode 33 through the eighth via V8, so that the shielding electrode 33 and the second plate 32 have the same potential as the first power line 41 .
  • the shielding electrode 33 is connected to the first power line 41, and the orthographic projection of at least a part of the shielding electrode 33 (such as the protrusion on the right side of the shielding electrode 33) on the base substrate is located at the first connection electrode 43 (as the first transistor Between the second pole of T1 and the first pole of the second transistor T2 (i.e., the second node N2) on the base substrate, the orthographic projection of the subsequently formed data signal line on the base substrate can be effectively shielded.
  • the impact of the data voltage jump on the key nodes in the pixel driving circuit is avoided, the potential of the key nodes of the pixel driving circuit is prevented from being affected by the data voltage jump, and the display effect is improved.
  • the orthographic projection of at least a partial area of the shielding electrode 33 on the base substrate may at least partially overlap with the orthographic projection of the subsequently formed data signal line on the base substrate.
  • shielding electrodes 33 in adjacent pixel driving circuits in the first direction X may be connected to each other to reduce resistance.
  • the data connection electrode 42 is connected to the first region of the fourth active layer through the fifth via hole V5, and the data connection electrode 42 is configured to be connected to a subsequently formed data signal line.
  • the first connection electrode 43 extends along the second direction Y, and its first end passes through the sixth via hole V6 and the second region of the first active layer (also the first region of the second active layer). The second terminal thereof is connected to the first pole plate 24 through the first via hole V1, so that the first pole plate 24, the second pole of the first transistor T1 and the first pole of the second transistor T2 have the same potential.
  • the first connection electrode 43 may function as a second pole of the first transistor T1 and a first pole of the second transistor T2.
  • the first end of the second connection electrode 44 is connected to the first initial signal line 31 through the ninth via hole V9, and the second end thereof is connected to the first region ( Also the first region of the first active layer) is connected so that the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1 have the same potential as the first initial signal line 31 .
  • the third connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4, so that the second electrode of the sixth transistor T6 and The second poles of the seventh transistor T7 have the same potential.
  • the third connection electrode 45 may function as a second pole of the sixth transistor T6 and a second pole of the seventh transistor T7.
  • the third connection electrode 45 is configured to be connected to a subsequently formed anode connection electrode.
  • Forming a first flat layer pattern may include: coating the first planar film on the base substrate on which the aforementioned pattern is formed, and patterning the first planar film by a patterning process to form a layer covering the third layer.
  • the first flat layer of the conductive layer is provided with an eleventh via hole V11 and a twelfth via hole V12, as shown in FIG. 10a and FIG. 10b, and FIG. Schematic plan view.
  • the orthographic projection of the eleventh via hole V11 on the base substrate is within the range of the orthographic projection of the data connection electrode 42 on the base substrate, and the eleventh via hole V11 inside the first A planar layer is removed to expose the surface of the data connection electrode 42 , and the eleventh via hole V11 is configured so that the subsequently formed data signal line is connected to the data connection electrode 42 through the via hole.
  • the eleventh via hole V11 may be in a bar shape, and the extension length of the eleventh via hole V11 in the second direction Y is greater than the extension length in the first direction X.
  • the eleventh via hole V11 in a strip shape extending along the second direction Y, the width of the eleventh via hole V11 in the first direction X can be reduced, and the degree of inclination of the subsequently formed anode can be reduced.
  • the orthographic projection of the twelfth via hole V12 on the base substrate is within the range of the orthographic projection of the third connecting electrode 45 on the base substrate, and the first flat layer in the twelfth via hole V12 is removed, exposing the On the surface of the third connection electrode 45 , the twelfth via hole V12 is configured so that the subsequently formed anode connection electrode is connected to the third connection electrode 45 through the via hole.
  • Forming a second conductive layer pattern may include: depositing a second conductive film on the base substrate on which the aforementioned pattern is formed, patterning the second conductive film by a patterning process, and forming a layer disposed on the first conductive layer.
  • the fourth conductive layer on the flat layer, the fourth conductive layer at least includes: data signal line 51 and anode connection electrode 52, as shown in Figure 11a and Figure 11b, Figure 11b is a schematic plan view of the fourth conductive layer in Figure 11a.
  • the data signal line 51 is arranged in each cell column.
  • the data signal line 51 may extend along the second direction Y, and the data signal line 51 is connected to the data connection electrode 42 through the eleventh via hole V11 . Since the data connection electrode 42 is connected to the first region of the fourth active layer through the fifth via hole V5, the data signal line 51 is connected to the first region of the fourth active layer through the data connection electrode 42, and the data signal is connected to the first region of the fourth active layer.
  • the fourth transistor T4 is connected to the first region of the fourth active layer through the data connection electrode 42, and the data signal is connected to the first region of the fourth active layer.
  • the anode connection electrode 52 is disposed in at least part of the pixel driving circuit.
  • the anode connection electrode 52 is connected to the third connection electrode 45 through the twelfth via hole V12 . Since the third connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4, the anode connection electrode 53 is connected to the second region of the seventh active layer through the third connection electrode 45. The second region of the sixth active layer (also the second region of the seventh active layer) is connected.
  • Forming a second flat layer pattern may include: coating a second planar thin film on the base substrate on which the foregoing pattern is formed, and patterning the second planar thin film by a patterning process to form a layer covering the fourth planar layer.
  • the second flat layer of the conductive layer is provided with a thirteenth via hole V13, as shown in FIG. 12a and FIG. 12b, and FIG. 12b is a schematic plan view of multiple via holes in FIG. 12a.
  • the orthographic projection of the thirteenth via hole V13 on the base substrate is within the range of the orthographic projection of the anode connection electrode 53 on the base substrate, and the thirteenth via hole V13 inside the thirteenth via hole V13
  • the two planar layers are removed to expose the surface of the anode connection electrode 52 , and the thirteenth via hole V13 is configured so that the subsequently formed anode is connected to the anode connection electrode 52 through the via hole.
  • the driving circuit layer is prepared on the base substrate.
  • the driving circuit layer may include a plurality of pixel driving circuits, each pixel driving circuit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, and a first scanning signal line connected to the pixel driving circuit. Lighting control lines, data signal lines, first power lines, and first initial signal lines.
  • the driving circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, and a second conductive layer sequentially stacked on the base substrate. , a fourth insulating layer, a third conductive layer, a first planar layer, a fourth conductive layer and a second planar layer.
  • Forming an anode pattern may include: depositing a fifth conductive film on the base substrate with the aforementioned pattern, patterning the fifth conductive film by a patterning process, and forming an anode disposed on the second planar layer pattern, the anode forms the GGRB pixel arrangement, as shown in Figure 13a and Figure 13b, and Figure 13b is a schematic plan view of the anode in Figure 13a.
  • the anode pattern may include a first anode 71A of a red light-emitting device, a second anode 71B of a blue light-emitting device, a third anode 71C of a first green light-emitting device, and a first anode 71C of a second green light-emitting device.
  • the area where the first anode 71A is located can form a red sub-pixel R that emits red light
  • the area where the second anode 71B is located can form a blue sub-pixel B that emits blue light
  • the area where the third anode 71C is located can form a green sub-pixel that emits green light.
  • the first green sub-pixel G1 of the light, the area where the fourth anode 71D is located can form the second green sub-pixel G2 emitting green light
  • the red sub-pixel R and the blue sub-pixel B are arranged in sequence along the second direction Y
  • the first green The sub-pixel G1 and the second green sub-pixel G2 are arranged in sequence along the second direction Y
  • the first green sub-pixel G1 and the second green sub-pixel G2 are respectively arranged in the first direction X of the red sub-pixel R and the blue sub-pixel B.
  • the red sub-pixel R, the blue sub-pixel B, the first green sub-pixel G1 and the second green sub-pixel G2 form a pixel unit.
  • the first anode 71A is connected to the anode connection electrode 52 in the pixel driving circuit through the thirteenth via hole V13 in the pixel driving circuit in the Mth row and the Nth column
  • the second anode 71B is connected to the anode connection electrode 52 in the pixel driving circuit through
  • the thirteenth via hole V13 in the pixel driving circuit in the M+1th row and the Nth column is connected to the anode connection electrode 52 in the pixel driving circuit
  • the third anode 71C passes through the Mth row and the N+1th column in the pixel driving circuit.
  • the thirteenth via hole V13 is connected to the anode connection electrode 52 in the pixel driving circuit, and the fourth anode 71D is connected to the pixel driving circuit through the thirteenth via V13 in the pixel driving circuit in the M+1th row and the N+1th column.
  • the anode in the connection electrode 52 is connected.
  • the first anode 71A is connected to the anode connection electrode 52 in the pixel driving circuit through the thirteenth via hole V13 in the pixel driving circuit in the M+1th row and the N+2th column
  • the second anode 71B is connected to the anode connection electrode 52 in the pixel driving circuit through
  • the fourteenth via hole V14 in the pixel driving circuit in the Mth row and the N+2th column is connected to the anode connection electrode 52 in the pixel driving circuit
  • the third anode 71C passes through the M+1th row and the N+3th column pixel driving circuit
  • the thirteenth via hole V13 in the pixel driving circuit is connected to the anode connection electrode 52 in the pixel driving circuit
  • the fourth anode 71D is connected to the pixel driving circuit through the thirteenth via hole V13 in the pixel driving circuit in the Mth row and the N+3 column.
  • structures such as a pixel defining layer, a light-emitting layer, and an encapsulation layer are formed to form a plurality of light-emitting devices of the light-emitting structure layer.
  • Conventional process steps can be used for the formation process of the light emitting device, so details will not be repeated here.
  • the substrate substrate can be a flexible substrate substrate, or it can be a rigid substrate substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone , polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, one or more of textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second
  • the material of the second flexible material layer can adopt materials such as polyimide (PI), polyethylene terephthalate (PET) or the polymer soft film through surface treatment, the first inorganic material layer and the second inorganic material layer
  • PI polyimide
  • PET polyethylene terephthalate
  • the material of the silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can use metal materials, such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo) Any one or more of these metals, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may use any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), Can be single layer, multilayer or composite layer.
  • the first insulating layer is called the buffer (Buffer) layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the interlayer insulating (ILD) layer.
  • the active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), Materials such as hexathiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • the first flat layer and the second flat layer can be made of organic materials, such as resin and the like.
  • the signal lines on the display substrate include the first scanning signal line, the second scanning signal line, the light emission control line, the first initial signal line, and the main body extending along the first direction.
  • the signal lines must be designed for winding or disconnection, so that the display substrate
  • the pixel driver circuit in provides the signal.
  • a display substrate is provided with a functional area in the display area.
  • the display substrate is similar to the above-mentioned substrate in that it also includes the above-mentioned film layers, and the signal line may include the above-mentioned first scanning signal. line, the second scanning signal line, the light emission control line, the first initial signal line, the data line, and the first power line.
  • an embodiment of the present disclosure provides a display substrate, the display substrate has a display area, and the display area includes a functional area and a main display area. There is at least one functional unit in the functional area; each functional unit has a blank area, a winding area and a circuit area. Wherein, the winding area surrounds at least part of the blank area, and the blank area in the functional unit and other areas outside the winding area are circuit areas.
  • the display substrate includes a base substrate, and a multi-layer conductive layer disposed on the base substrate, for example, includes the above-mentioned first conductive layer to fifth conductive layer.
  • the multi-layer conductive layer in the embodiment of the present disclosure forms at least one hollow pattern, and the hollow pattern is provided in the blank area.
  • the multi-layer conductive layer includes a first signal line, and the first signal line includes a first line segment located in the main display area, a second line segment located in the circuit area, and a third line segment located in the winding area; wherein, The first line segment and the second line segment extend in the same direction, the third line segment electrically connects the first line segment and the second line segment, and the third line segment includes at least two sub-line segments extending in different directions.
  • the display substrate includes a first type of signal line whose main body extends along the first direction, and the first type of signal line includes but not limited to the above-mentioned first scanning signal line, second scanning signal line, light emission control line and first initial signal line. Wire.
  • the first type of signal line includes a first subtype of signal line and a second subtype of signal line.
  • the signal lines of the first subtype only include the part located in the main display area; the signal lines of the second subtype include not only the part located in the main display area, but also the part located in the functional area.
  • the second subtype signal line may be the above-mentioned first signal line.
  • the second scanning signal line including the main display area and the function area is located on the first signal line.
  • Both the first line segment and the second line segment of the first signal line extend along the first direction, and the third line segment includes not only sub-line segments extending along the first direction, but also sub-line segments extending along the second direction.
  • the first scanning signal line, light emission control line and first initial signal line located in the main display area and functional area can also be set in the same way as the second scanning signal line located in the main display area and functional area.
  • the display substrate includes a second type of signal line extending along a second direction of the main body, and the second type of signal line includes but not limited to a data line and a first power line.
  • the second type signal line includes the third subtype signal line and the fourth type signal line; the third subtype signal line only includes the part located in the main display area; the fourth subtype signal line includes not only the part located in the main display area but also the part located in the main display area. section of the ribbon.
  • the signal line of the fourth subtype may be the above-mentioned first signal line.
  • the second type of signal lines as data lines as an example, the data lines located in the main display area and the function area at this time are the first signal lines.
  • the first line segment and the second line segment of the first signal line extend along the second direction
  • the third line segment includes not only sub-line segments extending along the first direction, but also sub-line segments extending along the second direction.
  • the first power line located in the main display area and the functional area it can also be set according to the arrangement of the data lines located in the display area and the functional area.
  • the first signal lines are referred to as the second scanning signal lines located in the main display area and the functional area (hereinafter referred to as the second scanning signal lines for short), and the second scanning signal lines located in the main
  • the data lines of the display area and the function area (hereinafter referred to as the first signal line for short) are taken as an example.
  • the hollow pattern formed in the blank area Q21 of the functional unit is a rectangle or a type rectangle
  • the winding area Q22 is set around the blank area Q21
  • the winding area Q22 is a rectangular ring
  • the remaining positions are
  • the circuit area Q23 is a functional unit.
  • the length of the blank area Q21 in the first direction X is smaller than the length in the second direction Y, that is, the blank area Q21 is in the shape of "1".
  • only the pixel driving circuit is provided in the circuit area Q23.
  • the first line segment of the first scanning signal line 21 is located in the main display area Q1, and the second line segment is located in the circuit area Q23, both of which extend along the first direction X and connect the first line segment 211 and the second line segment on the same straight line.
  • Line segments 212 are electrically connected.
  • the third line segment 213 of the first scanning signal line 21 includes a first sub-line segment 213a extending along the first direction X and a second sub-line segment 213b extending along the second direction Y.
  • the third line segment of any first scanning signal line 21 includes a first sub-line segment 213a and two second sub-line segments 213b, and the two ends of the first sub-line segment 213a are respectively connected to the two sub-line segments. a second sub-line segment 213b.
  • the first sub-line segment 213a is located on one side of the blank area Q21 in the second direction Y, and the two second sub-line segments 213b are respectively located on two opposite sides of the blank area Q21 in the first direction X.
  • the second segment of the first scanning signal line 21 may extend from the circuit area Q23 to the routing area Q22 and be electrically connected to the second sub-segment 213 b of the third segment 213 .
  • first scanning signal lines 21 there are multiple first scanning signal lines 21 including the part of the main display area Q1 and the part of the functional area.
  • the plurality of first scanning signal lines 21 run through the blank area Q21 in the first direction X.
  • the straight line in the center is the axis of symmetry, which is mirror symmetric. That is, half of the first scanning signal lines 21 are routed from the upper side of the blank area Q21 , and the other half of the first scanning signal lines 21 are routed from the lower side of the blank area Q21 .
  • the first line segment of the data line 51 is located in the main display area Q1
  • the second line segment is located in the circuit area Q23, both of which extend along the second direction Y, and are located on the same line in the second direction Y.
  • the first line segment and the second line segment of the straight line are electrically connected.
  • the third line segment of the data line 51 includes two first sub-line segments and one second sub-line segment, and the two ends of the second sub-line segment are respectively connected to the two first sub-line segments.
  • the two first sub-line segments extend along the first direction X and are respectively located on both sides of the blank area Q21 in the second direction Y, and the second sub-line segments are respectively located on one side of the blank area Q21 in the first direction X.
  • the second segment of the data line 51 may extend from the circuit area Q23 to the routing area Q22 to be electrically connected to the first sub-segment of the third segment.
  • the second example similar to the first example, the only difference is that the rectangle of the blank area Q21 is in the shape of "one". Referring to Figures 16 and 17, when the blank area Q21 is in the shape of "one", the first The winding method of a scan signal line 21 and data line 51 is the same as the above-mentioned first method, so the description will not be repeated here.
  • the hollow pattern formed in the blank area Q21 in the functional unit is cross-shaped or similar to a cross, that is, the blank area Q21 includes a first blank area Q211 extending along the first direction X and a second blank area Q212 extending along the second direction Y.
  • the winding area Q22 surrounds the blank area Q21 and is adapted to the shape of the blank area Q21.
  • the winding area Q22 is a cross-shaped ring, and the part of the winding area Q22 extending in the first direction X is called the first
  • the part of the routing region Q22 extending in the second direction Y is referred to as the second routing region Q22.
  • the rest of the functional unit outside the blank area Q21 and the winding area Q22 is the circuit area Q23.
  • the first scanning signal line 21 connected to the pixel driving circuit in the main display area Q1 and the circuit area Q23 covered by the first wiring area Q22 extending in the first direction X
  • the first The first line segment 211 of a scanning signal line 21 is located in the main display area Q1
  • the second line segment 212 is located in the circuit area Q23
  • the third line segment 213 is located in the first routing area Q22 and the second routing area Q22.
  • the third line segment 213 includes two first sub-line segments 213a located in the first winding area Q22 and respectively located on both sides of the second winding area Q22, respectively located on two opposite sides of the second winding area Q22 in the first direction X.
  • the first sub-line segment 213a extends along the first direction X
  • the second sub-line segment 213b extends along the second direction Y.
  • the third line segment 213b is located in accordance with the first sub-line segment located in the first winding area Q22, the second sub-line segment 213b located in the second winding area Q22, the first sub-line segment 213a located in the second winding area Q22, and the second line segment located in the second winding area Q22.
  • the second sub-line segment 213b of the second routing area Q22 is sequentially connected to the first sub-line segment 213a located in the first routing area Q22.
  • the first scanning signal line 21 connected to the pixel driving circuit in the main display area Q1 covered by the extension area of the second wiring area Q22 in the first direction X and the circuit area Q23
  • the first scanning The first line segment 211 of the signal line 21 is located in the main display area Q1
  • the second line segment 212 is located in the circuit area Q23
  • the third line segment 213 is located in the second wiring area Q22 .
  • the third segment 213 of the first scanning signal line 21 includes two second sub-segments 213b located on two opposite sides of the second winding area Q22 in the first direction X, and two sub-segments 213b located in the second direction Y-
  • the first sub-line segment 213a on the side, the first sub-line segment 213a electrically connects the two second sub-line segments 213b.
  • the first sub-line segment 213a extends along the first direction X
  • the second sub-line segment 213b extends along the second direction Y.
  • the second line segment 212 of the first scanning signal line 21 may extend from the circuit area Q23 to the winding area Q22 and be electrically connected to the second sub-line segment 212 of the third line segment.
  • first scanning signal lines 21 there are multiple first scanning signal lines 21 including the part of the main display area Q1 and the part of the functional area.
  • the plurality of first scanning signal lines 21 run through the blank area Q21 in the first direction X.
  • the straight line in the center is the axis of symmetry, which is mirror symmetric. That is, half of the first scanning signal lines 21 are routed from the upper side of the blank area Q21 , and the other half of the first scanning signal lines 21 are routed from the lower side of the blank area Q21 .
  • the data line 51 connected to the pixel driving circuit in the main display area Q1 and the circuit area Q23 covered by the second wiring area Q22 extending in the second direction Y
  • the data line 51 The first line segment is located in the main display area Q1
  • the second line segment is located in the circuit area Q23
  • the third line segment is located in the first wiring area Q22 and the second wiring area Q22.
  • the third line segment includes two second sub-line segments located in the second winding area Q22 and respectively located on both sides of the first winding area Q22, respectively located on both sides of the first winding area Q22 in the second direction Y Two first sub-line segments, and one second sub-line segment located on one side of the first routing area Q22 in the first direction X.
  • the first sub-line segment extends along the first direction X
  • the second sub-line segment extends along the second direction Y.
  • the third line segment is in accordance with the second sub-line segment located in the second winding area Q22, the first sub-line segment located in the first winding area Q22, the second sub-line segment located in the first winding area Q22, and the second line segment located in the second winding area.
  • the second sub-line segment of the line area Q22 is connected in sequence.
  • the first segment of the data line 51 is located at In the main display area Q1
  • the second line segment is located in the circuit area Q23
  • the third line segment is located in the first winding area Q22.
  • the third segment of the data line 51 includes two opposite first sub-segments respectively located in the first routing area Q22 in the second direction Y, and a sub-segment located on one side of the first routing area Q22 in the second direction Y.
  • a second sub-segment wherein, the first sub-segment extends along the first direction X, the second sub-segment extends along the second direction Y, and the third sub-segment follows the first sub-segment, the second sub-segment, and the first sub-segment connected sequentially.
  • the second segment of the data line 51 may extend from the circuit area Q23 to the routing area Q22 to be electrically connected to the first sub-segment of the third segment.
  • the multiple data lines 51 including the part of the main display area Q1 and the part of the functional area.
  • the multiple data lines 51 take the straight line passing through the blank area Q21 in the second direction Y as the axis of symmetry, It is mirror symmetrical. That is to say, the general data lines 51 are wound from the left side, and the other half of the data lines 51 are wound from the right side.
  • the blank area Q21 in each functional unit also includes a first blank area Q211 extending along the first direction X and a second blank area Q212 extending along the second direction Y. But the first blank area Q211 and the second blank area Q212 do not intersect, and the corresponding routing area Q22 includes a first routing area Q221 surrounding the first blank area Q211 and a second routing area Q222 surrounding the second blank area Q212.
  • the winding manner of the first scanning signal line 21 and the data line 51 in the first blank area Q211 is the same as that of the first example, and the winding manner of the second blank area Q212 is the same as that of the second example. Therefore, it will not be repeated here.
  • the above only gives several winding methods corresponding to the shapes of the blank area Q21.
  • the shape of the blank area Q21 can also be “I” type, “Tian” type, etc., because " The blank area Q21 of "I” shape and "Tian” shape includes a first blank area Q211 extending along the first direction X and a second blank area Q212 extending along the second direction Y, so for these two blank areas Q21
  • the winding of the first signal wire is performed by referring to the above-mentioned example.
  • the third line segment of the first signal line includes a first sub-line segment along the first direction X and a second sub-line segment along the second direction Y
  • the first sub-line segment and the second sub-line segment can be integrally formed, that is, the first sub-segment and the second sub-segment are directly electrically connected.
  • the first sub-segment and the second sub-segment use the same material, so the two can be composed at the same time. formed in the process.
  • the first sub-line segment extending along the first direction X and the second sub-line segment extending along the second direction Y in the third line segment can also be distributed in two conductive layers, for example: the first conductive layer
  • the first sub-line segment is included in the layer
  • the second sub-line segment is included in the second conductive layer
  • an interlayer insulating layer is arranged between the first conductive layer and the second conductive layer.
  • the first sub-line segment and the second sub-line segment can pass through Via electrical connection through the interlayer insulating layer.
  • the line spacing of the third line segment of the first signal line is smaller than the line spacing between the first line segments, and the line spacing between the first line segments may be equal to the distance between the second line segments. line spacing.
  • the main display area Q1 of the display substrate and the circuit area Q23 in the functional area are both provided with pixel driving circuits, and the arrangement density of the pixel driving circuits is the same.
  • the pixel driving circuits in the display substrate can be arranged in an array, only that no pixel driving is provided in the wiring area Q22 and the blank area Q21.
  • the arrangement rules of the pixel driving circuits in the main display area Q1 and the circuit area Q23 are the same, which facilitates the preparation of the pixel driving circuits.
  • the display substrate not only includes the above structure, but also includes multiple light emitting devices, such as OLED devices, and a pixel driving circuit is configured to drive one light emitting device to emit light. Since no pixel driving circuit is set in the blank area Q21 and the winding area Q22 in the functional area of the display substrate, if the arrangement of the pixel driving circuits in the main display area Q1 in the circuit area Q23 is the same, if the main When the anodes of the same luminous color in the display area Q1 and the functional area have the same area, the arrangement density of the light-emitting devices in the main display area Q1 and the functional area is different.
  • the arrangement density of is greater than the arrangement density of the light emitting devices in the functional area.
  • the arrangement density of light-emitting devices refers to the number of light-emitting devices of any same light-emitting color per unit area located in the same area. Among them, the greater the number, the greater the density.
  • the sizes of the anodes of the light-emitting devices with the same light-emitting color in the main display area Q1 and the functional area may also be different, for example :
  • the size of the anode of the light emitting device in the functional area is larger than the size of the anode of the light emitting device in the main display area Q1.
  • the orthographic projection of the anodes of at least part of the light emitting devices in the display substrate on the base substrate covers the blank area Q21. That is to say, the positive projection pattern covering the blank area Q21 determines the outline style of the hollow pattern.
  • FIG. 21 is a schematic diagram of an electronic device according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a display electronic device, which includes any of the aforementioned display substrates 100 and functional components 200, the functional component 200 is located on the side of the display substrate 100 facing away from the light-emitting surface, and in the embodiment of the present disclosure, the functional component 200 overlaps with the hollow pattern in the functional area of the display substrate 100. At this time, the functional component 200 can cooperate with the hollow pattern realize its function.
  • the functional component 200 may specifically be at least one of a camera, a distance sensor, a fingerprint sensor, a near field communication (Near Field Communication, NFC) antenna, and a radio frequency chip.
  • a camera a distance sensor
  • a fingerprint sensor a fingerprint sensor
  • a near field communication (Near Field Communication, NFC) antenna a radio frequency chip.
  • NFC Near Field Communication
  • the functional component 200 is a camera
  • only one functional unit may be included in the functional area, and the blank area in the functional unit forms a hollow pattern, and the orthographic projection of the camera on the base substrate is located at the position of the hollow pattern on the base substrate.
  • the orthographic projection that is to say, for the conductive elements in any conductive layer in the display substrate 100 (for example: the first scan line, the second scan line, the data line, the anode of the light emitting device, etc.)
  • the orthographic projections on the substrate are non-overlapping, thereby ensuring the image acquisition function of the camera.
  • the electronic device can realize the distance measuring function.
  • the hollow pattern in the functional unit can overlap with the existing part of the distance sensor on the base substrate, and it will not affect the distance sensor at this time. Ranging function.
  • the orthographic projection of the hollow pattern on the base substrate covers the orthographic projection of the distance sensor on the base substrate, so as to prevent the signal sent by the distance sensor from affecting the operation of the display element.
  • the functional component 200 is a fingerprint sensor
  • only one functional unit can be included in the functional area, and there are multiple functional units, and a fingerprint sensor is correspondingly arranged in each functional unit.
  • the orthographic projections on the substrate overlap, as long as it is ensured that the light emitted by the light-emitting device can interfere with the fingerprint sensor after it irradiates the finger, so as to realize the fingerprint recognition function.
  • the functional component 200 is a near-field communication antenna
  • only one functional unit may be included in the functional area, and the blank area in the functional unit forms a hollow pattern, and the orthographic projection of the near-field communication antenna on the base substrate is located in the hollow pattern.
  • the signal radiation of the near-field communication antenna is prevented from affecting the operation of the display element.
  • the radio frequency chip can at least partially overlap with the orthographic projection of the hollow pattern in the functional area on the base substrate. At this time, the microwave signal transmitted by the radio frequency chip can pass through the hollow pattern in the functional area.
  • the frequency is selected to realize the radiation of microwave signals in a specific frequency band.
  • the electronic device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator, and the embodiments of the present invention are not limited thereto.

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Abstract

一种显示基板及电子装置，属于显示技术领域。显示基板具有显示区，显示区包括功能区和主显示区(Q1)；功能区具有至少一个功能单元；功能单元具有空白区(Q21)、绕线区(Q22)和电路区(Q23)；显示基板包括：衬底基板，设置在衬底基板上的多层导电层；多层导电层形成至少一个镂空图案，且一个空白区(Q21)形成有一个镂空图案；多层导电层包括第一信号线(21)，且第一信号线(21)包括位于主显示区(Q1)的第一线段(211)、位于电路区(Q23)的第二线段(212)，以及位于绕线区(Q22)的第三线段(213)；其中，第一线段(211)和第二线段(212)的延伸方向相同，第三线段(213)将第一线段(211)和第二线段(212)电连接，且第三线段(213)至少包括两个延伸方向不同的子线段(213a、213b)。

Description

显示基板及电子装置 技术领域
本公开属于显示技术领域，具体涉及一种显示基板及电子装置。
背景技术
随着科技的进步，近年来，异形屏以及全面屏已经逐渐走入大家的视野。不论是异形屏还是全面屏目的都是为了提升显示设备的屏占比。那么，为了实现更高的屏占比，在显示屏的一些位置上需要为一些附加部件(例如摄像头、传感器等等)预留一些开口区域(例如开孔)。
随着显示器技术发展和更新换代，有机电致发光显示器件(Organic Electroluminance Display，简称为：OLED)由于具有自发光、高亮度、高对比度、低工作电压、可制作柔性显示器等特点，已经逐渐成为显示领域的主流产品。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板及电子装置。
第一方面，本公开实施例提供一种显示基板，其具有显示区，所述显示区包括功能区和环绕所述功能区的主显示区；所述功能区具有至少一个功能单元；所述功能单元具有空白区、绕线区和电路区；所述显示基板包括：衬底基板，设置在所述衬底基板上的多层导电层；所述多层导电层形成至少一个镂空图案，且一个所述空白区形成有一个所述镂空图案；
所述多层导电层包括第一信号线，且所述第一信号线包括位于所述主显示区的第一线段、位于所述电路区的第二线段，以及位于所述绕线区的第三线段；其中，
所述第一线段和所述第二线段的延伸方向相同，所述第三线段将所述第一线段和所述第二线段电连接，且所述第三线段至少包括两个延伸方向不同的子线段。
其中，在所述功能单元中，所述绕线区环绕所述空白区，所述电路区环绕所述绕线区；所述第一信号线的第一线段、第二线段和第三线段直接电连接。
其中，所述多层导电层包括设置在所述衬底基板上的第一导电层、第二导电层；
所述第一导电层包括主体部分沿第一方向延伸的第一类信号线，所述第一类信号线包括第一子类信号线和第二子类信号线；所述第一子类信号线仅位于所述主显示区；所述第二子类信号线位于所述主显示区和所述绕线区；
所述第二导电层包括主体部分沿第二方向延伸的第二类信号线，所述第二类信号线包括第三子类信号线和第四子类信号线；所述第三子类信号线仅位于所述主显示区；所述第四子类信号线位于所述主显示区和所述绕线区；
所述第一信号线包括所述第二子类信号线和/或所述第四子类信号线。
其中，所述第三线段包括沿所述第一方向延伸的第一子线段和沿所述第二方向延伸的第二子线段。
其中，所述第三线段中的所述第一子线段和所述第二子线段直接电连接。
其中，所述第一导电层包括第一子线段，所述第二导电层包括第二子线段，所述第三线段中的所述第一线段和所述第二子线段通过贯穿层间绝缘层的过孔电连接。
其中，当所述信号线为所述第二子类信号线时，各所述第二子类信号线以贯穿所述功能区中心、且沿所述第一方向延伸的直线为对称轴，呈镜像对称设置；
当所述信号线为所述第四子类信号线时，各所述第四子类信号线以贯穿所述功能区中心、且沿所述第二方向延伸的直线为对称轴，呈镜像对称设置。
其中，所述第一类信号线包括栅线、复位信号线、发光控制线中的至少一种。
其中，所述第二类信号线包括数据线、初始信号线、电源信号线中的至少一种。
其中，所述第三信号线之间的间距小于所述第一信号线段之间的间距。
其中，所述显示基板还包括位于所述主显示区和所述电路区中的像素驱动电路；所述主显示区中的像素驱动电路的分布密度与所述电路区中的分布密度相同。
其中，所述显示基板还包括位于所述主显示区和所述功能区的中发光器件；所述发光器件均包括设置在所述衬底基板上的阳极；对于同一发光颜色的发光器件，位于所述主显示区中的发光器件的阳极的面积小于位于所述功能区中的发光器件的阳极的面积。
其中，部分所述发光器件的阳极覆盖所述空白区。
第二方面，本公开实施例一种电子装置，其包括显示基板和功能组件，所述功能组件位于所述显示基板背离出光面的一侧；其中，所述显示基板具有显示区，所述显示区包括功能区和环绕所述功能区的主显示区；所述功能区具有至少一个功能单元；所述功能单元具有空白区、绕线区和电路区；所述显示基板包括：衬底基板，设置在所述衬底基板上的多层导电层；所述多层导电层形成至少一个镂空图案，且一个所述空白区形成有一个所述镂空图案；
所述多层导电层包括第一信号线，且所述第一信号线包括位于所述主显示区的第一线段、位于所述电路区的第二线段，以及位于所述绕线区的第三线段；
所述第一线段和所述第二线段的延伸方向相同，所述第三线段将所述第一线段和所述第二线段电连接，且所述第三线段至少包括两个延伸方向不同的子线段；
所述功能组件与所述镂空图案至少部分交叠。
其中，在所述功能单元中，所述绕线区环绕所述空白区，所述电路区环绕所述绕线区；所述第一信号线的第一线段、第二线段和第三线段直接电连 接。
其中，所述多层导电层包括设置在所述衬底基板上的第一导电层、第二导电层；
所述第一导电层包括主体部分沿第一方向延伸的第一类信号线，所述第一类信号线包括第一子类信号线和第二子类信号线；所述第一子类信号线仅位于所述主显示区；所述第二子类信号线位于所述主显示区和所述绕线区；
所述第二导电层包括主体部分沿第二方向延伸的第二类信号线，所述第二类信号线包括第三子类信号线和第四子类信号线；所述第三子类信号线仅位于所述主显示区；所述第四子类信号线位于所述主显示区和所述绕线区；
所述第一信号线包括所述第二子类信号线和/或所述第四子类信号线；
所述功能组件与所述第一信号线在所述衬底基板上的正投影无重叠。
其中，所述第三线段包括沿所述第一方向延伸的第一子线段和沿所述第二方向延伸的第二子线段。
其中，所述第三线段中的所述第一子线段和所述第二子线段为直接电连接。
其中，所述第一导电层包括第一子线段，所述第二导电层包括第二子线段，所述第三线段中的所述第一线段和所述第二子线段通过贯穿层间绝缘层的过孔电连接。
其中，当所述信号线为所述第二子类信号线时，各所述第二子类信号线以贯穿所述功能区中心、且沿所述第一方向延伸的直线为对称轴，呈镜像对称设置；
当所述信号线为所述第四子类信号线时，各所述第四子类信号线以贯穿所述功能区中心、且沿所述第二方向延伸的直线为对称轴，呈镜像对称设置。
其中，所述第一类信号线包括栅线、复位信号线、发光控制线中的至少一种。
其中，所述第二类信号线包括数据线、初始信号线、电源信号线中的至 少一种。
其中，所述第三信号线之间的间距小于所述第一信号线段之间的间距。
其中，所述显示基板还包括位于所述主显示区和所述电路区中的像素驱动电路；所述主显示区中的像素驱动电路的分布密度与所述电路区中的分布密度相同。
其中，所述显示基板还包括位于所述主显示区和所述功能区的中发光器件，且位于所述主显示区中的发光器件的分布密度大于位于所述功能区中的发光器件的分布密度。
其中，所述显示基板还包括位于所述主显示区和所述功能区的中发光器件；所述发光器件均包括设置在所述衬底基板上的阳极；对于同一发光颜色的发光器件，位于所述主显示区中的发光器件的阳极的面积小于位于所述功能区中的发光器件的阳极的面积。
其中，部分所述发光器件的阳极部分覆盖所述空白区；所述功能组件与所述阳极在所述衬底基板上的正投影无重叠。
附图说明
图1为一种显示基板的各区域分布示意图。
图2a为一种显示基板的平面结构示意图。
图2b为另一种显示基板的平面结构示意图。
图3为一种显示基板的剖面结构示意图。
图4为一种像素驱动电路的等效电路图。
图5为本公开显示基板形成半导体层图案后的示意图。
图6a为本公开显示基板形成第一导电层图案后的示意图.
图6b为图6a中第一导电层的平面示意图。
图7a为本公开显示基板形成第四导电层图案后的示意图。
图7b为图7a中第四导电层的平面示意图。
图8a为本公开显示基板形成第四绝缘层图案后的示意图。
图8b为图8a中多个过孔的平面示意图。
图9a为本公开显示基板形成第三导电层图案后的示意图。
图9b为图9a中第三导电层的平面示意图。
图10a为本公开显示基板形成第一平坦层图案后的示意图。
图10b为图10a中多个过孔的平面示意图。
图11a为本公开显示基板形成一种第二导电层图案后的示意图。
图11b为图11a中第二导电层的平面示意图。
图12a为本公开显示基板形成第二平坦层图案后的示意图。
图12b为图12a中多个过孔的平面示意图。
图13a为本公开显示基板形成阳极图案后的示意图。
图13b为图13a中阳极的平面示意图。
图14a为本公开实施例的一种显示基板的局部示意图。
图14b为图14a中的第一扫描信号线的示意图。
图15为本公开实施例的一种显示基板的局部示意图。
图16为本公开实施例的一种显示基板的局部示意图。
图17为本公开实施例的一种显示基板的局部示意图。
图18a为本公开实施例的一种显示基板的局部示意图。
图18b为图18a中的一种第一扫描信号线的示意图。
图18c为图18a中的另一种第一扫描信号线的示意图。
图19为本公开实施例的一种显示基板的局部示意图。
图20为本公开实施例的一种显示基板的局部示意图。
图21为本公开实施例的一种电子装置的示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示技术的发展，用户对显示面板的功能要求越来越多，例如：在显示面板的显示区中集成一系列的功能元件，也即在原有的显示面板中预先设置功能区，以便后续形成功能元件，如图1所示。但是为了保证显示区中不会因为设置功能元件而造成显示面板的显示均一性受到影响，因此，在功能区中依旧会设置显示元件，例如：像素驱动电路、发光器件等。但应当理解的是，功能区中设置的显示元件不能够对功能元件的工作造成影响。也就是说，位于功能区中的像素驱动电路、发光器件等之间的间距将会限定出功能元件所在的空白区。由于功能区中的空白区的设置，则导致该位置无法设置像素驱动电路和发光器件设置，进而导致位于空白区两相对侧的信号线无法贯穿空白区连接，进而导致位于功能区中的显示元件无法正常工作。
针对上述问题，在本公开实施例中提供一种显示基板结构。为了更清楚本公开实施例的显示基板结构，首先对显示基板中的所采用的像素驱动电路和发光器件，以及像素驱动电路和发光器件的膜层关系进行说明。
图2a和图2b为一种显示基板的平面结构示意图。在示例性实施方式中， 显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括一个出射第一颜色光线的第一子像素P1、一个出射第二颜色光线的第二子像素P2和二个出射第三颜色光线的第三子像素P3和第四子像素P4，四个子像素可以均包括像素驱动电路和发光器件，像素驱动电路可以包括扫描信号线、数据信号线和发光信号线，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在一些示例中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形。在一种示例性实施方式中，四个子像素可以采用正方形(Square)方式排列，形成GGRB像素排布，如图2a所示。在另一种示例性实施方式中，四个子像素可以采用钻石形(Diamond)方式排列，形成RGBG像素排布，如图2b所示。在其它示例性实施方式中，四个子像素可以采用水平并列或竖直并列等方式排列。在示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在一些示例中，水平方向依次设置的多个子像素称为像素行，竖直方向依次设置的多个子像素称为像素列，多个像素行和多个像素列构成阵列排布的像素阵列。
图3为一种显示基板的剖面结构示意图，示意了显示基板三个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底一侧的发光结构层103以及设置在发光结构层103远离基底一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此 不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括多个信号线和像素驱动电路，像素驱动电路可以包括多个晶体管和存储电容，图3中仅以一个驱动晶体管210和一个存储电容211为例进行示意。每个子像素的发光结构层103可以包括构成发光器件的多个膜层，多个膜层可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠层设置的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层和电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层和电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层和电子阻挡层可以有少量的交叠，或者可以是隔离的。
在一些示例中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。图4为一种像素驱动电路的等效电路示意图。如图4所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，像素驱动电路分别与7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管T1的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压 输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第二扫描信号线S2连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第二扫描信号线S2时，第七晶体管T7将初始电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能 的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在衬底基板上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一些示例中，以八个像素驱动电路(2个单元行4个单元列)为例， 驱动电路层的制备过程可以包括如下操作。
(1)形成半导体层图案。在一些示例中，形成半导体层图案可以包括：在衬底基板上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖衬底基板的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图5所示。
在一些示例中，每个像素驱动电路的半导体层可以包括第一晶体管T1的第一有源层11至第七晶体管T7的第七有源层17，且第一有源层11至第七有源层17为相互连接的一体结构，每个单元列中第M行像素驱动电路的第六有源层16与第M+1行像素驱动电路的第七有源层17相互连接，即每个单元列中相邻像素驱动电路的半导体层为相互连接的一体结构。
(2)形成第一导电层图案。在一些示例中，形成第一导电层图案可以包括：在形成前述图案的衬底基板上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、发光控制线23和第一极板24，如图6a和图6b所示，图6b为图6a中第一导电层的平面示意图。
结合图5至图6b所示，第一扫描信号线21、第二扫描信号线22和发光控制线23可以主体部分沿第一方向X延伸。第M行S2像素驱动电路中的第一扫描信号线21和第二扫描信号线22位于本像素驱动电路的第一极板24远离第M+1行像素驱动电路的一侧，第二扫描信号线22位于本像素驱动电路的第一扫描信号线21远离第一极板24的一侧，发光控制线23可以位于本像素驱动电路的第一极板24靠近第M+1行像素驱动电路的一侧。
在一些示例中，第一极板24可以为矩形状，矩形状的角部可以设置倒角，第一极板24在衬底基板上的正投影与第三晶体管T3的第三有源层在衬底基板上的正投影存在重叠区域。在示例性实施例中，第一极板24可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在一些示例中，第一扫描信号线21与第二有源层12相重叠的区域作为 第二晶体管T2的栅电极，第一扫描信号线21设置有向第二扫描信号线22一侧凸起的栅极块21-1，栅极块21-1在衬底基板上的正投影与第二有源层12在衬底基板上的正投影存在重叠区域，形成双栅结构的第二晶体管T2。第一扫描信号线21与第四有源层14相重叠的区域作为第四晶体管T4的栅电极。第二扫描信号线22与第一有源层11相重叠的区域作为双栅结构的第一晶体管T1的栅电极，第二扫描信号线22与第七有源层17相重叠的区域作为第七晶体管T7的栅电极，发光控制线23与第五有源层15相重叠的区域作为第五晶体管T5的栅电极，发光控制线23与第六有源层16相重叠的区域作为第六晶体管T6的栅电极。
在一些示例中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第七有源层的第一区和第二区均被导体化。
(3)形成第四导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的衬底基板上，依次沉积第三绝缘薄膜和第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，第二导电层图案至少包括：第一初始信号线31、第二极板32、屏蔽电极33和极板连接线35，如图7a和图7b所述，图7b为图7a中第四导电层的平面示意图。
结合图5至图7b所示，第一初始信号线31可以主体部分沿第一方向X延伸，第M行像素驱动电路中的第一初始信号线31位于本像素驱动电路的第二扫描信号线22远离第M+1行像素驱动电路的一侧，第二极板32作为存储电容的另一个极板，位于本像素驱动电路的第一扫描信号线21和发光控制线23之间，屏蔽电极33位于本像素驱动电路的第二扫描信号线22与第一扫描信号线21(不包含栅极块21-1的主体部分)之间，屏蔽电极33配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在一些示例中，第二极板32的轮廓可以为矩形状，矩形状的角部可以 设置倒角，第二极板32在衬底基板上的正投影与第一极板24在衬底基板上的正投影存在重叠区域，第一极板24和第二极板32构成像素驱动电路的存储电容。第二极板32上设置有开口34，开口34可以位于第二极板32的中部。开口34可以为矩形，使第二极板32形成环形结构。开口34暴露出覆盖第一极板24的第三绝缘层，且第一极板24在衬底基板上的正投影包含开口34在衬底基板上的正投影。在示例性实施例中，开口34配置为容置后续形成的第一过孔，第一过孔位于开口34内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极与第一极板24连接。
在示例性实施例中，极板连接线35设置在第一方向X上或第一方向X的反方向上相邻像素驱动电路的第二极板32之间，极板连接线35的第一端与本像素驱动电路的第二极板32连接，极板连接线35的第二端沿着第一方向X或者第一方向X的反方向延伸，并与相邻像素驱动电路的第二极板32连接，即极板连接线35配置为使一单元行上相邻像素驱动电路的第二极板相互连接。在示例性实施例中，通过极板连接线35可以使一单元行中多个像素驱动电路的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，保证一单元行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
(4)形成第四绝缘层图案。在示例性实施例中，形成第四绝缘层图案可以包括：在形成前述图案的衬底基板上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，每个像素驱动电路中设置有多个过孔，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8和第九过孔V9，如图8a和图8b所示，图8b为图8a中多个过孔的平面示意图。
结合图5至图8b所示，第一过孔V1位于第二极板32的开口34内，第一过孔V1在衬底基板上的正投影位于开口34在衬底基板上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一 极板24的表面。第一过孔V1配置为使后续形成的第一晶体管T1的第二极与通过该过孔与第一极板24连接。
在一些示例中，第二过孔V2位于第二极板32在衬底基板上的正投影的范围之内，第二过孔V2在衬底基板上的正投影位于第二极板32在衬底基板上的正投影的范围之内，第二过孔V2内的第四绝缘层被刻蚀掉，暴露出第二极板32的表面。第二过孔V2配置为使后续形成的第一电源线通过该过孔与第二极板32连接。在一些示例中，作为电源过孔的第二过孔V2可以包括多个，多个第二过孔V2可以沿着第二方向Y依次排列，以增加第一电源线与第二极板32的连接可靠性。
在一些示例中，第三过孔V3在衬底基板上的正投影位于第五有源层在衬底基板上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面。第三过孔V3配置为使后续形成的第一电源线通过该过孔与第五有源层连接。
在一些示例中，第四过孔V4在衬底基板上的正投影位于第六有源层在衬底基板上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面。第四过孔V4配置为使后续形成的第六晶体管T6的第二极通过该过孔与第六有源层连接，以及使后续形成的第七晶体管T7的第二极通过该过孔与第七有源层连接。
在一些示例中，第五过孔V5在衬底基板上的正投影位于第四有源层在衬底基板上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面。第五过孔V5配置为使后续形成的数据信号线通过该过孔与第四有源层连接，第五过孔V5称为数据写入孔。
在一些示例中，第六过孔V6在衬底基板上的正投影位于第二有源层在衬底基板上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第一区(也是第一有源层的 第二区)的表面。第六过孔V6配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一有源层连接，以及使后续形成的第二晶体管T2的第一极通过该过孔与第二有源层连接。
在一些示例中，第七过孔V7在衬底基板上的正投影位于第七有源层在衬底基板上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区(也是第一有源层的第一区)的表面。第七过孔V7配置为使后续形成的第七晶体管T7的第一极通过该过孔与第七有源层连接，以及使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层连接。
在一些示例中，第八过孔V8在衬底基板上的正投影位于屏蔽电极33在衬底基板上的正投影的范围之内，第八过孔V8内的第四绝缘层被刻蚀掉，暴露出屏蔽电极33的表面。第八过孔V8配置为使后续形成的第一电源线通过该过孔与屏蔽电极33连接。
在一些示例中，第九过孔V9在衬底基板上的正投影位于第一初始信号线31在衬底基板上的正投影的范围之内，第九过孔V9内的第四绝缘层被刻蚀掉，暴露出第一初始信号线31的表面。第九过孔V9配置为使后续形成的第七晶体管T7的第一极(也是第一晶体管T1的第一极)通过该过孔与第一初始信号线31连接。
(5)形成第三导电层图案。在一些示例中，形成第三导电层可以包括：在形成前述图案的衬底基板上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，第三导电层至少包括：第一电源线41、数据连接电极42、第一连接电极43、第二连接电极44和第三连接电极45，如图9a和图9b所示，图9b为图9a中第三导电层的平面示意图。
结合图5至图9b所示，第一电源线41主体部分沿着第二方向Y延伸，第一电源线41一方面通过第二过孔V2与第二极板32连接，另一方面通过第三过孔V3与第五有源层连接，又一方面通过第八过孔V8与屏蔽电极33 连接，使屏蔽电极33和第二极板32具有与第一电源线41相同的电位。由于屏蔽电极33与第一电源线41连接，且屏蔽电极33的至少部分区域(如屏蔽电极33右侧的突出部)在衬底基板上的正投影位于第一连接电极43(作为第一晶体管T1的第二极和第二晶体管T2的第一极，即第二节点N2)在衬底基板上的正投影与后续形成的数据信号线在衬底基板上的正投影之间，可以有效屏蔽了数据电压跳变对像素驱动电路中关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在一些示例中，屏蔽电极33的至少部分区域在衬底基板上的正投影可以与后续形成的数据信号线在衬底基板上的正投影至少部分重叠。在示例性实施例中，第一方向X上相邻像素驱动电路中的屏蔽电极33可以相互连接，以降低电阻。
在一些示例中，数据连接电极42通过第五过孔V5与第四有源层的第一区连接，数据连接电极42配置为与后续形成的数据信号线连接。
在一些示例中，第一连接电极43沿着第二方向Y延伸，其第一端通过第六过孔V6与第一有源层的第二区(也是第二有源层的第一区)连接，其第二端通过第一过孔V1与第一极板24连接，使第一极板24、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位。在示例性实施例中，第一连接电极43可以作为第一晶体管T1的第二极和第二晶体管T2的第一极。
在一些示例中，第二连接电极44的第一端通过第九过孔V9与第一初始信号线31连接，其第二端通过第七过孔V7与第七有源层的第一区(也是第一有源层的第一区)连接，使第七晶体管T7的第一极和第一晶体管T1的第一极具有与第一初始信号线31相同的电位。
在一些示例中，第三连接电极45通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接，使第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位。在示例性实施例中，第三连接电极45可以作为第六晶体管T6的第二极和第七晶体管T7的第二极。在一些示例中， 第三连接电极45配置为与后续形成的阳极连接电极连接。
(6)形成第一平坦层图案。在示例性实施例中，形成第一平坦层图案可以包括：在形成前述图案的衬底基板上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第三导电层的第一平坦层，第一平坦层上设置有第十一过孔V11、和第十二过孔V12，如图10a和图10b所示，图10b为图10a中多个过孔的平面示意图。
结合图5至图10b所示，第十一过孔V11在衬底基板上的正投影位于数据连接电极42在衬底基板上的正投影的范围之内，第十一过孔V11内的第一平坦层被去掉，暴露出数据连接电极42的表面，第十一过孔V11配置为使后续形成的数据信号线通过该过孔与数据连接电极42连接。
在一些示例中，第十一过孔V11可以是条形状，第十一过孔V11中第二方向Y的延伸长度大于第一方向X的延伸长度。本公开通过将第十一过孔V11设置沿着第二方向Y延伸的条形状，可以减小第十一过孔V11第一方向X上的宽度，可以减少后续形成的阳极的倾斜程度。
第十二过孔V12在衬底基板上的正投影位于第三连接电极45在衬底基板上的正投影的范围之内，第十二过孔V12内的第一平坦层被去掉，暴露出第三连接电极45的表面，第十二过孔V12配置为使后续形成的阳极连接电极通过该过孔与第三连接电极45连接。
(7)形成第二导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的衬底基板上，沉积第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，第四导电层至少包括：数据信号线51和阳极连接电极52，如图11a和图11b所示，图11b为图11a中第四导电层的平面示意图。
结合图5至图11b所示，数据信号线51设置在每个单元列中。数据信号线51可以沿着第二方向Y延伸，数据信号线51通过第十一过孔V11与数据连接电极42连接。由于数据连接电极42通过第五过孔V5与第四有源层的第一区连接，因而实现了数据信号线51通过数据连接电极42与第四有 源层的第一区连接，将数据信号写入第四晶体管T4。
在一些示例中，阳极连接电极52设置在至少部分像素驱动电路中。阳极连接电极52通过第十二过孔V12与第三连接电极45连接。由于第三连接电极45通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接，因而实现了阳极连接电极53通过第三连接电极45与第六有源层的第二区(也是第七有源层的第二区)连接。
(8)形成第二平坦层图案。在示例性实施例中，形成第二平坦层图案可以包括：在形成前述图案的衬底基板上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层的第二平坦层，第二平坦层上设置有第十三过孔V13，如图12a和图12b所示，图12b为图12a中多个过孔的平面示意图。
结合图5至图12b所示，第十三过孔V13在衬底基板上的正投影位于阳极连接电极53在衬底基板上的正投影的范围之内，第十三过孔V13内的第二平坦层被去掉，暴露出阳极连接电极52的表面，第十三过孔V13配置为使后续形成的阳极通过该过孔与阳极连接电极52连接。
至此，在衬底基板上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个像素驱动电路，每个像素驱动电路可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、发光控制线、数据信号线、第一电源线、第一初始信号线。在垂直于显示基板的平面内，驱动电路层可以包括在衬底基板上依次叠设的第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第一平坦层、第四导电层和第二平坦层。
(9)形成阳极图案。在一些示例中，形成阳极图案可以包括：在形成前述图案的衬底基板上，沉积第五导电薄膜，采用图案化工艺对第五导电薄膜进行图案化，形成设置在第二平坦层上的阳极图案，阳极形成GGRB像素排布，如图13a和图13b所示，图13b为图13a中阳极的平面示意图。
结合图5至图13b所示，阳极图案可以包括红色发光器件的第一阳极 71A、蓝色发光器件的第二阳极71B、第一绿色发光器件的第三阳极71C和第二绿色发光器件的第四阳极71D，第一阳极71A所在区域可以形成出射红色光线的红色子像素R，第二阳极71B所在区域可以形成出射蓝色光线的蓝色子像素B，第三阳极71C所在区域可以形成出射绿色光线的第一绿色子像素G1，第四阳极71D所在区域可以形成出射绿色光线的第二绿色子像素G2，红色子像素R和蓝色子像素B沿着第二方向Y依次设置，第一绿色子像素G1和第二绿色子像素G2沿着第二方向Y依次设置，第一绿色子像素G1和第二绿色子像素G2分别设置在红色子像素R和蓝色子像素B第一方向X的一侧，红色子像素R、蓝色子像素B、第一绿色子像素G1和第二绿色子像素G2组成一个像素单元。
在一些示例中，一个像素单元中，第一阳极71A通过第M行第N列像素驱动电路中的第十三过孔V13与该像素驱动电路中的阳极连接电极52连接，第二阳极71B通过第M+1行第N列像素驱动电路中的第十三过孔V13与该像素驱动电路中的阳极连接电极52连接，第三阳极71C通过第M行第N+1列像素驱动电路中的第十三过孔V13与该像素驱动电路中的阳极连接电极52连接，第四阳极71D通过第M+1行第N+1列像素驱动电路中的第十三过孔V13与该像素驱动电路中的阳极连接电极52连接。另一个像素单元中，第一阳极71A通过第M+1行第N+2列像素驱动电路中的第十三过孔V13与该像素驱动电路中的阳极连接电极52连接，第二阳极71B通过第M行第N+2列像素驱动电路中的第十四过孔V14与该像素驱动电路中的阳极连接电极52连接，第三阳极71C通过第M+1行第N+3列像素驱动电路中的第十三过孔V13与该像素驱动电路中的阳极连接电极52连接，第四阳极71D通过第M行第N+3列像素驱动电路中的第十三过孔V13与该像素驱动电路中的阳极连接电极53连接。
在形成完发光器件的阳极图案后还包括形成像素限定层、发光层、封装层等结构，以形成发光结构层的多个发光器件。对于发光器件的形成工艺可以采用常规的工艺步骤，故在此不再详细赘述。
在一些示例中，衬底基板可以是柔性衬底基板，或者可以是刚性衬底基 板。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性衬底基板可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高衬底基板的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在一些示例中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高衬底基板的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层。有源层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。第一平坦层和第二平坦层可以采用有机材料，如树脂等。
如前所述，可以看出的是，显示基板上的信号线包括主体部分沿第一方向延伸的第一扫描信号线、第二扫描信号线、发光控制线、第一初始信号线，以及主体部分沿第二方向延伸的数据线、第一电源线，当在显示基板的显示区预留空白区以形成功能元件时，这些信号线势必要进行绕线设计或者断线设计，以便于显示基板中的像素驱动电路提供信号。在本公开实施例中，提 供一种显示区中设置功能区的显示基板，该显示基板与上述基板相类似的是，同样包括上述的各个膜层，其中信号线可以包括上述的第一扫描信号线、第二扫描信号线、发光控制线、第一初始信号线、数据线、第一电源线中的至少一种。以下对本公开实施例的显示基板进行具体介绍。
第一方面，本公开实施例提供一种显示基板，该显示基板具有显示区，显示区中包括功能区和主显示区。功能区中具有至少一个功能单元；每个功能单元均具有空白区、绕线区和电路区。其中，绕线区环绕至少部分空白区，功能单元中处空白区和绕线区外的其他区域均为电路区。该显示基板包括衬底基板，设置在衬底基板上的多层导电层，例如包括上述的第一导电层至第五导电层。本公开实施例中的多层导电层形成至少一个镂空图案，且在空白区中设置有镂空图案。多层导电层包括第一信号线，且第一信号线包括位于所述主显示区的第一线段、位于电路区的第二线段，以及位于所述绕线区的第三线段；其中，第一线段和第二线段的延伸方向相同，第三线段将第一线段和第二线段电连接，且第三线段至少包括两个延伸方向不同的子线段。
例如：显示基板包括主体部分沿第一方向延伸的第一类信号线，第一类信号线包括但不限于上述的第一扫描信号线、第二扫描信号线、发光控制线和第一初始信号线。第一类信号线包括第一子类信号线和第二子类信号线。第一子类信号线仅包括位于主显示区的部分；第二子类信号线包括不仅包括位于主显示区的部分，而且还包括位于功能区中的部分。其中，第二子类信号线可以上述的第一信号线。为了便于理解，以第一类信号线为第二扫描信号线为例，此时包括位于主显示区和功能区的第二扫描信号线则位于第一信号线。该第一信号线的第一线段和第二线段均沿第一方向延伸，第三线段不仅包括沿第一方向延伸的子线段，而且还包括沿第二方向延伸的子线段。同理，位于主显示区和功能区的第一扫描信号线、发光控制线和第一初始信号线，也可以按照位于主显示区和功能区的第二扫描信号线的设置方式进行设置。
再例如：显示基板包括主体部分沿第二方向延伸的第二类信号线，第二类信号线包括但不限于数据线和第一电源线。第二类信号线包括第三子类信 号线和第四类信号线；第三子类信号线仅包括位于主显示区的部分；第四子类信号线不仅包括主显示区的部分还包括位于功能区的部分。其中，第四子类信号线可以为上述的第一信号线。为了便于理解，以第二类信号线为数据线为例，此时位于主显示区和功能区的数据线则为第一信号线。该第一信号线的第一线段和第二线段沿第二方向延伸，第三线段不仅包括沿第一方向延伸的子线段，而且还包括沿第二方向延伸的子线段。同理，包括位于主显示区部分和位于功能区部分的第一电源线，也可以按照位于显示区和功能区的数据线的设置方式进行设置。
为了更清楚本公开实施例中的第一信号线的结构，以下结合具体示例进行说明。为了便于理解，在下述描述中，分别以第一信号线为位于主显示区和功能区的第二扫描信号线(以下将该种第一信号线简称为第二扫描信号线)，以及位于主显示区和功能区的数据线(以下将该种第一信号线简称为数据线)为例。
第一种示例：参照图14a和图14b，功能单元的空白区Q21中形成的镂空图案为矩形或者类型矩形，绕线区Q22环绕空白区Q21设置，绕线区Q22为矩形环，剩余位置则为功能单元的电路区Q23，图14a中以空白区Q21第一方向X上的长度小于其第二方向Y上长度，也即空白区Q21为“1”字型。其中，仅在电路区Q23设置像素驱动电路。第一扫描信号线21的第一线段位于主显示区Q1，第二线段位于电路区Q23，二者均沿第一方向X延伸，且连接在同一直线上的第一线段211和第二线段212电连接。第一扫描信号线21的第三线段213包括沿第一方向X延伸的第一子线段213a和沿第二方向Y延伸的第二子线段213b。由于镂空图案为矩形或者类型矩形，任一第一扫描信号线21的第三线段包括一条第一子线段213a和两条第二子线段213b，且第一子线段213a的两端分别连接这两个第二子线段213b。第一子线段213a位于空白区Q21在第二方向Y上的一侧，两个第二子线段213b分别位于空白区Q21在第一方向X的两相对侧。另外，需要说明的是，第一扫描信号线21的第二线段可以由电路区Q23延伸至绕线区Q22与第三线段213的第二子线段213b电连接。
在一些示例中，包括位于主显示区Q1的部分和功能区的部分的第一扫描信号线21为多条，此时多条第一扫描信号线21以在第一方向X上贯穿空白区Q21中心的直线为对称轴，呈镜像对称。也就是说，一半的第一扫描信号线21由空白区Q21的上侧进行绕线，另一半第一扫描信号线21由空白区Q21的下侧进行绕线。
相应的，如图15所示，数据线51的第一线段位于主显示区Q1，第二线段位于电路区Q23，二者均沿第二方向Y延伸，且在第二方向Y位于同一条直线的第一线段和第二线段电连接。数据线51的第三线段包括两条第一子线段和一条第二子线段，且第二子线段的两端分别连接这两个第一子线段。两条第一子线段沿第一方向X延伸，分别位于空白区Q21在第二方向Y两侧，第二子线段分别空白区Q21在第一方向X的一侧。另外，需要说明的是，数据线51的第二线段可以由电路区Q23延伸至绕线区Q22与第三线段的第一子线段电连接。在一些示例中，包括位于主显示区Q1的部分和功能区的部分的数据线51为多条，此时多条数据线51以在第二方向Y上贯穿空白区Q21的直线为对称轴，呈镜像对称。也就是说一半数据线51由左侧绕线，另一半数据线51由右侧绕线。
第二种示例：与第一种示例相类似的是，区别仅在于空白区Q21的矩形为“一”字型，参照图16和图17，在空白区Q21为“一”字型时，第一扫描信号线21和数据线51的绕线方式与上述的第一种方式相同，故在此不再重复描述。
第三种示例：参照图18a所示，功能单元中的空白区Q21中所形成的镂空图案为十字型或者类似十字型，也即空白区Q21包括沿第一方向X延伸的第一空白区Q211和沿第二方向Y延伸的第二空白区Q212。绕线区Q22环绕空白区Q21，且与空白区Q21的形状相适配，此时绕线区Q22呈十字型环，并将绕线区Q22在第一方向X延伸的部分称之为第一绕线区Q22，在第二方向Y上延伸的部分称之为第二绕线区Q22。功能单元中出空白区Q21和绕线区Q22外的其余位置为电路区Q23。
具体的，参照图18b，对于第一绕线区Q22在第一方向X上延伸区域所 覆盖的主显示区Q1和电路区Q23中的像素驱动电路所连接的第一扫描信号线21，该第一扫描信号线21中的第一线段211位于主显示区Q1，第二线段212位于电路区Q23，第三线段213位于第一绕线区Q22和第二绕线区Q22。该第三线段213包括位于第一绕线区Q22、且分别位于第二绕线区Q22两侧的两条第一子线段213a，分别位于第二绕线区Q22在第一方向X的两相对侧的两条第二子线段213b，以及位于第二绕线区Q22在第二方向Y的一侧的一条第一子线段213a。第一子线段213a沿第一方向X延伸，第二子线段213b沿第二方向Y延伸。此时，第三线段213b按照位于第一绕线区Q22的第一子线段、位于第二绕线区Q22的第二子线段213b、位于第二绕线区Q22的第一子线段213a、位于第二绕线区Q22的第二子线段213b、位于第一绕线区Q22的第一子线段213a的方式依次连接。
参照图18c，对于第二绕线区Q22在第一方向X上的延伸区域所覆盖的主显示区Q1和电路区Q23中的像素驱动电路所连接的第一扫描信号线21，该第一扫描信号线21中的第一线段211位于主显示区Q1，第二线段212位于电路区Q23，第三线段213位于第二绕线区Q22。具体的，该第一扫描信号线21的第三线段213包括分别位于第二绕线区Q22在第一方向X上的两相对侧的两条第二子线段213b，以及位于第二方向Y一侧的第一子线段213a，第一子线段213a将两条第二子线段213b电连接。第一子线段213a沿第一方向X延伸，第二子线段213b沿第二方向Y延伸。另外，需要说明的是，该第一扫描信号线21的第二线段212可以由电路区Q23延伸至绕线区Q22与第三线段的第二子线段212电连接。
在一些示例中，包括位于主显示区Q1的部分和功能区的部分的第一扫描信号线21为多条，此时多条第一扫描信号线21以在第一方向X上贯穿空白区Q21中心的直线为对称轴，呈镜像对称。也就是说，一半的第一扫描信号线21由空白区Q21的上侧进行绕线，另一半第一扫描信号线21由空白区Q21的下侧进行绕线。
相应的，参照图19，对于第二绕线区Q22在第二方向Y上延伸区域所覆盖的主显示区Q1和电路区Q23中的像素驱动电路所连接的数据线51，该 数据线51的第一线段位于主显示区Q1，第二线段位于电路区Q23，第三线段位于第一绕线区Q22和第二绕线区Q22。该第三线段包括位于第二绕线区Q22，且分别位于第一绕线区Q22的两侧的两条第二子线段，分别位于第一绕线区Q22在第二方向Y上两侧的两条第一子线段，以及位于第一绕线区Q22在第一方向X上一侧的一条第二子线段。第一子线段沿第一方向X延伸，第二子线段沿第二方向Y延伸。此时，第三线段按照位于第二绕线区Q22的第二子线段、位于第一绕线区Q22的第一子线段、位于第一绕线区Q22的第二子线段、位于第二绕线区Q22的第二子线段的方式依次连接。对于第一绕线区Q22在第二方向Y上的延伸区域，所覆盖的主显示区Q1和电路区Q23中的像素驱动电路所连接的数据线51，该数据线51的第一线段位于主显示区Q1，第二线段位于电路区Q23，第三线段位于第一绕线区Q22。具体的，该数据线51的第三线段包括分别位于第一绕线区Q22在第二方向Y的两相对的第一子线段，以及位于第一绕线区Q22在第二方向Y一侧的一条第二子线段；其中，第一子线段沿第一方向X延伸，第二子线段沿第二方向Y延伸，该第三线段按照第一子线段、第二子线段、第一子线段的方式依次连接。另外，需要说明的是，数据线51的第二线段可以由电路区Q23延伸至绕线区Q22与第三线段的第一子线段电连接。
在一些示例中，包括位于主显示区Q1的部分和功能区的部分的数据线51为多条，此时多条数据线51以在第二方向Y上贯穿空白区Q21的直线为对称轴，呈镜像对称。也就是说一般数据线51由左侧绕线，另一半数据线51由右侧绕线。
第四种示例：参照图20，每个功能单元中的空白区Q21同样包括沿第一方向X延伸的第一空白区Q211和沿第二方向Y延伸的第二空白区Q212。但第一空白区Q211和第二空白区Q212无交叉，相应的绕线区Q22包括环绕第一空白区Q211的第一绕线区Q221和环绕第二空白区Q212的第二绕线区Q222。此时，第一扫描信号线21和数据线51的在第一空白区Q211的绕线方式与第一示例相同，在第二空白区Q212的绕线方式与第二示例相同。故在此不再重复赘述。
需要说明的是，以上仅给出几种空白区Q21的形状所对应的绕线方式，在实际产品中空白区Q21的形状还可以是“工”字型，“田”字型等，由于“工”字型，“田”字型的空白区Q21均包括沿第一方向X延伸的第一空白区Q211和沿第二方向Y延伸的第二空白区Q212，因此对于这两种空白区Q21的存在，第一信号线的绕线均采用参照上述示例进行绕线。
在一些示例中，无论上述任一情况，当第一信号线的第三线段包括沿第一方向X的第一子线段和沿第二方向Y的第二子线段时，第一子线段和第二子线段均可以为一体成型结构，也即第一子线段和第二子线段直接电连接，此时，第一子线段和第二子线段采用同种材料，故二者可以在同一次构图工艺中形成。当然，在一些示例中，第三线段中的沿第一方向X延伸的第一子线段和沿第二方向Y延伸的第二子线段也可以分布在两层导电层中，例如：第一导电层中包括第一子线段，第二导电层中包括第二子线段，第一导电层和第二导电层之间设置有层间绝缘层，此时第一子线段和第二子线段可以通过贯穿层间绝缘层的过孔电连接。
在一些示例中，无论上述任一情况，第一信号线的第三线段的线间距小于第一线段之间的线间距，第一线段之间的线间距可以与等于第二线段之间的线间距。
在一些示例中，显示基板的主显示区Q1和功能区中的电路区Q23中均设置有像素驱动电路，且像素驱动电路的排布密度相同。例如，显示基板中的像素驱动电路可以呈阵列排布，仅仅是在绕线区Q22和空白区Q21中不设置像素驱动即可。在该种情况下，主显示区Q1和电路区Q23中的像素驱动电路的排布规律相同，方便像素驱动电路的制备。
在一些示例中，显示基板中不仅包括上述结构，而且还包括多个发光器件，例如OLED器件，一个像素驱动电路被配置为驱动一个发光器件进行发光。由于显示基板的功能区中的空白区Q21和绕线区Q22中未设置像素驱动电路，因此，在电路区Q23中主显示区Q1中的像素驱动电路的排布规律相同的情况下，若主显示区Q1和功能区中的同种发光颜色的阳极的面积相同的情况下，位于主显示区Q1和功能区中的发光器件的排布密度不同，具 体的，主显示区Q1中的发光器件的排布密度大于功能区中的发光器件的排布密度。需要说明的是，发光器件的排布密度是指位于同一区域内、单位面积下任一同种发光颜色的发光器件的个数。其中，个数越多密度越大。当然，当主显示区Q1的发光器件的排布密度大于功能区中的发光器件的排布密度时，主显示区Q1和功能区中发光颜色相同的发光器件的阳极的尺寸大小也可以不同，例如：功能区中的发光器件的阳极尺寸大于主显示区Q1中的发光器件的阳极尺寸。
在一些示例中，显示基板中至少部分发光器件的阳极在衬底基板上的正投影覆盖所述空白区Q21。也就是说，正投影覆盖空白区Q21的阳极图案决定了镂空图案的轮廓样式。
第二方面，图21为本公开实施例的一种电子装置的示意图；如图21所示，本公开实施例提供一种显示电子装置，该显示装置包括前述的任一显示基板100和功能组件200，功能组件200位于显示基板100背离出光面的一侧，而且在本公开实施例中功能组件200与显示基板100的功能区中镂空图案存在交叠，此时功能组件200则可以配合镂空图案实现其功能。
在一些示例中，功能组件200具体可以摄像头、距离传感器、指纹传感器、近场通信(Near Field Communication，NFC)天线和射频芯片中的至少一种等。
当功能组件200为摄像头时，功能区中可以仅包括一个功能单元，该功能单元中的空白区形成一镂空图案，该摄像头在衬底基板上的正投影位于该镂空图案在衬底基板上的正投影内，也就是说，对于显示基板100中的任一导电层中的导电元件(例如：第一扫描线、第二扫描线、数据线、发光器件的阳极等)均与摄像头在衬底基板上的正投影无重叠，从而保证摄像头的图像采集功能。
当功能组件200为距离传感器时，该电子装置可以实现测距功能，此时功能单元中的镂空图案可以与距离传感器在衬底基板上的存在部分交叠，此时并不会影响距离传感器的测距功能。优选的，镂空图案在衬底基板上正投 影覆盖距离传感器在衬底基板上的正投影，以此避免距离传感器工作时发送的信号对显示元件的工作造成影响。
当功能组件200为指纹传感器时，功能区中可以仅包括一个功能单元为多个，每个功能单元中对应设置一个指纹传感器，每个指纹传感器在衬底基板上的正投影可以与镂空图案在衬底基板上的正投影部分交叠，只要保证发光器件所发出的光照射至手指之后能够干涉值指纹传感器即可，从而实现指纹识别的功能。
当功能组件200为近场通信天线时，功能区中可以仅包括一个功能单元，该功能单元中的空白区形成一镂空图案，该近场通信天线在衬底基板上的正投影位于该镂空图案在衬底基板上的正投影内，以避免近场通信天线的信号辐射影响显示元件的工作。
当功能组件200为射频芯片时，该射频芯片可以与功能区中的镂空图案在衬底基板上的正投影至少部分交叠，此时射频芯片传输的微波信号，可以通过功能区中的镂空图案进行频率的选择，以实现特定频段的微波信号的辐射。
以上仅给出几种功能组件200，但这并不构成对本公开实施例保护范围的限制。
电子装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (28)

  1. 一种显示基板，其具有显示区，所述显示区包括功能区和环绕所述功能区的主显示区；所述功能区具有至少一个功能单元；所述功能单元具有空白区、绕线区和电路区；所述显示基板包括：衬底基板，设置在所述衬底基板上的多层导电层；所述多层导电层形成至少一个镂空图案，且一个所述空白区形成有一个所述镂空图案；
    所述多层导电层包括第一信号线，且所述第一信号线包括位于所述主显示区的第一线段、位于所述电路区的第二线段，以及位于所述绕线区的第三线段；其中，
    所述第一线段和所述第二线段的延伸方向相同，所述第三线段将所述第一线段和所述第二线段电连接，且所述第三线段至少包括两个延伸方向不同的子线段。
  2. 根据权利要求1所述的显示基板，其中，在所述功能单元中，所述绕线区环绕所述空白区，所述电路区环绕所述绕线区；所述第一信号线的第一线段、第二线段和第三线段直接电连接。
  3. 根据权利要求1所述的显示基板，其中，所述多层导电层包括设置在所述衬底基板上的第一导电层、第二导电层；
    所述第一导电层包括主体部分沿第一方向延伸的第一类信号线，所述第一类信号线包括第一子类信号线和第二子类信号线；所述第一子类信号线仅位于所述主显示区；所述第二子类信号线位于所述主显示区和所述绕线区；
    所述第二导电层包括主体部分沿第二方向延伸的第二类信号线，所述第二类信号线包括第三子类信号线和第四子类信号线；所述第三子类信号线仅位于所述主显示区；所述第四子类信号线位于所述主显示区和所述绕线区；
    所述第一信号线包括所述第二子类信号线和/或所述第四子类信号线。
  4. 根据权利要求3所述的显示基板，其中，所述第三线段包括沿所述第一方向延伸的第一子线段和沿所述第二方向延伸的第二子线段。
  5. 根据权利要求4所述的显示基板，其中，所述第三线段中的所述第 一子线段和所述第二子线段为直接电连接。
  6. 根据权利要求4所述的显示基板，其中，所述第一导电层包括第一子线段，所述第二导电层包括第二子线段，所述第三线段中的所述第一线段和所述第二子线段通过贯穿层间绝缘层的过孔电连接。
  7. 根据权利要求3所述的显示基板，其中，当所述信号线为所述第二子类信号线时，各所述第二子类信号线以贯穿所述功能区中心、且沿所述第一方向延伸的直线为对称轴，呈镜像对称设置；
    当所述信号线为所述第四子类信号线时，各所述第四子类信号线以贯穿所述功能区中心、且沿所述第二方向延伸的直线为对称轴，呈镜像对称设置。
  8. 根据权利要求3所述的显示基板，其中，所述第一类信号线包括栅线、复位信号线、发光控制线中的至少一种。
  9. 根据权利要求3所述的显示基板，其中，所述第二类信号线包括数据线、初始信号线、电源信号线中的至少一种。
  10. 根据权利要求1-9中任一项所述的显示基板，其中，所述第三信号线之间的间距小于所述第一信号线段之间的间距。
  11. 根据权利要求1-9中任一项所述的显示基板，其中，还包括位于所述主显示区和所述电路区中的像素驱动电路；所述主显示区中的像素驱动电路的分布密度与所述电路区中的分布密度相同。
  12. 根据权利要求1-9中任一项所述的显示基板，其中，还包括位于所述主显示区和所述功能区的中发光器件，且位于所述主显示区中的发光器件的分布密度大于位于所述功能区中的发光器件的分布密度。
  13. 根据权利要求1-9中任一项所述的显示基板，其中，还包括位于所述主显示区和所述功能区的中发光器件；所述发光器件均包括设置在所述衬底基板上的阳极；对于同一发光颜色的发光器件，位于所述主显示区中的发光器件的阳极的面积小于位于所述功能区中的发光器件的阳极的面积。
  14. 根据权利要求13所述的显示基板，其中，部分所述发光器件的阳极部分覆盖所述空白区。
  15. 一种电子装置，其包括显示基板和功能组件，所述功能组件位于所述显示基板背离出光面的一侧；其中，所述显示基板具有显示区，所述显示区包括功能区和环绕所述功能区的主显示区；所述功能区具有至少一个功能单元；所述功能单元具有空白区、绕线区和电路区；所述显示基板包括：衬底基板，设置在所述衬底基板上的多层导电层；所述多层导电层形成至少一个镂空图案，且一个所述空白区形成有一个所述镂空图案；
    所述多层导电层包括第一信号线，且所述第一信号线包括位于所述主显示区的第一线段、位于所述电路区的第二线段，以及位于所述绕线区的第三线段；
    所述第一线段和所述第二线段的延伸方向相同，所述第三线段将所述第一线段和所述第二线段电连接，且所述第三线段至少包括两个延伸方向不同的子线段；
    所述功能组件与所述镂空图案至少部分交叠。
  16. 根据权利要求15所述的电子装置，其中，在所述功能单元中，所述绕线区环绕所述空白区，所述电路区环绕所述绕线区；所述第一信号线的第一线段、第二线段和第三线段直接电连接。
  17. 根据权利要求15所述的电子装置，其中，所述多层导电层包括设置在所述衬底基板上的第一导电层、第二导电层；
    所述第一导电层包括主体部分沿第一方向延伸的第一类信号线，所述第一类信号线包括第一子类信号线和第二子类信号线；所述第一子类信号线仅位于所述主显示区；所述第二子类信号线位于所述主显示区和所述绕线区；
    所述第二导电层包括主体部分沿第二方向延伸的第二类信号线，所述第二类信号线包括第三子类信号线和第四子类信号线；所述第三子类信号线仅位于所述主显示区；所述第四子类信号线位于所述主显示区和所述绕线区；
    所述第一信号线包括所述第二子类信号线和/或所述第四子类信号线；
    所述功能组件与所述第一信号线在所述衬底基板上的正投影无重叠。
  18. 根据权利要求17所述的电子装置，其中，所述第三线段包括沿所 述第一方向延伸的第一子线段和沿所述第二方向延伸的第二子线段。
  19. 根据权利要求18所述的电子装置，其中，所述第三线段中的所述第一子线段和所述第二子线段为直接电连接。
  20. 根据权利要求18所述的电子装置，其中，所述第一导电层包括第一子线段，所述第二导电层包括第二子线段，所述第三线段中的所述第一线段和所述第二子线段通过贯穿层间绝缘层的过孔电连接。
  21. 根据权利要求17所述的电子装置，其中，当所述信号线为所述第二子类信号线时，各所述第二子类信号线以贯穿所述功能区中心、且沿所述第一方向延伸的直线为对称轴，呈镜像对称设置；
    当所述信号线为所述第四子类信号线时，各所述第四子类信号线以贯穿所述功能区中心、且沿所述第二方向延伸的直线为对称轴，呈镜像对称设置。
  22. 根据权利要求17所述的电子装置，其中，所述第一类信号线包括栅线、复位信号线、发光控制线中的至少一种。
  23. 根据权利要求17所述的电子装置，其中，所述第二类信号线包括数据线、初始信号线、电源信号线中的至少一种。
  24. 根据权利要求15-23中任一项所述的电子装置，其中，所述第三信号线之间的间距小于所述第一信号线段之间的间距。
  25. 根据权利要求15-23中任一项所述的电子装置，其中，还包括位于所述主显示区和所述电路区中的像素驱动电路；所述主显示区中的像素驱动电路的分布密度与所述电路区中的分布密度相同。
  26. 根据权利要求15-23中任一项所述的电子装置，其中，还包括位于所述主显示区和所述功能区的中发光器件，且位于所述主显示区中的发光器件的分布密度大于位于所述功能区中的发光器件的分布密度。
  27. 根据权利要求15-23中任一项所述的电子装置，其中，还包括位于所述主显示区和所述功能区的中发光器件；所述发光器件均包括设置在所述衬底基板上的阳极；对于同一发光颜色的发光器件，位于所述主显示区中的发光器件的阳极的面积小于位于所述功能区中的发光器件的阳极的面积。
  28. 根据权利要求27所述的电子装置，其中，部分所述发光器件的阳极部分覆盖所述空白区；所述功能组件与所述阳极在所述衬底基板上的正投影无重叠。
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CN110874990A (zh) * 2019-12-02 2020-03-10 武汉天马微电子有限公司 一种显示面板和显示装置
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