WO2021135632A1 - 发光器件及其制作方法 - Google Patents

发光器件及其制作方法 Download PDF

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Publication number
WO2021135632A1
WO2021135632A1 PCT/CN2020/126789 CN2020126789W WO2021135632A1 WO 2021135632 A1 WO2021135632 A1 WO 2021135632A1 CN 2020126789 W CN2020126789 W CN 2020126789W WO 2021135632 A1 WO2021135632 A1 WO 2021135632A1
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layer
source
substrate
pixel
drain
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PCT/CN2020/126789
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English (en)
French (fr)
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陈颖
付东
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广东聚华印刷显示技术有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • This application relates to the field of display technology, in particular to a light-emitting device and a manufacturing method thereof.
  • OLED organic light emitting display
  • the vertical channel thin film transistor (VTFT) technology has certain advantages: 1.
  • the channel length is equal to or less than the device thickness, often less than 1 micron, so it is easy to provide a larger current; 2.
  • TFT It vertically overlaps the light-emitting device and no longer takes up additional space on the panel. It is easy to achieve a higher aperture ratio, especially if the electrode with high transparency is used, it will be beneficial to realize a transparent display; 3.
  • the key channel Parameters such as length will have higher stability under the environment of repeated bending and flexible display, and it is more suitable for flexible display; 4. Because the core steps of this technology can be realized by printing, it is very suitable for printing display technology and large area production. The process is mainly controlled by the uniformity of printing, and is no longer controlled by other sensitive factors such as heating and crystallization, so as to facilitate the realization of a TFT array with uniform production performance for large-area panels.
  • the three electrodes of the gate, source and drain in the VTFT structure are vertically distributed. Therefore, it is necessary to ensure the smooth wiring of the circuit while avoiding short circuit between the top and bottom.
  • the ink dries into a film in the bank structure. Due to the lyophilicity of the ink and the bank material, it will form an edge accumulation on the bank edge. In the multi-layer structure, since this accumulation is difficult to control, a thinner film layer is often formed on the edge, as shown by the circle in Figure 1.
  • the current OLED printing is mainly based on organic materials, and the conductivity is low.
  • the edge accumulation will cause uneven thickness of the pixel edge and uneven light emission, it is acceptable.
  • the source, channel layer, and drain are printed directly in the same bank pixel pit, it is very easy to cause current crosstalk at the edge, and may even cause a short circuit due to the electrical connection of the source and the drain.
  • a light emitting device including:
  • the substrate includes a substrate, a gate layer and an insulating layer, the gate layer is disposed on the substrate, and the insulating layer is disposed on the gate layer;
  • a pixel defining layer disposed on the substrate, the pixel defining layer having pixel pits exposing the insulating layer;
  • the source layer is arranged in the pixel pit and covers the bottom of the pixel pit;
  • the barrier layer is arranged in the pixel pit and covers at least part of the inner sidewall of the pixel pit.
  • the substrate further includes a source wiring, the source wiring is exposed at the bottom edge of the pixel pit, the source layer is connected to the exposed part of the source wiring, and the barrier The layer covers at least the source wiring and the inner sidewall of the pixel defining layer corresponding to the edge position.
  • the substrate further includes a flat layer disposed on the substrate and covering the gate layer, the insulating layer, and the source wiring, and one of the flat layers
  • the side is flush with the side of the insulating layer away from the substrate, the side of the flat layer is provided with a connection groove exposing the source wiring, and the source layer extends from the insulating layer to the
  • the inner wall of the connection groove covers the exposed part of the source wiring, the connection groove covers the source layer and then forms a deposition groove, and the barrier layer fills the deposition groove and extends to the pixel defining layer On the inner wall.
  • the light emitting device further includes a channel layer, and the channel layer is disposed on the source layer.
  • the light-emitting device further includes a light-emitting functional layer, and the light-emitting functional layer is disposed on the channel layer.
  • the light-emitting device further includes a drain layer, and the drain layer is disposed on the light-emitting function layer.
  • the drain layer entirely covers the pixel defining layer, the barrier layer, and the light-emitting function layer
  • the substrate further includes a drain wiring
  • the drain layer passes through the The via hole in the pixel defining layer is connected to the drain wiring.
  • a method for manufacturing a light-emitting device includes:
  • a substrate provided with a pixel defining layer, the substrate including a substrate, a gate layer and an insulating layer, the gate layer is disposed on the substrate, and the insulating layer is disposed on the gate layer ,
  • the pixel defining layer has pixel pits exposing the insulating layer;
  • a barrier layer is formed in the pixel pit so that the barrier layer covers at least part of the inner sidewall of the pixel pit.
  • the source layer is produced by a solution method.
  • the substrate further includes a source wiring, the source wiring exposes the bottom edge of the pixel pit, and the source layer and the source wiring are exposed when the source layer is fabricated
  • the barrier layer at least covers the source wiring and the inner sidewall of the pixel defining layer corresponding to the edge position.
  • the substrate further includes a flat layer disposed on the substrate and covering the gate layer, the insulating layer, and the source wiring, and one of the flat layers
  • the side is flush with the side of the insulating layer away from the substrate, and the side of the flat layer is formed with a connecting groove exposing the source wiring, so that the source layer extends from the insulating layer to the
  • the inner wall of the connection groove covers the exposed part of the source wiring, and the connection groove covers the source layer and then forms a deposition groove, so that the barrier layer fills the deposition groove and extends to the pixel defining layer On the inner wall.
  • the above-mentioned light-emitting device and the manufacturing method thereof have the following beneficial effects:
  • the source layer is formed, at least part of the inner sidewall of the pixel pit is covered by a barrier layer to separate the edge accumulation portion of the source layer on the pixel defining layer from the subsequently formed film layer to prevent crosstalk current problems and avoid electrical connection between the source layer and the drain layer and cause a short circuit.
  • FIG. 1 is a schematic diagram of the edge accumulation of the dried film layer in the pixel pit after inkjet printing
  • FIG. 2 is a schematic diagram of the structure of a light emitting device according to an embodiment
  • FIG. 3 is a schematic diagram of the structure of a substrate and a pixel defining layer in the light emitting device shown in FIG. 2;
  • Fig. 4 is a flowchart of a manufacturing method of a light emitting device according to an embodiment.
  • the light emitting device 100 of an embodiment includes a substrate, a pixel defining layer 140, a source layer 150 and a barrier layer 160.
  • the substrate includes a substrate (not shown), a gate layer 120 and an insulating layer 130.
  • the gate layer 120 is disposed on the substrate, and the insulating layer 130 is disposed on the gate layer 120.
  • the pixel defining layer 140 is disposed on the substrate, specifically on the side of the insulating layer 130.
  • the pixel defining layer 140 has pixel pits exposing the insulating layer 130.
  • the source layer 150 is disposed in the pixel pit and covers the bottom of the pixel pit.
  • the barrier layer 160 is disposed in the pixel pit and covers at least part of the inner sidewall of the pixel pit.
  • the barrier layer 160 covers at least part of the inner sidewalls of the pixel pits to separate the edge accumulation portion of the source layer on the pixel defining layer 140 from the subsequently formed film layer to prevent the problem of crosstalk current and avoid the source layer 150 and subsequent layers.
  • the formed drain layer is electrically connected to cause a short circuit.
  • the gate layer 120 can be a metal electrode, such as aluminum, silver, copper, gold, etc., or an oxide conductive electrode, such as ITO, IZO, etc., with a thickness ranging from 5 nanometers to 50 microns.
  • the gate layer 120 can be realized by sputtering, evaporation and other technologies, and then pixelized by traditional photolithography technology.
  • the substrate further includes a gate wiring 112 for connecting the gate layer 120 to the switching TFT.
  • the gate wiring 112 can be made by conventional semiconductor technology.
  • the insulating layer 130 is used to insulate and separate the gate layer 120 and the source layer 150, and functions to block current but constitute a voltage difference.
  • the insulating layer 130 can be a metal oxide, such as SiO 2 , HfO 2 , Al 2 O 3, etc., with a thickness ranging from 5 to 1000 nanometers. It can be made by sputtering deposition, chemical vapor deposition, or atomic layer deposition. Pixelated by photolithography process.
  • the source layer 150 is the key structure of the VTFT, which can be a thin carbon nanotube layer, a porous metal electrode, a porous conductive oxide electrode, a metal nanowire, a metal nanoparticle layer, an ultra-thin metal layer (such as a silver electrode with a thickness of less than 3nm), etc. .
  • the thickness of the source layer 150 ranges from 0.5 to 20 nanometers.
  • the source layer 150 can be made by a solution method, such as jet printing, inkjet printing, blade coating, and the like. Since this layer is manufactured by a solution method, the ink should be limited between the insulating pixel defining layers 140 during the manufacturing process, and the final film formation is also separated and pixelated by the pixel defining layer 140.
  • the substrate further includes a source wiring 111, and the source wiring 111 is exposed at the bottom edge of the pixel pit.
  • the source layer 150 is connected to the exposed portion of the source wiring 111.
  • the barrier layer 160 at least covers the source wiring 111 and the inner sidewall of the pixel defining layer 140 corresponding to the edge position. Since the pixel defining layer 140 near the position of the source wiring 111 needs to be hydrophilic, so that when the source layer 150 is produced by the solution method, the solution can be spread at this position so as to be better connected to the source wiring 111, the source The electrode layer 150 has edge accumulation on the pixel defining layer 140 due to the hydrophilic property of the pixel defining layer 140.
  • the barrier layer 160 is made to cover at least the inner sidewall of the pixel defining layer 140 corresponding to the edge position, and the source layer 150 is placed on the pixel
  • the portion accumulated on the defining layer 140 is separated from the film layer to be subsequently fabricated, thereby preventing the problem of crosstalk current, and preventing the source wiring 111 from breaking down at the thin edge position and causing a short circuit.
  • the other positions of the pixel defining layer can be designed to be hydrophobic to reduce the influence of the above-mentioned problems.
  • the substrate further includes a flat layer 110, and the flat layer 110 is disposed on the substrate and covers the gate layer 120, the insulating layer 130 and the source wiring 111.
  • One side of the flat layer 110 is flush with the side of the insulating layer 130 away from the substrate.
  • the side of the flat layer 110 is provided with a connecting groove 114 exposing the source wiring 111, and the source layer 150 extends from the insulating layer 130 to the inner wall of the connecting groove 114 and covers the exposed portion of the source wiring 111.
  • the connection groove 114 covers the source layer 150 and forms a deposition groove.
  • the barrier layer 160 fills the deposition groove and extends to the inner sidewall of the pixel defining layer 140.
  • the light emitting device 100 further includes a channel layer 170, which plays a role of injecting and transmitting current.
  • the channel layer 170 is provided on the source layer 150. More specifically, in the illustrated example, the channel layer 170 is provided on a portion of the source layer 150 that is not covered by the barrier layer 160.
  • the channel layer 170 may be an organic semiconductor material, such as P3HT, PTCDI-C8, pentacene, In 2 O 3 , PC 60 BM, etc.
  • the channel layer 170 can be produced by processes such as inkjet printing, squeegee coating, or spray coating.
  • the thickness of the channel layer 170 ranges from 1 to 1000 nanometers. Due to the existence of the barrier layer 160, this layer and the printing layer thereafter are pixelated on the panel and isolated from each other, thereby preventing problems such as crosstalk current or mixed pollution.
  • V G When in use, a gate voltage V G is connected between the gate layer 120 and the source layer 150, and a voltage V D is connected between the source layer 150 and the drain layer 190.
  • V G When V G is less than a certain voltage V ON , it is difficult to inject current even if V D is greater than zero, so the current is very low.
  • V G When V G is greater than V ON , due to the electric field formed by the gate voltage at the source, the source layer The injection characteristic of 150 is changed, and electrons can be injected, so that the source layer 150 and the drain layer 190 are connected, and a more obvious current I SD appears.
  • the light emitting device 100 further includes a light emitting function layer 180, and the light emitting function layer 180 is disposed on the channel layer 170.
  • the light-emitting functional layer 180 includes a light-emitting layer, and may also include one or more of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.
  • the light-emitting function layer 180 can be made by inkjet printing with necessary vapor deposition technology.
  • the light emitting device 100 further includes a drain layer 190, and the drain layer 190 is disposed on the light emitting function layer 180.
  • the drain layer 190 can be a metal electrode, such as aluminum, silver, copper, gold, etc., or an oxide conductive electrode, such as ITO, IZO, graphene, and carbon nanotubes.
  • the drain layer 190 can be produced by evaporation, sputter coating, inkjet printing, squeegee coating, spray coating, and the like.
  • the thickness of the drain layer 190 ranges from 1 nanometer to 10 microns.
  • the drain layer 190 entirely covers the pixel defining layer 140, the barrier layer 160, and the light-emitting function layer 180.
  • the substrate further includes a drain wiring 113.
  • the drain layer 190 passes through the pixel defining layer 140.
  • the via is connected to the drain wiring 113.
  • Step S110 Obtain or fabricate a substrate provided with a pixel defining layer 140.
  • the substrate includes a substrate, a gate layer 120 and an insulating layer 130.
  • the gate layer 120 is disposed on the substrate, and the insulating layer 130 is disposed on the substrate.
  • the pixel defining layer 140 has pixel pits 142 exposing the insulating layer 130.
  • step S120 a source layer 150 is formed in the pixel pit 142 so that the source layer 150 covers the bottom of the pixel pit 142.
  • a barrier layer 160 is formed in the pixel pit 142 so that the barrier layer 160 covers at least part of the inner sidewall of the pixel pit 142.
  • the source layer 150 is produced by a solution method, specifically, it can be produced by spray printing, inkjet printing, blade coating, or the like.
  • the substrate further includes a source wiring 111, which exposes the bottom edge of the pixel pit 142.
  • the source layer 150 is connected to the exposed portion of the source wiring 111 to form a barrier layer.
  • the barrier layer 160 at least covers the source wiring 111 and the inner sidewall of the pixel defining layer 140 corresponding to the edge position.
  • the substrate further includes a flat layer 110, the flat layer 110 is disposed on the substrate and covers the gate layer 120, the insulating layer 130, and the source wiring 111.
  • One side of the flat layer 110 and the insulating layer 130 are away from the liner.
  • One side of the bottom is flush, and the side of the flat layer 110 is formed with a connecting groove 114 exposing the source wiring 111, so that the source layer 150 extends from the insulating layer 130 to the inner wall of the connecting groove 114 and covers the exposed part of the source wiring 111
  • a deposition groove is formed, so that the barrier layer 160 fills the deposition groove and extends to the inner sidewall of the pixel defining layer 140.
  • the source layer 150 is formed, at least part of the inner sidewalls of the pixel pits are covered by the barrier layer 160, and the edge accumulation portion of the source layer 150 on the pixel defining layer 140 and the subsequently formed film
  • the layers are separated to prevent the problem of crosstalk current and prevent the source layer 150 and the drain layer 190 from being electrically connected to cause a short circuit.

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Abstract

公开了一种发光器件(100)及其制作方法。该发光器件(100)包括基板、像素界定层(140)、源极层(150)以及阻隔层(160)，基板包括衬底、栅极层(120)以及绝缘层(130)，所述栅极层(120)设置在所述衬底上，所述绝缘层(130)设置在所述栅极层(120)上；像素界定层(140)设置在所述基板上，所述像素界定层(140)具有露出所述绝缘层(130)的像素坑，源极层(150)设置在所述像素坑内，并且覆盖所述像素坑的底部，阻隔层(160)设置在所述像素坑内，并且覆盖所述像素坑的至少部分内侧壁。

Description

发光器件及其制作方法
相关申请的交叉引用
本申请要求于2019年12月31日提交中国专利局、申请号为2019114217238、发明名称为“发光器件及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及一种发光器件及其制作方法。
技术背景
随着有机发光显示(OLED)技术的不断发展，显示器市场呈现应用越来越多样化的发展趋势，比如柔性显示、透明显示等等。针对这些新型应用，目前已有的驱动技术主要是基于多晶硅或者氧化物薄膜晶体管技术。
相比传统的薄膜晶体管(TFT)，垂直沟道薄膜晶体管(VTFT)技术具有一定优势：1、沟道长度等于或者小于器件厚度，往往小于1微米，因此容易提供较大的电流；2、TFT与发光器件垂直重叠，不再额外占用面板空间，容易实现较高的开口率，尤其如果使用透明度高的电极，将有利于实现透明显示；3、由于采用了纵向叠层结构，关键的沟道长度等参数在反复弯折的柔性显示使用环境下将具有较高的稳定性，更适用于柔性显示；4、由于此技术核心步骤可用打印的方式实现，十分适合印刷显示技术，且大面积制作过程中主要受打印均匀度控制，不再受其他比如加热结晶等敏感的因素控制，从而有利于实现大面积面板制作性能均匀的TFT阵列。
与传统TFT中源极、漏极水平布置不同，VTFT结构中栅极、源极和漏极三个电极为垂直分布，因此必须在保证电路顺利接线的同时避免发生上下短路。如图1所示，实际打印过程中，墨水在堤岸结构内干燥成膜，由于受到墨水与堤岸材料亲液性的作用，会在堤岸边缘形成边缘堆积。而多层结构 中，由于这种堆积很难控制，因此往往在边缘形成较为薄的膜层，如图1中圆圈所示。目前的OLED打印均为有机材料为主，导电率较低，边缘堆积虽然会导致像素边缘厚度不均从而发光不均，但亦可接受。而在VTFT技术中，如果直接采用同个堤岸像素坑内叠层打印源极、沟道层以及漏极，极易造成边缘处电流串扰，甚至可能由于源极与漏极电连接而造成短路。
发明内容
基于此，有必要提供一种发光器件及其制作方法，以解决VTFT驱动发光器件像素坑边缘处电流串扰甚至短路的问题。
一种发光器件，包括：
基板，包括衬底、栅极层以及绝缘层，所述栅极层设置在所述衬底上，所述绝缘层设置在所述栅极层上；
像素界定层，设置在所述基板上，所述像素界定层具有露出所述绝缘层的像素坑；
源极层，设置在所述像素坑内，并且覆盖所述像素坑的底部；以及
阻隔层，设置在所述像素坑内，并且覆盖所述像素坑的至少部分内侧壁。
在其中一个实施例中，所述基板还包括源极接线，所述源极接线露出于所述像素坑的底部边缘，所述源极层与所述源极接线露出的部分连接，所述阻隔层至少覆盖所述源极接线以及该边缘位置对应的像素界定层的内侧壁。
在其中一个实施例中，所述基板还包括平坦层，所述平坦层设置在衬底上且包覆所述栅极层、所述绝缘层以及所述源极接线，所述平坦层的一侧与所述绝缘层远离所述衬底的一侧齐平，所述平坦层的该侧设有露出所述源极接线的连接槽，所述源极层从所述绝缘层上延伸至所述连接槽的内壁并覆盖所述源极接线露出的部分，所述连接槽内覆盖所述源极层后形成沉积槽，所述阻隔层填充所述沉积槽并延伸至所述像素界定层的内侧壁上。
在其中一个实施例中，所述发光器件还包括沟道层，所述沟道层设置在所述源极层上。
在其中一个实施例中，所述发光器件还包括发光功能层，所述发光功能层设置在所述沟道层上。
在其中一个实施例中，所述发光器件还包括漏极层，所述漏极层设置在所述发光功能层上。
在其中一个实施例中，所述漏极层整体覆盖于所述像素界定层、所述阻隔层以及所述发光功能层上，所述基板还包括漏极接线，所述漏极层经由所述像素界定层中的过孔连接于所述漏极接线。
一种发光器件的制作方法，包括：
获取或制作设置有像素界定层的基板，所述基板包括衬底、栅极层以及绝缘层，所述栅极层设置在所述衬底上，所述绝缘层设置在所述栅极层上，所述像素界定层具有露出所述绝缘层的像素坑；
在所述像素坑内制作源极层，使所述源极层覆盖所述像素坑的底部；
在所述像素坑内制作阻隔层，使所述阻隔层覆盖所述像素坑的至少部分内侧壁。
在其中一个实施例中，所述源极层通过溶液法制作。
在其中一个实施例中，所述基板还包括源极接线，所述源极接线露出所述像素坑的底部边缘，制作所述源极层时使所述源极层与所述源极接线露出的部分连接，制作所述阻隔层时使所述阻隔层至少覆盖所述源极接线以及该边缘位置对应的像素界定层的内侧壁。
在其中一个实施例中，所述基板还包括平坦层，所述平坦层设置在衬底上且包覆所述栅极层、所述绝缘层以及所述源极接线，所述平坦层的一侧与所述绝缘层远离所述衬底的一侧齐平，所述平坦层的该侧制作露出所述源极接线的连接槽，使所述源极层从所述绝缘层上延伸至所述连接槽的内壁并覆盖所述源极接线露出的部分，所述连接槽内覆盖所述源极层后形成沉积槽，使所述阻隔层填充所述沉积槽并延伸至所述像素界定层的内侧壁上。
与现有方案相比，上述发光器件及其制作方法具有以下有益效果：
上述发光器件及其制作方法，在源极层形成之后，通过阻隔层覆盖所述 像素坑的至少部分内侧壁，将源极层在像素界定层上的边缘堆积部分与后续形成的膜层分隔开，防止串扰电流的问题，避免源极层与漏极层电连接而造成短路。
附图说明
图1为喷墨打印后干燥膜层在像素坑中形成边缘堆积的示意图；
图2为一实施例的发光器件的结构示意图；
图3为图2所示发光器件中基板及像素界定层的结构示意图；
图4为一实施例的发光器件的制作方法的流程图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
需要说明的是，当元件被称为“设置于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
如图2所示，一实施例的发光器件100，包括基板、像素界定层140、源极层150以及阻隔层160。
其中，基板包括衬底(图未示)、栅极层120以及绝缘层130。栅极层120设置在衬底上，绝缘层130设置在栅极层120上。
像素界定层140设置在基板上，具体是设置在绝缘层130一侧，像素界定层140具有露出绝缘层130的像素坑。
源极层150设置在像素坑内，并且覆盖像素坑的底部。
阻隔层160设置在像素坑内，并且覆盖至少部分像素坑的内侧壁。通过阻隔层160覆盖至少部分像素坑的内侧壁，将源极层在像素界定层140上的边缘堆积部分与后续形成的膜层分隔开，防止串扰电流的问题，避免源极层150与后续形成的漏极层电连接而造成短路。
栅极层120可为金属电极，如铝、银、铜、金等，亦可为氧化物导电电极，如ITO、IZO等，厚度范围为5纳米-50微米。栅极层120可通过溅射、蒸镀等技术实现，再通过传统光刻技术进行像素化。如图2所示，基板上还包括栅极接线112，用于将栅极层120连接至开关TFT，栅极接线112可用传统半导体技术制成。
绝缘层130用于将栅极层120和源极层150绝缘隔开，起到阻断电流但是构成电压差的作用。绝缘层130可为金属氧化物，如SiO 2、HfO 2、Al 2O 3等，厚度范围为5-1000纳米，可通过溅射沉积、化学气相法沉积或者原子层沉积等技术制作，再通过光刻工艺像素化。
源极层150为VTFT关键结构，可以是碳纳米管薄层、多孔金属电极、多孔导电氧化物电极、金属纳米线、金属纳米颗粒层、超薄金属层(如厚度小于3nm的银电极)等。源极层150厚度范围为0.5-20纳米。源极层150可采用溶液法制作，例如喷印、喷墨打印、刮涂等。由于此层用溶液法制造，故而制作过程中墨水应被限制在绝缘的像素界定层140之间，最终成膜也由像素界定层140隔离像素化。
在其中一个示例中，基板还包括源极接线111，源极接线111露出于像素坑的底部边缘。源极层150与源极接线111露出的部分连接。阻隔层160至少覆盖源极接线111以及该边缘位置对应的像素界定层140的内侧壁。由于靠近源极接线111位置的像素界定层140需要为亲水性，以使得源极层150在通过溶液法制作时溶液能够在该位置铺展开从而能够更好地与源极接线 111连接，源极层150由于像素界定层140的亲水性能在像素界定层140上出现边缘堆积，因此，使阻隔层160至少覆盖该边缘位置对应的像素界定层140的内侧壁，将源极层150在像素界定层140上堆积的部分与后续制作的膜层隔离开，从而防止串扰电流的问题，以及防止源极接线111在边缘较薄位置发生击穿而导致短路。在像素界定层的其他位置，可设计为疏水性，来降低上述问题的影响。
在图2所示的示例中，基板还包括平坦层110，平坦层110设置在衬底上且包覆栅极层120、绝缘层130以及源极接线111。平坦层110的一侧与绝缘层130远离衬底的一侧齐平。如图3所示，平坦层110的该侧设有露出源极接线111的连接槽114，源极层150从绝缘层130上延伸至连接槽114的内壁并覆盖源极接线111露出的部分，连接槽114内覆盖源极层150后形成沉积槽，阻隔层160填充沉积槽并延伸至像素界定层140的内侧壁上。
进一步地，如图2所示，发光器件100还包括沟道层170，起到注入和传输电流的作用。沟道层170设置在源极层150上，更具体地，在图示的示例中，沟道层170设置在源极层150未被阻隔层160覆盖的部分上。沟道层170可为有机半导体材料，如P3HT、PTCDI-C8、并五苯(pentacene)、In 2O 3、PC 60BM等。沟道层170可以通过喷墨打印、刮涂或者喷涂等工艺制作。沟道层170的厚度范围为1-1000纳米。由于阻隔层160的存在，此层以及其后的打印层在面板上均实现了像素化，彼此隔离，从而防止了串扰电流或混合污染等问题。
使用时，栅极层120和源极层150之间接入栅极电压V G，源极层150和漏极层190之间接入电压V D。当V G小于某特定电压V ON时，即便V D大于零也难以注入电流，因此电流很低；而当V G大于V ON时，由于源极处栅极电压形成的电场作用，源极层150的注入特性改变，可以注入电子，于是源极层150和漏极层190之间导通，出现较明显电流I SD。
进一步地，发光器件100还包括发光功能层180，发光功能层180设置在沟道层170上。发光功能层180包括发光层，还可以包括空穴注入层、空 穴传输层、电子传输层和电子注入层中的一层或多层。发光功能层180可通过喷墨打印配合必要的蒸镀技术制作。
进一步地，发光器件100还包括漏极层190，漏极层190设置在发光功能层180上。漏极层190可为金属电极，如铝、银、铜、金等，亦可为氧化物导电电极，如ITO、IZO、石墨烯以及碳纳米管等。漏极层190可通过蒸镀、溅射镀膜、喷墨打印、刮涂、喷涂等方式制作。漏极层190的厚度范围为1纳米-10微米。
在图2所示的示例中，漏极层190整体覆盖于像素界定层140、阻隔层160以及发光功能层180上，基板还包括漏极接线113，漏极层190经由像素界定层140中的过孔连接于漏极接线113。
进一步地，参阅图4，还提供一种上述任一示例的发光器件100的制作方法，包括：
步骤S110，获取或制作设置有像素界定层140的基板，如图3所示，基板包括衬底、栅极层120以及绝缘层130，栅极层120设置在衬底上，绝缘层130设置在栅极层120上，像素界定层140具有露出绝缘层130的像素坑142。
步骤S120，在像素坑142内制作源极层150，使源极层150覆盖像素坑142的底部。
步骤S130，在像素坑142内制作阻隔层160，使阻隔层160覆盖像素坑142的至少部分内侧壁。
在其中一个示例中，源极层150通过溶液法制作，具体可以通过喷印、喷墨打印、刮涂等方式制作。
在其中一个示例中，基板还包括源极接线111，源极接线111露出像素坑142的底部边缘，制作源极层150时使源极层150与源极接线111露出的部分连接，制作阻隔层160时使阻隔层160至少覆盖源极接线111以及该边缘位置对应的像素界定层140的内侧壁。
在其中一个示例中，基板还包括平坦层110，平坦层110设置在衬底上且 包覆栅极层120、绝缘层130以及源极接线111，平坦层110的一侧与绝缘层130远离衬底的一侧齐平，平坦层110的该侧制作露出源极接线111的连接槽114，使源极层150从绝缘层130上延伸至连接槽114的内壁并覆盖源极接线111露出的部分，连接槽114内覆盖源极层150后形成沉积槽，使阻隔层160填充沉积槽并延伸至像素界定层140的内侧壁上。
上述发光器件100及其制作方法，在源极层150形成之后，通过阻隔层160覆盖像素坑的至少部分内侧壁，将源极层150在像素界定层140上的边缘堆积部分与后续形成的膜层分隔开，防止串扰电流的问题，避免源极层150与漏极层190电连接而造成短路。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种发光器件，包括：
    基板，包括衬底、栅极层以及绝缘层，所述栅极层设置在所述衬底上，所述绝缘层设置在所述栅极层上；
    像素界定层，设置在所述基板上，所述像素界定层具有露出所述绝缘层的像素坑；
    源极层，设置在所述像素坑内，并且覆盖所述像素坑的底部；以及
    阻隔层，设置在所述像素坑内，并且覆盖所述像素坑的至少部分内侧壁。
  2. 如权利要求1所述的发光器件，其中，所述基板还包括源极接线，所述源极接线露出于所述像素坑的底部边缘，所述源极层与所述源极接线露出的部分连接，所述阻隔层至少覆盖所述源极接线以及该边缘位置对应的像素界定层的内侧壁。
  3. 如权利要求2所述的发光器件，其中，所述基板还包括平坦层，所述平坦层设置在衬底上且包覆所述栅极层、所述绝缘层以及所述源极接线，所述平坦层的一侧与所述绝缘层远离所述衬底的一侧齐平，所述平坦层的该侧设有露出所述源极接线的连接槽，所述源极层从所述绝缘层上延伸至所述连接槽的内壁并覆盖所述源极接线露出的部分，所述连接槽内覆盖所述源极层后形成沉积槽，所述阻隔层填充所述沉积槽并延伸至所述像素界定层的内侧壁上。
  4. 如权利要求1所述的发光器件，其中，还包括沟道层，所述沟道层设置在所述源极层上。
  5. 如权利要求2所述的发光器件，其中，还包括沟道层，所述沟道层设置在所述源极层上。
  6. 如权利要求3所述的发光器件，其中，还包括沟道层，所述沟道层设置在所述源极层上。
  7. 如权利要求4所述的发光器件，其中，还包括发光功能层，所述发光功能层设置在所述沟道层上。
  8. 如权利要求5所述的发光器件，其中，还包括发光功能层，所述发光功能层设置在所述沟道层上。
  9. 如权利要求6所述的发光器件，其中，还包括发光功能层，所述发光功能层设置在所述沟道层上。
  10. 如权利要求7所述的发光器件，其中，还包括漏极层，所述漏极层设置在所述发光功能层上。
  11. 如权利要求8所述的发光器件，其中，还包括漏极层，所述漏极层设置在所述发光功能层上。
  12. 如权利要求9所述的发光器件，其中，还包括漏极层，所述漏极层设置在所述发光功能层上。
  13. 如权利要求10所述的发光器件，其中，所述漏极层整体覆盖于所述像素界定层、所述阻隔层以及所述发光功能层上，所述基板还包括漏极接线，所述漏极层经由所述像素界定层中的过孔连接于所述漏极接线。
  14. 如权利要求11所述的发光器件，其中，所述漏极层整体覆盖于所述像素界定层、所述阻隔层以及所述发光功能层上，所述基板还包括漏极接线，所述漏极层经由所述像素界定层中的过孔连接于所述漏极接线。
  15. 如权利要求12所述的发光器件，其中，所述漏极层整体覆盖于所述像素界定层、所述阻隔层以及所述发光功能层上，所述基板还包括漏极接线，所述漏极层经由所述像素界定层中的过孔连接于所述漏极接线。
  16. 一种发光器件的制作方法，包括：
    获取或制作设置有像素界定层的基板，所述基板包括衬底、栅极层以及绝缘层，所述栅极层设置在所述衬底上，所述绝缘层设置在所述栅极层上，所述像素界定层具有露出所述绝缘层的像素坑；
    在所述像素坑内制作源极层，使所述源极层覆盖所述像素坑的底部；及
    在所述像素坑内制作阻隔层，使所述阻隔层覆盖所述像素坑的至少部分内侧壁。
  17. 如权利要求16所述的方法，其中，所述源极层通过溶液法制作。
  18. 如权利要求16所述的方法，其中，所述基板还包括源极接线，所述源极接线露出所述像素坑的底部边缘，制作所述源极层时使所述源极层与所述源极接线露出的部分连接，制作所述阻隔层时使所述阻隔层至少覆盖所述源极接线以及该边缘位置对应的像素界定层的内侧壁。
  19. 如权利要求17所述的方法，其中，所述基板还包括源极接线，所述源极接线露出所述像素坑的底部边缘，制作所述源极层时使所述源极层与所述源极接线露出的部分连接，制作所述阻隔层时使所述阻隔层至少覆盖所述源极接线以及该边缘位置对应的像素界定层的内侧壁。
  20. 如权利要求18所述的方法，其中，所述基板还包括平坦层，所述平坦层设置在衬底上且包覆所述栅极层、所述绝缘层以及所述源极接线，所述平坦层的一侧与所述绝缘层远离所述衬底的一侧齐平，所述平坦层的该侧制作露出所述源极接线的连接槽，使所述源极层从所述绝缘层上延伸至所述连接槽的内壁并覆盖所述源极接线露出的部分，所述连接槽内覆盖所述源极层后形成沉积槽，使所述阻隔层填充所述沉积槽并延伸至所述像素界定层的内侧壁上。
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