WO2021135427A1 - 静态随机存储器及其故障检测电路 - Google Patents

静态随机存储器及其故障检测电路 Download PDF

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Publication number
WO2021135427A1
WO2021135427A1 PCT/CN2020/117029 CN2020117029W WO2021135427A1 WO 2021135427 A1 WO2021135427 A1 WO 2021135427A1 CN 2020117029 W CN2020117029 W CN 2020117029W WO 2021135427 A1 WO2021135427 A1 WO 2021135427A1
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Prior art keywords
bit line
potential
coupled
circuit
sram
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PCT/CN2020/117029
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English (en)
French (fr)
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彭增发
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展讯通信（上海）有限公司
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Priority to US17/790,244 priority Critical patent/US20230031649A1/en
Publication of WO2021135427A1 publication Critical patent/WO2021135427A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1204—Bit line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • the invention relates to a static random access memory, in particular to a static random access memory and a fault detection circuit thereof.
  • SRAM Static Random-Access Memory
  • Low power consumption is a very important indicator in electronic products, but as SRAM accounts for an increasing proportion of circuits in digital circuit systems, the power consumption of SRAM accounts for an increasing proportion of the power consumption of the entire digital circuit system.
  • the digital circuit system will power off or sleep the temporarily unused SRAM.
  • the digital circuit system requires the SRAM to be in a sleep state, only the data of the SRAM storage unit when the power supply potential is in a low state remains unchanged, so as to achieve the purpose of greatly reducing the power consumption of the system.
  • CMOS Complementary Metal Oxide Semiconductor
  • the technical problem solved by the present invention is to improve the detection accuracy of whether the SRAM has a data retention failure.
  • an embodiment of the present invention provides a fault detection circuit for a static random access memory.
  • the static random access memory includes: a writing circuit for performing data writing operations on a storage unit, and for performing data reading on the storage unit.
  • the operating read circuit, and the memory array composed of multiple memory cells, the memory cells in each column share the same pair of logical complementary bit lines; it is characterized in that it includes:
  • the bit line coupling circuit is coupled between the first bit line and the second bit line, and is adapted to use the first bit line when performing data write operations on the memory cell in the test mode through the write circuit And a bit line with a lower potential in the second bit line, coupling the bit line with a higher potential in the first bit line and the second bit line to a floating low potential; wherein, the first bit line and the bit line The second bit line is a pair of logic complementary bit lines;
  • the fault judgment circuit is adapted to obtain the written data and the read data corresponding to the written data when the storage unit is in the test mode, and compare them, and determine whether the SRAM has data retention based on the comparison result malfunction.
  • bit line coupling circuit includes:
  • the first bit line coupling circuit coupled between the first bit line and the second bit line, is suitable for performing data write operations on the memory cell through the write circuit, if the first bit line When the potential is at a low level and the potential of the second bit line is at a high level, coupling the potential of the second bit line to a low level;
  • the second bit line coupling circuit coupled between the first bit line and the second bit line, is suitable for performing data write operations on the memory cell through the write circuit, when the potential of the second bit line is When it is a low level and the potential of the first bit line is a high level, the potential of the first bit line is coupled to a low level.
  • the first bit line coupling circuit includes: a first switch and a first capacitor; wherein:
  • the first switch has one end coupled to the first bit line and the other end coupled to the first capacitor, and is suitable for when the potential of the first bit line is low and the second bit line Is turned on when the potential of is at a high level, and turned off when the potential of the first bit line is at a high level and the potential of the second bit line is at a low level;
  • One end of the first capacitor is coupled to the first switch, and the other end is coupled to the second bit line.
  • the first switch includes:
  • the first NMOS transistor has a drain coupled to the first bit line, a source coupled to the first capacitor, and a gate coupled to the first switch signal output terminal.
  • the first switch includes: a first NMOS tube and a first PMOS tube; wherein:
  • the drain is coupled to the first bit line, the source is coupled to the first capacitor, and the gate is coupled to the first switch signal output terminal;
  • the drain is coupled to the first bit line, the source is coupled to the first capacitor, and the gate is coupled to the second switch signal output terminal;
  • the first switch signal output terminal is suitable for outputting a high level first switch signal when the potential of the first bit line is at a low level and the potential of the second bit line is at a high level, When the potential of the first bit line is at a high level and the potential of the second bit line is at a low level, outputting a first switch signal of a low level;
  • the second switching signal output terminal is adapted to output a high-level second switching signal when the potential of the first bit line is high and the potential of the second bit line is low.
  • a second switch signal of a low level is output.
  • the second bit line coupling circuit includes: a second switch and a second capacitor; wherein:
  • the second switch has one end coupled to the second bit line and the other end coupled to the second capacitor, and is suitable for when the potential of the second bit line is low and the first bit line Turn on when the potential of the second bit line is at a high level, and turn off when the potential of the second bit line is at a high level and the potential of the first bit line is at a low level;
  • One end of the second capacitor is coupled to the second switch, and the other end is coupled to the first bit line.
  • the second switch includes:
  • the second NMOS transistor has a drain coupled to the second bit line, a source coupled to the second capacitor, and a gate coupled to the first switch signal output terminal.
  • the second switch includes: a second NMOS tube and a second PMOS tube; where:
  • the drain is coupled to the second bit line, the source is coupled to the second capacitor, and the gate is coupled to the first switch signal output terminal;
  • the drain is coupled to the second bit line, the source is coupled to the second capacitor, and the gate is coupled to the second switch signal output terminal;
  • the first switch signal output terminal is suitable for outputting a high level first switch signal when the potential of the first bit line is at a low level and the potential of the second bit line is at a high level, When the potential of the first bit line is at a high level and the potential of the second bit line is at a low level, outputting a first switch signal of a low level;
  • the second switching signal output terminal is adapted to output a high-level second switching signal when the potential of the first bit line is high and the potential of the second bit line is low.
  • a second switch signal of a low level is output.
  • the fault detection circuit of the SRAM further includes:
  • the switch signal generating circuit is suitable for generating the first switch signal and the second switch signal.
  • the switching signal generating circuit includes: a NAND circuit and an inverter circuit, wherein:
  • the first input terminal is suitable for inputting a test enable signal
  • the second input terminal is suitable for inputting a write enable signal
  • the output terminal is suitable for outputting the second switch signal
  • the input terminal of the inverter circuit is coupled with the output terminal of the NAND circuit, and the output terminal is suitable for outputting the first switch signal.
  • the embodiment of the present invention also provides a static random access memory, the static random access memory includes any one of the above-mentioned fault detection circuits of the static random access memory.
  • bit line coupling circuit is provided between each pair of logic complementary bit lines in the SRAM.
  • bit line coupling circuit is provided between only a pair of logic complementary bit lines in the SRAM.
  • the first bit line coupling circuit can when the potential of the first bit line is low and the potential of the second bit line is high, if the static random access memory is There is a data retention failure.
  • the potential of the second bit line By coupling the potential of the second bit line to a low level, the corresponding memory cell cannot successfully write data, so that an error result occurs when the memory cell is read to determine the memory cell. Whether the unit has a data retention failure.
  • the first bit line is coupled to a low level, so that the corresponding memory cell cannot successfully write data, and an error result occurs when data is read from the memory cell, so as to determine whether the memory cell has a data retention failure.
  • Figure 1 is a schematic diagram of the circuit structure of a storage unit in a 6T SRAM
  • FIG. 2 is a schematic diagram of an open circuit or a weak connection of the storage unit in FIG. 1;
  • Fig. 3 is a schematic structural diagram of a static random access memory in an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the circuit structure of a bit line coupling circuit in an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the circuit structure of another bit line coupling circuit in an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the circuit structure of a switching signal generating circuit in an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a circuit structure for performing data retention fault detection on a storage unit in a 6T SRAM in an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of the waveforms of various signals when a logic "1" is successfully written to the memory cell shown in FIG. 7;
  • FIG. 9 is a schematic diagram of the waveforms of various signals when writing logic "1" to the memory cell shown in FIG. 7 fails;
  • FIG. 10 is a schematic diagram of the connection between a memory array and a bit line coupling circuit in an embodiment of the present invention.
  • the first step is to write data to the storage unit, and then read the data of the storage unit and compare it with the written data to confirm Whether the data is written correctly;
  • the second step is to put the memory into a sleep state and wait for a long time (above 100 milliseconds);
  • the third step is to wake up from the sleep state, read the memory unit, and check whether it is in the same state as the data written Unanimous.
  • the disadvantage of the above detection method is that since the storage unit enters the sleep state, it takes a long time to wake up.
  • the data written in the memory cell may be flipped due to unlocking, which affects the accuracy of the detection.
  • Fig. 1 is a schematic diagram of a circuit structure of a memory cell in a 6T SRAM.
  • the storage unit has six transistors, which are a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a third PMOS tube MP3, and a fourth PMOS tube MP4. among them:
  • the gates of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are connected to the word line WL.
  • the source of the fifth NMOS transistor MN5 is connected to the first bit line BL, and the source of the sixth NMOS transistor MN6 is connected to the second bit line BLB.
  • the third PMOS tube MP3 and the third NMOS tube MN3 form an inverter INV1, and the fourth PMOS tube MP4 and the fourth NMOS tube MN4 form an inverter INV2.
  • the inverter INV1 and the inverter INV2 are connected end to end.
  • the drains of the third PMOS tube MP3 and the third NMOS tube MN3 are connected to the drain of the fifth NMOS tube MN5, the source of the third PMOS tube MP3 is connected to the power supply potential VDD, and the third NMOS tube The source of MN3 is grounded.
  • the drains of the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 are connected to the drain of the sixth NMOS transistor MN6.
  • the source of the fourth PMOS transistor MP4 is connected to the power supply potential VDD, and the source of the fourth NMOS transistor MN4 is grounded.
  • FIG. 2 is a schematic diagram of an open circuit or a weak connection of the storage unit shown in FIG. 1.
  • the storage unit when there is an open circuit or weak connection at OC0 to OC7, it will cause a data retention failure in the SRAM.
  • the third NMOS transistor MN3 When performing a read operation on the memory cell, the third NMOS transistor MN3 is turned on, and the potential of the Q point will be pulled to the "0" potential, but the potential of the QB point will be refreshed due to the bit line precharging phase during the read operation Therefore, even if there is an OC0 failure, the result of the read operation is still 0, so it is determined that the memory cell does not have a data retention failure, and ultimately it cannot be detected that the memory cell has a data retention failure due to an open circuit or a weak connection at OC0.
  • an embodiment of the present invention provides a fault detection circuit of a static random access memory.
  • the fault detection circuit includes a first bit line coupling circuit, a second bit line coupling circuit, and a fault judgment circuit.
  • the first bit line coupling circuit and the second bit line coupling circuit Through the first bit line coupling circuit and the second bit line coupling circuit, when the SRAM has a data retention failure, whether it is writing data through the first bit line or writing data through the second bit line, it can make The storage unit fails to write data, and then an error result occurs when data is read from the storage unit, and finally it is accurately judged whether the storage unit has a data retention failure.
  • the invention provides a fault detection circuit of a static random access memory.
  • static memory In order to facilitate those skilled in the art to implement the present invention more clearly, the static memory will be briefly described first.
  • the SRAM 30 includes: a write circuit 31 for performing data write operations on the memory cell, a read circuit 32 for performing data read operations on the memory cell, and a plurality of memory cells.
  • Storage array 33 The memory cells in each column of the memory array 33 share the same pair of logic complementary bit lines, and the memory cells in each row share the same word line.
  • the fault detection circuit 34 is usually integrated in the SRAM 30.
  • the fault detection circuit 34 may also be provided outside the SRAM 30.
  • the failure detection circuit 34 is described in detail by taking the integration of the failure detection circuit 34 inside the SRAM 30 as an example. Those skilled in the art can understand that when the fault detection circuit 34 is arranged outside the SRAM 30, it can be implemented with reference to the specific description about the integration of the fault detection circuit 34 in the SRAM 30. I won't repeat it here.
  • the fault detection circuit 34 may include:
  • the bit line coupling circuit 341 is coupled between the first bit line and the second bit line, and is adapted to use the first bit line when performing data write operations on the memory cell in the test mode through the write circuit.
  • a bit line with a lower potential in the bit line and the second bit line couples the bit line with a higher potential in the first bit line and the second bit line to a floating low potential; wherein, the first bit line The line and the second bit line are a pair of complementary logic bit lines;
  • the fault judgment circuit 342 is adapted to obtain the written data and the read data corresponding to the written data when the storage unit is in the test mode, and compare them, and determine whether the SRAM has data based on the comparison result Keep malfunctioning.
  • the fault detection circuit 34 performs fault detection when the SRAM 30 is in the test mode, and stops working when the SRAM 30 is in the normal operating mode.
  • the writing circuit 31 writes data to the storage cells in the SRAM 30.
  • the bit line coupling circuit 341 can use the bit line with the lower potential of the first bit line and the second bit line to transfer the bit line with the higher potential of the first bit line and the second bit line. Coupled to floating low potential. If the SRAM has a data retention failure, the storage unit cannot successfully write data, and the reading circuit 32 will read the wrong data from the storage unit, so that the failure judgment circuit 342 judges the SRAM There is a data retention failure.
  • bit line coupling circuit 41 may include: a first bit line coupling circuit 41 and a second bit line coupling circuit 42. among them:
  • the first bit line coupling circuit 41 is coupled between the first bit line BL and the second bit line BLB, and is suitable for performing data write operations on the memory cell through the write circuit, if the When the potential of the first bit line BL is at a low level and the potential of the second bit line BLB is at a high level, coupling the potential of the second bit line BLB to a low level;
  • the second bit line coupling circuit 42 is coupled between the first bit line BL and the second bit line BLB, and is adapted to perform a data write operation on a memory cell through the write circuit.
  • the potential of the two bit line BLB is at a low level and the potential of the first bit line BL is at a high level, the potential of the first bit line BL is coupled to a low level.
  • first bit line coupling circuit 41 and the second bit line coupling circuit 42 may adopt a variety of circuit structures, which are not specifically limited.
  • the circuit structures of the first bit line coupling circuit 41 and the second bit line coupling circuit 42 may be the same or different.
  • the first bit line coupling circuit 41 includes: a first switch 411 and a first capacitor C1. among them:
  • the first switch 411 has one end coupled to the first bit line BL, and the other end coupled to the first capacitor C1, and is suitable for when the potential of the first bit line BL is low and the Turn on when the potential of the second bit line BLB is at a high level, and turn off when the potential of the first bit line BL is at a high level and the potential of the second bit line BLB is at a low level;
  • One end of the first capacitor C1 is coupled to the first switch 411, and the other end is coupled to the second bit line BLB.
  • a device can be used as the first switch 411.
  • the first switch 411 may include: a first NMOS transistor MN1.
  • the drain of the first NMOS transistor MN1 is coupled to the first bit line BL, the source is coupled to the first capacitor C1, and the gate is coupled to the first switch signal output terminal.
  • the first switch 411 may include: a first NMOS transistor MN1 and a first PMOS transistor MP1. among them:
  • the drain of the first NMOS transistor MN1 is coupled to the first bit line BL.
  • the source of the first NMOS transistor MN1 is coupled to the first capacitor C1.
  • the gate of the first NMOS transistor MN1 is coupled to the first switch signal output terminal.
  • the drain of the first PMOS transistor MP1 is coupled to the first bit line BL.
  • the source of the first PMOS transistor MP1 is coupled to the first capacitor C1.
  • the gate of the first PMOS transistor MP1 is coupled to the second switch signal output terminal.
  • the first switch signal output terminal is adapted to output a high-level first switch when the potential of the first bit line BL is low and the potential of the second bit line BLB is high Signal SW_EN, when the potential of the first bit line is high and the potential of the second bit line is low, outputting the first switch signal SW_EN of low level;
  • the second switch signal output terminal is adapted to output a high-level second switch signal SW_ENB when the potential of the first bit line BL is at a high level and the potential of the second bit line BLB is at a low level
  • the second switch signal SW_ENB of a low level is output.
  • the resistance of the first switch 411 can be reduced, and the switching efficiency of the first switch 411 can be improved, thereby improving the memory cell The speed at which data is written.
  • the second bit line coupling circuit 42 and the first bit line coupling circuit 41 have the same circuit structure.
  • the second bit line coupling circuit 42 may include: a second switch 421 and a second capacitor C2. among them:
  • the first bit line BL is turned on when the potential of the first bit line BL is at a high level, and turned off when the potential of the second bit line BLB is at a high level and the potential of the first bit line BL is at a low level.
  • One end of the second capacitor C2 is coupled to the second switch 421, and the other end is coupled to the first bit line BL.
  • the second switch 421 In a specific implementation, a variety of devices can be used as the second switch 421.
  • the second switch 421 may include: a second NMOS transistor MN2.
  • the drain of the second NMOS transistor MN2 is coupled to the second bit line BLB, the source is coupled to the second capacitor C2, and the gate is coupled to the first switch signal output terminal.
  • the second switch 421 may include: a second NMOS transistor MN2 and a second PMOS transistor MP2. among them:
  • the drain of the second NMOS transistor MN2 is coupled to the second bit line BLB.
  • the source of the second NMOS transistor MN2 is coupled to the second capacitor C2, and the gate is coupled to the first switch signal output terminal.
  • the drain of the second PMOS transistor MP2 is coupled to the second bit line BLB.
  • the source of the second PMOS transistor MP2 is coupled to the second capacitor C2.
  • the gate of the second PMOS transistor MP2 is coupled to the second switch signal output terminal.
  • the resistance of the second switch 421 can be reduced, and the switching efficiency of the second switch 421 can be improved, thereby improving the memory cell The speed at which data is written.
  • the fault detection circuit may further include: a switch signal generating circuit 61.
  • the switch signal generating circuit 61 is suitable for generating the first switch signal SW_EN and the second switch signal SW_ENB.
  • the switch signal generating circuit 61 may include: a NAND circuit 611 and an inverter circuit 612. among them:
  • the first input terminal is suitable for inputting the test enable signal TEST_EN
  • the second input terminal is suitable for inputting the write enable signal WE
  • the output terminal is suitable for outputting the second switch signal SW_ENB.
  • the input terminal of the inverter circuit 612 is coupled to the output terminal of the NAND circuit 611, and the output terminal is suitable for outputting the first switch signal SW_EN.
  • test enable signal TEST_EN is suitable for controlling the SRAM to enter the test mode.
  • the write enable signal WE is suitable for controlling a write circuit to perform a write operation on the memory cell in the SRAM.
  • the first bit line coupling circuit 41 and the second bit line coupling circuit 42 are compared with the first bit line BL of the memory cell in FIG. Connected to the second bit line BLB, the circuit structure diagram shown in FIG. 7 is obtained.
  • the 6T SRAM includes a writing circuit 31.
  • the writing circuit 31 is composed of two inverters connected in series.
  • the data written by the writing circuit 31 is determined by the writing control signal DI.
  • the write control signal DI changes from logic “1” to logic “0”, logic “1” is written to the memory cell.
  • the write control signal DI changes from logic “0” to logic “1”, logic “0” is written to the memory cell.
  • the write circuit 31 writes logic "1" to the memory cell shown in FIG. 7 through the first bit line BL and the second bit line BLB.
  • the logic "1" is successfully written, that is, there is no open circuit or weak connection in the memory cell shown in FIG. 7, and the corresponding waveforms of the respective signals are shown in FIG. 8.
  • the writing of logic "1” fails, that is, the memory cell shown in FIG. 7 has an open circuit or a weak connection, and the corresponding waveforms of each signal are shown in FIG. 9.
  • the test enable signal TEST_EN is logic "1"
  • the first bit line BL is precharged to VDD (voltage potential) and floats at the VDD potential.
  • the SRAM control clock CLK changes from logic “0” to logic “1”
  • the write enable signal WE changes from logic “0” to logic “1”
  • the word line WL changes from logic “0” to logic “1”
  • the write control signal DI changes from logic “1” to logic "0”
  • the second bit line BLB is pulled to logic "0”
  • the potential of the memory cell node QB is also pulled to logic "0".
  • test enable signal TEST_EN is logic "1” and the write enable signal WE is also logic “1”
  • the potential of the first switch signal SW_EN is logic "1”
  • the potential of the second switch signal SW_ENB is logic "1” 0"
  • the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on, and the second bit line BLB passes through the first capacitor C1 and the second capacitor C2, and the first bit line originally at the VDD potential is coupled to the low potential and Floating at low potential.
  • the potential of the memory cell node Q is pulled to a low potential and floats.
  • the memory cell has no data retention failure problem, that is, there is no open circuit or weak connection problem in OC0, OC6 or OC7 (as shown in Figure 2)
  • the potential of the memory cell node QB is logic "0”
  • the third NMOS The tube MN3 is turned off and the third PMOS tube MP3 is turned on, thereby pulling the potential of the memory cell node Q to logic "1”, and the memory cell writes data successfully.
  • the write circuit 31 writes logic "0" to the memory cell shown in FIG. 7 through the first bit line BL and the second bit line BLB, similarly, if the memory cell has no data retention failure problem, the memory cell node The potential of Q is pulled to logic "0". If the memory cell has a data retention failure problem, the potential of the memory cell node Q will not be pulled from logic "1" to logic "0" in a short time, so that it can be accurately determined that the memory cell has a data retention failure.
  • the memory array in the SRAM includes at least two columns of memory cells Cell, the memory cells in each column correspond to the same pair of logic complementary bit lines, and the memory cells in each row correspond to the same word line.
  • the logic complementary bit lines corresponding to the memory cells in the first column are bit lines BL0 and BL0B
  • the logic complementary bit lines corresponding to the memory cells in the second column are bit lines BL1 and BL1B
  • the logic complementary bit lines corresponding to the memory cells in the last column are bit lines. These are the bit lines BLn and BLnB.
  • bit line coupling circuit 342 may be provided between each pair of logic complementary bit lines of the SRAM.
  • the bit line coupling circuit may be provided only between only a pair of logic complementary bit lines of the SRAM.
  • a bit line selector can be set in the static random access memory, one pair of logic complementary bit lines is selected through the bit line selector, and the bit line coupling is set between the selected pair of logic complementary bit lines. Circuit 342.
  • the fault detection circuit of the SRAM in the embodiment of the present invention uses the first capacitor C1 and the second capacitor C2 to implement a bit line to couple its complementary bit line to the floating point when the memory cell is written.
  • the empty low potential makes the memory cell with the data retention failure problem unable to successfully write data, so that an error result occurs when the data is read from this memory cell, and the purpose of detecting whether the memory cell has a data retention failure is achieved, especially when using BIST
  • the March algorithm detects SRAM data retention failures, it can not only shorten the test time, but also improve the accuracy of failure detection.

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Abstract

一种静态随机存储器及其故障检测电路。故障检测电路包括：位线耦合电路，耦接于第一位线及第二位线之间，适于在通过写入电路对处于测试模式下的存储单元执行数据写操作时，利用第一位线及第二位线中具有较低电位的位线，将第一位线及第二位线中具有较高电位的位线耦合至浮空低电位；其中，第一位线与第二位线为一对逻辑互补位线；故障判断电路，适于在存储单元处于测试模式时，获取写入数据及与写入数据对应的读取数据，并进行比较，基于比较结果判断静态随机存储器是否存在数据保持故障。应用上述方案，可以提高故障检测的准确性。

Description

静态随机存储器及其故障检测电路
本申请要求于2019年12月31日提交中国专利局、申请号为201911409744.8、发明名称为“静态随机存储器及其故障检测电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及静态随机存储器，具体涉及一种静态随机存储器及其故障检测电路。
背景技术
静态随机存储器(Static Random-Access Memory，SRAM)广泛应用于电子产品中。低功耗是电子产品中一项非常重要的指标，但随着SRAM在数字电路系统中的电路占比越来越大，SRAM的功耗占整个数字电路系统功耗的比重越来越大。
为了延长芯片电池寿命、尽量减小静态电流，数字电路系统会将暂时未被用到的SRAM处于断电或者睡眠状态。当数字电路系统需要SRAM处于睡眠状态时，只需要SRAM存储单元在供电电位处于低位状态下的数据保持不变，从而达到大幅降低系统功耗的目的。
但是，由于互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)工艺缺陷，会导致SRAM存储单元所存储的数据无法在长时间的睡眠状态下一直保持固有状态，进而在SRAM从睡眠状态被唤醒后，数字电路系统会从SRAM抓取到错误的数据，最终导致整个数字电路系统功能出错。上述SRAM的数据保持问题，被称为SRAM的数据保持故障(Data Retention Faults)。
然而，现有检测SRAM是否存在数据保持故障的方法，准确性较差。
发明内容
本发明解决的技术问题是提高SRAM是否存在数据保持故障的检测准确性。
为解决上述技术问题，本发明实施例提供一种静态随机存储器的故障检测电路，所述静态随机存储器包括：用于对存储单元执行数据写操作的写入电路，用于对存储单元执行数据读操作的读取电路，以及由多个存储单元组成的存储阵列，每一列的存储单元共用同一对逻辑互补位线；其特征在于，包括：
位线耦合电路，耦接于第一位线及第二位线之间，适于在通过所述写入电路对处于测试模式下的存储单元执行数据写操作时，利用所述第一位线及第二位线中具有较低电位的位线，将述第一位线及第二位线中具有较高电位的位线耦合至浮空低电位；其中，所述第一位线与所述第二位线为一对逻辑互补位线；
故障判断电路，适于在所述存储单元处于测试模式时，获取写入数据及与所述写入数据对应的读取数据，并进行比较，基于比较结果判断所述静态随机存储器是否存在数据保持故障。
可选地，所述位线耦合电路，包括：
第一位线耦合电路，耦接于所述第一位线及第二位线之间，适于在通过所述写入电路对存储单元执行数据写操作时，若所述第一位线的电位为低电平而所述第二位线的电位为高电平时，将所述第二位线的电位耦合至低电平；
第二位线耦合电路，耦接于所述第一位线及第二位线之间，适于 通过所述写入电路对存储单元执行数据写操作时，在所述第二位线的电位为低电平而所述第一位线的电位为高电平时，将所述第一位线的电位耦合至低电平。
可选地，所述第一位线耦合电路，包括：第一开关及第一电容；其中：
所述第一开关，一端与所述第一位线耦接，另一端与所述第一电容耦接，适于在所述第一位线的电位为低电平而所述第二位线的电位为高电平时导通，在所述第一位线的电位为高电平而所述第二位线的电位为低电平时断开；
所述第一电容，一端与所述第一开关耦接，另一端与所述第二位线耦接。
可选地，所述第一开关包括：
第一NMOS管，漏极与所述第一位线耦接，源极与所述第一电容耦接，栅极与第一开关信号输出端耦接。
可选地，所述第一开关包括：第一NMOS管及第一PMOS管；其中：
所述第一NMOS管，漏极与所述第一位线耦接，源极与所述第一电容耦接，栅极与第一开关信号输出端耦接；
所述第一PMOS管，漏极与所述第一位线耦接，源极与所述第一电容耦接，栅极与第二开关信号输出端耦接；
其中，所述第一开关信号输出端，适于在所述第一位线的电位为低电平而所述第二位线的电位为高电平时，输出高电平的第一开关信号，在所述第一位线的电位为高电平而所述第二位线的电位为低电平时，输出低电平的第一开关信号；
所述第二开关信号输出端，适于在所述第一位线的电位为高电平而所述第二位线的电位为低电平时，输出高电平的第二开关信号，在 所述第一位线的电位为低电平而所述第二位线的电位为高电平时，输出低电平的第二开关信号。
可选地，所述第二位线耦合电路，包括：第二开关及第二电容；其中：
所述第二开关，一端与所述第二位线耦接，另一端与所述第二电容耦接，适于在所述第二位线的电位为低电平而所述第一位线的电位为高电平时导通，在所述第二位线的电位为高电平而所述第一位线的电位为低电平时断开；
所述第二电容，一端与所述第二开关耦接，另一端与所述第一位线耦接。
可选地，所述第二开关包括：
第二NMOS管，漏极与所述第二位线耦接，源极与所述第二电容耦接，栅极与第一开关信号输出端耦接。
可选地，所述第二开关包括：第二NMOS管及第二PMOS管；其中：
所述第二NMOS管，漏极与所述第二位线耦接，源极与所述第二电容耦接，栅极与第一开关信号输出端耦接；
所述第二PMOS管，漏极与所述第二位线耦接，源极与所述第二电容耦接，栅极与第二开关信号输出端耦接；
其中，所述第一开关信号输出端，适于在所述第一位线的电位为低电平而所述第二位线的电位为高电平时，输出高电平的第一开关信号，在所述第一位线的电位为高电平而所述第二位线的电位为低电平时，输出低电平的第一开关信号；
所述第二开关信号输出端，适于在所述第一位线的电位为高电平而所述第二位线的电位为低电平时，输出高电平的第二开关信号，在所述第一位线的电位为低电平而所述第二位线的电位为高电平时，输 出低电平的第二开关信号。
可选地，所述静态随机存储器的故障检测电路还包括：
开关信号产生电路，适于产生所述第一开关信号及第二开关信号。
可选地，所述开关信号产生电路，包括：与非门电路及反相器电路，其中：
所述与非门电路，第一输入端适于输入测试使能信号，第二输入端适于输入写使能信号，输出端适于输出所述第二开关信号；
所述反相器电路，输入端与所述与非门电路的输出端耦接，输出端适于输出所述第一开关信号。
本发明实施例还提供了一种静态随机存储器，所述静态随机存储器包括上述任一种所述的静态随机存储器的故障检测电路。
可选地，所述静态随机存储器每对逻辑互补位线之间，均设置有所述位线耦合电路。
可选地，所述静态随机存储器中仅一对逻辑互补位线之间，设置有所述位线耦合电路。
与现有技术相比，本发明实施例的技术方案具有以下有益效果：
采用上述方案，在通过第一位线写入数据时，即第一位线耦合电路可以在第一位线的电位为低电平而第二位线的电位为高电平时，若静态随机存储器存在数据保持故障，通过将第二位线的电位耦合至低电平，可以使得相应的存储单元无法成功写入数据，从而在对该存储单元进行数据读取时出现错误结果，以判断该存储单元是否存在数据保持故障。
同理，在通过第二位线写入数据时，即第二位线的电位为低电平而第一位线的电位为高电平时，若静态随机存储器存在数据保持故障，通过将第一位线的电位耦合至低电平，可以使得相应的存储单元 无法成功写入数据，从而在对该存储单元进行数据读取时出现错误结果，以判断该存储单元是否存在数据保持故障。
附图说明
图1是一种6T SRAM中存储单元的电路结构示意图；
图2是图1中存储单元开路或弱连接的示意图；
图3是本发明实施例中一种静态随机存储器的结构示意图；
图4是本发明实施例中一种位线耦合电路的电路结构示意图；
图5是本发明实施例中另一种位线耦合电路的电路结构示意图；
图6是本发明实施例中一种开关信号产生电路的电路结构示意图；
图7是本发明实施例中一种对6T SRAM中存储单元进行数据保持故障检测的电路结构示意图；
图8是对图7中示出的存储单元成功写入逻辑“1”时各个信号的波形示意图；
图9是对图7中示出的存储单元写入逻辑“1”失败时各个信号的波形示意图；
图10是本发明实施例中一种存储阵列与位线耦合电路连接的示意图。
具体实施方式
现有技术中，为了检测SRAM是否存在数据保持故障，通常的做法是：第一步，先写入数据到存储单元，然后将读取该存储单元的数据，并与写入数据作比较，确认数据写入是否正确；第二步，使存储器进入睡眠状态并长时间等待(100毫秒以上)；第三步，从睡眠 状态唤醒，对存储单元进行读操作，并检查是否与写入数据的状态一致。
上述检测方法的缺点是：由于存储单元进入睡眠状态，故需要等待较长的时间才能唤醒。并且，由于CMOS工艺缺陷，会出现存储单元内所写入的数据因锁不住而出现翻转，影响检测的准确性。
为了缩短检测时间，提出使用基于March算法的嵌入式存储器BIST技术，对SRAM的数据保持故障进行检测。但采用BIST March算法对SRAM的数据保持故障进行检测时，由于每次对存储单元执行写操作与执行读操作的时间间隔很短，故仅能检测部分故障类型，而难以覆盖所有的故障类型，最终导致检测的准确性较差。
下面结合图1及图2进行详细说明：
图1为一种6T SRAM中存储单元的电路结构示意图。所述存储单元具有六个晶体管，分别为第三NMOS管MN3、第四NMOS管MN4、第五NMOS管MN5、第六NMOS管MN6，第三PMOS管MP3及第四PMOS管MP4。其中：
第五NMOS管MN5及第六NMOS管MN6的栅极连接字线WL。第五NMOS管MN5的源极连接第一位线BL，第六NMOS管MN6的源极连接第二位线BLB。第三PMOS管MP3与第三NMOS管MN3构成反相器INV1，第四PMOS管MP4与第四NMOS管MN4构成反相器INV2。反相器INV1与反相器INV2首尾相连。
反相器INV1中，第三PMOS管MP3与第三NMOS管MN3的漏极，与第五NMOS管MN5的漏极连接，第三PMOS管MP3的源极与电源电位VDD连接，第三NMOS管MN3的源极接地。
反相器INV2中，第四PMOS管MP4与第四NMOS管MN4的漏极，与第六NMOS管MN6的漏极连接。第四PMOS管MP4的源极与电源电位VDD连接，第四NMOS管MN4的源极接地。
图2为图1中示出的存储单元开路或弱连接的示意图。在所述存 储单元中，当OC0至OC7处存在开路或弱连接时，会导致SRAM存在数据保持故障。
在OC2、OC3、OC4或OC5处存在开路或弱连接时，存储单元的Q点无法成功写入，故在采用BIST March算法对SRAM的数据保持故障进行检测时，即便每次对存储单元执行写操作与执行读操作的时间间隔很短，仍然能检测到存储单元存在数据保持故障。在OC1处存在开路或弱连接时，只要对存储单元作写“0”、读“0”操作，也能检测到存储单元存在数据保持故障。
然而，对于OC6或OC7处存在开路或弱连接的情况，Q点可以成功写入“1”，但由于第三PMOS管MP3的开路或弱连接无法补充被第三NMOS管MN3漏掉的电流，使得存储单元经过长时间的睡眠之后，最终Q点由“1”变“0”，锁存的数据丢失。此时，采用BIST March算法对SRAM的数据保持故障进行检测时，由于每次对存储单元的写入操作与读出操作的时间间隔很短，故无法检测到存储单元可能存在的数据保持故障。
对于OC0处存在开路或弱连接的情况，如果对存储单元写入“0”，此时第一位线BL的电位被写驱动电路拉到“0”，存储单元Q点的电位也被拉到“0”，而第二位线BLB的电位为电源电位VDD，QB点电位为VDD-Vth，Vth为第六NMOS管的阈值电位。在对存储单元执行读操作时，由于第三NMOS管MN3的导通，会将Q点的电位拉到“0”电位，但由于读操作时的位线预充电阶段会将QB点的电位刷新，故即使存在OC0故障，读操作的结果仍然为0，从而判定存储单元不存在数据保持故障，最终无法检测到因OC0处存在开路或弱连接而导致存储单元存在数据保持故障。
由上述内容可以看出，针对目前的存储单元，在采用BIST March算法对SRAM的数据保持故障进行检测时，难以在OC0、OC6或OC7处存在开路或弱连接时，准确地检测到存储单元存在的数据保持故障，严重影响采用BIST March算法对SRAM的数据保持故障进行检 测的准确性。
针对上述问题，本发明实施例提供了一种静态随机存储器的故障检测电路，所述故障检测电路包括第一位线耦合电路、第二位线耦合电路及故障判断电路。通过第一位线耦合电路及第二位线耦合电路，可以在静态随机存储器存在数据保持故障时，无论是通过第一位线写入数据，还是通过第二位线写入数据，均可以使得存储单元写入数据失败，进而在对该存储单元进行数据读取时出现错误结果，最终准确地判断存储单元是否存在数据保持故障。
为使本发明的上述目的、特征和有益效果能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
本发明提供了一种静态随机存储器的故障检测电路。为了便于本领域技术人员更加清楚地实施本发明，首先对所述静态存储器进行简要描述。
参照图3，所述静态随机存储器30包括：用于对存储单元执行数据写操作的写入电路31，用于对存储单元执行数据读操作的读取电路32，以及由多个存储单元组成的存储阵列33。所述存储阵列33中每一列的存储单元共用同一对逻辑互补位线，每一行的存储单元共用同一字线。
在具体实施中，参照图3，所述故障检测电路34通常集成于所述静态随机存储器30内部。当然，在其它实施例中，所述故障检测电路34也可以设置在静态随机存储器30外部。
本发明的实施例中，以所述故障检测电路34集成于所述静态随机存储器30内部为例，对所述故障检测电路34进行详细描述。本领域技术人员可以理解的是，当所述故障检测电路34设置在静态随机存储器30外部时，可以参照关于所述故障检测电路34集成于所述静态随机存储器30内的具体描述进行实施，此处不再赘述。
具体地，所述故障检测电路34可以包括：
位线耦合电路341，耦接于所述第一位线及第二位线之间，适于在通过所述写入电路对处于测试模式下的存储单元执行数据写操作时，利用所述第一位线及第二位线中具有较低电位的位线，将述第一位线及第二位线中具有较高电位的位线耦合至浮空低电位；其中，所述第一位线与所述第二位线为一对逻辑互补位线；
故障判断电路342，适于在所述存储单元处于测试模式时，获取写入数据及与所述写入数据对应的读取数据，并进行比较，基于比较结果判断所述静态随机存储器是否存在数据保持故障。
在具体实施中，所述故障检测电路34在静态随机存储器30处于测试模式时进行故障检测，而在静态随机存储器30处于正常工作模式时停止工作。在静态随机存储器30处于测试模式时，写入电路31向静态随机存储器30中存储单元写入数据。此时，位线耦合电路341，可以利用所述第一位线及第二位线中具有较低电位的位线，将述第一位线及第二位线中具有较高电位的位线耦合至浮空低电位。若所述静态随机存储器存在数据保持故障，则会使得存储单元无法成功写入数据，进而读取电路32从存储单元中会读取到错误的数据，使得故障判断电路342判定所述静态随机存储器存在数据保持故障。
图4为本发明实施例提供的一种位线耦合电路的电路结构示意图。参照图4，所述位线耦合电路可以包括：第一位线耦合电路41及第二位线耦合电路42。其中：
所述第一位线耦合电路41，耦接于所述第一位线BL及第二位线BLB之间，适于在通过所述写入电路对存储单元执行数据写操作时，若所述第一位线BL的电位为低电平而所述第二位线BLB的电位为高电平时，将所述第二位线BLB的电位耦合至低电平；
所述第二位线耦合电路42，耦接于所述第一位线BL及第二位线BLB之间，适于通过所述写入电路对存储单元执行数据写操作时，在所述第二位线BLB的电位为低电平而所述第一位线BL的电位为高电平时，将所述第一位线BL的电位耦合至低电平。
在具体实施中，所述第一位线耦合电路41与所述第二位线耦合电路42可以采用多种电路结构，具体不作限制。所述第一位线耦合电路41与所述第二位线耦合电路42的电路结构可以相同，也可以不同。
在本发明的一实施例中，所述第一位线耦合电路41，包括：第一开关411及第一电容C1。其中：
所述第一开关411，一端与所述第一位线BL耦接，另一端与所述第一电容C1耦接，适于在所述第一位线BL的电位为低电平而所述第二位线BLB的电位为高电平时导通，在所述第一位线BL的电位为高电平而所述第二位线BLB的电位为低电平时断开；
所述第一电容C1，一端与所述第一开关411耦接，另一端与所述第二位线BLB耦接。
在具体实施中，可以采用器件，作为所述第一开关411。
在本发明的一实施例中，第一开关411可以包括：第一NMOS管MN1。第一NMOS管MN1的漏极与所述第一位线BL耦接，源极与所述第一电容C1耦接，栅极与第一开关信号输出端耦接。
在本发明的另一实施例中，参照图5，所述第一开关411可以包括：第一NMOS管MN1及第一PMOS管MP1。其中：
所述第一NMOS管MN1的漏极与所述第一位线BL耦接。所述第一NMOS管MN1的源极与所述第一电容C1耦接。所述第一NMOS管MN1的栅极与第一开关信号输出端耦接。
所述第一PMOS管MP1的漏极与所述第一位线BL耦接。所述第一PMOS管MP1的源极与所述第一电容C1耦接。所述第一PMOS管MP1的栅极与第二开关信号输出端耦接。
其中，所述第一开关信号输出端，适于在所述第一位线BL的电位为低电平而所述第二位线BLB的电位为高电平时，输出高电平的 第一开关信号SW_EN，在所述第一位线的电位为高电平而所述第二位线的电位为低电平时，输出低电平的第一开关信号SW_EN；
所述第二开关信号输出端，适于在所述第一位线BL的电位为高电平而所述第二位线BLB的电位为低电平时，输出高电平的第二开关信号SW_ENB，在所述第一位线BL的电位为低电平而所述第二位线BLB的电位为高电平时，输出低电平的第二开关信号SW_ENB。
采用第一NMOS管MN1及第一PMOS管MP1作为所述第一开关411，可以减小所述第一开关411的电阻，进而提高所述第一开关411的开关效率，进而可以提高对存储单元写入数据的速度。
在本发明的一实施例中，参照图4，所述第二位线耦合电路42与所述第一位线耦合电路41的电路结构相同。
具体地，所述第二位线耦合电路42，可以包括：第二开关421及第二电容C2。其中：
所述第二开关421，一端与所述第二位线BLB耦接，另一端与所述第二电容C2耦接，适于在所述第二位线BLB的电位为低电平而所述第一位线BL的电位为高电平时导通，在所述第二位线BLB的电位为高电平而所述第一位线BL的电位为低电平时断开。
所述第二电容C2，一端与所述第二开关421耦接，另一端与所述第一位线BL耦接。
在具体实施中，可以采用多种器件，作为所述第二开关421。
在本发明的一实施例中，所述第二开关421可以包括：第二NMOS管MN2。所述第二NMOS管MN2的漏极与所述第二位线BLB耦接，源极与所述第二电容C2耦接，栅极与第一开关信号输出端耦接。
在本发明的另一实施例中，参照图5，所述第二开关421可以包括：第二NMOS管MN2及第二PMOS管MP2。其中：
所述第二NMOS管MN2的漏极与所述第二位线BLB耦接。所述第二NMOS管MN2的源极与所述第二电容C2耦接，栅极与第一开关信号输出端耦接。
所述第二PMOS管MP2的漏极与所述第二位线BLB耦接。所述第二PMOS管MP2的源极与所述第二电容C2耦接。所述第二PMOS管MP2的栅极与第二开关信号输出端耦接。
采用第二NMOS管MN2及第二PMOS管MP2作为所述第二开关421，可以减小所述第二开关421的电阻，进而提高所述第二开关421的开关效率，进而可以提高对存储单元写入数据的速度。
在具体实施中，参照图6，所述故障检测电路还可以包括：开关信号产生电路61。所述开关信号产生电路61适于产生所述第一开关信号SW_EN及第二开关信号SW_ENB。
在本发明的一实施例中，所述开关信号产生电路61，可以包括：与非门电路611及反相器电路612。其中：
所述与非门电路611，第一输入端适于输入测试使能信号TEST_EN，第二输入端适于输入写使能信号WE，输出端适于输出所述第二开关信号SW_ENB。所述反相器电路612，输入端与所述与非门电路611的输出端耦接，输出端适于输出所述第一开关信号SW_EN。
其中，所述测试使能信号TEST_EN适于控制所述静态随机存储器进入测试模式。所述写使能信号WE适于控制写入电路对所述静态随机存储器中的存储单元执行写入操作。当测试使能信号TEST_EN及写使能信号WE同时为高电平时，用于控制所述静态随机存储器进入测试模式并对静态随机存储器中的存储单元执行写入操作。
下面以所述静态存储器为图1中示出的6T SRAM的存储单元为例，将第一位线耦合电路41及第二位线耦合电路42，与图1中存储单元的第一位线BL及第二位线BLB连接，得到图7中示出的电路 结构图。
所述6T SRAM包括写入电路31。所述写入电路31由两个顺序连接的反相器构成。写入电路31所写入的数据由写入控制信号DI决定。当写入控制信号DI由逻辑“1”变为逻辑“0”时，向该存储单元写入逻辑“1”。当写入控制信号DI由逻辑“0”变为逻辑“1”时，向该存储单元写入逻辑“0”。
写入电路31通过第一位线BL及第二位线BLB向该图7中示出的存储单元写入逻辑“1”。当逻辑“1”成功写入时，即图7中示出的存储单元不存在开路或弱连接的情况，对应的各个信号的波形如图8所示。当逻辑“1”写入失败时，即图7中示出的存储单元存在开路或弱连接的情况，对应的各个信号的波形如图9所示。
结合图7至图9，首先，测试使能信号TEST_EN为逻辑“1”，第一位线BL预充电到VDD(电压电位)并浮空在VDD电位。在t1时刻，静态随机存储器控制时钟CLK由逻辑“0”变为逻辑“1”，写入使能信号WE由逻辑“0”变为逻辑“1”，字线WL由逻辑“0”变逻辑“1”，写入控制信号DI由逻辑“1”变为逻辑“0”，进而将第二位线BLB拉到逻辑“0”，存储单元节点QB的电位也被拉到逻辑“0”。
由于测试使能信号TEST_EN为逻辑“1”，写入使能信号WE也为逻辑“1”，则第一开关信号SW_EN的电位为逻辑“1”，而第二开关信号SW_ENB的电位为逻辑“0”，由此使得第一NMOS管MN1及第二NMOS管MN2导通，第二位线BLB通过第一电容C1及第二电容C2，原本在VDD电位的第一位线耦合到低电位并浮空在低电位。相应地，存储单元节点Q的电位被拉到低电位并浮空。
如果存储单元没有数据保持故障问题，也即在OC0、OC6或OC7不存在开路或弱连接问题(如图2所示)，则存储单元节点QB的电位为逻辑“0”，此时第三NMOS管MN3关闭，第三PMOS管MP3导通，从而将存储单元节点Q的电位拉到逻辑“1”，存储单元写入数据成功。
若OC6或OC7存在开路或弱连接问题，或者，OC0处存在开路或弱连接的问题，则存储单元节点QB的电位为逻辑“0”，使得第三NMOS管MN3关闭，但同时第三PMOS管MP3不导通或者弱导通，进而会使得短时间内(高速或全速时钟下)，存储单元节点Q的电位不会从逻辑“0”拉到逻辑“1”，存储单元写入数据失败。对该存储单元进行读操作，在t2时刻之前，读取数据与写入数据始终不一致，故可以准确地判定存储单元出现数据保持故障。
若写入电路31通过第一位线BL及第二位线BLB向该图7中示出的存储单元写入逻辑“0”，相似地，若存储单元没有数据保持故障问题，则存储单元节点Q的电位拉到逻辑“0”。若存储单元存在数据保持故障问题，则存储单元节点Q的电位在短时间内不会从逻辑“1”拉到逻辑“0”，进而可以准确地判定存储单元出现数据保持故障。
在具体实施中，如图10所示，静态随机存储器中存储阵列至少包含两列的存储单元Cell，每列的存储单元对应同一对逻辑互补位线，每一行的存储单元对应同一字线。比如，第一列的存储单元对应的逻辑互补位线为位线BL0及BL0B，第二列的存储单元对应的逻辑互补位线为位线BL1及BL1B，最后一列存储单元对应的逻辑互补位线为位线BLn及BLnB。
在具体实施中，可以在所述静态随机存储器每对逻辑互补位线之间，均设置有所述位线耦合电路342。
在一实施例中，为了减小存储器占用的芯片面积，可以仅在静态随机存储器的仅一对逻辑互补位线之间，设置有所述位线耦合电路。比如，可以在静态随机存储器设置一位线选择器，通过所述位线选择器选择其中一对逻辑互补位线，并在所选择的一对逻辑互补位线之间，设置所述位线耦合电路342。
由上述内容可知，本发明实施例中静态随机存储器的故障检测电路，在对存储单元执行写操作时，利用第一电容C1及第二电容C2 实现一条位线对其互补位线进行耦合到浮空低电位，使得存在数据保持故障问题的存储单元无法成功写入数据，从而在对此存储单元进行数据读取时出现错误结果，达到检测存储单元是否存在数据保持故障的目的，尤其在采用BIST March算法对SRAM的数据保持故障进行检测时，不仅可以缩短测试时间，而且可以提高故障检测的准确性。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (13)

  1. 一种静态随机存储器的故障检测电路，所述静态随机存储器包括：用于对存储单元执行数据写操作的写入电路，用于对存储单元执行数据读操作的读取电路，以及由多个存储单元组成的存储阵列，每一列的存储单元共用同一对逻辑互补位线；其特征在于，包括：
    位线耦合电路，耦接于第一位线及第二位线之间，适于在通过所述写入电路对处于测试模式下的存储单元执行数据写操作时，利用所述第一位线及第二位线中具有较低电位的位线，将述第一位线及第二位线中具有较高电位的位线耦合至浮空低电位；其中，所述第一位线与所述第二位线为一对逻辑互补位线；
    故障判断电路，适于在所述存储单元处于测试模式时，获取写入数据及与所述写入数据对应的读取数据，并进行比较，基于比较结果判断所述静态随机存储器是否存在数据保持故障。
  2. 如权利要求1所述的静态随机存储器的故障检测电路，其特征在于，所述位线耦合电路，包括：
    第一位线耦合电路，耦接于所述第一位线及第二位线之间，适于在通过所述写入电路对存储单元执行数据写操作时，若所述第一位线的电位为低电平而所述第二位线的电位为高电平时，将所述第二位线的电位耦合至低电平；
    第二位线耦合电路，耦接于所述第一位线及第二位线之间，适于通过所述写入电路对存储单元执行数据写操作时，在所述第二位线的电位为低电平而所述第一位线的电位为高电平时，将所述第一位线的电位耦合至低电平。
  3. 如权利要求2所述的静态随机存储器的故障检测电路，其特征在于，所述第一位线耦合电路，包括：第一开关及第一电容；其中：
    所述第一开关，一端与所述第一位线耦接，另一端与所述第一电容耦接，适于在所述第一位线的电位为低电平而所述第二位线的电位 为高电平时导通，在所述第一位线的电位为高电平而所述第二位线的电位为低电平时断开；
    所述第一电容，一端与所述第一开关耦接，另一端与所述第二位线耦接。
  4. 如权利要求3所述的静态随机存储器的故障检测电路，其特征在于，所述第一开关包括：
    第一NMOS管，漏极与所述第一位线耦接，源极与所述第一电容耦接，栅极与第一开关信号输出端耦接。
  5. 如权利要求3所述的静态随机存储器的故障检测电路，其特征在于，所述第一开关包括：第一NMOS管及第一PMOS管；其中：
    所述第一NMOS管，漏极与所述第一位线耦接，源极与所述第一电容耦接，栅极与第一开关信号输出端耦接；
    所述第一PMOS管，漏极与所述第一位线耦接，源极与所述第一电容耦接，栅极与第二开关信号输出端耦接；
    其中，所述第一开关信号输出端，适于在所述第一位线的电位为低电平而所述第二位线的电位为高电平时，输出高电平的第一开关信号，在所述第一位线的电位为高电平而所述第二位线的电位为低电平时，输出低电平的第一开关信号；
    所述第二开关信号输出端，适于在所述第一位线的电位为高电平而所述第二位线的电位为低电平时，输出高电平的第二开关信号，在所述第一位线的电位为低电平而所述第二位线的电位为高电平时，输出低电平的第二开关信号。
  6. 如权利要求3所述的静态随机存储器的故障检测电路，其特征在于，所述第二位线耦合电路，包括：第二开关及第二电容；其中：
    所述第二开关，一端与所述第二位线耦接，另一端与所述第二电容耦接，适于在所述第二位线的电位为低电平而所述第一位线的电位 为高电平时导通，在所述第二位线的电位为高电平而所述第一位线的电位为低电平时断开；
    所述第二电容，一端与所述第二开关耦接，另一端与所述第一位线耦接。
  7. 如权利要求6所述的静态随机存储器的故障检测电路，其特征在于，所述第二开关包括：
    第二NMOS管，漏极与所述第二位线耦接，源极与所述第二电容耦接，栅极与第一开关信号输出端耦接。
  8. 如权利要求6所述的静态随机存储器的故障检测电路，其特征在于，所述第二开关包括：第二NMOS管及第二PMOS管；其中：
    所述第二NMOS管，漏极与所述第二位线耦接，源极与所述第二电容耦接，栅极与第一开关信号输出端耦接；
    所述第二PMOS管，漏极与所述第二位线耦接，源极与所述第二电容耦接，栅极与第二开关信号输出端耦接；
    其中，所述第一开关信号输出端，适于在所述第一位线的电位为低电平而所述第二位线的电位为高电平时，输出高电平的第一开关信号，在所述第一位线的电位为高电平而所述第二位线的电位为低电平时，输出低电平的第一开关信号；
    所述第二开关信号输出端，适于在所述第一位线的电位为高电平而所述第二位线的电位为低电平时，输出高电平的第二开关信号，在所述第一位线的电位为低电平而所述第二位线的电位为高电平时，输出低电平的第二开关信号。
  9. 如权利要求5或8所述的静态随机存储器的故障检测电路，其特征在于，还包括：
    开关信号产生电路，适于产生所述第一开关信号及第二开关信号。
  10. 如权利要求9所述的静态随机存储器的故障检测电路，其特征在于，所述开关信号产生电路，包括：与非门电路及反相器电路，其中：
    所述与非门电路，第一输入端适于输入测试使能信号，第二输入端适于输入写使能信号，输出端适于输出所述第二开关信号；
    所述反相器电路，输入端与所述与非门电路的输出端耦接，输出端适于输出所述第一开关信号。
  11. 一种静态随机存储器，其特征在于，包括权利要求1至10任一项所述的静态随机存储器的故障检测电路。
  12. 如权利要求11所述的静态随机存储器，其特征在于，所述静态随机存储器每对逻辑互补位线之间，均设置有所述位线耦合电路。
  13. 如权利要求11所述的静态随机存储器，其特征在于，所述静态随机存储器中仅一对逻辑互补位线之间，设置有所述位线耦合电路。
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