WO2021135102A1 - 时钟产生电路及应用其的锁存器和计算设备 - Google Patents

时钟产生电路及应用其的锁存器和计算设备 Download PDF

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Publication number
WO2021135102A1
WO2021135102A1 PCT/CN2020/098899 CN2020098899W WO2021135102A1 WO 2021135102 A1 WO2021135102 A1 WO 2021135102A1 CN 2020098899 W CN2020098899 W CN 2020098899W WO 2021135102 A1 WO2021135102 A1 WO 2021135102A1
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Prior art keywords
terminal
circuit
latch
electrically connected
inverter
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PCT/CN2020/098899
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English (en)
French (fr)
Inventor
刘杰尧
张楠赓
吴敬杰
马晟厚
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杭州嘉楠耘智信息科技有限公司
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Priority to EP20908872.3A priority Critical patent/EP4068630A4/en
Priority to KR1020227025861A priority patent/KR102674336B1/ko
Publication of WO2021135102A1 publication Critical patent/WO2021135102A1/zh
Priority to US17/855,281 priority patent/US11799456B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Definitions

  • the present invention relates to a storage device controlled by a clock, in particular to a clock generation circuit used in a large-scale data operation device, a latch and a computing device using the same.
  • FIG. 1 is a circuit block diagram and timing diagram of a conventional latch.
  • the latch latch has an input terminal D, an output terminal Q, and a clock signal terminal CK.
  • the working principle is that when the clock signal CK is low level "0", the data of the input terminal D is transmitted to the output terminal Q, and is latched by the latch until the next clock cycle.
  • the data transmitted to the output terminal Q has a delay relative to the clock signal CK and the input terminal D.
  • the delay relative to the clock signal CK is CK2Q
  • the delay relative to the input terminal D is D2Q.
  • Figure 2 is a schematic diagram and timing diagram of the circuit structure of the cascade latch.
  • the clock signal terminal CK of each level of latch is connected to the same clock signal, because the clock signal is low
  • the data of the input terminal D of the previous level of latch will be directly transmitted to the output terminal Q, and the subsequent level of latch will transmit the new data directly to the next level of latch, which will produce The problem of data collusion.
  • the method of staggering the phase of the clock signal and reducing the pulse width of the clock signal is usually adopted.
  • FIG. 3 is a schematic diagram and timing diagram of the circuit structure of the cascade latch using different clock signals in the first mode.
  • the clock signal terminal CK of each level of latch is connected to a different clock signal, for example, latch latch1
  • the clock signal terminal CK of the latch is connected to the clock signal CK1
  • the clock signal terminal CK of the latch latch2 is connected to the clock signal CK2
  • the clock signal terminal CK of the latch latch3 is connected to the clock signal CK3, and so on.
  • the previous three-level latch latch1, latch2, and latch3 are examples.
  • the data input at the input terminal D is along the latches latch1, latch2, and latch3. That is, the data arrives at the latch latch1 first and arrives at latch3 at the latest. Because of the different delays of the clock signals CK1, CK2, CK3, the falling edge of the clock CK3 arrives at the latch3 first, and the falling edge of the clock CK1 arrives at the latest Reach latch1, that is, the latch where the data arrives first, the later the falling edge of the clock arrives.
  • the data transmitted by the latches latch1, latch2, and latch3 can be sequentially transmitted among the plurality of latches latch1, latch2, and latch3 in sequence, which can effectively avoid the problem of data collusion. At this time, it will bring another problem.
  • FIG. 4 is a schematic diagram and timing diagram of the circuit structure of a cascade latch using different clock signals in another manner.
  • the clock signal terminal CK of each level of latch is connected to a different clock signal, for example, latch latch1
  • the clock signal terminal CK of the latch is connected to the clock signal CK1
  • the clock signal terminal CK of the latch latch2 is connected to the clock signal CK2
  • the clock signal terminal CK of the latch latch3 is connected to the clock signal CK3, and so on.
  • the present invention provides a clock generation circuit and a latch and computing device using it, which can effectively shape the clock pulse, reduce the number of clock buffers used, and improve the accuracy and accuracy of data transmission and latching. Accuracy.
  • the present invention provides a clock generation circuit, which includes an input terminal for inputting a pulse signal; a first output terminal for outputting a first clock signal; and a second output terminal for outputting A second clock signal; an input driving circuit, a latch circuit, an edge shaping circuit, a feedback delay unit, and an output driving circuit; the input driving circuit, the latch circuit, the edge shaping circuit, the The feedback delay unit and the output driving circuit are sequentially connected in series between the input terminal and the first output terminal and the second output terminal.
  • the present invention also provides a latch, which includes: a data input terminal for inputting a data signal; a data output terminal for outputting the data signal; a clock signal input Terminal, used to input a first clock signal; a multi-level latch circuit connected in series between the data input terminal and the data output terminal in a first order; a multi-level clock generation circuit, according to a second The sequence is connected in series in sequence and electrically connected to the multi-level latch circuit; wherein the direction of the first sequence is opposite to the direction of the second sequence, and the clock generating circuit is the above-mentioned clock generating circuit.
  • the present invention also provides a computing device including one or more of the above-mentioned latches.
  • FIG. 1 is a circuit block diagram and timing diagram of a conventional latch.
  • FIG. 2 is a schematic diagram and timing diagram of the circuit structure of a conventional cascade latch.
  • FIG. 3 is a schematic diagram and timing diagram of the circuit structure of the cascaded latch using different clock signals in the first method in the prior art.
  • FIG. 4 is a schematic diagram and timing diagram of a circuit structure of another conventional cascade latch using different clock signals.
  • FIG. 5 is a schematic diagram of the circuit structure of a clock generating circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the circuit structure of an input driving circuit according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the circuit structure of a latch circuit according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of the circuit structure of an edge shaping circuit according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a circuit structure of a feedback delay unit according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of the circuit structure of an output driving circuit according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of the clock signal waveform at the second output terminal of the clock generating circuit.
  • FIG. 12 is a timing diagram of a latch unit under the control of a clock generating circuit according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram and timing diagram of a circuit structure of a latch according to an embodiment of the present invention.
  • FIG. 14 is a schematic diagram and timing diagram of a circuit structure of a latch according to another embodiment of the present invention.
  • INV1, INV2, INV3, INV4, INV5 inverter
  • N1, N2, N3 NMOS transistor
  • CKP1, CKP2, CKP3 clock signal
  • VDD power supply
  • connection here includes any direct and indirect electrical connection means. Indirect electrical connection means include connection through other devices.
  • FIG. 5 is a schematic diagram of the circuit structure of a clock generating circuit according to an embodiment of the present invention.
  • the clock generating circuit 100 includes an input terminal CKI, a first output terminal CKO1, and a second output terminal CKO2, an input driving circuit 101, a latch circuit 102, an edge shaping circuit 103, a feedback delay unit 104, and an output driving circuit 105 is sequentially connected in series between the input terminal CKI and the first output terminal CKO1 and the second output terminal CKO2.
  • FIG. 6 is a schematic diagram of a circuit structure of an input driving circuit according to an embodiment of the present invention.
  • the input driving circuit 101 is composed of two inverters INV1 and INV2 connected in series.
  • the inverters INV1 and INV2 each have an input terminal and an output terminal.
  • the input terminal of the inverter INV1 is electrically connected to the input terminal CKI of the clock generating circuit 100 for providing a starting clock signal to the clock generating circuit 100.
  • the output terminal of the inverter INV1 is electrically connected to the input terminal of the inverter INV2 and is electrically connected to the edge shaping circuit 103, and the output terminal of the inverter INV2 is electrically connected to the latch circuit 102.
  • the present invention only takes two inverters connected in series with each other as an example.
  • the input drive circuit 101 can also be composed of a plurality of inverters connected in series, so as to be electrically connected to the edge shaping circuit 103 and electrically connected to the The two output signals of the latch circuit 102 are reversed, and the present invention is not limited thereto.
  • FIG. 7 is a schematic diagram of the circuit structure of a latch circuit according to an embodiment of the present invention.
  • the latch circuit 102 is composed of two NAND gates NAND1 and NAND2 that are cross-connected with each other.
  • the NAND gates NAND1 and NAND2 each have a first input terminal, a second input terminal and an output terminal.
  • the first input terminal of the NAND gate NAND1 is electrically connected to the output terminal of the NAND gate NAND2, and the first input terminal of the NAND gate NAND1 is electrically connected to the output terminal of the NAND gate NAND2.
  • the two input terminals are electrically connected to the feedback delay unit 104, the output terminal of the NAND gate NAND1 is electrically connected to the edge shaping circuit 103 and the second input terminal of the NAND gate NAND2, and the first input terminal of the NAND gate NAND2 is electrically connected To the output terminal of the inverter INV2.
  • FIG. 8 is a schematic diagram of the circuit structure of an edge shaping circuit according to an embodiment of the present invention.
  • the edge shaping circuit includes PMOS transistors P1, P2, P3 and NMOS transistors N1, N2, N3.
  • Each PMOS transistor or NMOS transistor has a first terminal, a second terminal, and a control terminal. .
  • the first ends of the PMOS transistors P1 and P2 are electrically connected to the power supply VDD, the second ends of the PMOS transistors P1 and P2 are electrically connected to the first end of the PMOS transistor P3, and the second ends of the PMOS transistor P3 are electrically connected respectively To the first ends of the NMOS transistors N1 and N2, the second end of the NMOS transistor N2 is electrically connected to the first end of the NMOS transistor N3, the second ends of the NMOS transistors N1 and N3 are electrically connected to the ground VSS, the PMOS transistor P1 and The control terminal of the NMOS transistor N2 is electrically connected to the output terminal of the inverter INV1, the control terminals of the PMOS transistor P3 and the NMOS transistor N1 are electrically connected to the output terminal of the NAND gate NAND1, and the control terminals of the PMOS transistor P2 and the NMOS transistor N3 It is electrically connected to the second end of the PMOS transistor P3, and electrically connected to the feedback delay unit 104
  • FIG. 9 is a schematic diagram of a circuit structure of a feedback delay unit according to an embodiment of the present invention.
  • the feedback delay circuit 104 is composed of a plurality of inverters connected in series.
  • the feedback delay circuit 104 has an input terminal and an output terminal.
  • the input terminal of the feedback delay circuit 104 is electrically connected to the edge shaping circuit 103
  • the second terminal of the middle PMOS transistor P3 and the output terminal of the feedback delay circuit 104 are electrically connected to the second input terminal of the NAND gate NAND1.
  • the number of inverters constituting the feedback delay circuit 104 is an odd number to output a signal that is opposite to the input terminal. The specific number depends on the length of time required to delay the input signal, and the present invention is not limited to this.
  • FIG. 10 is a schematic diagram of the circuit structure of an output driving circuit according to an embodiment of the present invention.
  • the output driving circuit 105 includes inverters INV3, INV4, and INV5.
  • the inverters INV3, INV4, and INV5 all have an input terminal and an output terminal.
  • the input terminal of the inverter INV3 is electrically connected to the second terminal of the PMOS transistor P3 in the edge shaping circuit 103, and the output terminal of the inverter INV3 is electrically connected.
  • the input terminal of the inverter INV4 is electrically connected to the input terminal of the inverter INV3 and is connected together to the second terminal of the PMOS transistor P3 in the edge shaping circuit 103, the inverter INV4
  • the output terminal of the inverter is electrically connected to the input terminal of the inverter INV5, and the output terminal of the inverter INV5 is electrically connected to the second output terminal CKO2.
  • the present invention is only described by taking the number of inverters INV3, INV4, and INV5 as 1.
  • inverters INV3, INV4, and INV5 can also be formed by connecting multiple inverters in series, with the first output terminal CKO1 and the second output terminal CKO1 connected in series.
  • the output signal of the output terminal CKO2 is reversed, and the present invention is not limited to this.
  • the clock generating circuit 100 inputs an initial clock signal from the input terminal CKI, and generates two inverted clock signals through the clock generating circuit 100, which respectively pass through the first output terminal CKO1 and the second output terminal CKO1 and the second output terminal CKO1.
  • the output terminal CKO2 outputs.
  • FIG. 11 is a schematic diagram of the clock signal waveform at the second output terminal of the clock generating circuit.
  • FIG. 12 is a timing diagram of a latch unit under the control of a clock generating circuit according to an embodiment of the present invention.
  • the latch unit latch determines whether the data can be transmitted correctly depending on the data establishment time and data retention time, the time required for data retention (Hold Require Time), and the time required for data establishment ( Setup Require Time, latch unit hold time (Latch Hold), latch unit setup time (Latch Setup), clock delay time (CK Gen Delay), and clock pulse width (Pulse Width) must satisfy the following relationships:
  • FIG. 13 is a schematic diagram and timing diagram of a circuit structure of a latch according to an embodiment of the present invention.
  • the latch 200 includes cascaded latch circuits latch1, latch2, and latch3 and cascaded clock generating circuits CKG1, CKG2, CKG3.
  • the present invention is schematically illustrated with the number of stages being three. In practical applications, the number of stages may be more, and the present invention is not limited thereto.
  • the cascade sequence of latch circuits latch1, latch2, and latch3, that is, the data transmission sequence is from latch1 to latch2 to latch3, and the cascade sequence of clock generation circuits CKG1, CKG2, CKG3, that is, the transmission sequence of clock signals is from CKG1 to CKG2 and then CKG3.
  • the first-level clock generation circuit CKG1 is electrically connected to the third-level latch circuit latch3
  • the second-level clock generation circuit CKG2 is electrically connected to the second-level latch circuit latch2
  • the third-level clock generation circuit CKG3 It is electrically connected to the first-stage latch circuit latch1, that is, the cascade sequence of the latch circuits latch1, latch2, and latch3 is opposite to the cascade sequence of the clock generation circuit.
  • the second output terminals CKO2 of the clock generation circuits CKG1, CKG2, and CKG3 provide clock signals CKP1, CKP2, and CKP3 to the latch circuits latch3, latch2, and latch1, respectively.
  • the clock generation circuit CKG1 The first output terminal CKO1 is electrically connected to the input terminal CKI of the clock generating circuit CKG2, and the first output terminal CKO1 of the clock generating circuit CKG2 is electrically connected to the input terminal CKI of the clock generating circuit CKG3.
  • FIG. 14 is a schematic diagram and timing diagram of a circuit structure of a latch according to an embodiment of the present invention. As shown in FIG. 14, the difference from the embodiment shown in FIG. 13 is that the first output terminal CKO1 of the clock generating circuit CKG1 is electrically connected to the input terminal CKI of the clock generating circuit CKG2 and the input terminal CKI of the clock generating circuit CKG3.
  • the first-level latch circuit can correspond to the first-level clock generation circuit, that is, the first-level clock generation circuit provides a clock signal to the first-level latch circuit.
  • each level of latch circuit includes multiple latch units connected in series, multiple latch units connected in parallel, or multiple latch units combined in series and parallel, that is, the primary clock generation circuit provides multiple latch units Provide a clock signal.
  • each level of clock generation circuit may also include multiple clock generation circuits, and one clock generation circuit corresponds to one latch unit. Therefore, the multiple clock generating circuits formed in this way are connected to each other to form a clock tree.
  • the cascading sequence of the latch circuits is opposite to the cascading sequence of the clock generating circuits, a reverse clock tree is formed.
  • the second output terminal CKO2 of the clock generating circuit 100 is used to realize the function of signal re-establishment and enhancement.
  • the clock generation circuit provided by the present invention can generate a clock signal with the same pulse width regardless of the waveform of the initial clock signal, and can effectively reshape the pulse of the clock signal; in addition, the latch uses In the reverse clock tree design structure, the latch provided by the present invention can effectively realize the complete staggering of the phases between the clock signals, reduce the number of clock buffers used, and improve the accuracy and accuracy of data transmission and latching.
  • the present invention also provides a computing device, wherein the computing device includes one or more of the above-mentioned latches for storing and transmitting data.
  • the present invention can also have various other embodiments.
  • those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding All changes and deformations shall belong to the protection scope of the appended claims of the present invention.
  • the clock generation circuit provided by the present invention can generate a clock signal with the same pulse width regardless of the waveform of the initial clock signal, and can effectively shape the pulse of the clock signal; in addition, the latch adopts a reverse clock tree design
  • the structure can effectively realize the complete staggering of the phases between the clock signals, reduce the number of clock buffers used, and improve the correctness and accuracy of data transmission and latching.

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  • Engineering & Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种时钟产生电路及应用其的锁存器和计算设备，时钟产生电路包括一输入端，用于输入一脉冲信号（CKI）；一第一输出端，用于输出一第一时钟信号（CKO1）；一第二输出端，用于输出一第二时钟信号（CKO2）；一输入驱动电路（101）、一锁存电路（102）、一边沿整形电路（103）、一反馈延迟单元（104）以及一输出驱动电路（105）；所述输入驱动电路（101）、所述锁存电路（102）、所述边沿整形电路（103）、所述反馈延迟单元（104）以及所述输出驱动电路（105）依次串接在所述输入端与所述第一输出端以及所述第二输出端之间。可以有效对时钟脉冲进行整形，减少使用时钟缓冲器，提高数据传输、锁存的正确性和准确率。

Description

时钟产生电路及应用其的锁存器和计算设备 技术领域
本发明涉及一种受时钟控制的存储器件，尤其涉及一种在大规模数据运算设备中应用的时钟产生电路及应用其的锁存器和计算设备。
背景技术
锁存器应用非常广泛，可用做数字信号的寄存。图1为现有锁存器的电路框图及时序图。如图1所示，锁存器latch具有输入端D、输出端Q以及时钟信号端CK。其工作原理为当时钟信号CK为低电平“0”时，输入端D的数据传输至输出端Q，并被锁存器latch锁存，直至下一个时钟周期。且，由图1可以看出，传输至输出端Q的数据相对于时钟信号CK以及输入端D均具有延迟，例如，相对于时钟信号CK的延迟为CK2Q，相对于输入端D的延迟为D2Q。当多个锁存器串联连接在一起时，就会发生数据串通的问题。
图2为级联锁存器的电路结构示意图及时序图。如图2所示，当多个锁存器latch1、latch2、latch3...串联连接在一起时，每一级锁存器的时钟信号端CK均连接至相同的时钟信号，由于时钟信号在低电平时，前一级锁存器输入端D的数据会直接传送到输出端Q，而其后一级锁存器会把新的数据直接向下一级锁存器传输，由此将会产生数据串通的问题。为解决数据串通的问题，通常采用错开时钟信号相位以及减小时钟信号脉冲宽度的方式。
图3为第一方式采用不同时钟信号的级联锁存器的电路结构示意图及时序图。如图3所示，多个锁存器latch1、latch2、latch3...串联连接在一起时，每一级锁存器的时钟信号端CK均连接至不同的时钟信号，例如，锁存器latch1的时钟信号端CK连接至时钟信号CK1，锁存器latch2的时钟信号端CK连接至时钟信号CK2，锁存器latch3的时钟信号端CK连接至时钟信号CK3，以此类推。以前三级锁存器latch1、latch2以及latch3为例，由图3可以看出，由于时钟信号CK1、CK2以及CK3之间的相位错开，输入端D输入的数据沿锁存器latch1、latch2、latch3的方向进行传输，即数据最先到达锁存器latch1，最晚到达latch3，而时钟信号CK1、CK2、CK3由于延迟的不同，时钟CK3的下降沿最先到达latch3，时钟CK1的下降沿最晚到达latch1，也就 是说，数据先到达的锁存器，时钟的下降沿越晚到达。由此，可以使得锁存器latch1、latch2、latch3所传输的数据依次在多个锁存器latch1、latch2、latch3之间依序传输，能够有效避免数据串通的问题。而此时，又会带来另一个问题。
图4为另一方式采用不同时钟信号的级联锁存器的电路结构示意图及时序图。如图4所示，多个锁存器latch1、latch2、latch3...串联连接在一起时，每一级锁存器的时钟信号端CK均连接至不同的时钟信号，例如，锁存器latch1的时钟信号端CK连接至时钟信号CK1，锁存器latch2的时钟信号端CK连接至时钟信号CK2，锁存器latch3的时钟信号端CK连接至时钟信号CK3，以此类推。由图4可以看出，当时钟信号CK1、CK2以及CK3之间的相位不能完全错开，或者时钟信号CK1、CK2、CK3的脉冲宽度过宽时，将会导致锁存器不稳定状态之间的数据发生串通，由此产生的数据串通会将非理想的脉冲信号(glitch)直接串通到下一级，产生更大的功耗，进而导致应用锁存器的计算芯片所消耗的功耗超出预期，这种脉冲信号的串通在传统时序分析中又被称作保持失效。另外，为了实现时钟信号之间的相位能够完全错开，则需要数量巨大的缓冲器。
因此，如何有效减少缓冲器的数量，避免级联锁存器数据串通问题，提高数据传输、锁存的正确性和准确率实为需要解决的问题。
发明公开
为了解决上述问题，本发明提供一种时钟产生电路及应用其的锁存器和计算设备，可以有效对时钟脉冲进行整形，减少时钟缓冲器的使用数量，提高数据传输、锁存的正确性和准确率。
为了实现上述目的，本发明提供一种时钟产生电路，包括一输入端，用于输入一脉冲信号；一第一输出端，用于输出一第一时钟信号；一第二输出端，用于输出一第二时钟信号；一输入驱动电路、一锁存电路、一边沿整形电路、一反馈延迟单元以及一输出驱动电路；所述输入驱动电路、所述锁存电路、所述边沿整形电路、所述反馈延迟单元以及所述输出驱动电路依次串接在所述输入端与所述第一输出端以及所述第二输出端之间。
为了更好地实现上述目的，本发明还提供了一种锁存器，包括：一数据输 入端，用于输入一数据信号；一数据输出端，用于输出所述数据信号；一时钟信号输入端，用于输入一第一时钟信号；多级锁存电路，按照一第一顺序依次串联连接在所述数据输入端与所述数据输出端之间；多级时钟产生电路，按照一第二顺序依次串联连接，并电性连接至所述多级锁存电路；其中，所述第一顺序与所述第二顺序的方向相反，且所述时钟产生电路为上述的时钟产生电路。
为了更好地实现上述目的，本发明还提供了一种计算设备，包括一个或多个上述的锁存器。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图简要说明
图1为现有锁存器的电路框图及时序图。
图2为现有级联锁存器的电路结构示意图及时序图。
图3为现有第一方式采用不同时钟信号的级联锁存器的电路结构示意图及时序图。
图4为现有另一方式采用不同时钟信号的级联锁存器的电路结构示意图及时序图。
图5为本发明一实施例时钟产生电路的电路结构示意图。
图6为本发明一实施例输入驱动电路的电路结构示意图。
图7为本发明一实施例锁存电路的电路结构示意图。
图8为本发明一实施例边沿整形电路的电路结构示意图。
图9为本发明一实施例反馈延迟单元的电路结构示意图。
图10为本发明一实施例输出驱动电路的电路结构示意图。
图11为时钟产生电路第二输出端的时钟信号波形示意图。
图12为本发明一实施例在时钟产生电路控制下锁存单元的时序图。
图13为本发明一实施例锁存器的电路结构示意图及时序图。
图14为本发明另一实施例锁存器的电路结构示意图及时序图。
其中，附图标记：
100：时钟产生电路
101：输入驱动电路
102：锁存电路
103：边沿整形电路
104：反馈延迟单元
105输出驱动电路
200：锁存器
INV1、INV2、INV3、INV4、INV5：反向器
NAND1、NAND2：与非门
P1、P2、P3：PMOS晶体管
N1、N2、N3：NMOS晶体管
CKG、CKG1、CKG2、CKG3：时钟产生电路
CKI：输入端
CKO1：第一输出端
CKO2：第二输出端
CKP1、CKP2、CKP3：时钟信号
latch1、latch2、latch3：锁存电路
D1、D2、D3：输入端
Q1、Q2、Q3：输出端
DC：延迟电路
VDD：电源
VSS：地
实现本发明的最佳方式
下面结合附图对本发明的结构原理和工作原理作具体的描述：
在说明书及后续的权利要求当中使用了某些词汇来指称特定组件。所属领域中具有通常知识者应可理解，制造商可能会用不同的名词来称呼同一个组件。本说明书及后续的权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。
在通篇说明书及后续的权利要求当中所提及的“包括”和“包含”为一开放式的用语，故应解释成“包含但不限定于”。以外，“连接”一词在此为包含任何 直接及间接的电性连接手段。间接的电性连接手段包括通过其它装置进行连接。
图5为本发明一实施例时钟产生电路的电路结构示意图。如图5所示，时钟产生电路100包括输入端CKI、第一输出端CKO1以及第二输出端CKO2，输入驱动电路101、锁存电路102、边沿整形电路103、反馈延迟单元104以及输出驱动电路105依次串联连接在输入端CKI与第一输出端CKO1以及第二输出端CKO2之间。
具体的，图6为本发明一实施例输入驱动电路的电路结构示意图。结合图5、图6所示，输入驱动电路101由串联连接的两个反向器INV1、INV2构成。其中，反向器INV1、INV2均具有输入端和输出端，反向器INV1的输入端电性连接至时钟产生电路100的输入端CKI，用于向时钟产生电路100提供一起始时钟信号，反向器INV1的输出端电性连接至反向器INV2的输入端，并电性连接至边沿整形电路103，反向器INV2的输出端电性连接至锁存电路102。本发明仅以相互串联连接的两个反向器为例，当然，输入驱动电路101也可以多个串联连接的反向器构成，以能够实现电性连接至边沿整形电路103以及电性连接至锁存电路102的两个输出信号反向为准，本发明并不以此为限。
具体的，图7为本发明一实施例锁存电路的电路结构示意图。结合图5-图7所示，锁存电路102由相互交叉连接的两个与非门NAND1、NAND2构成。其中，与非门NAND1、NAND2均具有第一输入端、第二输入端和输出端，与非门NAND1的第一输入端电性连接至与非门NAND2的输出端，与非门NAND1的第二输入端电性连接至反馈延迟单元104，与非门NAND1的输出端电性连接至边沿整形电路103以及与非门NAND2的第二输入端，与非门NAND2的第一输入端电性连接至反向器INV2的输出端。
具体的，图8为本发明一实施例边沿整形电路的电路结构示意图。结合图5-图8所示，所述边沿整形电路包括PMOS晶体管P1、P2、P3以及NMOS晶体管N1、N2、N3，每一PMOS晶体管或NMOS晶体管均具有第一端、第二端以及控制端。其中，PMOS晶体管P1、P2的第一端电性连接至电源VDD，PMOS晶体管P1、P2的第二端电性连接至PMOS晶体管P3的第一端，PMOS晶体管P3的第二端分别电性连接至NMOS晶体管N1、N2的第一端，NMOS晶体管N2的第二端电性连接至NMOS晶体管N3的第一端，NMOS晶体管N1、N3的第二端电性 连接至地VSS，PMOS晶体管P1以及NMOS晶体管N2的控制端电性连接至反向器INV1的输出端，PMOS晶体管P3以及NMOS晶体管N1的控制端电性连接至与非门NAND1的输出端，PMOS晶体管P2与NMOS晶体管N3的控制端电性连接至PMOS晶体管P3的第二端，并电性连接至反馈延迟单元104以及输出驱动电路105。
图9为本发明一实施例反馈延迟单元的电路结构示意图。如图5-图9所示，反馈延迟电路104由多个串联连接的反向器构成，反馈延迟电路104具有输入端以及输出端，反馈延迟电路104的输入端电性连接至边沿整形电路103中PMOS晶体管P3的第二端，反馈延迟电路104的输出端电性连接至与非门NAND1的第二输入端。需要说明的是，构成反馈延迟电路104的反向器数量为奇数个，以输出与输入端反向的信号。具体数量取决于需要对输入信号延迟的时间长短，本发明并不以此为限。
图10为本发明一实施例输出驱动电路的电路结构示意图。如图5-图10所示，输出驱动电路105包括反向器INV3、INV4以及INV5。其中，反向器INV3、INV4以及INV5均具有输入端以及输出端，反向器INV3的输入端电性连接至边沿整形电路103中PMOS晶体管P3的第二端，反向器INV3的输出端电性连接至第一输出端CKO1，反向器INV4的输入端电性与反向器INV3的输入端电性连接并共同连接至边沿整形电路103中PMOS晶体管P3的第二端，反向器INV4的输出端电性连接至反向器INV5的输入端，反向器INV5的输出端电性连接至第二输出端CKO2。本发明仅以反向器INV3、INV4以及INV5的数量为1进行描述，当然，反向器INV3、INV4以及INV5也可以由多个反向器串联连接形成，以第一输出端CKO1与第二输出端CKO2的输出信号反向为准，本发明并不以此为限。
由此，结合图5-图10所示，时钟产生电路100由输入端CKI输入一起始时钟信号，经过时钟产生电路100产生两个反向的时钟信号，分别通过第一输出端CKO1和第二输出端CKO2输出。图11为时钟产生电路第二输出端的时钟信号波形示意图。如图1、图11所示，由于时钟产生电路100中第一输出端CKO1以及第二输出端CKO2输出的时钟信号仅仅与输入端CKI输入的起始时钟信号的上升沿有关，因此，不论时钟产生电路100中输入端CKI输入的起始时钟信号脉冲宽度为宽或窄，时钟产生电路100的第二输出端CKO2输出的时钟 信号脉冲宽度不会发生变化。
图12为本发明一实施例在时钟产生电路控制下锁存单元的时序图。如图12所示，对于锁存单元latch而言，数据是否能正确的进行传输取决于数据的建立时间和数据的保持时间，数据保持需要的时间(Hold Require Time)、数据建立需要的时间(Setup Require Time)、锁存单元的保持时间(Latch Hold)、锁存单元的建立时间(Latch Setup)、时钟延迟时间(CK Gen Delay)以及时钟脉冲宽度(Pulse Width)之间需满足如下关系：
Hold Require Time＝Latch Hold+(CK Gen Delay+Pulse Width)(式一)
Setup Require Time＝Latch Setup-(CK Gen Delay+Pulse Width)(式二)。如果Latch Setup＜Pulse Width，为保证级联的锁存单元不稳定状态之间的数据不串通，则需要Setup Require Time＝max(Latch setup，Pulse Width)，如此，就会限制时钟信号的脉冲宽度(Pulse Width)。如果Latch Setup＞Pulse Width，则会出现无法写入问题。也就是说，在锁存单元的整个数据写入阶段都无法满足数据建立需求。为此，本发明提出如下的锁存器。
图13为本发明一实施例锁存器的电路结构示意图及时序图。如图13所示，锁存器200包括级联的锁存电路latch1、latch2、latch3以及级联的时钟产生电路CKG1、CKG2、CKG3。本发明以级数为3级进行示意性说明，在实际应用中，级数可能为更多，本发明并不以此为限。其中，锁存电路latch1、latch2、latch3的级联顺序即数据的传输顺序为由latch1至latch2再至latch3，时钟产生电路CKG1、CKG2、CKG3的级联顺序即时钟信号的传输顺序为由CKG1至CKG2再至CKG3。需要说明的是，第一级时钟产生电路CKG1电性连接至第三级锁存电路latch3，第二级时钟产生电路CKG2电性连接至第二级锁存电路latch2，第三级时钟产生电路CKG3电性连接至第一级锁存电路latch1，也就是说，锁存电路latch1、latch2、latch3的级联顺序与时钟产生电路的级联顺序方向相反。
为更详细说明，再参照图13所示，时钟产生电路CKG1、CKG2以及CKG3的第二输出端CKO2分别向锁存电路latch3、latch2、latch1提供时钟信号CKP1、CKP2以及CKP3，时钟产生电路CKG1的第一输出端CKO1电性连接至时 钟产生电路CKG2的输入端CKI，时钟产生电路CKG2的第一输出端CKO1电性连接至时钟产生电路CKG3的输入端CKI。由于，第一输出端CKO1与第二输出端CKO2输出的时钟信号反向，所以，时钟信号CKP1、CKP2以及CKP3之间的相位完全错开，不会出现相位重叠的情况，相较于通过连接缓冲器来使时钟信号CKP1、CKP2以及CKP3之间实现相位错开而言更有效率，也更能确保相位完全错开，还可以节约使用缓冲器。
图14为本发明一实施例锁存器的电路结构示意图及时序图。如图14所示，与图13所示实施例不同之处在于，时钟产生电路CKG1的第一输出端CKO1电性连接至时钟产生电路CKG2的输入端CKI以及时钟产生电路CKG3的输入端CKI。由此，当相邻的两级锁存电路例如latch1和latch2之间存在较大的逻辑延迟时，例如latch1的输出端Q1与latch2的输入端D2之间电性连接有延迟电路DC时，根据(式二)：Setup Require Time＝Latch Setup-(CK Gen Delay+Pulse Width)，可以解决关键时序路径(critical path)的时钟建立问题，从而提高锁存器的工作频率。
当然，在实际应用中，一级锁存电路可以与一级时钟产生电路相对应，即一级时钟产生电路向一级锁存电路提供时钟信号。也可以是每一级锁存电路包括多个串联连接的锁存单元、多个并联连接的锁存单元或串并结合的多个锁存单元，即一级时钟产生电路向多个锁存单元提供时钟信号。另外，根据负载驱动需要，每一级时钟产生电路也可以包括多个时钟产生电路，一个时钟产生电路与一个锁存单元相对应。由此，这样形成的多个时钟产生电路相互连接在一起，就构成了时钟树，由于锁存电路的级联顺序与时钟产生电路的级联顺序方向相反，也就构成了逆向时钟树。同时，利用时钟产生电路100的第二输出端CKO2，实现信号重新建立与增强的功能。在时钟树扇出(fanout)很大即其负载(loading)很大的情况下，可以改善数据的传输性能。
综上所述，本发明提供的时钟产生电路无论其起始时钟信号的波形如何，都可以产生脉冲宽度相同的时钟信号，可以有效对时钟信号的脉冲进行整形；另外，锁存器由于采用了逆向时钟树的设计结构，本发明提供的锁存器可以有效实现完全错开时钟信号之间的相位，减少时钟缓冲器的使用数量，提高数据传输、锁存的正确性和准确率。
本发明还提供一种计算设备，其中，计算设备中包括一个或多个上述的锁 存器，用于存储和传输数据。
换言之，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
工业应用性
采用本发明的时钟产生电路及应用其的锁存器和计算设备，具有以下有益效果：
本发明提供的时钟产生电路无论其起始时钟信号的波形如何，都可以产生脉冲宽度相同的时钟信号，可以有效对时钟信号的脉冲进行整形；另外，锁存器由于采用了逆向时钟树的设计结构，可以有效实现完全错开时钟信号之间的相位，减少时钟缓冲器的使用数量，提高数据传输、锁存的正确性和准确率。

Claims (15)

  1. 一种时钟产生电路，其特征在于，包括：
    一输入端，用于输入一脉冲信号；
    一第一输出端，用于输出一第一时钟信号；
    一第二输出端，用于输出一第二时钟信号；
    一输入驱动电路、一锁存电路、一边沿整形电路、一反馈延迟单元以及一输出驱动电路；
    所述输入驱动电路、所述锁存电路、所述边沿整形电路、所述反馈延迟单元以及所述输出驱动电路依次串接在所述输入端与所述第一输出端以及所述第二输出端之间。
  2. 如权利要求1所述的时钟产生电路，其特征在于：所述输入驱动电路包括依次串联连接的一第一反向器以及一第二反向器，所述第一反向器、所述第二反向器具有一第一端以及一第二端，所述第一反向器的所述第一端电性连接至所述输入端，所述第二反向器的所述第二端电性连接至所述锁存电路，所述第一反向器的所述第二端电性连接至所述第二反向器的所述第一端以及所述边沿整形电路。
  3. 如权利要求2所述的时钟产生电路，其特征在于：所述锁存电路包括相互交叉连接的一第一与非门以及一第二与非门，所述第一与非门、所述第二与非门具有一第一端、一第二端以及一第三端，所述第一与非门的所述第一端电性连接至所述第二与非门的所述第三端，所述第一与非门的所述第二端电性连接至所述反馈延迟单元，所述第一与非门的所述第三端电性连接至所述第二与非门的所述第二端以及所述边沿整形电路，所述第二与非门的所述第一端电性连接至所述第二反向器的所述第二端，所述第二与非门的所述第一端电性连接至所述第二反向器的所述第二端。
  4. 如权利要求3所述的时钟产生电路，其特征在于：所述边沿整形电路包括一第一PMOS晶体管、一第二PMOS晶体管、一第三PMOS晶体管、一第一NMOS晶体管、一第二NMOS晶体管以及一第三NMOS晶体管，所述第一PMOS晶体管、所述第二PMOS晶体管、所述第三PMOS晶体管、所述第一NMOS晶体管、所述第二NMOS晶体管以及所述第三NMOS晶体管具有一第一端、一第二端以及 一控制端，所述第一PMOS晶体管以及所述第二PMOS晶体管的所述第一端电性连接至一电源，所述第一PMOS晶体管以及所述第二PMOS晶体管的所述第二端电性连接至所述第三PMOS晶体管的所述第一端，所述第三PMOS晶体管的所述第二端分别电性连接至所述第一NMOS晶体管以及所述第二NMOS晶体管的所述第一端，所述第二NMOS晶体管的所述第二端电性连接至所述第三NMOS晶体管的所述第一端，所述第一NMOS晶体管以及所述第三NMOS晶体管的所述第二端电性连接至一地，所述第一PMOS晶体管以及所述第二NMOS晶体管的所述控制端电性连接至所述第一反向器的所述第二端，所述第三PMOS晶体管以及所述第一NMOS晶体管的所述控制端电性连接至所述第一与非门的所述第三端，所述第二PMOS晶体管与所述第三NMOS晶体管的所述控制端电性连接至所述第三PMOS晶体管的所述第二端、所述反馈延迟单元以及所述输出驱动电路。
  5. 如权利要求4所述的时钟产生电路，其特征在于：所述反馈延迟电路包括一第一端、一第二端，以及多个串联连接在所述反馈延迟电路的所述第一端与所述反馈延迟电路的所述第二端之间的反向器，所述反馈延迟电路的所述第一端电性连接至所述第三PMOS晶体管的所述第二端，所述反馈延迟电路的所述第二端电性连接至所述第一与非门的所述第二端。
  6. 如权利要求5所述的时钟产生电路，其特征在于：所述输出驱动电路包括一第三反向器、一第四反向器以及一第五反向器，所述第三反向器、所述第四反向器以及所述第五反向器具有一第一端以及一第二端，所述第三反向器的所述第一端电性连接至所述第三PMOS晶体管的所述第二端，所述第三反向器的所述第二端电性连接至所述第一输出端，所述第四反向器的所述第一端电性连接至所述第三PMOS晶体管的所述第二端，所述第四反向器的所述第二端电性连接至所述第五反向器的所述第一端，所述第五反向器的所述第二端电性连接至所述第二输出端。
  7. 一种锁存器，其特征在于，包括：
    一数据输入端，用于输入一数据信号；
    一数据输出端，用于输出所述数据信号；
    一时钟信号输入端，用于输入一第一时钟信号；
    多级锁存电路，按照一第一顺序依次串联连接在所述数据输入端与所述数据输出端之间；
    多级时钟产生电路，按照一第二顺序依次串联连接，并电性连接至所述多级锁存电路；
    其中，所述第一顺序与所述第二顺序的方向相反，且所述时钟产生电路为如权利要求1所述的时钟产生电路。
  8. 如权利要求7所述的锁存器，其特征在于：一级所述锁存电路与一级所述时钟产生电路相对应。
  9. 如权利要求8所述的锁存器，其特征在于：每一级所述锁存电路进一步包括多个锁存单元。
  10. 如权利要求9所述的锁存器，其特征在于：每一级所述时钟产生电路进一步包括多个所述时钟产生电路。
  11. 如权利要求9所述的锁存器，其特征在于：所述多个锁存单元的连接方式为串联连接。
  12. 如权利要求9所述的锁存器，其特征在于：所述多个锁存单元的连接方式为并联连接。
  13. 如权利要求9所述的锁存器，其特征在于：所述多个锁存单元的连接方式为串并结合。
  14. 如权利要求10所述的锁存器，其特征在于：每一所述锁存单元与每一所述时钟产生电路相对应。
  15. 一种计算设备，其特征在于，包括一个或多个如权利要求7-14中所述的任意一种锁存器。
PCT/CN2020/098899 2019-12-30 2020-06-29 时钟产生电路及应用其的锁存器和计算设备 WO2021135102A1 (zh)

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