WO2021129887A1 - 一种视频光纤坐席接收装置 - Google Patents

一种视频光纤坐席接收装置 Download PDF

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WO2021129887A1
WO2021129887A1 PCT/CN2020/141934 CN2020141934W WO2021129887A1 WO 2021129887 A1 WO2021129887 A1 WO 2021129887A1 CN 2020141934 W CN2020141934 W CN 2020141934W WO 2021129887 A1 WO2021129887 A1 WO 2021129887A1
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video
circuit
signal processing
sub
fpga
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PCT/CN2020/141934
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English (en)
French (fr)
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王晓杰
王飞
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威创集团股份有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/22—Adaptations for optical transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/765—Interface circuits between an apparatus for recording and another apparatus

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  • the present invention relates to the field of FPGA-based processing technology, and more specifically, to a video optical fiber seat receiving device.
  • the processing process of the optical fiber access network video signal stream in the prior art is to first access the Ethernet network through a switch chip, and then use a proprietary decoding chip or FPGA to analyze the received video The signal is decoded and restored, and then transmitted to the video transmission interface chip in a specific format, which is driven by the interface chip and sent to the display unit to complete the receiving process of the optical fiber video signal stream.
  • the video signal stream is transmitted based on the network protocol, and the video signal stream is decoded and restored in the video decoder and the main video signal processing is completed. Due to the need to buffer multiple frames of images during the decoding process, there are varying degrees of delay between the video signal source and the output real-time video, and because the video signal processing process is highly concentrated on the proprietary decoding chip, the requirements for the chip itself are relatively high. High, high requirements for heat dissipation conditions, and reduced system reliability.
  • the present invention aims to overcome at least one of the above-mentioned defects of the prior art and provide a video optical fiber seat receiving device for optimizing the signal processing of the original video, reducing system delay, simplifying system design, and enhancing the reliability of system operation.
  • a video optical fiber seat receiving device includes a redundant optical module receiving circuit, an FPGA signal processing circuit group, an output encoding circuit and an output interface circuit.
  • the FPGA signal processing circuit group includes a main FPGA signal processing circuit and at least two sub-FPGA signals Processing circuit
  • the redundant optical module receiving circuit which is connected to the main FPGA signal processing circuit, is used to convert the received serial video optical signal into a serial video electrical signal, and input it to the main FPGA signal processing circuit;
  • the main FPGA signal processing circuit which is connected to at least two sub-FPGA signal processing circuits, is used to deserialize the serial video electrical signal and reduce the clock frequency of the video electrical signal, and transmit the processed video electrical signal to at least Two sub-FPGA signal processing circuits;
  • Sub-FPGA signal processing circuit which is connected to the output encoding circuit, and is used to transfer the video electrical signal processed by the main FPGA signal processing circuit to the output encoding circuit after completing the time sequence conversion;
  • An output encoding circuit which is connected to the output interface circuit, and is used to synthesize the multiple video electrical signals after the timing conversion is completed;
  • the output interface circuit is used to output the complete video electrical signal synthesized by the output coding circuit.
  • the video optical fiber receiving device of the present invention integrates a redundant optical module receiving circuit, a main FPGA signal processing circuit, at least two sub-FPGA signal processing circuits, an output coding circuit and an output interface circuit to reduce system delay and optimize signal processing functions. .
  • the redundant optical module receiving circuit first use the redundant optical module receiving circuit to receive the real-time serial video optical signal, convert the serial video optical signal into a serial video electrical signal, and input the converted serial video electrical signal to the main FPGA signal processing circuit, Secondly, the main FPGA signal processing circuit is used to deserialize the serial video electrical signal, reduce the clock frequency of the video electrical signal, complete the main signal processing process, and transmit the processed video electrical signal to at least two sub-FPGA signals.
  • the processing circuit then performs specific timing conversion on the video electrical signal processed by the main FPGA signal processing circuit in the sub-FPGA signal processing circuit, and finally completes the synthesis of multiple video electrical signals after the timing conversion is completed in the output encoding circuit, and The combined complete video electrical signal is output through the output interface circuit.
  • the signal processing completed by the original video in the process is greatly optimized, and the buffered image is reduced, thereby optimizing the delay of the device;
  • the image quality of the original video signal is highly retained, and the image quality degradation caused by different video encoding is reduced;
  • the video signal of the device is directly input to the FPGA signal processing circuit for processing after photoelectric conversion, without the need for Ethernet Protocol conversion thus simplifies system design; and the maximum resolution that the device of the invention can support can reach 4k ultra-high definition resolution.
  • the device of the present invention uses multiple FPGA signal processing circuits to perform different signal processing respectively, which reduces the integration requirements of the main FPGA, makes the selection of FPGA combination more flexible, reduces the power consumption of the main FPGA, and enhances the reliability of the operation of the device.
  • a control method of a video optical fiber seat receiving device includes the following steps:
  • the steps of the control method of a video optical fiber receiving device of the present invention are as follows: firstly, controlling the video optical fiber receiving device to receive real-time serial video optical signals, and convert the real-time serial video optical signals into serial video electrical signals; secondly, controlling the serial video
  • the electrical signal is deserialized, the clock frequency of the video electrical signal is reduced, the main signal processing process is completed, the processed video electrical signal is obtained, and the processed video electrical signal is divided according to the division of the display screen corresponding to the video signal.
  • the control method of the present invention from receiving the real-time serial video optical signal to outputting the complete video electrical signal, the signal processing completed in the original video process has been greatly optimized, and the buffered image is reduced, thereby optimizing the delay problem;
  • the image quality of the original video signal is highly preserved, and the image quality degradation caused by different video encoding is reduced; and the control method of the device of the present invention enables the device to support a maximum resolution of up to 4k ultra-high-definition resolution .
  • the method of the present invention reduces the power consumption of the main signal processing by splitting and streaming multiple sub-video electrical signals, so that the reliability of the system operation is enhanced.
  • the present invention provides a video optical fiber receiving device and control method. From receiving real-time serial video optical signals to outputting the complete video electrical signal after signal processing, the signal processing completed by the original video in the whole process has been greatly optimized, reducing The buffered image is reduced, and the delay of the device is reduced; in the process of video signal processing, the image quality of the original video signal is highly retained, and the image quality degradation caused by different video encoding is reduced; the video signal of the device is directly input after photoelectric conversion
  • the FPGA signal processing circuit is processed without Ethernet protocol conversion, thereby simplifying the system design; and the maximum resolution that the device of the present invention can support can reach 4k ultra-high-definition resolution.
  • the device of the present invention uses multiple FPGA signal processing circuits to complete different signal processing, which reduces the signal processing pressure of the main FPGA and reduces the integration requirements of the main FPGA compared with the overall function completed by a single FPGA, so that the FPGA
  • the combination selection is more flexible, the power consumption of the main FPGA is reduced, and the operation reliability of the device is strengthened.
  • Fig. 1 is a schematic diagram of structural connection of an embodiment of the present invention.
  • Fig. 2 is a structural relationship diagram of multiple FPGA signal processing circuits in an embodiment of the present invention.
  • Fig. 3 is a block diagram of the entire device structure in an embodiment of the present invention.
  • Fig. 4 is a flowchart of a control method according to an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of the structural connection of a video optical fiber seat receiving device according to an embodiment of the present invention.
  • a video optical fiber seat receiving device may include a redundant optical module receiving circuit, an FPGA signal processing circuit group, and an output encoding circuit. And an output interface circuit, the FPGA signal processing circuit group includes a main FPGA signal processing circuit and at least two sub-FPGA signal processing circuits;
  • Redundant optical module receiving circuit which is connected to the main FPGA signal processing circuit, used to convert the received serial video optical signal into a serial video electrical signal, and input to the main FPGA signal processing circuit, specifically, the redundant optical module
  • the receiving circuit is connected to the optical fiber to receive the serial video optical signal transmitted from the optical fiber;
  • the main FPGA signal processing circuit which is connected to at least two sub-FPGA signal processing circuits, is used to deserialize the serial video electrical signal and reduce the clock frequency of the video electrical signal, and transmit the processed video electrical signal to at least Two sub-FPGA signal processing circuits;
  • the high-speed serial video electrical signal input by the redundant optical module receiving circuit completes the main signal processing processes such as deserialization and OSD superposition at the main FPGA signal processing circuit, reducing the clock frequency of the video electrical signal , And then transmit the video signal after the main signal processing is completed to at least two sub-FPGA signal processing circuits according to the actual split screen situation.
  • Sub-FPGA signal processing circuit which is connected to the output encoding circuit, and is used to transfer the video electrical signal processed by the main FPGA signal processing circuit to the output encoding circuit after completing the time sequence conversion;
  • the embodiment of the present invention includes at least two sub-FPGA signal processing circuits, and the number of the sub-FPGA signal processing circuits is determined in the following manner:
  • the display screen corresponding to the video signal is divided into at least two sub-screen areas, and the number of sub-FPGA signal processing circuits is correspondingly determined according to the number of sub-screen areas.
  • the display screen is divided into upper and lower or left and right sub-screen areas
  • the plurality of sub-FPGA signal processing circuits include two sub-FPGA signal processing circuits corresponding to the two sub-screen areas, and the two sub-FPGA signals
  • the processing circuit respectively completes the time sequence conversion of the video signals of the two split screen areas and transmits them to the output encoding circuit.
  • the split screen area it can be divided into upper and lower split screen areas or left and right split screen areas. This embodiment only proposes Divided into the left and right split screen areas.
  • the display screen is divided into two left and right split screen areas.
  • the main FPGA signal processing circuit completes the signal processing of the high-speed serial electrical signal, it is divided into left and right split screen video signals input to two according to the split screen area.
  • a sub-FPGA signal processing circuit, left and right sub-FPGA signal processing circuits respectively receive the left and right half of the image and video signal, complete the signal timing conversion process of the left and right half of the screen image area, and output the left half of the screen image data signal and the right half of the screen image data signal.
  • An output encoding circuit which is connected to the output interface circuit, and is used to synthesize the multiple video electrical signals after the timing conversion is completed;
  • the output encoding circuit adopts an HDMI output encoding circuit
  • the HDMI output encoding circuit includes an HDMI encoding and equalization chip to realize the encoding function of the serial video electrical signal.
  • the HDMI output encoding circuit encodes the multiple video electrical signals and synthesizes a complete image signal before transmitting to the output interface circuit.
  • the output interface circuit is used to output the complete video electrical signal synthesized by the output coding circuit.
  • the output interface circuit in the embodiment of the present invention adopts the HDMI output interface circuit.
  • HDMI High Definition Multimedia Interface
  • the maximum data transmission speed is 2.25 GB/s, and there is no need to perform digital/analog or analog/digital conversion before signal transmission.
  • the embodiment of the present invention adopts the HDMI interface, the signal transmission speed is fast, and the video signal quality loss is small, and the best video quality can be provided.
  • the embodiment of the present invention further includes a control circuit, which is connected to the main FPGA signal processing circuit, and is used to control the sending and receiving and scheduling of video signals.
  • a control circuit which is connected to the main FPGA signal processing circuit, and is used to control the sending and receiving and scheduling of video signals.
  • FIG. 3 is a structural block diagram of the entire device according to an embodiment of the present invention.
  • the control circuit in the embodiment of the present invention includes an MPU main controller and a peripheral circuit connected to the MPU main controller, and the MPU main controller is connected to the main FPGA signal processing circuit.
  • the MPU is used to control the sending and receiving and scheduling of video signals, and to control the processing process of the video signal by the FPGA signal processing circuit in the device.
  • the peripheral circuit connected with the MPU main controller is controlled by the MPU main controller and is used to complete a series of seat functions.
  • the peripheral circuit in the embodiment of the present invention includes a USB interface circuit and a USB HUB interface circuit,
  • the USB interface circuit is used to import existing external video data signals
  • the USB HUB interface circuit is used to access keyboard and mouse information to complete the interaction between optical fiber seats.
  • the embodiment of the present invention includes a USB interface circuit and two USB HUB interface circuits.
  • the USB interface circuit can import U disk data signals, so that the device can read not only real-time video sources, but also existing video files.
  • the specific signal processing process of the existing video signal is the same as the real-time video signal processing process.
  • the signal processing process is completed through the FPGA signal processing circuit, and finally the complete video signal is output through the HDMI output encoding circuit and the HDMI output interface circuit.
  • Two USB HUB interface circuits are used to access keyboard and mouse information, and complete the interaction between optical fiber seats through the keyboard and mouse information.
  • the peripheral circuit in the embodiment of the present invention may also include a memory chipset circuit, an Ethernet interface circuit, an RS232 debugging circuit, an LCD control circuit, an audio receiving and loop-out circuit, among which developers can easily debug the serial port through the RS232 debugging circuit.
  • the audio signal is connected in the processing, and the audio signal is processed to realize the combination of video and audio to output a complete image effect.
  • the video optical fiber receiving device from receiving the real-time serial video optical signal to outputting the complete video electrical signal after signal processing, the signal processing completed by the original video in the whole process has been greatly optimized.
  • signal delay there are optimizations ranging from tens of milliseconds to a few seconds, which reduces the buffered image and realizes the reduction of device delay; in the process of video signal processing, the image quality of the original video signal is highly retained, and the difference is reduced.
  • the video encoding of the device causes the image quality to drop; the video signal of the device is directly input to the FPGA signal processing circuit for processing after photoelectric conversion, without the need for Ethernet protocol conversion, thereby simplifying the system design; and the maximum resolution that the device of the present invention can support can reach 4k ultra high definition resolution.
  • the device of the present invention uses multiple FPGA signal processing circuits to complete different signal processing, which reduces the signal processing pressure of the main FPGA and reduces the integration requirements of the main FPGA compared with the overall function completed by a single FPGA, so that the FPGA The combination selection is more flexible, the power consumption of the main FPGA is reduced, and the operation reliability of the device is strengthened.
  • FIG. 4 is a step diagram of a control method of a video optical fiber seat receiving device.
  • the control method includes the following steps:
  • step S2 in the embodiment of the present invention the number of sub-video electrical signals is determined in the following manner:
  • the display screen corresponding to the video signal is divided into upper and lower or left and right sub-screen areas, and the video electrical signal corresponds to the upper and lower or left and right sub-screen areas to split out two sub-video electrical signals.
  • the processed video electrical signal is divided into at least two divided video electrical signals.
  • the control method of the present invention from receiving the real-time serial video optical signal to outputting the complete video electrical signal, the signal processing completed in the original video process has been greatly optimized, and the buffered image is reduced, thereby optimizing the delay problem;
  • the image quality of the original video signal is highly preserved, and the image quality degradation caused by different video encoding is reduced; and the control method of the device of the present invention enables the device to support a maximum resolution of 4k ultra-high-definition resolution.
  • the method of the present invention reduces the power consumption of the main signal processing by splitting and streaming multiple sub-video electrical signals, so that the reliability of the system operation is enhanced.

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Abstract

一种视频光纤坐席接收装置，包括冗余光模块接收电路，与主FPGA信号处理电路连接，用于将接收的串行视频光信号转换为串行视频电信号，并输入至主FPGA信号处理电路；主FPGA信号处理电路，与至少两个分FPGA信号处理电路连接，用于解串化所述串行视频电信号并降低视频电信号的时钟频率，将处理后的视频电信号分别传输至至少两个分FPGA信号处理电路；分FPGA信号处理电路，与输出编码电路连接，用于对处理后的视频电信号完成时序转换后传输至输出编码电路；输出编码电路，其与输出接口电路连接，用于合成所述完成时序转换后的多个视频电信号；输出接口电路，用于输出完整视频电信号。本发明优化了信号处理，减少系统延时，简化系统设计，加强可靠性。

Description

一种视频光纤坐席接收装置
本申请要求于2019年12月23日提交中国专利局、申请号为201911342447.6、发明名称为“一种视频光纤坐席接收装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及基于FPGA处理技术领域，更具体地，涉及一种视频光纤坐席接收装置。
背景技术
目前在光纤坐席的视频接收装置中，现有技术中对于光纤接入网络视频信号流的处理过程是，先通过交换机芯片接入以太网络，然后使用专有的解码芯片或者FPGA对接收到的视频信号进行解码还原，然后以特定的格式传输至视频发送接口芯片处，由接口芯片驱动发送至显示单元完成光纤视频信号流的接收过程。
在现有技术的系统中，视频信号流基于网络协议传输，在视频解码器中解码还原视频信号流并完成主要的视频信号处理。由于解码过程中需要缓存多帧图像，使得视频信号源与输出的实时视频之间存在不同程度的延时，并且由于视频信号的处理过程高度集中在专有解码芯片处，对芯片本身的要求较高，散热条件要求高，系统可靠性下降。
发明内容
本发明旨在克服上述现有技术的至少一种缺陷，提供视频光纤坐席接收装置，用于优化原始视频的信号处理，减少系统延时，简化系统设计，加强系统运行的可靠性。
本发明采取的技术方案是：
一种视频光纤坐席接收装置，包括冗余光模块接收电路、FPGA信号处理电路组、输出编码电路及输出接口电路，所述FPGA信号处理电路组包括主FPGA信号处理电路和至少两个分FPGA信号处理电路；
冗余光模块接收电路，其与主FPGA信号处理电路连接，用于将接收的串行视频光信号转换为串行视频电信号，并输入至主FPGA信号处理电路；
主FPGA信号处理电路，其与至少两个分FPGA信号处理电路连接，用于解串化所述串行视频电信号并降低视频电信号的时钟频率，将处理后的视频电信号分别传输至至少两个分FPGA信号处理电路；
分FPGA信号处理电路，其与输出编码电路连接，用于对所述主FPGA信号处理电路处理后的视频电信号完成时序转换后传输至输出编码电路；
输出编码电路，其与输出接口电路连接，用于合成所述完成时序转换后的多个视频电信号；
输出接口电路，用于输出所述输出编码电路合成后的完整视频电信号。
本发明的视频光纤接收装置，由冗余光模块接收电路、主FPGA信号处理电路、至少两个分FPGA信号处理电路、输出编码电路和输出接口电路集成来实现减少系统延时，优化信号处理功能。其中，首先利用冗余光模块接收电路接收实时串行视频光信号，将串行视频光信号转换为串行视频电信号，并且将转换后的串行视频电信号输入至主FPGA信号处理电路，其次通过主FPGA信号处理电路对串行视频电信号进行解串化处理，降低视频电信号的时钟频率，完成主要的信号处理过程，将处理后的视频电信号分别传输至至少两个分FPGA信号处理电路，然后在分FPGA信号处理电路中将经主FPGA信号处理电路处理后的视频电信号进行特定的时序转换，最终在输出编码电路中完成合成时序转换完成后的多个视频电信号，并通过输出接口电路输出合成后的完整视频电信号。本发明从接收实时串行视频光信号到输出信号处理后的完整视频电信号，原始视频在过程中完成的信号处理得到了极大的优化，减少了缓冲的图像，从而优化了装置延时；在视频信号处理过程中，高度保留原始视频信号的图像质量，减少因不同的视频编码导致的图像质量下降；装置的视频信号经过光电转换后直接输入到FPGA信号处理电路进行处理，无需经过以太网协议转换从而简化系统设计；并且本发明装置能够支持的最大分辨率可达4k超高清分辨率。另外，本发明装置采用多个FPGA信号处理电路分别完成不同的信号 处理，降低了主FPGA的集成度要求，使得FPGA组合选型更为灵活，主FPGA功耗下降，装置运行可靠性加强。
一种视频光纤坐席接收装置的控制方法，所述控制方法包括以下步骤：
S1.接收串行视频光信号，并将串行视频光信号转换为串行视频电信号；
S2.解串化所述串行视频电信号，并降低解串化后的视频电信号的时钟频率，将处理后的视频电信号分流出至少两个分视频电信号；
S3.分别对所述至少两个分视频电信号进行时序转换处理；
S4.将时序转换后的至少两个分视频电信号合成为一个完整的视频电信号并进行编码处理；
S5.输出编码后的完整视频电信号。
本发明一种视频光纤接收装置的控制方法的步骤如下：首先，控制视频光纤接收装置接收实时串行视频光信号，将实时串行视频光信号转换为串行视频电信号；其次对串行视频电信号进行解串化处理，降低视频电信号的时钟频率，完成主要的信号处理过程，得到处理完成后的视频电信号，根据视频信号对应显示的显示屏划分情况将处理后的视频电信号分流出至少两个分视频电信号；然后对至少两个分视频电信号进行特定的时序转换后合成一个完整的视频电信号并对其进行编码处理；最后输出合成编码后的完整的视频电信号。本发明控制方法从接收实时串行视频光信号到输出完整的视频电信号，原始视频在过程中完成的信号处理得到了极大的优化，减少了缓冲的图像，从而优化了延时问题；在视频信号处理过程中，高度保留原始视频信号的图像质量，减少因不同的视频编码导致的图像质量下降；并且本发明装置的控制方法使得该装置能够支持的最大分辨率可达4k超高清分辨率。另外，本发明方法通过分流出多个分视频电信号，降低了主要信号处理的功耗，使得系统运行可靠性加强。
与现有技术相比，本发明的有益效果为：
本发明提供一种视频光纤接收装置及控制方法，从接收实时串行视频光信号到输出信号处理后的完整视频电信号，原始视频在整个过程中完成的信号处理得到了极大的优化，减少了缓冲的图像，实现了减少装置延时； 在视频信号处理过程中，高度保留原始视频信号的图像质量，减少因不同的视频编码导致的图像质量下降；装置的视频信号经过光电转换后直接输入到FPGA信号处理电路进行处理，无需经过以太网协议转换从而简化系统设计；并且本发明装置能够支持的最大分辨率可达4k超高清分辨率。另外，本发明装置采用多个FPGA信号处理电路分别完成不同的信号处理，相比于由单一FPGA完成整体功能而言降低了主FPGA的信号处理压力，降低了主FPGA的集成度要求，使得FPGA组合选型更为灵活，主FPGA功耗下降，装置运行可靠性加强。
附图说明
图1为本发明实施例的结构连接示意图。
图2为本发明实施例中多个FPGA信号处理电路的结构关系图。
图3为本发明实施例中整个装置结构框图。
图4为本发明实施例的控制方法流程图。
具体实施方式
本发明附图仅用于示例性说明，不能理解为对本发明的限制。为了更好说明以下实施例，附图某些部件会有省略、放大或缩小，并不代表实际产品的尺寸；对于本领域技术人员来说，附图中某些公知结构及其说明可能省略是可以理解的。
实施例1
如图1所示，图1是本发明实施例一种视频光纤坐席接收装置的结构连接示意图，一种视频光纤坐席接收装置可以包括冗余光模块接收电路、FPGA信号处理电路组、输出编码电路及输出接口电路，所述FPGA信号处理电路组包括主FPGA信号处理电路和至少两个分FPGA信号处理电路；
冗余光模块接收电路，其与主FPGA信号处理电路连接，用于将接收的串行视频光信号转换为串行视频电信号，并输入至主FPGA信号处理电路，具体地，冗余光模块接收电路与光纤连接，接收从光纤传输的串行视 频光信号；
主FPGA信号处理电路，其与至少两个分FPGA信号处理电路连接，用于解串化所述串行视频电信号并降低视频电信号的时钟频率，将处理后的视频电信号分别传输至至少两个分FPGA信号处理电路；
本发明实施例中，由冗余光模块接收电路输入的高速串行视频电信号在主FPGA信号处理电路处完成信号的解串及OSD叠加等主要的信号处理过程，降低视频电信号的时钟频率，然后根据实际分屏的情况将完成主要信号处理后的视频信号传输给至少两个分FPGA信号处理电路。
分FPGA信号处理电路，其与输出编码电路连接，用于对所述主FPGA信号处理电路处理后的视频电信号完成时序转换后传输至输出编码电路；
优选地，本发明实施例中至少包括两个分FPGA信号处理电路，所述分FPGA信号处理电路的个数由如下方式确定：
将视频信号对应显示的显示屏划分至少两个分屏区域，根据分屏区域数量对应确定分FPGA信号处理电路的数量。
优选地，所述显示屏划分为上下或左右两个分屏区域，所述多个分FPGA信号处理电路包括对应两个分屏区域设置两个分FPGA信号处理电路，所述两个分FPGA信号处理电路分别完成两个分屏区域的视频信号时序转换后传输至输出编码电路，具体地，根据分屏区域可分为上下两个分屏区域或者左右两个分屏区域，本实施例只提出分为左右两个分屏区域的情况。
具体地，如图2所示为显示屏划分为左右两个分屏区域，主FPGA信号处理电路完成高速串行电信号的信号处理后，按照分屏区域分为左右分屏视频信号输入至两个分FPGA信号处理电路，左右分FPGA信号处理电路分别接收左右半图像视频信号，完成左右半分屏图像区域的信号时序转换处理过程，输出左半屏图像数据信号和右半屏图像数据信号。
输出编码电路，其与输出接口电路连接，用于合成所述完成时序转换后的多个视频电信号；
本发明实施例中，输出编码电路采用的是HDMI输出编码电路，HDMI输出编码电路包括HDMI编码及均衡芯片，用来实现对串行视频电信号的 编码功能。对于两个分FPGA信号处理电路完成视频电信号时序转换处理后的多个视频信号，HDMI输出编码电路对多个视频电信号进行编码并合成一个完整的图像信号后传输至输出接口电路。
输出接口电路，用于输出所述输出编码电路合成后的完整视频电信号。
本发明实施例中输出接口电路采用的是HDMI输出接口电路，HDMI(高清晰度多媒体接口)是一种数字化视频/音频接口技术，是适合影像传输的专用型数字化接口，最高数据传输速度为2.25GB/s，同时无需在信号传送前进行数/模或者模/数转换。本发明实施例采用HDMI接口，信号的传输速度快，且视频信号质量损失小，能够提供最佳的视频质量。
优选地，本发明实施例还包括控制电路，其与主FPGA信号处理电路连接，用于控制视频信号的收发与调度。
如图3所示，图3为本发明实施例整个装置的结构框图。本发明实施例中所述控制电路包括MPU主控器和与MPU主控器连接的外围电路，MPU主控器与主FPGA信号处理电路连接。
MPU作为控制电路的主控器，其功能是用于控制视频信号的收发与调度，控制装置中FPGA信号处理电路对视频信号的处理过程。与MPU主控器连接的外围电路受MPU主控器控制，用于完成一系列坐席功能。
优选地，本发明实施例中所述外围电路包括USB接口电路和USB HUB接口电路，
所述USB接口电路，用于导入外部已有视频数据信号；
所述USB HUB接口电路，用于接入键鼠信息，完成光纤坐席之间的交互。
具体地，本发明实施例中包括一个USB接口电路和两个USB HUB接口电路，USB接口电路能够导入U盘数据信号，使得装置不仅可以读取实时视频源，也可以读取已有视频文件，其中已有视频信号的具体信号处理过程与实时视频信号处理过程相同，通过FPGA信号处理电路完成信号处理过程，最后通过HDMI输出编码电路和HDMI输出接口电路输出完整视频信号。两个USB HUB接口电路是用于接入键鼠信息，通过键鼠信息完成光纤坐席之间的交互。
本发明实施例中所述外围电路还可以包括存储芯片组电路、以太网接口电路、RS232调试电路、LCD控制电路、音频接收及环出电路，其中，开发者可以通过RS232调试电路简易调试串口实时观察装置的运行状况或者通过以太网接口电路实时调试装置电路；采用LCD控制电路直接输出显示装置配置信息，方便实时观察装置运行状况；音频接收及环出电路，用来基于本实施例对视频信号处理上接入音频信号，对音频信号进行处理，实现视频音频的结合输出完整的图像效果。
本发明实施例提供的一种视频光纤接收装置，从接收实时串行视频光信号到输出信号处理后的完整视频电信号，原始视频在整个过程中完成的信号处理得到了极大的优化，实际情况在信号延时方面有几十毫秒到几秒不等的优化，减少了缓冲的图像，实现了减少装置延时；在视频信号处理过程中，高度保留原始视频信号的图像质量，减少因不同的视频编码导致的图像质量下降；装置的视频信号经过光电转换后直接输入到FPGA信号处理电路进行处理，无需经过以太网协议转换从而简化系统设计；并且本发明装置能够支持的最大分辨率可达4k超高清分辨率。另外，本发明装置采用多个FPGA信号处理电路分别完成不同的信号处理，相比于由单一FPGA完成整体功能而言降低了主FPGA的信号处理压力，降低了主FPGA的集成度要求，使得FPGA组合选型更为灵活，主FPGA功耗下降，装置运行可靠性加强。
实施例2
如图4所示，图4为一种视频光纤坐席接收装置的控制方法的步骤图，所述控制方法包括以下步骤：
S1.接收串行视频光信号，并将串行视频光信号转换为串行视频电信号；
S2.解串化所述串行视频电信号，并降低解串化后的视频电信号的时钟频率，将处理后的视频电信号分流出至少两个分视频电信号；
S3.分别对所述至少两个分视频电信号进行时序转换处理；
S4.将时序转换后的至少两个分视频电信号合成为一个完整的视频电信号并进行编码处理；
S5.输出编码后的完整视频电信号。
优选地，本发明实施例中所述步骤S2，分视频电信号的数量由如下方式确定：
将视频信号对应显示的显示屏划分为上下或者左右两个分屏区域，所述视频电信号对应上下或者左右两个分屏区域分流出两个分视频电信号。
优选地，本发明实施例中所述步骤S2，将处理后的视频电信号分流出至少两个分视频电信号。
本发明控制方法从接收实时串行视频光信号到输出完整的视频电信号，原始视频在过程中完成的信号处理得到了极大的优化，减少了缓冲的图像，从而优化了延时问题；在视频信号处理过程中，高度保留原始视频信号的图像质量，减少因不同的视频编码导致的图像质量下降；并且本发明装置的控制方法使得装置能够支持的最大分辨率可达4k超高清分辨率。另外，本发明方法通过分流出多个分视频电信号，降低了主要信号处理的功耗，使得系统运行可靠性加强。
显然，本发明的上述实施例仅仅是为清楚地说明本发明技术方案所作的举例，而并非是对本发明的具体实施方式的限定。凡在本发明权利要求书的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明权利要求的保护范围之内。

Claims (10)

  1. 一种视频光纤坐席接收装置，其特征在于，包括冗余光模块接收电路、FPGA信号处理电路组、输出编码电路及输出接口电路，所述FPGA信号处理电路组包括主FPGA信号处理电路和至少两个分FPGA信号处理电路；
    冗余光模块接收电路，其与主FPGA信号处理电路连接，用于将接收的串行视频光信号转换为串行视频电信号，并输入至主FPGA信号处理电路；
    主FPGA信号处理电路，其与至少两个分FPGA信号处理电路连接，用于解串化所述串行视频电信号并降低视频电信号的时钟频率，将处理后的视频电信号分别传输至至少两个分FPGA信号处理电路；
    分FPGA信号处理电路，其与输出编码电路连接，用于对所述主FPGA信号处理电路处理后的视频电信号完成时序转换后传输至输出编码电路；
    输出编码电路，其与输出接口电路连接，用于合成所述完成时序转换后的多个视频电信号；
    输出接口电路，用于输出所述输出编码电路合成后的完整视频电信号。
  2. 根据权利要求1所述的一种视频光纤坐席接收装置，其特征在于，所述分FPGA信号处理电路的个数由如下方式确定：将视频信号对应显示的显示屏划分至少两个分屏区域，根据分屏区域数量对应确定分FPGA信号处理电路的数量。
  3. 根据权利要求2所述的一种视频光纤坐席接收装置，其特征在于，所述显示屏划分为上下或左右两个分屏区域，所述多个分FPGA信号处理电路包括对应两个分屏区域设置两个分FPGA信号处理电路，
    所述两个分FPGA信号处理电路分别完成两个分屏区域的视频信号时序转换后传输至输出编码电路。
  4. 根据权利要求1所述的一种视频光纤坐席接收装置，其特征在于，还包括控制电路，其与主FPGA信号处理电路连接，用于控制视频电信号的收发与调度。
  5. 根据权利要求4所述的一种视频光纤坐席接收装置，其特征在于， 所述控制电路包括MPU主控器和与MPU主控器连接的外围电路，MPU主控器与主FPGA信号处理电路连接。
  6. 根据权利要求5所述的一种视频光纤坐席接收装置，其特征在于，所述外围电路包括USB接口电路和USB HUB接口电路，
    所述USB接口电路，用于导入外部已有视频数据信号；
    所述USB HUB接口电路，用于接入键鼠信息，完成光纤坐席之间的交互。
  7. 根据权利要求1所述的一种视频光纤坐席接收装置，其特征在于，所述输出编码电路采用的是HDMI输出编码电路。
  8. 一种视频光纤坐席接收装置的控制方法，其特征在于，所述控制方法包括以下步骤：
    S1.接收串行视频光信号，并将串行视频光信号转换为串行视频电信号；
    S2.解串化所述串行视频电信号，并降低解串化后的视频电信号的时钟频率，将处理后的视频电信号分流出至少两个分视频电信号；
    S3.分别对所述至少两个分视频电信号进行时序转换处理；
    S4.将时序转换后的至少两个分视频电信号合成为一个完整的视频电信号并进行编码处理；
    S5.输出编码后的完整视频电信号。
  9. 根据权利要求8所述的一种视频光纤坐席接收装置的控制方法，其特征在于，所述步骤S2中，所述分视频电信号的数量由如下方式确定：
    将视频信号对应显示的显示屏划分为上下或者左右两个分屏区域，所述视频电信号对应上下或者左右两个分屏区域分流出两个分视频电信号。
  10. 根据权利要求8所述的一种视频光纤坐席接收装置的控制方法，其特征在于，所述步骤S2中，将处理后的视频电信号分流出两个分视频电信号。
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