WO2021121433A1 - 一种锁相环电路、芯片、电路板以及电子设备 - Google Patents

一种锁相环电路、芯片、电路板以及电子设备 Download PDF

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Publication number
WO2021121433A1
WO2021121433A1 PCT/CN2020/141563 CN2020141563W WO2021121433A1 WO 2021121433 A1 WO2021121433 A1 WO 2021121433A1 CN 2020141563 W CN2020141563 W CN 2020141563W WO 2021121433 A1 WO2021121433 A1 WO 2021121433A1
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module
phase
terminal
output terminal
locked loop
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PCT/CN2020/141563
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English (en)
French (fr)
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刘帅锋
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芯海科技（深圳）股份有限公司
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Publication of WO2021121433A1 publication Critical patent/WO2021121433A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

Definitions

  • This patent application relates to the field of semiconductor technology, in particular to a phase-locked loop circuit, chip, circuit board and electronic equipment.
  • the system clock usually needs to be switched between crystal oscillator, internal RC oscillator and PLL (Phase Locked Loop Circuit).
  • PLL Phase Locked Loop Circuit
  • the PLL clock has a period of time from starting to reaching stability (lock). In some applications, the requirements for this time are relatively high, and the lock needs to be reached in a very short time.
  • the conventional method to reduce the lock time is to increase the loop bandwidth of the PLL, and increase the loop bandwidth by changing the charge and discharge current of the charge pump in the PLL loop and the resistance value in the loop filter to speed up the PLL lock process. .
  • PLL Phase Locked Loop Circuit
  • the external crystal clock is usually required to support a relatively wide frequency range, and the minimum frequency can be as low as 1MHz.
  • the loop bandwidth needs to be less than 1/10 of the input reference clock frequency, or even smaller.
  • the loop bandwidth of the corresponding PLL should also take a relatively small value.
  • the lock time requirement of the PLL is relatively high, which makes it difficult for the conventional method of increasing the loop bandwidth to achieve the goal.
  • the main purpose of this patent application is to propose a phase-locked loop circuit, chip, circuit board and electronic equipment, which aims to solve the problem that the existing phase-locked loop circuit cannot speed up the locking of the phase-locked loop circuit without changing the loop bandwidth.
  • this patent application provides a phase-locked loop circuit, which includes a phase-frequency detector module, a charge pump module, a loop filter, and a voltage-controlled oscillator, and also includes a controllable current source module; the charge The control end of the pump module is connected to the output end of the frequency detector module, the output end of the charge pump module is connected to the input end of the loop filter, and the output end of the loop filter is connected to the voltage
  • the input terminal of the control oscillator, the output terminal of the voltage-controlled oscillator is connected to the feedback clock input terminal of the phase frequency detector module;
  • the input terminal of the controllable current source module is connected to the output of the loop filter
  • the output terminal of the controllable current source module is connected to the input terminal of the loop filter.
  • controllable current source module includes an auxiliary current source, a controllable switch, and a comparator.
  • the first input terminal of the comparator is connected to the output terminal of the loop filter, and the second input terminal of the comparator is connected to the output terminal of the loop filter.
  • the input terminal is connected to a preset reference voltage source, the output terminal of the comparator is connected to the control terminal of the controllable switch, and the auxiliary current source is connected to the input terminal of the loop filter via the controllable switch.
  • the frequency discriminator module includes a first D flip-flop, a second D flip-flop, and an AND gate circuit; the data terminal of the first D flip-flop and the data terminal of the second D flip-flop Set high respectively, the reset terminal of the first D flip-flop and the reset terminal of the second D flip-flop are respectively connected to the output terminal of the AND circuit, and the clock input terminal of the first D flip-flop is a reference clock Input terminal, the clock input terminal of the second D flip-flop is the feedback clock input terminal, the output terminal of the first D flip-flop is connected to the first input terminal of the AND circuit; the second D flip-flop The output terminal of the converter is connected to the second input terminal of the AND circuit.
  • the frequency discriminator module further includes a logic circuit, the first input terminal of the logic circuit is connected to the output terminal of the first D flip-flop, and the second input terminal of the logic circuit is connected to the The output terminal of the second D flip-flop, the first output terminal of the logic circuit is the first output terminal of the frequency discriminator module, and the second output terminal of the logic circuit is the frequency detector The second output terminal of the module.
  • the charge pump module includes a charging current source, a charging control switch, a discharging control switch, and a discharging current source connected in series in sequence; the control terminal of the charging control switch is connected to the first Output terminal, the control terminal of the discharge control switch is connected to the second output terminal of the frequency discriminator module, and the connection point of the charge control switch and the discharge control switch serves as the output terminal of the charge pump module and The input end of the loop filter is connected.
  • the loop filter includes a first resistor and a capacitor, the first resistor and the capacitor are connected in series, and an end of the capacitor away from the first resistor is grounded.
  • the voltage-controlled oscillator includes a current conversion module, a mirroring module, and a ring oscillator
  • the input terminal of the current conversion module is the input terminal of the voltage-controlled oscillator
  • the first output of the current conversion module The terminal is connected to the oscillation frequency control terminal of the ring oscillator via the mirroring module
  • the second output terminal of the current conversion module is grounded
  • the output terminal of the ring oscillator is the output terminal of the voltage controlled oscillator.
  • this patent application provides a chip including the above-mentioned phase-locked loop circuit.
  • this patent application provides a circuit board including the above-mentioned phase-locked loop circuit.
  • this patent application provides an electronic device including the above-mentioned chip or the above-mentioned circuit board.
  • the phase-locked loop circuit, chip, circuit board and electronic equipment provided in this patent application have a controllable current source module added to the phase-locked loop circuit.
  • the input end of the controllable current source module is connected to the output end of the loop filter, which is controllable
  • the output terminal of the current source module is connected to the input terminal of the loop filter.
  • the controllable current source module can be turned on or off according to the output of the loop filter. When it is turned on, the charging current of the charge pump module to the loop filter can be increased, so that the phase-locked loop circuit can be turned on or off.
  • the period of time close to lock is shortened due to the increase of the charging current, and the controllable current source module is closed after the phase-locked loop circuit is close to lock, without consuming additional power consumption, and without changing the overall structure and structure of the original phase-locked loop circuit. Realize quick lock under the premise of parameters.
  • Fig. 1 is a connection block diagram of a phase-locked loop circuit provided in an embodiment of the patent application.
  • Fig. 2 is a schematic diagram of the circuit principle of the phase-locked loop circuit shown in Fig. 1.
  • Fig. 3 is the phase model of the phase-locked loop circuit shown in Fig. 1.
  • FIG. 4 is a gain curve of the output clock of the voltage controlled oscillator of the phase-locked loop circuit shown in FIG. 1.
  • the phase-locked loop circuit 100 includes a frequency discriminator module 110, a charge pump module 120, a loop filter 130, and a voltage control The oscillator 140 and the controllable current source module 150.
  • the control terminal of the charge pump module 120 is connected to the output terminal of the frequency detector module 110, the output terminal of the charge pump module 120 is connected to the input terminal of the loop filter 130, and the output terminal of the loop filter 130 is connected to the voltage controlled oscillator 140
  • the input terminal of the voltage-controlled oscillator 140 is connected to the feedback clock input terminal of the phase frequency detector module 110.
  • the input terminal of the controllable current source module 150 is connected to the output terminal of the loop filter 130, and the output terminal of the controllable current source module 150 is connected to the input terminal of the loop filter 130.
  • the controllable current source module 150 can be turned on or off according to the output of the loop filter 130.
  • the charging current of the charge pump module 120 to the loop filter 130 can be increased, so that the phase-locked loop
  • the time from when the circuit 100 is turned on to close to being locked is shortened due to the increase of the charging current, and the controllable current source module 150 is turned off after the phase-locked loop circuit is close to being locked, without consuming additional power consumption, and without changing the original lock
  • the phase loop circuit 100 realizes quick locking under the premise of the overall structure and parameters.
  • the phase frequency detector module 110 includes a first D flip-flop D 0 , a second D flip-flop D 1 , an AND circuit X 0 and a logic circuit I 0 ;
  • the data terminal of the flip-flop D 0 and the data terminal of the second D flip-flop D 1 are respectively set high, and the reset terminal of the first D flip-flop D 0 and the reset terminal of the second D flip-flop D 1 are respectively connected to the AND circuit X 0
  • the clock input terminal of the first D flip-flop D 0 is the reference clock input terminal
  • the clock input terminal of the second D flip-flop D 1 is the feedback clock input terminal
  • the output terminal of the first D flip-flop D 0 is connected to The first input terminal of the gate circuit X 0
  • the output terminal of the second D flip-flop D 1 is connected to the second input terminal of the AND circuit X 0.
  • the first input terminal of the logic circuit I 0 is connected to the output terminal of the first D flip-flop D 0
  • the second input terminal of the logic circuit I 0 is connected to the output terminal of the second D flip-flop D 1 and the first output of the logic circuit I 0
  • the terminal is the first output terminal of the frequency detector module 110
  • the second output terminal of the logic circuit I 0 is the second output terminal of the frequency detector module 110.
  • the clock input of the phase frequency detector module 110 is the reference clock REFCLK and the frequency divider feedback clock FBCLK respectively. When the rising edge of the clock arrives, the output of the D flip-flop will be set high.
  • the output of the AND circuit X 0 becomes high and is applied to the first D flip-flop D 0 and the second D flip-flop D 0 and the second D flip-flop D 0.
  • the reset terminal of the flip-flop D 1 is reset, thereby resetting the first D flip-flop D 0 and the second D flip-flop D 1 .
  • the first D flip-flop D0 and the second D flip-flop D1 output high-level durations are also different, thereby distinguishing the phase difference between REFCLK and FBCLK.
  • the charge pump module 120 includes a charging current source I up , a charging control switch SW 0 , a discharging control switch SW 1 and a discharging current source I dn connected in series in sequence.
  • the control terminal of the charge control switch SW 0 is connected to the first output terminal of the frequency detector module 110
  • the control terminal of the discharge control switch SW 1 is connected to the second output terminal of the frequency detector module 110
  • the charge control switches SW 0 and The connection point of the discharge control switch SW 1 is used as the output terminal of the charge pump module 120 to be connected to the input terminal of the loop filter 130.
  • the loop filter 130 includes a first resistor R 0 and a capacitor C 0 , the first resistor R 0 and the capacitor C 0 are connected in series, and the end of the capacitor C 0 away from the first resistor R 0 is grounded.
  • the signal from the frequency discriminator module 110 can control the on and off of the charging control switch SW0 and the discharging control switch SW1, thereby completing the charging and discharging of the loop filter 130.
  • the loop filter 130 completes the current to voltage conversion and filters the output voltage.
  • the voltage-controlled oscillator 140 includes a current conversion module 141, a mirroring module 142, and a ring oscillator 143.
  • the input terminal of the current conversion module 141 is the input terminal of the voltage-controlled oscillator 140, and the current
  • the first output terminal of the conversion module 141 is connected to the oscillation frequency control terminal of the ring oscillator 143 via the mirror module 142, the second output terminal of the current conversion module 141 is grounded, and the output terminal of the ring oscillator 143 is the output terminal of the voltage controlled oscillator 140 .
  • the current conversion module 141 includes a first MOS tube MN 0 and a second resistor R 1.
  • the gate of the first MOS tube MN 0 is connected to the loop filter 130 At the output end, the drain of the first MOS transistor MN 0 is connected to the mirror module 142, and the source of the first MOS transistor MN 0 is grounded through the second resistor R 1.
  • the mirror module 142 includes a second MOS transistor MP 0 and a third MOS transistor MP 1 that are mirrored; the drain and gate of the second MOS transistor MP 0 and the gate of the third MOS transistor MP 1 are all connected to the first MOS transistor MN 0 of the drain, the source of the second MOS transistor MP 0 of the third MOS transistor MP and the source electrode connected to a predetermined power supply terminal; connected to the drain of the third MOS transistor MP 1 ring oscillation frequency control terminal of the oscillator 143.
  • the ring oscillator 143 includes a first inverter circuit, a second inverter circuit, and a third inverter circuit; the input terminal of the first inverter circuit is connected to the output terminal of the third inverter circuit, and the input terminal of the second inverter circuit is connected to The output terminal of the first inverter circuit, the input terminal of the third inverter circuit are connected to the output terminal of the second inverter circuit, and the output terminal of the third inverter circuit is the output terminal of the ring oscillator 143.
  • the first MOS tube MN 0 is an NMOS tube or can be a PMOS tube or a common field effect tube.
  • the phase-locked loop circuit 100 of this embodiment further includes a frequency divider 160, and the output terminal of the voltage-controlled oscillator 140 is connected to the frequency and phase discrimination via the frequency divider 160.
  • the feedback clock input terminal of the converter module 110 is not limited to the frequency divider 160.
  • the controllable current source module 150 specifically includes an auxiliary current source Iup_aux, a controllable switch SW2, and a comparator I3.
  • the first input terminal of the comparator I3 is connected to the output of the loop filter 130.
  • the second input terminal of the comparator I3 is connected to the preset reference voltage source Vth, the output terminal of the comparator I3 is connected to the control terminal of the controllable switch SW2, and the auxiliary current source Iup_aux is connected to the loop filter 130 via the controllable switch SW2. Input terminal.
  • the output voltage V ctrl of the loop filter 130 converts the control voltage into a control current through the first MOS tube MN 0 and the second resistor R 1 , and then passes through the second MOS tube MP 0 and the third mirror MOS transistor MP 1 to control the oscillation frequency of the ring oscillator 143.
  • the frequency of the output clock of the phase-locked loop circuit 100 (that is, the output clock of the voltage-controlled oscillator VCO) is Input n times the reference clock.
  • the loop bandwidth of the phase-locked loop circuit 100 is less than 1/10 of the reference clock frequency, the loop of the phase-locked loop circuit 100 can be approximately regarded as a linear system with respect to phase, as shown in FIG. 3.
  • ⁇ in , ⁇ fb , ⁇ e are the reference clock phase, the frequency divider feedback clock phase and the phase difference between the two respectively;
  • the gain of the charge pump is I cp /2 ⁇ ;
  • the transfer function of the loop filter is Z f ( s);
  • the gain of the ring oscillator is 2 ⁇ K vco /s;
  • the gain of the frequency divider is 1/n.
  • the closed-loop transfer function of the PLL can be obtained as:
  • controllable current source module 150 If the controllable current source module 150 is not connected in Figure 2, the transfer function of the loop filter at this time is:
  • the loop bandwidth of the phase-locked loop circuit 100 is
  • the frequency division ratio n is determined by the input and output frequency of the system and cannot be changed; K vco should be minimized to reduce clock jitter while meeting the tuning range requirements; the value of the resistor R 0 is determined by the stability requirements and area overhead. This makes the current of the charge pump module 120 often take a small value at a low clock frequency.
  • the lock time of the phase-locked loop circuit 100 is related to the size of the frequency jump and the loop bandwidth. Increasing the loop bandwidth of the phase-locked loop circuit 100 will reduce the lock time.
  • the loop bandwidth is usually less than 1/10 of the reference clock frequency, otherwise, due to the additional phase shift introduced by the discrete system characteristics of the PLL loop itself It will affect the stability of the PLL loop.
  • the output frequency requirement of the phase-locked loop circuit 100 can be as high as 72 MHz, and the lowest reference clock input may be only 1 MHz, which makes the loop bandwidth of the phase-locked loop circuit 100 very low.
  • the lock time requirement of the phase-locked loop circuit 100 is relatively high, which makes it difficult for the conventional method of increasing the loop bandwidth to achieve the goal. Therefore, the phase-locked loop circuit 100 of this embodiment is connected to the controllable current source module 150.
  • the system clock in the MCU is switched from other clock sources to the phase-locked loop circuit 100, or the phase-locked loop circuit 100 is switched from one frequency to another.
  • the phase-locked loop circuit 100 has undergone the process of turning off, turning on, and then turning on again. a process.
  • the frequency at which the phase-locked loop circuit 100 finally reaches lock is also the output frequency of the VCO.
  • Fig. 4 is the gain curve of the output clock of the phase-locked loop circuit 100. It can be seen that the output frequency of the VCO is related to the control voltage Vctrl, and the effective control voltage range [V min , V max ] corresponds to the output range of the VCO [f min ,f max ].
  • V min corresponds to the threshold voltage of the first MOS transistor MN 0.
  • the target frequency of the phase-locked loop circuit 100 is f c
  • the control voltage corresponding to the output clock is V c .
  • the reference clock frequency and the frequency of the frequency divider feedback clock are very different.
  • the frequency deviation of the reference clock frequency and the frequency of the frequency divider feedback clock is very large.
  • the output phase difference of the frequency discriminator module 110 is always 2 ⁇ , so the charge pump module 120 has been charging the loop filter 130, and the voltage on V ctrl continues to rise.
  • the relationship between the change of the control voltage and the charging current is:
  • the behavior of the phase-locked loop circuit 100 is similar to that of an op amp working in a large signal slew rate control region. Because the charging and discharging current of the phase-locked loop circuit 100 is very low under the low reference clock frequency, the charge pump module 120 takes a long time to charge the loop filter 130, and the charging process also goes through the V ctrl from 0 to V min . "Invalid" area (VCO has no clock output). A VCO control voltage V th that is smaller than V c can be set.
  • the output frequency of the phase-locked loop circuit 100 is lower than the target frequency by f c- f th or more, so that the frequency discrimination
  • the output of the phaser module 110 is always 2 ⁇ , and increasing the charging current of the charge pump within this voltage range will not cause stability problems. Increasing the charging current will make the frequency rise faster, and the VCO output frequency will approach the target frequency faster.
  • V ctrl is compared with the threshold voltage V th through the comparator I 3 , and the output is used to control the auxiliary current source I up_aux .
  • V ctrl ⁇ V th when the output of comparator I 3 is low, the auxiliary current source I up_aux is controlled to turn on, which increases the charging current.
  • the rising speed of V ctrl is much faster than before, and the frequency of VCO changes (increase) Also faster than before.
  • V ctrl exceeds the threshold voltage V th , at this time, the output of the comparator I 3 is reversed, the auxiliary current source I up_aux is turned off, and the phase-locked loop circuit 100 returns to a normal state.
  • the period of time from turning on to close to locking of the phase-locked loop circuit 100 is shortened due to the increase in charging current, and closes after being close to locking, so the overall structure and parameters of the original phase-locked loop circuit can be changed without changing the overall structure and parameters of the original phase-locked loop circuit. Achieve quick lock.
  • it provides a chip that includes the phase-locked loop circuit 100 mentioned in the above-mentioned embodiments.
  • it provides a circuit board that includes the phase-locked loop circuit 100 mentioned in the above-mentioned embodiments.
  • it provides an electronic device that includes the chip mentioned in the above-mentioned embodiment or the circuit board mentioned in the above-mentioned embodiment.
  • phase-locked loop circuit, chip, circuit board and electronic equipment provided by all embodiments of this patent application have a controllable current source module added to the phase-locked loop circuit, and the input end of the controllable current source module is connected to the output end of the loop filter , The output end of the controllable current source module is connected to the input end of the loop filter. In this way, the controllable current source module can be turned on or off according to the output of the loop filter.
  • the charging current of the charge pump module to the loop filter can be increased, so that the phase-locked loop circuit is turned on to
  • the period of time close to lock is shortened due to the increase of the charging current, and the controllable current source module is closed after the phase-locked loop circuit is close to lock, without consuming additional power consumption, and without changing the overall structure and structure of the original phase-locked loop circuit. Realize quick lock under the premise of parameters.

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Abstract

一种锁相环电路、芯片、电路板以及电子设备，包括鉴频鉴相器模块（110）、电荷泵模块（120）、环路滤波器（130）、压控振荡器（140）及可控电流源模块（150）；电荷泵模块（120）的控制端连接鉴频鉴相器模块（110）的输出端，电荷泵模块（120）的输出端连接环路滤波器（130）的输入端，环路滤波器（130）的输出端连接压控振荡器（140）的输入端，压控振荡器（140）的输出端连接鉴频鉴相器模块（110）的反馈时钟输入端；可控电流源模块（150）的输入端连接环路滤波器（130）的输出端，可控电流源模块（150）的输出端连接环路滤波器（130）的输入端。通过增加可控电流源模块（150），能在不改变环路带宽的前提下加快锁相环电路的锁定过程，且新增的可控电流源模块（150）只在锁相环电路启动后的一段时间内起作用，在锁相环电路接近锁定时关闭，不消耗额外的功耗。

Description

一种锁相环电路、芯片、电路板以及电子设备
相关申请的交叉引用
本申请要求于2019年12月20日提交中国专利局的申请号为CN201922343449.9、名称为“一种锁相环电路、芯片、电路板以及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本专利申请涉及半导体技术领域，特别涉及一种锁相环电路、芯片、电路板以及电子设备。
背景技术
现有在32位MCU产品中,系统时钟通常需要在晶振、内部RC振荡器和PLL(锁相环电路)之间进行切换。当时钟源由晶振或者内部RC振荡器切换到PLL时钟时，PLL时钟有一个从启动至达到稳定(锁定)的时间。在某些应用中，对这个时间的要求比较高，需要在很快的时间内达到锁定。常规的减小锁定时间的方法是增加PLL的环路带宽,通过改变PLL环路中电荷泵的充放电电流及环路滤波器中电阻值等方法来提高环路带宽,从而加快PLL的锁定过程。在MCU类产品的应用中，PLL(锁相环电路)被用来将外部晶振或者内部RC振荡器的频率倍频到一个比较高的频率上，然后用作系统时钟使用。外部晶振时钟通常要求支持比较宽的频率范围，最低频率可以低至1MHz。对于PLL的设计来说，其环路带宽需要小于输入参考时钟频率的1/10，甚至更小。当PLL输入频率比较低的时候，相应的PLL的环路带宽也应取比较小的值。而在有些应用场合，对PLL的锁定时间要求又比较高，这就使得常规的增加环路带宽的方法很难达到目的。
实用新型内容
本专利申请的主要目的在于提出一种锁相环电路、芯片、电路板以及电子 设备，其旨在解决现有锁相环电路无法在不改变环路带宽的前提下加快锁相环电路的锁定过程的技术问题。
为实现上述目的，本专利申请提供了一种锁相环电路，包括鉴频鉴相器模块、电荷泵模块、环路滤波器以及压控振荡器，还包括可控电流源模块；所述电荷泵模块的控制端连接所述鉴频鉴相器模块的输出端，所述电荷泵模块的输出端连接所述环路滤波器的输入端，所述环路滤波器的输出端连接所述压控振荡器的输入端，所述压控振荡器的输出端连接所述鉴频鉴相器模块的反馈时钟输入端；所述可控电流源模块的输入端连接所述环路滤波器的输出端，所述可控电流源模块的输出端连接所述环路滤波器的输入端。
可选地，所述可控电流源模块包括辅助电流源、可控开关及比较器，所述比较器的第一输入端连接所述环路滤波器的输出端，所述比较器的第二输入端连接预设的参考电压源，所述比较器的输出端连接所述可控开关的控制端，所述辅助电流源经所述可控开关连接所述环路滤波器的输入端。
可选地，所述鉴频鉴相器模块包括第一D触发器、第二D触发器以及与门电路；所述第一D触发器的数据端和所述第二D触发器的数据端分别置高，所述第一D触发器的复位端和所述第二D触发器的复位端分别连接所述与门电路的输出端，所述第一D触发器的时钟输入端为参考时钟输入端，所述第二D触发器的时钟输入端为所述反馈时钟输入端，所述第一D触发器的输出端连接所述与门电路的第一输入端；所述第二D触发器的输出端连接所述与门电路的第二输入端。
可选地，所述鉴频鉴相器模块还包括逻辑电路，所述逻辑电路的第一输入端连接所述第一D触发器的输出端，所述逻辑电路的第二输入端连接所述第二D触发器的输出端，所述逻辑电路的第一输出端为所述鉴频鉴相器模块的第一输出端，所述逻辑电路的第二输出端为所述鉴频鉴相器模块的第二输出端。
可选地，所述电荷泵模块包括依序串联的充电电流源、充电控制开关、放电控制开关和放电电流源；所述充电控制开关的控制端连接所述鉴频鉴相器模块的第一输出端，所述放电控制开关的控制端连接所述鉴频鉴相器模块的第二输出端，所述充电控制开关和所述放电控制开关的连接点作为所述电荷泵模块的输出端与所述环路滤波器的输入端连接。
可选地，所述环路滤波器包括第一电阻与电容，所述第一电阻与电容串联 连接，且所述电容远离所述第一电阻的一端接地。
可选地，所述压控振荡器包括电流转换模块、镜像模块以及环形振荡器，所述电流转换模块的输入端为所述压控振荡器的输入端，所述电流转换模块的第一输出端经所述镜像模块连接所述环形振荡器的振荡频率控制端，所述电流转换模块的第二输出端接地，所述环形振荡器的输出端为所述压控振荡器的输出端。
为实现上述目的，本专利申请提供了一种芯片，包括上述的锁相环电路。
为实现上述目的，本专利申请提供了一种电路板，包括上述的锁相环电路。
为实现上述目的，本专利申请提供了一种电子设备，包括上述的芯片或上述的电路板。
本专利申请提供的锁相环电路、芯片、电路板以及电子设备，其锁相环电路增加了可控电流源模块，可控电流源模块的输入端连接环路滤波器的输出端，可控电流源模块的输出端连接环路滤波器的输入端。这样一来，可控电流源模块可根据环路滤波器的输出进行打开或关闭，当其打开时，可增大电荷泵模块对环路滤波器的充电电流，使得锁相环电路从开启到接近锁定的这段时间由于充电电流的增大而缩短，且可控电流源模块在锁相环电路接近锁定后关闭，不消耗额外的功耗，可在不改变原锁相环电路整体结构和参数的前提下实现快速锁定。
附图说明
为了更清楚地说明本专利申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本专利申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本专利申请实施例中提供的锁相环电路的连接框图。
图2为图1所示锁相环电路的电路原理示意图。
图3为图1所示锁相环电路的相位模型。
图4为图1所示锁相环电路的压控振荡器的输出时钟的增益曲线。
具体实施方式
下面结合附图对本专利申请的具体实施方式作进一步说明。在此需要说明的是，对于这些实施方式的说明用于帮助理解本专利申请，但并不构成对本专利申请的限定。此外，下面所描述的本专利申请各个实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互组合。
在一些实施例中，如图1所示，其提供一种锁相环电路100，该锁相环电路100包括鉴频鉴相器模块110、电荷泵模块120、环路滤波器130、压控振荡器140以及可控电流源模块150。电荷泵模块120的控制端连接鉴频鉴相器模块110的输出端，电荷泵模块120的输出端连接环路滤波器130的输入端，环路滤波器130的输出端连接压控振荡器140的输入端，压控振荡器140的输出端连接鉴频鉴相器模块110的反馈时钟输入端。可控电流源模块150的输入端连接环路滤波器130的输出端，可控电流源模块150的输出端连接环路滤波器130的输入端。
这样一来，可控电流源模块150可根据环路滤波器130的输出进行打开或关闭，当其打开时，可增大电荷泵模块120对环路滤波器130的充电电流，使得锁相环电路100从开启到接近锁定的这段时间由于充电电流的增大而缩短，且可控电流源模块150在锁相环电路接近锁定后关闭，不消耗额外的功耗，可在不改变原锁相环电路100整体结构和参数的前提下实现快速锁定。
在一些实施例中，如图2所示，鉴频鉴相器模块110包括第一D触发器D 0、第二D触发器D 1、与门电路X 0以及逻辑电路I 0；第一D触发器D 0的数据端和第二D触发器D 1的数据端分别置高，第一D触发器D 0的复位端和第二D触发器D 1的复位端分别连接与门电路X 0的输出端，第一D触发器D 0的时钟输入端为参考时钟输入端，第二D触发器D 1的时钟输入端为反馈时钟输入端，第一D触发器D 0的输出端连接与门电路X 0的第一输入端；第二D触发器D 1的输出端连接与门电路X 0的第二输入端。逻辑电路I 0的第一输入端连接第一D触发器D 0的输出端，逻辑电路I 0的第二输入端连接第二D触发器D 1的输出端，逻辑电路I 0的第一输出端为鉴频鉴相器模块110的第一输出端，逻辑电路I 0的第二输出端为鉴频鉴相器模块110的第二输出端。鉴频鉴相器模块110的时钟输入分别是参考时钟REFCLK和分频器反馈时钟FBCLK，当时钟上升沿到来时，D触发器的输出会被置高。当第一D触发器D 0和第二D触发器D 1的输出都是高电平时，与门电路X 0的 输出变为高电平并施加在第一D触发器D 0和第二D触发器D 1的复位端，从而将第一D触发器D 0和第二D触发器D 1复位。根据参考时钟和分频器反馈时钟上升沿到达先后的不同，第一D触发器D0和第二D触发器D1输出高电平的持续时间也不同，从而将REFCLK和FBCLK的相位差别鉴别出来。第一D触发器D0和第二D触发器D1的输出经过逻辑电路I 0后，来控制后面电荷泵模块120的充、放电操作。
在一些实施例中，如图2所示，电荷泵模块120包括依序串联的充电电流源I up、充电控制开关SW 0、放电控制开关SW 1和放电电流源I dn。充电控制开关SW 0的控制端连接鉴频鉴相器模块110的第一输出端，放电控制开关SW 1的控制端连接鉴频鉴相器模块110的第二输出端，充电控制开关SW 0和放电控制开关SW 1的连接点作为电荷泵模块120的输出端与环路滤波器130的输入端连接。环路滤波器130包括第一电阻R 0与电容C 0，第一电阻R 0与电容C 0串联连接，且电容C 0远离第一电阻R 0的一端接地。工作时，来自鉴频鉴相器模块110的信号可控制充电控制开关SW0、放电控制开关SW1的导通和关闭，从而完成对环路滤波器130的充、放电。环路滤波器130完成电流到电压的转换并对输出电压进行滤波。
在一些实施例中，如图2所示，压控振荡器140包括电流转换模块141、镜像模块142以及环形振荡器143，电流转换模块141的输入端为压控振荡器140的输入端，电流转换模块141的第一输出端经镜像模块142连接环形振荡器143的振荡频率控制端，电流转换模块141的第二输出端接地，环形振荡器143的输出端为压控振荡器140的输出端。具体地，电流转换模块141包括第一MOS管MN 0与第二电阻R 1，以第一MOS管MN 0为NMOS管为例，第一MOS管MN 0的栅极连接环路滤波器130的输出端，第一MOS管MN 0的漏极连接镜像模块142，第一MOS管MN 0的源极经第二电阻R 1接地。镜像模块142包括镜像设置的第二MOS管MP 0与第三MOS管MP 1；第二MOS管MP 0的漏极、栅极与第三MOS管MP 1的栅极均连接第一MOS管MN 0的漏极，第二MOS管MP 0的源极和第三MOS管MP 1的源极接预设电源端；第三MOS管MP 1的漏极连接环形振荡器143的振荡频率控制端。环形振荡器143包括第一非门电路、第二非门电路以及第三非门电路；第一非门电路的输入端连接第三非门电路的输出端，第二非门电路的输入端连接第一非门电路的输出端，第三非门电路的输入端连接第二非门电路的输出端，第三非门电路的输出端为环形振荡器143的输出端。可以理解，在其他实施方式中，第一MOS管MN 0为NMOS管也可以是PMOS管或普通的场效应管。
在一些实施例中，可选地，如图2所示，本实施例的锁相环电路100还包括分频器160，压控振荡器140的输出端经分频器160连接鉴频鉴相器模块110的反馈时钟输入端。
在一些实施例中，如图2所示，可控电流源模块150具体包括辅助电流源Iup_aux、可控开关SW2及比较器I3，比较器I3的第一输入端连接环路滤波器130的输出端，比较器I3的第二输入端连接预设的参考电压源Vth，比较器I3的输出端连接可控开关SW2的控制端，辅助电流源Iup_aux经可控开关SW2连接环路滤波器130的输入端。
工作时，如图1及图2所示，环路滤波器130的输出电压V ctrl通过第一MOS管MN 0和第二电阻R 1将控制电压转换为控制电流，经过第二MOS管MP 0与第三MOS管MP 1的镜像，来控制环形振荡器143的振荡频率。环形振荡器143的输出时钟经过分频器160分频后，送至第二D触发器D 1的时钟输入端，形成了一个时钟的闭环负反馈系统。
当锁相环电路100达到锁定状态时，参考时钟REFCLK和分频器反馈时钟FBCLK的频率精确相等，因此，锁相环电路100的输出时钟(也即压控振荡器VCO的输出时钟)频率是输入参考时钟的n倍。当锁相环电路100的环路带宽小于参考时钟频率的1/10以上时，锁相环电路100的环路可以近似看作是一个关于相位的线性系统，如图3所示。其中,φ in，φ fb，φ e分别为参考时钟相位、分频器反馈时钟相位和二者的相位差；电荷泵的增益为I cp/2π；环路滤波器的传输函数为Z f(s)；环形振荡器的增益为2πK vco/s；分频器的增益为1/n。根据图3中所示的相位模型，可以得出PLL的闭环传输函数为：
Figure PCTCN2020141563-appb-000001
若图2中没有接入可控电流源模块150，此时的环路滤波器的传输函数为：
Figure PCTCN2020141563-appb-000002
代入上面式子，可得：
Figure PCTCN2020141563-appb-000003
在满足稳定性设计的前提下，锁相环电路100的环路带宽为
Figure PCTCN2020141563-appb-000004
分频比n由系统的输入输出频率决定，无法改变；K vco在满足调谐范围要求的前提下尽量降低以减小时钟抖动；电阻R 0的取值由稳定性要求和面积开销决定。这就使得在低的时钟频率下，电荷泵模块120的电流往往取值很小。锁相环电路100的锁定时间与频率跳变的大小和环路带宽有关，增大锁相环电路100的环路带宽会减小锁定时间。在锁定时间要求严格的应用场合，需要增加环路带宽，但环路带宽通常要小于参考时钟频率的1/10以上，不然的话，由于PLL环路本身的离散系统特性所引入的额外的相移会影响PLL环路的稳定性。
在32位MCU中，锁相环电路100的输出频率要求可高达72MHz以上，而最低的参考时钟输入可能只有1MHz，这就使得锁相环电路100的环路带宽取得很低。在有些应用场合，对锁相环电路100的锁定时间要求又比较高，这就使得常规的增加环路带宽的方法很难达到目的。因而，本实施例的锁相环电路100接入了可控电流源模块150。
MCU中的系统时钟由其他时钟源切换至锁相环电路100，或者锁相环电路100从一个频率切换到另外一个频率，锁相环电路100都经历了从关断到打开然后再到锁定的一个过程。锁相环电路100最终达到锁定的频率也是VCO的输出频率。图4是锁相环电路100的输出时钟的增益曲线，可以看出，VCO的输出频率与控制电压Vctrl有关，其有效的控制电压范围[V min,V max]对应于VCO的输出范围[f min,f max]。对于没有接入可控电流源模块150时的锁相环电路100的输出时钟来说，V min对应于第一MOS管MN 0的阈值电压。锁相环电路100的目标频率是f c,对应于输出时钟的控制电压是V c。
在锁相环电路100由打开到接近锁定的一段时间内，参考时钟频率和分频器反馈时钟频率的差别很大，在这段时间内，参考时钟频率和分频器反馈时钟的频率偏差很大，鉴频鉴相器模块110的输出相位差一直是2π，因此电荷泵模块120一直对环路滤波器130进行充电，V ctrl上的电压不断上升。控制电压的变化和充电电流的关系为：
Figure PCTCN2020141563-appb-000005
在此阶段，锁相环电路100的行为类似于运放工作在大信号的摆率控制区。由于低参考时钟频率下锁相环电路100的充放电电流很低，导致电荷泵模块120对环路滤波器130的充电时间很长，其充电过程还经历了V ctrl从0到V min的“无效”区(VCO无时钟输出)。可以设定一个比V c小的VCO的控制电压V th，[0， V th]的范围内，锁相环电路100的输出频率比目标频率低f c-f th以上，从而使鉴频鉴相器模块110的输出一直为2π，在这个电压范围内增加电荷泵的充电电流并不会引起稳定性问题。增大充电电流会使得频率上升的更快，VCO输出频率更快接近目标频率。
在图2中，V ctrl与阈值电压V th通过比较器I 3进行比较，输出来控制辅助电流源I up_aux。V ctrl<V th时，比较器I 3输出为低时，控制辅助电流源I up_aux打开，增大了充电电流，V ctrl的上升速度与原来相比加快了很多，VCO的频率变化(增加)也比原来要快。V ctrl超过阈值电压V th，此时比较器I 3输出翻转，辅助电流源I up_aux关闭，锁相环电路100恢复正常的状态。整个过程中，锁相环电路100从开启到接近锁定的这段时间由于充电电流的增大而缩短，在接近锁定后关闭，因此可以在不改变原锁相环电路整体结构和参数的前提下实现快速锁定。
在一些实施例中，其提供一种芯片，该芯片包括上述实施例中提到的锁相环电路100。
在一些实施例中，其提供一种电路板，该电路板包括上述实施例中提到的锁相环电路100。
在一些实施例中，其提供一种电子设备，该电子设备包括上述实施例中提到的芯片或上述实施例中提到的电路板。
本专利申请所有实施例提供的锁相环电路、芯片、电路板以及电子设备，其锁相环电路增加了可控电流源模块，可控电流源模块的输入端连接环路滤波器的输出端，可控电流源模块的输出端连接环路滤波器的输入端。这样一来，可控电流源模块可根据环路滤波器的输出进行打开或关闭，当其打开时，可增大电荷泵模块对环路滤波器的充电电流，使得锁相环电路从开启到接近锁定的这段时间由于充电电流的增大而缩短，且可控电流源模块在锁相环电路接近锁定后关闭，不消耗额外的功耗，可在不改变原锁相环电路整体结构和参数的前提下实现快速锁定。
以上结合附图对本专利申请的实施方式作了详细说明，但本专利申请不限于所描述的实施方式。对于本领域的技术人员而言，在不脱离本专利申请原理和精神的情况下，对这些实施方式进行多种变化、修改、替换和变型，仍落入本专利申请的保护范围内。

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  1. 一种锁相环电路，包括鉴频鉴相器模块、电荷泵模块、环路滤波器以及压控振荡器，其特征在于，所述锁相环电路还包括可控电流源模块；
    所述电荷泵模块的控制端连接所述鉴频鉴相器模块的输出端，所述电荷泵模块的输出端连接所述环路滤波器的输入端，所述环路滤波器的输出端连接所述压控振荡器的输入端，所述压控振荡器的输出端连接所述鉴频鉴相器模块的反馈时钟输入端；
    所述可控电流源模块的输入端连接所述环路滤波器的输出端，所述可控电流源模块的输出端连接所述环路滤波器的输入端。
  2. 根据权利要求1所述的锁相环电路，其特征在于，所述可控电流源模块包括辅助电流源、可控开关及比较器，所述比较器的第一输入端连接所述环路滤波器的输出端，所述比较器的第二输入端连接预设的参考电压源，所述比较器的输出端连接所述可控开关的控制端，所述辅助电流源经所述可控开关连接所述环路滤波器的输入端。
  3. 根据权利要求1所述的锁相环电路，其特征在于，所述鉴频鉴相器模块包括第一D触发器、第二D触发器以及与门电路；所述第一D触发器的数据端和所述第二D触发器的数据端分别置高，所述第一D触发器的复位端和所述第二D触发器的复位端分别连接所述与门电路的输出端，所述第一D触发器的时钟输入端为参考时钟输入端，所述第二D触发器的时钟输入端为所述反馈时钟输入端，所述第一D触发器的输出端连接所述与门电路的第一输入端；所述第二D触发器的输出端连接所述与门电路的第二输入端。
  4. 根据权利要求3所述的锁相环电路，其特征在于，所述鉴频鉴相器模块还包括逻辑电路，所述逻辑电路的第一输入端连接所述第一D触发器的输出端，所述逻辑电路的第二输入端连接所述第二D触发器的输出端，所述逻辑电路的第一输出端为所述鉴频鉴相器模块的第一输出端，所述逻辑电路的第二输出端为所述鉴频鉴相器模块的第二输出端。
  5. 根据权利要求1-4任一项所述的锁相环电路，其特征在于，所述电荷泵模块包括依序串联的充电电流源、充电控制开关、放电控制开关和放电电流源；所述充电控制开关的控制端连接所述鉴频鉴相器模块的第一输出端，所述放电控制开关的控制端连接所述鉴频鉴相器模块的第二输出端，所述充电控制开关和所述放电控制开关的连接点作为所述电荷泵模块的输出端与所述环路滤波器 的输入端连接。
  6. 根据权利要求1所述的锁相环电路，其特征在于，所述环路滤波器包括第一电阻与电容，所述第一电阻与电容串联连接，且所述电容远离所述第一电阻的一端接地。
  7. 根据权利要求1所述的锁相环电路，其特征在于，所述压控振荡器包括电流转换模块、镜像模块以及环形振荡器，所述电流转换模块的输入端为所述压控振荡器的输入端，所述电流转换模块的第一输出端经所述镜像模块连接所述环形振荡器的振荡频率控制端，所述电流转换模块的第二输出端接地，所述环形振荡器的输出端为所述压控振荡器的输出端。
  8. 一种芯片，其特征在于，包括如权利要求1-7任一项所述的锁相环电路。
  9. 一种电路板，其特征在于，包括如权利要求1-7任一项所述的锁相环电路。
  10. 一种电子设备，其特征在于，包括如权利要求8所述的芯片或如权利要求9所述的电路板。
PCT/CN2020/141563 2019-12-20 2020-12-30 一种锁相环电路、芯片、电路板以及电子设备 WO2021121433A1 (zh)

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CN112671397B (zh) * 2021-01-13 2023-06-09 河南科技大学 辅助锁相环加速充电的开关控制逻辑电路及锁相环电路
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