WO2021120774A1 - Tranche et carte de carte de sondage - Google Patents

Tranche et carte de carte de sondage Download PDF

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Publication number
WO2021120774A1
WO2021120774A1 PCT/CN2020/118168 CN2020118168W WO2021120774A1 WO 2021120774 A1 WO2021120774 A1 WO 2021120774A1 CN 2020118168 W CN2020118168 W CN 2020118168W WO 2021120774 A1 WO2021120774 A1 WO 2021120774A1
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WIPO (PCT)
Prior art keywords
circuit
functional circuit
test
terminal
functional
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Application number
PCT/CN2020/118168
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English (en)
Chinese (zh)
Inventor
李南
雷张伟
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华为技术有限公司
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Publication of WO2021120774A1 publication Critical patent/WO2021120774A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads

Definitions

  • This application relates to the technical field of chip manufacturing, in particular to a wafer and a test board.
  • the packaging cost of the chip is also increasing.
  • a test board can be used to test the bare chip, and multiple chip probing (CP) probes are provided in the test board.
  • CP chip probing
  • multiple CP probes of the test board can be connected to the input and output ends of the functional circuit respectively.
  • the functional circuit can output test signals from the output end, and the test signals return to the functional circuit after being transmitted by the test board.
  • the functional circuit can further complete the function detection according to the test signal received at the input end.
  • test board when the test signal output by the functional circuit is a high-speed signal, the test board will have a large insertion loss, causing the test signal fed back by the test board to the functional circuit to be attenuated seriously, which will adversely affect the accuracy of the functional test. Therefore, the existing bare chip testing technology needs to be further studied.
  • the present application provides a wafer and a test board to reduce the insertion loss of the test board.
  • an embodiment of the present application provides a wafer including: a plurality of test units; for any one of the test units, the test unit includes a functional circuit and an auxiliary circuit, and there is an open circuit between the functional circuit and the auxiliary circuit.
  • the functional circuit includes a first input terminal and a first output terminal
  • the auxiliary circuit includes a second input terminal and a second output terminal
  • the functional circuit can output a test signal through the first output terminal
  • the auxiliary circuit can receive a function through the second input terminal
  • the test signal output by the circuit is fed back to the functional circuit through the second output terminal
  • the functional circuit can also receive the test signal through the first input terminal, and perform function detection according to the received test signal.
  • the test board needs to connect the first output terminal of the functional circuit with the second input terminal of the auxiliary circuit, and connect the first input terminal of the functional circuit with the second output terminal of the auxiliary circuit.
  • the test board and auxiliary circuit form a test loop.
  • the test board can electrically connect the auxiliary circuit and the functional circuit through the probe, and the length of the electrical connection (that is, the length of the probe) is not limited by the structure of the functional circuit. Therefore, even if the linear distance between the first input terminal and the first output terminal in the functional circuit is too large, the length of the probe will not be increased.
  • the embodiments of the present application are beneficial to reduce the length of the probes in the test board, thereby helping to reduce the insertion loss generated by the test board, and thereby helping to reduce the insertion loss of the test circuit.
  • the test board in order to suppress insertion loss, the test board needs to use high-quality probes.
  • the length of the probe in the test board is reduced by adding an auxiliary circuit, thereby helping to reduce the insertion loss generated by the test board, thereby helping to suppress the insertion loss of the test circuit.
  • the quality requirements for the probe can be appropriately reduced, so the embodiment of the present application is beneficial to reduce the test cost.
  • the auxiliary circuit includes a coupling capacitor, one end of the coupling capacitor is connected to the second input terminal, and the other end of the coupling capacitor is connected to the second output terminal.
  • Setting the coupling capacitor C in the auxiliary circuit is beneficial to isolate the DC noise in the test signal, thereby helping to improve the accuracy of the function detection of the functional circuit.
  • the coupling capacitor C is added to the auxiliary circuit, which does not affect the length of the electrical connection between the auxiliary circuit and the functional circuit of the test board (that is, the length of the probe of the test board), so the embodiment of the application Conducive to both suppression of insertion loss and removal of DC noise.
  • the embodiment of the present application can be applied to a test board with a simpler structure, so as to achieve the purpose of removing the direct current, thereby helping to improve the stability and accuracy of the test result.
  • the coupling capacitor C in the auxiliary circuit can be designed according to the working requirements of the functional circuit during the chip design stage, so as to improve the stability of the coupling capacitor C.
  • the auxiliary circuit includes an amplifier, the input end of the amplifier is connected to the second input end, and the output end of the amplifier is connected to the second output end.
  • the auxiliary circuit provided by the embodiment of the present application can enhance the signal strength of the test signal. Especially in a small signal scenario, the strength of the test signal output by the functional circuit is relatively small. After being transmitted through the test loop, the strength of the test signal input to the functional circuit will be further reduced. Using the auxiliary circuit provided by the embodiment of the present application can amplify the strength of the test signal, thereby helping to improve the accuracy of the function detection of the functional circuit.
  • the auxiliary circuit in the auxiliary circuit, the second input terminal and the second output terminal are short-circuited.
  • the auxiliary circuit can be an interconnection line.
  • the auxiliary circuit has a simple structure and is easy to implement, which is beneficial to simplify the process cost of the auxiliary circuit.
  • the auxiliary circuit is added to the wafer, and the subsequent processing process of the wafer will not be affected:
  • the auxiliary circuit is located in the dicing channel of the wafer.
  • dicing can be performed along the dicing channel.
  • the obtained die includes the complete functional circuit and the remaining parts of the auxiliary circuit.
  • the remaining part of the auxiliary circuit can be packaged as a part of the packaging structure to obtain a finished chip. Adopting this arrangement is beneficial to improving the utilization rate of wafers, and can also be understood as helping to increase the total chip output of wafers.
  • adjacent test units are spaced apart from the first dicing channel.
  • cutting can be performed along the first cutting channel.
  • the obtained die includes a complete functional circuit and auxiliary circuit.
  • the auxiliary circuit can be packaged as a part of the packaging structure to obtain a finished chip.
  • a first cutting channel is spaced between adjacent test units, and a second cutting channel is spaced between the functional circuit and the auxiliary circuit in the test unit.
  • cutting can be performed along the first cutting channel and the second cutting channel.
  • the obtained die includes a complete functional circuit, and does not include auxiliary circuits, so the obtained die can be equivalent to the current conventional die.
  • the functional circuit can be packaged to obtain a finished chip. Adopting this implementation method is beneficial to eliminate the influence of the auxiliary circuit on the finished chip.
  • the functional circuit further includes a communication terminal; the functional circuit may also output detection information through the communication terminal, where the detection information is used to indicate the result of the functional detection.
  • the functional circuit further includes a power supply terminal; the functional circuit may also receive a power signal through the power supply terminal, where the power signal is used to supply power to the functional circuit.
  • an embodiment of the present application provides a test board, which mainly includes: a first connection end, a second connection end, a third connection end, and a fourth connection end, wherein the first connection end is connected to the second connection end ,
  • the third connection terminal is connected to the fourth connection terminal;
  • the first connection terminal can be connected to the first output terminal of the functional circuit to receive the test signal output by the functional circuit;
  • the second connection terminal can be connected to the second input terminal of the auxiliary circuit, Input the test signal output by the functional circuit into the auxiliary circuit;
  • the third connection terminal can be connected with the second output terminal of the auxiliary circuit to receive the test signal output by the auxiliary circuit;
  • the fourth connection terminal can be connected with the first input terminal of the functional circuit, The test signal output by the auxiliary circuit is input to the first input terminal.
  • the test board card further includes a fifth connection terminal, which can be connected to the communication terminal of the functional circuit to receive detection information output by the functional circuit, wherein the detection information is used to indicate the function The result of the function test of the circuit.
  • the test board card further includes a sixth connection terminal, which can be connected to the power supply terminal of the functional circuit to input a power signal to the functional circuit, where the power signal is used for the functional circuit powered by.
  • Figure 1 is a schematic diagram of a wafer
  • Figure 2 is a schematic diagram of a CP test
  • FIG. 3 is a schematic diagram of a wafer provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a structure of a test unit provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of an auxiliary circuit structure provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of an auxiliary circuit provided by an embodiment of the application.
  • FIG. 7 is a schematic structural diagram of an auxiliary circuit provided by an embodiment of the application.
  • FIG. 8 is a schematic diagram of signal amplification according to an embodiment of the application.
  • FIG. 9 is a schematic diagram of an arrangement of auxiliary circuits in a wafer according to an embodiment of the application.
  • FIG. 10 is a schematic diagram of an arrangement of auxiliary circuits in a wafer according to an embodiment of the application.
  • FIG. 11 is a schematic diagram of an arrangement of auxiliary circuits in a wafer according to an embodiment of the application.
  • FIG. 12 is a schematic diagram of the relative positional relationship between the auxiliary circuit and the functional circuit provided by an embodiment of the application;
  • FIG. 13 is a schematic diagram of the relative positional relationship between the auxiliary circuit and the functional circuit provided by an embodiment of the application;
  • 15 is a schematic diagram of the relative positional relationship between the auxiliary circuit and the functional circuit provided by an embodiment of the application;
  • FIG. 16 is a schematic diagram of the relative size relationship between the auxiliary circuit and the functional circuit provided by an embodiment of the application.
  • the device described as “above the other device or structure” or “above the other device or structure” will then be positioned as “below the other device or structure” or “on Under other devices or structures”. Therefore, the exemplary term “above” can include both orientations “above” and “below”.
  • the device can also be positioned in other different ways (rotated by 90 degrees or in other orientations), and the relative description of the space used here shall be explained accordingly.
  • the production process of a chip mainly includes: chip design, wafer processing, wafer cutting, packaging manufacturing, and final test (FT).
  • the chip design mainly includes designing the circuit structure of the functional circuit in the chip according to the functional requirements of the chip.
  • the functional circuit in the chip may include a switching power supply circuit to realize the charging function.
  • the functional circuits in the chip may include logic operation circuits to implement logic operation functions.
  • Wafer processing mainly includes batch processing of dies through a tape-out process.
  • a wafer is usually composed of a semiconductor substrate and a circuit layer laid on the semiconductor substrate.
  • Semiconductor devices such as transistors, capacitors, and inductors are formed on the semiconductor substrate.
  • the circuit layer is provided with multiple circuit layers.
  • the circuit layer and the semiconductor The semiconductor devices on the substrate are coupled to form a complete functional circuit structure.
  • the processed wafer includes a plurality of dies arranged in an array, as shown in FIG. 1, where one small square represents one die.
  • a die is an unpackaged die, and it can generally be understood that a die is a functionally independent, unpackaged chip.
  • the wafer shown in FIG. 1 is cut, specifically, the six adjacent dies as shown by the ellipse and dotted lines in FIG. 1, and the enlarged structure can be as shown on the left side. There are scribe lines between six adjacent dies. When cutting the wafer, it can be cut along the cutting channel. Furthermore, multiple independent dies can be obtained.
  • the multiple dies obtained are packaged separately, that is, package manufacturing.
  • This process is mainly used to make the package structure of the chip, including the package layer of the chip, the electrode of the chip, etc., so as to obtain the finished chip.
  • the qualified chips can be sold at the factory.
  • whether the finished chip is qualified is not only related to whether the package structure of the chip is qualified, but also related to whether the die of the chip is qualified. If the finished chip is unqualified due to the unqualified bare chip, the cost of packaging and manufacturing the chip will be wasted.
  • the CP test of the bare chip is mostly carried out through a test board (probe card).
  • the test board includes a plurality of probes, which can be respectively connected (contacted) with the functional circuits in the tested die.
  • the probes in the test board can be connected to the input terminal and the output terminal of the functional circuit respectively.
  • the functional circuit can output a test signal from the output end, the test board receives the test signal output by the test board through the probe, and the test signal is retransmitted back to the input end of the functional circuit through the test board.
  • the corresponding function detection circuit is designed in the functional circuit, so that in the CP test process, the functional circuit can complete the function detection according to the test signal received at the input terminal.
  • the result of the function test is normal, the die on which the functional circuit is located can be considered qualified, and if the result of the function test is abnormal, the die on which the functional circuit is located can be considered as unqualified.
  • the output end and the input end of the functional circuit are connected through an external test loop, where the test loop includes the probes of the test board.
  • the test board When the test signal passes through the probe of the test board, the test board will produce a certain amount of insertion loss, which will cause the test signal to attenuate.
  • the insertion loss generated by the probe of the test board will further increase as the frequency of the test signal increases.
  • the test signal fed back by the test board to the functional circuit will be seriously attenuated, which will adversely affect the accuracy of the function test.
  • the longer the probe the greater the insertion loss generated by the probe, and the more severe the attenuation of the test signal.
  • the length of the test loop must be greater than the linear distance between the output terminal and the input terminal of the functional circuit, so the test loop will be corresponding increase. Consequently, the length of the probe in the test board must be greater than the linear distance between the output terminal and the input end of the functional circuit, which makes the insertion loss of the test board larger.
  • some current test boards will also be equipped with capacitors and other components. These components limit the further reduction in the size of the test board, so that even if the linear distance between the output end and the input end of the functional circuit is short, the test board produces The insertion loss is still relatively large.
  • the embodiments of the present application provide a wafer and a test board.
  • the auxiliary circuit and the test board jointly realize the input and output ends of the functional circuit.
  • the electrical connection between the two is beneficial to reduce the insertion loss of the test board.
  • FIG. 3 exemplarily shows a wafer provided by an embodiment of the present application.
  • the wafer provided by the embodiment of the present application includes a plurality of test units. Similar to the current arrangement of the dies on the wafer, the multiple test units provided in the embodiments of the present application can also be arranged in an array on the wafer.
  • each test unit may have the same circuit structure, that is, the test unit provided in the embodiment of the present application may be mass-produced through a wafer processing process.
  • the wafer processing technology for manufacturing a bare chip in the prior art which will not be repeated.
  • the test unit includes a functional circuit and an auxiliary circuit.
  • the small white squares represent functional circuits
  • the rectangular area filled with the image adjacent to the small white squares represents auxiliary circuits.
  • FIG. 4 it is a schematic diagram of the structure of a test unit. As shown in Figure 4, there is an open circuit between the functional circuit and the auxiliary circuit. It can also be understood that there is no direct electrical connection between the two on the wafer.
  • the functional circuit includes an output terminal 1o and an input terminal 1i
  • the auxiliary circuit includes an output terminal 2o and an input terminal 2i.
  • the output terminal 1o of the functional circuit can be connected to the input terminal 2i of the auxiliary circuit, and the output terminal 2o of the auxiliary circuit can be connected to the input terminal 1i of the functional circuit through the test board.
  • the test board in FIG. 4 is represented by a dotted line, which is a perspective representation.
  • the test board includes a first connection end, a second connection end, a third connection end and a fourth connection end. Wherein, the first connection end is connected to the second connection end, and the third connection end is connected to the fourth connection end.
  • the first connection end and the second connection end of the test board in the embodiment of the present application may be the two ends of the probe 1, and the third connection end of the test board And the fourth connection end may be the two ends of the probe 2.
  • the test board in the embodiment of the present application may include probe 1 and probe 2.
  • the probe 1 is used to connect the output terminal 1o of the functional circuit and the input terminal 2i of the auxiliary circuit
  • the probe 2 is used to connect the multi-input terminal 1i of the functional circuit and the output terminal 2o of the auxiliary circuit.
  • the functional circuit can output a test signal through the output terminal 1o.
  • the auxiliary circuit can receive the test signal output by the functional circuit through the input terminal 2i, and feedback the test signal to the functional circuit through the output terminal 2o.
  • the functional circuit can receive the test signal fed back by the auxiliary circuit through the 1i, and perform function detection according to the received test signal.
  • the probe of the test board and the auxiliary circuit constitute a test loop.
  • the test board is used to provide an electrical connection for connecting the auxiliary circuit and the functional circuit (such as probe 1 and probe 2 in FIG. 4), and the length of the electrical connection is not limited by the structure of the functional circuit. Then, even if the linear distance between the input terminal 1i and the output terminal 1o in the functional circuit is too large, the length of the probe 1 and the probe 2 will not be increased. Therefore, the embodiment of the present application is beneficial to reduce the lengths of the probe 1 and the probe 2, thereby helping to reduce the insertion loss generated by the probe 1 and the probe 2, and further helping to reduce the insertion loss generated by the test loop.
  • the test board in order to suppress insertion loss, the test board needs to use high-quality probes.
  • an auxiliary circuit is added to suppress the insertion loss of the test board. In this case, the quality requirements for the probe 1 and the probe 2 can be appropriately reduced, which is beneficial to reduce the test cost.
  • the input terminal 2i of the auxiliary circuit can be arranged as close to the output terminal 1o of the functional circuit as possible, and the output terminal 2o of the auxiliary circuit is close to the functional circuit.
  • the input terminal 1i of the circuit is set to minimize the length of probe 1 and probe 2 of the test board.
  • the functional circuit may perform function detection according to the detection signal received by the input terminal 1i.
  • the functional circuit may further include a communication terminal 3o
  • the test board may further include a fifth connection terminal (not shown in the figure).
  • the fifth connection terminal of the test board can be connected to the communication terminal 3o of the functional circuit.
  • the functional circuit After the functional circuit completes the function test, it can also output test information to the test board through the communication terminal, and the test information can indicate the result of the function test.
  • the detection information may indicate whether the function of the functional circuit is normal.
  • the functional circuit may also store the result of the function detection. After the CP test is completed on the entire wafer, each functional circuit in the wafer can uniformly output the result of the functional test. For specific implementation, reference can be made to the prior art, which will not be repeated here.
  • the functional circuit may further include a power supply terminal 3i, and the test board may also include a sixth connection terminal (not shown in the summary of the figure).
  • the sixth connection terminal of the test board is connected to the power supply terminal 3i of the functional circuit, and the test board can input a power signal to the functional circuit through the sixth connection terminal, and the power signal can be used to power the functional circuit.
  • the functional circuit can perform actions such as generating a test signal and performing function detection on the basis of the received power signal.
  • terminal 1o may be connected to one or more input terminals 2i of the auxiliary circuit in a one-to-one correspondence
  • one or more input terminals 1i of the functional circuit may be connected to one or more output terminals 2o of the auxiliary circuit in a one-to-one correspondence
  • FIG. 4 only exemplarily shows the detection of one test unit by the test board.
  • the test board can detect multiple test units at one time.
  • the rectangular dashed frame in Figure 3 can represent the test board, which can complete the detection of 2 ⁇ 2 test units at one time.
  • the embodiment of the present application uses the following specific examples to further illustrate the auxiliary circuit.
  • the input terminal 2i and the output terminal 2o are short-circuited.
  • the auxiliary circuit can be an interconnection line.
  • the auxiliary circuit has a simple structure and is easy to implement, which is beneficial to simplify the process cost of the auxiliary circuit.
  • the auxiliary circuit may include a coupling capacitor C, one end of the coupling capacitor C is connected to the input terminal 2i, and the other end of the coupling capacitor C is connected to the output terminal 2o.
  • the coupling capacitor C is provided in the auxiliary circuit to help isolate the DC noise in the test signal, thereby helping to improve the accuracy of the function detection of the functional circuit.
  • test boards equipped with coupling capacitors.
  • additional probes need to be added to the test board to connect the coupling capacitor.
  • the current test board can be connected to the output of the functional circuit through a probe.
  • Terminal 1o and input terminal 1i when the test board is equipped with a capacitor, a probe is required to connect the output terminal 1o and one end of the coupling capacitor, and another probe is connected to the input terminal 1i and the other end of the coupling capacitor.
  • the insertion loss of the test board will be further increased, thereby further increasing the insertion loss of the test circuit.
  • setting a capacitor in the test board will limit the reduction of the physical size of the test board, so that even if the length of the probe is shortened as much as possible, the length of the test loop is still longer, and it will still cause greater insertion loss.
  • the embodiment of the present application even if the coupling capacitor C is added to the auxiliary circuit, or other circuit elements are added, the number and length of the probes 1 and 2 in FIG. 4 may not be affected. Therefore, the embodiment of the present application is beneficial to Further suppress the insertion loss of the test board. Moreover, compared with the current test boards provided with coupling capacitors, the embodiments of the present application can be applied to test boards with a simpler structure. Generally, the simpler the structure of the test board, the more conducive to improving the stability and reliability of the test results. Therefore, compared with the current solution of arranging components such as capacitors in the test board, the embodiments of the present application are beneficial to improve the stability and accuracy of the test results.
  • coupling capacitors are currently set in test boards. Since test boards will be used to test different types of functional circuits, coupling capacitors are generally not designed specifically according to the working scenarios of the functional circuits. For example, some functional circuits need to work in high-temperature scenarios, so CP testing is generally performed in high-temperature scenarios. If the coupling capacitor in the test board fails to work normally in a high temperature scenario, it will affect the accuracy of the function detection of the functional circuit.
  • the coupling capacitor C in the auxiliary circuit can be designed according to the working requirements of the functional circuit during the chip design stage. For example, if the functional circuit works in a high temperature scene, in the chip design stage, the coupling capacitor C is specifically designed to improve the high temperature resistance characteristics of the coupling capacitor C.
  • the auxiliary circuit may include an amplifier OP.
  • one input terminal of the amplifier is connected to the input terminal 2i of the auxiliary circuit, the other input terminal of the amplifier is grounded, and the output terminal of the amplifier is connected to the output terminal 2o of the auxiliary circuit.
  • the auxiliary circuit shown in Fig. 7 is used so that the auxiliary circuit can amplify the received test signal.
  • the left side is the waveform diagram of the test signal received by the input terminal 2i of the auxiliary circuit.
  • the abscissa represents time
  • the ordinate represents signal strength.
  • the right side is the waveform diagram of the test signal output by the output terminal 2o of the auxiliary circuit.
  • the abscissa represents time
  • the ordinate represents signal strength. Comparing the two waveform diagrams in FIG. 8, it can be seen that the auxiliary circuit provided by the embodiment of the present application can enhance the signal strength of the test signal. Especially in a small signal scenario, the strength of the test signal output by the functional circuit is relatively small. After being transmitted through the test loop, the strength of the test signal input to the functional circuit will be further reduced. Using the test loop provided by the embodiment of the present application can amplify the strength of the test signal, thereby helping to improve the accuracy of the function detection of the functional circuit.
  • auxiliary circuit may also include other circuit elements that can optimize the test effect, which will not be listed in the embodiment of the present application.
  • an auxiliary circuit is added to the wafer, and the subsequent processing process of the wafer will not be affected.
  • the auxiliary circuit can be arranged in the dicing channel of the wafer.
  • FIG. 9 is an image obtained after zooming in on the 4 test units in the rectangular dashed box in FIG. 3.
  • adjacent test units are closely arranged.
  • the auxiliary circuits are spaced between adjacent functional circuits.
  • adjacent test cells are spaced apart by cutting trenches. That is, part of the dicing channels in the wafer is provided with auxiliary circuits, and part of the dicing channels is not provided with auxiliary circuits.
  • cutting can be performed along the cutting channel.
  • the obtained die includes the complete functional circuit and the remaining parts of the auxiliary circuit.
  • the remaining part of the auxiliary circuit can be packaged as a part of the packaging structure to obtain a finished chip.
  • Adopting the arrangement shown in FIG. 9 is beneficial to improving the utilization rate of the wafer, and can also be understood as helping to increase the total chip output of the wafer.
  • FIG. 10 it is an image obtained after zooming in on the four test units in the rectangular dashed line frame in FIG. 3. As shown in FIG. 10, in the row direction, adjacent test cells are spaced to cut trenches, and in the column direction, adjacent test cells are also spaced to cut trenches.
  • cutting can be performed along the cutting channel.
  • the obtained die includes a complete functional circuit and auxiliary circuit.
  • the auxiliary circuit can be packaged as a part of the packaging structure to obtain a finished chip.
  • FIG. 11 it is an image obtained after zooming in on the four test units in the rectangular dashed box in FIG. 3.
  • adjacent test units are spaced apart with cutting channels, and inside the test units, there are also cutting channels spaced between the functional circuit and the auxiliary circuit.
  • adjacent test cells are also spaced apart by cutting trenches.
  • cutting can be performed along the cutting channel.
  • the obtained die includes a complete functional circuit, and does not include auxiliary circuits, so the obtained die can be equivalent to the current conventional die.
  • the functional circuit can be packaged to obtain a finished chip.
  • the implementation shown in FIG. 11 is beneficial to eliminate the influence of the auxiliary circuit on the finished chip.
  • auxiliary circuit is located in the dicing channel of the wafer, it will not limit the relative position between the auxiliary circuit and the functional circuit.
  • the auxiliary circuit can be located on either side of the functional circuit. As shown in (a) to (d) in Figure 12, the auxiliary circuit can be located on the right side of the functional circuit (a), on the left side of the functional circuit (b), or below the functional circuit (c) , Can also be located above the functional circuit (d).
  • the auxiliary circuit can also be located on both sides of the functional circuit.
  • the auxiliary circuit can be located above and below the functional circuit (a), can also be located on the left and right side of the functional circuit (b), or can be located on the functional circuit
  • the left and top (c) of the function circuit can also be located on the right and above the functional circuit (d), it can also be located on the left and below the functional circuit (e), or it can be located on the right and below the functional circuit (f) .
  • the auxiliary circuit can also be located on three sides of the functional circuit. As shown in (a) to (d) in Figure 14, the auxiliary circuit can be located above, below, and on the left side (a) of the functional circuit, or above, on the left side, and on the right side (b) of the functional circuit. It can also be located above, below, and right of the functional circuit (c), or located below, left, and right of the functional circuit (d).
  • auxiliary circuit can also be arranged around the functional circuit, as shown in FIG. 15.
  • the embodiments of the present application do not limit the relative size relationship between the functional circuit and the auxiliary circuit.
  • the length of the auxiliary circuit can be greater than the length (d) of the right side of the functional circuit, or less than The length of the right side of the functional circuit (a) to (c), (e).
  • the auxiliary circuit can be located near the lower right side of the functional circuit (a), or located near the upper right side of the functional circuit (b), or Set (c) close to the middle of the right side of the functional circuit, or part of the area may be adjacent to the right side of the functional circuit, and part of the area exceeds the area (e) where the functional circuit is located, and so on.
  • the embodiments of the present application will not enumerate them one by one.

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Environmental & Geological Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne une tranche et une carte de carte de sondage, qui facilitent la réduction de la perte d'insertion générée par la carte de carte de sondage pendant la CP. La tranche comprend une pluralité d'unités de sondage ; pour n'importe quelle unité de sondage à l'intérieur de celle-ci, l'unité de sondage comprend un circuit fonctionnel et un circuit auxiliaire ; au cours de la CP, une première extrémité de sortie du circuit fonctionnel peut être connectée à une seconde extrémité d'entrée du circuit auxiliaire au moyen de la carte de carte de sondage ; et une première extrémité d'entrée du circuit fonctionnel est connectée à une seconde extrémité de sortie du circuit auxiliaire. Les modes de réalisation de la présente invention facilitent la réduction de la longueur d'une sonde dans une carte de carte de sondage, ce qui facilite la réduction de la perte d'insertion générée par la carte de carte de sondage, et facilite la réduction du coût de sondage.
PCT/CN2020/118168 2019-12-20 2020-09-27 Tranche et carte de carte de sondage WO2021120774A1 (fr)

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CN201911330991.9A CN113013143B (zh) 2019-12-20 2019-12-20 一种晶圆及测试板卡
CN201911330991.9 2019-12-20

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006287821A (ja) * 2005-04-05 2006-10-19 Epson Toyocom Corp 弾性表面波装置
CN101587165A (zh) * 2008-05-23 2009-11-25 旺矽科技股份有限公司 晶圆验收测试方法、接触垫、及探针卡
CN105826286A (zh) * 2015-01-07 2016-08-03 中芯国际集成电路制造(上海)有限公司 芯片结构及其制作方法
CN107367678A (zh) * 2016-05-11 2017-11-21 中芯国际集成电路制造(上海)有限公司 测试结构、测试探针卡、测试系统及测试方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5506499A (en) * 1995-06-05 1996-04-09 Neomagic Corp. Multiple probing of an auxilary test pad which allows for reliable bonding to a primary bonding pad
CN1705075A (zh) * 2004-05-31 2005-12-07 台湾类比科技股份有限公司 具有测试电路之半导体晶圆及制造方法
KR101647302B1 (ko) * 2009-11-26 2016-08-10 삼성전자주식회사 프로브 카드 및 이를 포함하는 테스트 장치
TWI443341B (zh) * 2011-07-28 2014-07-01 Star Techn Inc 半導體元件測試裝置
CN203350300U (zh) * 2013-06-17 2013-12-18 上海华虹Nec电子有限公司 一种兼容晶圆针测和封装测试的多功能探针卡

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006287821A (ja) * 2005-04-05 2006-10-19 Epson Toyocom Corp 弾性表面波装置
CN101587165A (zh) * 2008-05-23 2009-11-25 旺矽科技股份有限公司 晶圆验收测试方法、接触垫、及探针卡
CN105826286A (zh) * 2015-01-07 2016-08-03 中芯国际集成电路制造(上海)有限公司 芯片结构及其制作方法
CN107367678A (zh) * 2016-05-11 2017-11-21 中芯国际集成电路制造(上海)有限公司 测试结构、测试探针卡、测试系统及测试方法

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