WO2021120774A1

WO2021120774A1 - Wafer and probing board card

Info

Publication number: WO2021120774A1
Application number: PCT/CN2020/118168
Authority: WO
Inventors: 李南; 雷张伟
Original assignee: 华为技术有限公司
Priority date: 2019-12-20
Filing date: 2020-09-27
Publication date: 2021-06-24
Also published as: CN113013143B; CN113013143A

Abstract

Provided are a wafer and a probing board card, which facilitate the reduction of insertion loss generated by the probing board card during CP. The wafer comprises a plurality of probing units; for any probing unit therein, the probing unit comprises a functional circuit and an auxiliary circuit; during the CP, a first output end of the functional circuit can be connected to a second input end of the auxiliary circuit by means of the probing board card; and a first input end of the functional circuit is connected to a second output end of the auxiliary circuit. The embodiments of the present application facilitate the reduction of the length of a probe in a probing board card, thereby facilitating the reduction of the insertion loss generated by the probing board card, and facilitating the reduction of the probing cost.

Description

Wafer and test board

Cross-references to related applications

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office, the application number is 201911330991.9, and the application name is "a kind of wafer and test board" on December 20, 2019, the entire content of which is incorporated into this application by reference in.

Technical field

This application relates to the technical field of chip manufacturing, in particular to a wafer and a test board.

Background technique

With the increase in chip integration and complexity, the packaging cost of the chip is also increasing. In order to save the packaging cost wasted by unqualified chips, it is generally necessary to inspect the functional circuits on the die before packaging the die. After the function of the functional circuit is determined to be normal, the die is packaged.

Currently, a test board can be used to test the bare chip, and multiple chip probing (CP) probes are provided in the test board. In the test process, multiple CP probes of the test board can be connected to the input and output ends of the functional circuit respectively. The functional circuit can output test signals from the output end, and the test signals return to the functional circuit after being transmitted by the test board. At the input end, the functional circuit can further complete the function detection according to the test signal received at the input end.

However, when the test signal output by the functional circuit is a high-speed signal, the test board will have a large insertion loss, causing the test signal fed back by the test board to the functional circuit to be attenuated seriously, which will adversely affect the accuracy of the functional test. Therefore, the existing bare chip testing technology needs to be further studied.

Summary of the invention

In view of this, the present application provides a wafer and a test board to reduce the insertion loss of the test board.

In a first aspect, an embodiment of the present application provides a wafer including: a plurality of test units; for any one of the test units, the test unit includes a functional circuit and an auxiliary circuit, and there is an open circuit between the functional circuit and the auxiliary circuit. Among them, the functional circuit includes a first input terminal and a first output terminal, the auxiliary circuit includes a second input terminal and a second output terminal; the functional circuit can output a test signal through the first output terminal; the auxiliary circuit can receive a function through the second input terminal The test signal output by the circuit is fed back to the functional circuit through the second output terminal; the functional circuit can also receive the test signal through the first input terminal, and perform function detection according to the received test signal.

In the CP test process, the test board needs to connect the first output terminal of the functional circuit with the second input terminal of the auxiliary circuit, and connect the first input terminal of the functional circuit with the second output terminal of the auxiliary circuit. In other words, the test board and auxiliary circuit form a test loop. Among them, the test board can electrically connect the auxiliary circuit and the functional circuit through the probe, and the length of the electrical connection (that is, the length of the probe) is not limited by the structure of the functional circuit. Therefore, even if the linear distance between the first input terminal and the first output terminal in the functional circuit is too large, the length of the probe will not be increased. Therefore, the embodiments of the present application are beneficial to reduce the length of the probes in the test board, thereby helping to reduce the insertion loss generated by the test board, and thereby helping to reduce the insertion loss of the test circuit. Moreover, in some current CP testing schemes, in order to suppress insertion loss, the test board needs to use high-quality probes. In the embodiment of the present application, the length of the probe in the test board is reduced by adding an auxiliary circuit, thereby helping to reduce the insertion loss generated by the test board, thereby helping to suppress the insertion loss of the test circuit. In this case , The quality requirements for the probe can be appropriately reduced, so the embodiment of the present application is beneficial to reduce the test cost.

In the embodiments of the present application, there are at least the following three implementation modes for the auxiliary circuit:

For example, the auxiliary circuit includes a coupling capacitor, one end of the coupling capacitor is connected to the second input terminal, and the other end of the coupling capacitor is connected to the second output terminal. Setting the coupling capacitor C in the auxiliary circuit is beneficial to isolate the DC noise in the test signal, thereby helping to improve the accuracy of the function detection of the functional circuit. Moreover, in the embodiment of the application, the coupling capacitor C is added to the auxiliary circuit, which does not affect the length of the electrical connection between the auxiliary circuit and the functional circuit of the test board (that is, the length of the probe of the test board), so the embodiment of the application Conducive to both suppression of insertion loss and removal of DC noise. In addition, the embodiment of the present application can be applied to a test board with a simpler structure, so as to achieve the purpose of removing the direct current, thereby helping to improve the stability and accuracy of the test result. Finally, in the embodiments of the present application, the coupling capacitor C in the auxiliary circuit can be designed according to the working requirements of the functional circuit during the chip design stage, so as to improve the stability of the coupling capacitor C.

For another example, the auxiliary circuit includes an amplifier, the input end of the amplifier is connected to the second input end, and the output end of the amplifier is connected to the second output end. The auxiliary circuit provided by the embodiment of the present application can enhance the signal strength of the test signal. Especially in a small signal scenario, the strength of the test signal output by the functional circuit is relatively small. After being transmitted through the test loop, the strength of the test signal input to the functional circuit will be further reduced. Using the auxiliary circuit provided by the embodiment of the present application can amplify the strength of the test signal, thereby helping to improve the accuracy of the function detection of the functional circuit.

For another example, in the auxiliary circuit, the second input terminal and the second output terminal are short-circuited. In other words, the auxiliary circuit can be an interconnection line. In this case, the auxiliary circuit has a simple structure and is easy to implement, which is beneficial to simplify the process cost of the auxiliary circuit.

In the embodiment of the application, the auxiliary circuit is added to the wafer, and the subsequent processing process of the wafer will not be affected:

For example, the auxiliary circuit is located in the dicing channel of the wafer. In the subsequent wafer dicing process, dicing can be performed along the dicing channel. The obtained die includes the complete functional circuit and the remaining parts of the auxiliary circuit. In the subsequent packaging process, the remaining part of the auxiliary circuit can be packaged as a part of the packaging structure to obtain a finished chip. Adopting this arrangement is beneficial to improving the utilization rate of wafers, and can also be understood as helping to increase the total chip output of wafers.

For another example, in the wafer, adjacent test units are spaced apart from the first dicing channel. In the subsequent wafer cutting process, cutting can be performed along the first cutting channel. The obtained die includes a complete functional circuit and auxiliary circuit. In the subsequent packaging process, the auxiliary circuit can be packaged as a part of the packaging structure to obtain a finished chip.

For another example, in a wafer, a first cutting channel is spaced between adjacent test units, and a second cutting channel is spaced between the functional circuit and the auxiliary circuit in the test unit. In the subsequent wafer cutting process, cutting can be performed along the first cutting channel and the second cutting channel. The obtained die includes a complete functional circuit, and does not include auxiliary circuits, so the obtained die can be equivalent to the current conventional die. In the subsequent packaging process, the functional circuit can be packaged to obtain a finished chip. Adopting this implementation method is beneficial to eliminate the influence of the auxiliary circuit on the finished chip.

In a possible implementation manner, the functional circuit further includes a communication terminal; the functional circuit may also output detection information through the communication terminal, where the detection information is used to indicate the result of the functional detection.

In a possible implementation manner, the functional circuit further includes a power supply terminal; the functional circuit may also receive a power signal through the power supply terminal, where the power signal is used to supply power to the functional circuit.

In the second aspect, an embodiment of the present application provides a test board, which mainly includes: a first connection end, a second connection end, a third connection end, and a fourth connection end, wherein the first connection end is connected to the second connection end , The third connection terminal is connected to the fourth connection terminal; the first connection terminal can be connected to the first output terminal of the functional circuit to receive the test signal output by the functional circuit; the second connection terminal can be connected to the second input terminal of the auxiliary circuit, Input the test signal output by the functional circuit into the auxiliary circuit; the third connection terminal can be connected with the second output terminal of the auxiliary circuit to receive the test signal output by the auxiliary circuit; the fourth connection terminal can be connected with the first input terminal of the functional circuit, The test signal output by the auxiliary circuit is input to the first input terminal.

In a possible implementation manner, the test board card further includes a fifth connection terminal, which can be connected to the communication terminal of the functional circuit to receive detection information output by the functional circuit, wherein the detection information is used to indicate the function The result of the function test of the circuit.

In a possible implementation manner, the test board card further includes a sixth connection terminal, which can be connected to the power supply terminal of the functional circuit to input a power signal to the functional circuit, where the power signal is used for the functional circuit powered by.

These and other aspects of the application will be more concise and understandable in the description of the following embodiments.

Description of the drawings

Figure 1 is a schematic diagram of a wafer;

Figure 2 is a schematic diagram of a CP test;

FIG. 3 is a schematic diagram of a wafer provided by an embodiment of the application;

FIG. 4 is a schematic diagram of a structure of a test unit provided by an embodiment of the application;

FIG. 5 is a schematic diagram of an auxiliary circuit structure provided by an embodiment of the application;

FIG. 6 is a schematic structural diagram of an auxiliary circuit provided by an embodiment of the application;

FIG. 7 is a schematic structural diagram of an auxiliary circuit provided by an embodiment of the application;

FIG. 8 is a schematic diagram of signal amplification according to an embodiment of the application;

FIG. 9 is a schematic diagram of an arrangement of auxiliary circuits in a wafer according to an embodiment of the application;

10 is a schematic diagram of an arrangement of auxiliary circuits in a wafer according to an embodiment of the application;

FIG. 11 is a schematic diagram of an arrangement of auxiliary circuits in a wafer according to an embodiment of the application;

12 is a schematic diagram of the relative positional relationship between the auxiliary circuit and the functional circuit provided by an embodiment of the application;

FIG. 13 is a schematic diagram of the relative positional relationship between the auxiliary circuit and the functional circuit provided by an embodiment of the application;

14 is a schematic diagram of the relative positional relationship between the auxiliary circuit and the functional circuit provided by an embodiment of the application;

15 is a schematic diagram of the relative positional relationship between the auxiliary circuit and the functional circuit provided by an embodiment of the application;

FIG. 16 is a schematic diagram of the relative size relationship between the auxiliary circuit and the functional circuit provided by an embodiment of the application.

Detailed ways

In order to make the purpose, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operation method in the method embodiment can also be applied to the device embodiment or the system embodiment. It should be noted that in the description of this application, "at least one" refers to one or more, and multiple refers to two or more. In view of this, in the embodiments of the present invention, “a plurality of” may also be understood as “at least two”. "And/or" describes the association relationship of the associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone. In addition, the character "/", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship. In addition, it should be understood that in the description of this application, words such as "first" and "second" are only used for the purpose of distinguishing description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating Or imply the order. In the description of the embodiments of the present application, "coupled" refers to a direct or indirect electrical connection relationship. For example, "A and B coupled" may mean that A and B are directly electrically connected, or that A and B are electrically connected through C.

For convenience, a specific spatial relative terminology system is used in the following description, and this is not restrictive. The terms "upper" and "lower" identify directions in the drawings to which reference is made. The terms include the terms specifically mentioned above, their derivatives, and similarly introduced terms. "Above", "Above", "Above the surface", "Above", etc., are used to describe the difference between a device or feature and other devices or features as shown in the figure Spatial location relationship. It should be understood that the spatial relative terms are intended to encompass different orientations other than the orientation of the device described in the figure. For example, if the device in the figure is inverted, then the device described as "above the other device or structure" or "above the other device or structure" will then be positioned as "below the other device or structure" or "on Under other devices or structures". Therefore, the exemplary term "above" can include both orientations "above" and "below". The device can also be positioned in other different ways (rotated by 90 degrees or in other orientations), and the relative description of the space used here shall be explained accordingly.

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

With the development of electronic technology, chips have become the cornerstone of modern society. At present, the production process of a chip mainly includes: chip design, wafer processing, wafer cutting, packaging manufacturing, and final test (FT). Among them, the chip design mainly includes designing the circuit structure of the functional circuit in the chip according to the functional requirements of the chip. For example, if the chip is a charging chip, the functional circuit in the chip may include a switching power supply circuit to realize the charging function. For another example, if the chip is a processor chip, the functional circuits in the chip may include logic operation circuits to implement logic operation functions.

Wafer processing mainly includes batch processing of dies through a tape-out process. Specifically, a wafer is usually composed of a semiconductor substrate and a circuit layer laid on the semiconductor substrate. Semiconductor devices such as transistors, capacitors, and inductors are formed on the semiconductor substrate. The circuit layer is provided with multiple circuit layers. The circuit layer and the semiconductor The semiconductor devices on the substrate are coupled to form a complete functional circuit structure. The processed wafer includes a plurality of dies arranged in an array, as shown in FIG. 1, where one small square represents one die. A die is an unpackaged die, and it can generally be understood that a die is a functionally independent, unpackaged chip.

The wafer shown in FIG. 1 is cut, specifically, the six adjacent dies as shown by the ellipse and dotted lines in FIG. 1, and the enlarged structure can be as shown on the left side. There are scribe lines between six adjacent dies. When cutting the wafer, it can be cut along the cutting channel. Furthermore, multiple independent dies can be obtained.

The multiple dies obtained are packaged separately, that is, package manufacturing. This process is mainly used to make the package structure of the chip, including the package layer of the chip, the electrode of the chip, etc., so as to obtain the finished chip. After the FT test is performed on the chips, the qualified chips can be sold at the factory.

However, whether the finished chip is qualified is not only related to whether the package structure of the chip is qualified, but also related to whether the die of the chip is qualified. If the finished chip is unqualified due to the unqualified bare chip, the cost of packaging and manufacturing the chip will be wasted.

In view of this, in current chip manufacturing, it is usually necessary to perform a CP test before wafer dicing to identify unqualified dies in the wafer. In the wafer shown in Figure 1, there are two defective dies. In the subsequent packaging and manufacturing, these two unqualified dies can be discarded, so that the packaging cost of the chip can be saved as a whole.

As shown in Figure 2, at present, the CP test of the bare chip is mostly carried out through a test board (probe card). The test board includes a plurality of probes, which can be respectively connected (contacted) with the functional circuits in the tested die. Specifically, the probes in the test board can be connected to the input terminal and the output terminal of the functional circuit respectively. The functional circuit can output a test signal from the output end, the test board receives the test signal output by the test board through the probe, and the test signal is retransmitted back to the input end of the functional circuit through the test board.

Generally speaking, in the stage of designing the chip, the corresponding function detection circuit is designed in the functional circuit, so that in the CP test process, the functional circuit can complete the function detection according to the test signal received at the input terminal. Exemplarily, if the result of the function test is normal, the die on which the functional circuit is located can be considered qualified, and if the result of the function test is abnormal, the die on which the functional circuit is located can be considered as unqualified.

In the above process, the output end and the input end of the functional circuit are connected through an external test loop, where the test loop includes the probes of the test board. When the test signal passes through the probe of the test board, the test board will produce a certain amount of insertion loss, which will cause the test signal to attenuate. Especially when the test signal output by the functional circuit is a high-speed signal, the insertion loss generated by the probe of the test board will further increase as the frequency of the test signal increases. When the insertion loss generated by the probe of the test board is too large, the test signal fed back by the test board to the functional circuit will be seriously attenuated, which will adversely affect the accuracy of the function test.

Generally speaking, when other factors related to insertion loss (such as probe material) remain unchanged, the longer the probe, the greater the insertion loss generated by the probe, and the more severe the attenuation of the test signal. In the current CP test, if the linear distance between the output terminal and the input terminal of the functional circuit is too long, the length of the test loop must be greater than the linear distance between the output terminal and the input terminal of the functional circuit, so the test loop will be corresponding increase. Consequently, the length of the probe in the test board must be greater than the linear distance between the output terminal and the input end of the functional circuit, which makes the insertion loss of the test board larger. In addition, some current test boards will also be equipped with capacitors and other components. These components limit the further reduction in the size of the test board, so that even if the linear distance between the output end and the input end of the functional circuit is short, the test board produces The insertion loss is still relatively large.

In view of this, the embodiments of the present application provide a wafer and a test board. By setting a corresponding auxiliary circuit for the functional circuit in the wafer, the auxiliary circuit and the test board jointly realize the input and output ends of the functional circuit. The electrical connection between the two is beneficial to reduce the insertion loss of the test board.

FIG. 3 exemplarily shows a wafer provided by an embodiment of the present application. As shown in FIG. 3, the wafer provided by the embodiment of the present application includes a plurality of test units. Similar to the current arrangement of the dies on the wafer, the multiple test units provided in the embodiments of the present application can also be arranged in an array on the wafer.

It can be understood that each test unit may have the same circuit structure, that is, the test unit provided in the embodiment of the present application may be mass-produced through a wafer processing process. For a specific implementation manner, reference may be made to the wafer processing technology for manufacturing a bare chip in the prior art, which will not be repeated.

For any one of the test units, the test unit includes a functional circuit and an auxiliary circuit. As shown in Figure 3, the small white squares represent functional circuits, and the rectangular area filled with the image adjacent to the small white squares represents auxiliary circuits. In the embodiment of the present application, there is an open circuit between the functional circuit and the auxiliary circuit.

Exemplarily, as shown in FIG. 4, it is a schematic diagram of the structure of a test unit. As shown in Figure 4, there is an open circuit between the functional circuit and the auxiliary circuit. It can also be understood that there is no direct electrical connection between the two on the wafer. The functional circuit includes an output terminal 1o and an input terminal 1i, and the auxiliary circuit includes an output terminal 2o and an input terminal 2i.

In the embodiment of the present application, the output terminal 1o of the functional circuit can be connected to the input terminal 2i of the auxiliary circuit, and the output terminal 2o of the auxiliary circuit can be connected to the input terminal 1i of the functional circuit through the test board. Exemplarily, the test board in FIG. 4 is represented by a dotted line, which is a perspective representation. The test board includes a first connection end, a second connection end, a third connection end and a fourth connection end. Wherein, the first connection end is connected to the second connection end, and the third connection end is connected to the fourth connection end.

During the CP test, you can connect the first connection terminal to the output terminal 1o of the functional circuit, connect the second connection terminal to the input terminal 2i of the auxiliary circuit, connect the third connection terminal to the output terminal 2o of the auxiliary circuit, and connect the first connection terminal to the output terminal 2o of the auxiliary circuit. The four connecting terminals are connected to the input terminal 1i of the functional circuit.

In a possible implementation, as shown in FIG. 4, the first connection end and the second connection end of the test board in the embodiment of the present application may be the two ends of the probe 1, and the third connection end of the test board And the fourth connection end may be the two ends of the probe 2. That is to say, the test board in the embodiment of the present application may include probe 1 and probe 2. Among them, the probe 1 is used to connect the output terminal 1o of the functional circuit and the input terminal 2i of the auxiliary circuit, and the probe 2 is used to connect the multi-input terminal 1i of the functional circuit and the output terminal 2o of the auxiliary circuit.

After the output terminal 1o of the functional circuit is connected with the input terminal 2i of the auxiliary circuit, and the output terminal 2o of the auxiliary circuit is connected with the input terminal 1i of the functional circuit, the functional circuit can output a test signal through the output terminal 1o. The auxiliary circuit can receive the test signal output by the functional circuit through the input terminal 2i, and feedback the test signal to the functional circuit through the output terminal 2o. The functional circuit can receive the test signal fed back by the auxiliary circuit through the 1i, and perform function detection according to the received test signal.

In the embodiment of the present application, the probe of the test board and the auxiliary circuit constitute a test loop. Among them, the test board is used to provide an electrical connection for connecting the auxiliary circuit and the functional circuit (such as probe 1 and probe 2 in FIG. 4), and the length of the electrical connection is not limited by the structure of the functional circuit. Then, even if the linear distance between the input terminal 1i and the output terminal 1o in the functional circuit is too large, the length of the probe 1 and the probe 2 will not be increased. Therefore, the embodiment of the present application is beneficial to reduce the lengths of the probe 1 and the probe 2, thereby helping to reduce the insertion loss generated by the probe 1 and the probe 2, and further helping to reduce the insertion loss generated by the test loop.

Moreover, in some current CP testing schemes, in order to suppress insertion loss, the test board needs to use high-quality probes. In the embodiment of the present application, an auxiliary circuit is added to suppress the insertion loss of the test board. In this case, the quality requirements for the probe 1 and the probe 2 can be appropriately reduced, which is beneficial to reduce the test cost.

In a possible implementation manner, when the circuit between the functional circuit and the auxiliary circuit is maintained, the input terminal 2i of the auxiliary circuit can be arranged as close to the output terminal 1o of the functional circuit as possible, and the output terminal 2o of the auxiliary circuit is close to the functional circuit. The input terminal 1i of the circuit is set to minimize the length of probe 1 and probe 2 of the test board.

In the embodiment of the present application, the functional circuit may perform function detection according to the detection signal received by the input terminal 1i. In a possible implementation manner, as shown in FIG. 4, the functional circuit may further include a communication terminal 3o, and the test board may further include a fifth connection terminal (not shown in the figure). During the CP test, the fifth connection terminal of the test board can be connected to the communication terminal 3o of the functional circuit. After the functional circuit completes the function test, it can also output test information to the test board through the communication terminal, and the test information can indicate the result of the function test. For example, the detection information may indicate whether the function of the functional circuit is normal.

In another possible implementation manner, the functional circuit may also store the result of the function detection. After the CP test is completed on the entire wafer, each functional circuit in the wafer can uniformly output the result of the functional test. For specific implementation, reference can be made to the prior art, which will not be repeated here.

As shown in FIG. 4, the functional circuit may further include a power supply terminal 3i, and the test board may also include a sixth connection terminal (not shown in the summary of the figure). During the CP test, the sixth connection terminal of the test board is connected to the power supply terminal 3i of the functional circuit, and the test board can input a power signal to the functional circuit through the sixth connection terminal, and the power signal can be used to power the functional circuit. For example, the functional circuit can perform actions such as generating a test signal and performing function detection on the basis of the received power signal.

It should be pointed out that there can be one or more output terminals 1o and input terminals 1i of the functional circuit, so there can also be one or more input terminals 2i and output terminals 2o of the auxiliary circuit, so that one or more output terminals of the functional circuit The terminal 1o may be connected to one or more input terminals 2i of the auxiliary circuit in a one-to-one correspondence, and one or more input terminals 1i of the functional circuit may be connected to one or more output terminals 2o of the auxiliary circuit in a one-to-one correspondence. Correspondingly, there may also be one or more first connection terminals and second connection terminals in the test board to realize one-to-one correspondence between one or more output terminals 1o and one or more input terminals 2i. There may also be one or more of the third connection terminal and the fourth connection terminal in the test board, so as to realize a one-to-one correspondence between one or more output terminals 2o and one or more input terminals 1i.

It should be pointed out that FIG. 4 only exemplarily shows the detection of one test unit by the test board. In the actual implementation process, the test board can detect multiple test units at one time. The rectangular dashed frame in Figure 3 can represent the test board, which can complete the detection of 2×2 test units at one time.

Next, the embodiment of the present application uses the following specific examples to further illustrate the auxiliary circuit. In the embodiments of the present application, there are at least the following three possible implementation modes for the auxiliary circuit:

Realization method one

As shown in Figure 5, the input terminal 2i and the output terminal 2o are short-circuited. In other words, the auxiliary circuit can be an interconnection line. In this case, the auxiliary circuit has a simple structure and is easy to implement, which is beneficial to simplify the process cost of the auxiliary circuit.

Realization method two

As shown in FIG. 6, the auxiliary circuit may include a coupling capacitor C, one end of the coupling capacitor C is connected to the input terminal 2i, and the other end of the coupling capacitor C is connected to the output terminal 2o.

When the test signal is a high-speed signal, the coupling capacitor C is provided in the auxiliary circuit to help isolate the DC noise in the test signal, thereby helping to improve the accuracy of the function detection of the functional circuit.

At present, there are also some test boards equipped with coupling capacitors. However, in this case, additional probes need to be added to the test board to connect the coupling capacitor. Specifically, when there is no coupling capacitor, the current test board can be connected to the output of the functional circuit through a probe. Terminal 1o and input terminal 1i, when the test board is equipped with a capacitor, a probe is required to connect the output terminal 1o and one end of the coupling capacitor, and another probe is connected to the input terminal 1i and the other end of the coupling capacitor. Due to the addition of additional probes, the insertion loss of the test board will be further increased, thereby further increasing the insertion loss of the test circuit. In addition, setting a capacitor in the test board will limit the reduction of the physical size of the test board, so that even if the length of the probe is shortened as much as possible, the length of the test loop is still longer, and it will still cause greater insertion loss.

In the embodiment of the present application, even if the coupling capacitor C is added to the auxiliary circuit, or other circuit elements are added, the number and length of the probes 1 and 2 in FIG. 4 may not be affected. Therefore, the embodiment of the present application is beneficial to Further suppress the insertion loss of the test board. Moreover, compared with the current test boards provided with coupling capacitors, the embodiments of the present application can be applied to test boards with a simpler structure. Generally, the simpler the structure of the test board, the more conducive to improving the stability and reliability of the test results. Therefore, compared with the current solution of arranging components such as capacitors in the test board, the embodiments of the present application are beneficial to improve the stability and accuracy of the test results.

In addition, coupling capacitors are currently set in test boards. Since test boards will be used to test different types of functional circuits, coupling capacitors are generally not designed specifically according to the working scenarios of the functional circuits. For example, some functional circuits need to work in high-temperature scenarios, so CP testing is generally performed in high-temperature scenarios. If the coupling capacitor in the test board fails to work normally in a high temperature scenario, it will affect the accuracy of the function detection of the functional circuit.

In the embodiment of the present application, the coupling capacitor C in the auxiliary circuit can be designed according to the working requirements of the functional circuit during the chip design stage. For example, if the functional circuit works in a high temperature scene, in the chip design stage, the coupling capacitor C is specifically designed to improve the high temperature resistance characteristics of the coupling capacitor C.

Implementation mode three

As shown in Figure 7, it is a side view of the auxiliary circuit. In FIG. 7, the auxiliary circuit may include an amplifier OP. Among them, one input terminal of the amplifier is connected to the input terminal 2i of the auxiliary circuit, the other input terminal of the amplifier is grounded, and the output terminal of the amplifier is connected to the output terminal 2o of the auxiliary circuit.

The auxiliary circuit shown in Fig. 7 is used so that the auxiliary circuit can amplify the received test signal. For example, in Figure 8, the left side is the waveform diagram of the test signal received by the input terminal 2i of the auxiliary circuit. Among them, the abscissa represents time, and the ordinate represents signal strength.

In Figure 8, the right side is the waveform diagram of the test signal output by the output terminal 2o of the auxiliary circuit. Among them, the abscissa represents time, and the ordinate represents signal strength. Comparing the two waveform diagrams in FIG. 8, it can be seen that the auxiliary circuit provided by the embodiment of the present application can enhance the signal strength of the test signal. Especially in a small signal scenario, the strength of the test signal output by the functional circuit is relatively small. After being transmitted through the test loop, the strength of the test signal input to the functional circuit will be further reduced. Using the test loop provided by the embodiment of the present application can amplify the strength of the test signal, thereby helping to improve the accuracy of the function detection of the functional circuit.

It can be understood that the auxiliary circuit may also include other circuit elements that can optimize the test effect, which will not be listed in the embodiment of the present application.

In the embodiment of the present application, an auxiliary circuit is added to the wafer, and the subsequent processing process of the wafer will not be affected. E.g:

In a possible implementation, the auxiliary circuit can be arranged in the dicing channel of the wafer. Exemplarily, FIG. 9 is an image obtained after zooming in on the 4 test units in the rectangular dashed box in FIG. 3. As shown in Figure 9, in the row direction, adjacent test units are closely arranged. It can also be understood that the auxiliary circuits are spaced between adjacent functional circuits. In the column direction, adjacent test cells are spaced apart by cutting trenches. That is, part of the dicing channels in the wafer is provided with auxiliary circuits, and part of the dicing channels is not provided with auxiliary circuits.

Based on the arrangement of the test units shown in FIG. 9, in the subsequent wafer cutting process, cutting can be performed along the cutting channel. The obtained die includes the complete functional circuit and the remaining parts of the auxiliary circuit. In the subsequent packaging process, the remaining part of the auxiliary circuit can be packaged as a part of the packaging structure to obtain a finished chip.

Adopting the arrangement shown in FIG. 9 is beneficial to improving the utilization rate of the wafer, and can also be understood as helping to increase the total chip output of the wafer.

In another possible implementation manner, as shown in FIG. 10, it is an image obtained after zooming in on the four test units in the rectangular dashed line frame in FIG. 3. As shown in FIG. 10, in the row direction, adjacent test cells are spaced to cut trenches, and in the column direction, adjacent test cells are also spaced to cut trenches.

Based on the arrangement of the test units shown in FIG. 10, in the subsequent wafer cutting process, cutting can be performed along the cutting channel. The obtained die includes a complete functional circuit and auxiliary circuit. In the subsequent packaging process, the auxiliary circuit can be packaged as a part of the packaging structure to obtain a finished chip.

In yet another possible implementation manner, as shown in FIG. 11, it is an image obtained after zooming in on the four test units in the rectangular dashed box in FIG. 3. As shown in FIG. 11, in the row direction, adjacent test units are spaced apart with cutting channels, and inside the test units, there are also cutting channels spaced between the functional circuit and the auxiliary circuit. In the column direction, adjacent test cells are also spaced apart by cutting trenches.

Based on the arrangement of the test units shown in FIG. 11, in the subsequent wafer cutting process, cutting can be performed along the cutting channel. The obtained die includes a complete functional circuit, and does not include auxiliary circuits, so the obtained die can be equivalent to the current conventional die. In the subsequent packaging process, the functional circuit can be packaged to obtain a finished chip. The implementation shown in FIG. 11 is beneficial to eliminate the influence of the auxiliary circuit on the finished chip.

It should be understood that no matter whether the auxiliary circuit is located in the dicing channel of the wafer, it will not limit the relative position between the auxiliary circuit and the functional circuit.

For example, the auxiliary circuit can be located on either side of the functional circuit. As shown in (a) to (d) in Figure 12, the auxiliary circuit can be located on the right side of the functional circuit (a), on the left side of the functional circuit (b), or below the functional circuit (c) , Can also be located above the functional circuit (d).

For another example, the auxiliary circuit can also be located on both sides of the functional circuit. As shown in Figure 13 (a) to (f), the auxiliary circuit can be located above and below the functional circuit (a), can also be located on the left and right side of the functional circuit (b), or can be located on the functional circuit The left and top (c) of the function circuit can also be located on the right and above the functional circuit (d), it can also be located on the left and below the functional circuit (e), or it can be located on the right and below the functional circuit (f) .

For another example, the auxiliary circuit can also be located on three sides of the functional circuit. As shown in (a) to (d) in Figure 14, the auxiliary circuit can be located above, below, and on the left side (a) of the functional circuit, or above, on the left side, and on the right side (b) of the functional circuit. It can also be located above, below, and right of the functional circuit (c), or located below, left, and right of the functional circuit (d).

For another example, the auxiliary circuit can also be arranged around the functional circuit, as shown in FIG. 15.

In addition, the embodiments of the present application do not limit the relative size relationship between the functional circuit and the auxiliary circuit. Taking the auxiliary circuit arranged on the right side of the functional circuit as an example, as shown in (a) to (e) in Figure 16, the length of the auxiliary circuit can be greater than the length (d) of the right side of the functional circuit, or less than The length of the right side of the functional circuit (a) to (c), (e). In the case that the length of the auxiliary circuit is less than the length of the right side of the functional circuit, the auxiliary circuit can be located near the lower right side of the functional circuit (a), or located near the upper right side of the functional circuit (b), or Set (c) close to the middle of the right side of the functional circuit, or part of the area may be adjacent to the right side of the functional circuit, and part of the area exceeds the area (e) where the functional circuit is located, and so on. The embodiments of the present application will not enumerate them one by one.

Obviously, those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. In this way, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, then this application is also intended to include these modifications and variations.

Claims

A wafer, characterized by comprising: a plurality of test units;

The test unit includes a functional circuit and an auxiliary circuit, and there is an open circuit between the functional circuit and the auxiliary circuit;

The functional circuit includes a first input terminal and a first output terminal, and the auxiliary circuit includes a second input terminal and a second output terminal;

The functional circuit is used to output a test signal through the first output terminal;

The auxiliary circuit is configured to receive a test signal output by the functional circuit through the second input terminal, and feed back the test signal to the functional circuit through the second output terminal;

The functional circuit is further configured to receive the test signal through the first input terminal, and perform function detection according to the received test signal.
The wafer according to claim 1, wherein the auxiliary circuit includes a coupling capacitor, one end of the coupling capacitor is connected to the second input terminal, and the other end of the coupling capacitor is connected to the second output terminal.端连接。 End connection.
The wafer according to claim 1, wherein the auxiliary circuit includes an amplifier, an input end of the amplifier is connected to the second input end, and an output end of the amplifier is connected to the second output end .
The wafer according to claim 1, wherein the second input terminal and the second output terminal are short-circuited.
The wafer according to any one of claims 1 to 4, wherein the auxiliary circuit is located in a dicing channel of the wafer.
The wafer according to any one of claims 1 to 4, wherein in the wafer, a first cutting channel is spaced between adjacent test units.
7. The wafer according to claim 6, wherein in the test unit, a second dicing channel is spaced between the functional circuit and the auxiliary circuit.
The wafer according to any one of claims 1 to 7, wherein the functional circuit further comprises a communication terminal;

The functional circuit is further configured to output detection information through the communication terminal, and the detection information is used to indicate the result of the functional detection.
The wafer according to any one of claims 1 to 8, wherein the functional circuit further comprises a power supply terminal;

The functional circuit is also used to receive a power signal through the power supply terminal, and the power signal is used to supply power to the functional circuit.
A test board is characterized by comprising: a first connection end, a second connection end, a third connection end and a fourth connection end, wherein the first connection end is connected to the second connection end, so The third connecting end is connected to the fourth connecting end;

The first connection terminal is used to connect with the first output terminal of the functional circuit to receive the test signal output by the functional circuit;

The second connection terminal is used to connect with the second input terminal of the auxiliary circuit, and input the test signal output by the functional circuit into the auxiliary circuit;

The third connection terminal is used to connect with the second output terminal of the auxiliary circuit to receive the test signal output by the auxiliary circuit;

The fourth connection terminal is used to connect with the first input terminal of the functional circuit, and input the test signal output by the auxiliary circuit into the first input terminal.
The test board according to claim 10, wherein the test board further comprises a fifth connection terminal, and the fifth connection terminal is used to connect with the communication terminal of the functional circuit to receive the function The detection information output by the circuit, where the detection information is used to indicate the result of the function detection of the functional circuit.
The test board according to claim 10 or 11, wherein the test board further comprises a sixth connection terminal, and the sixth connection terminal is used to connect to the power supply terminal of the functional circuit and connect to the power supply terminal of the functional circuit. The functional circuit inputs a power signal, and the power signal is used to supply power to the functional circuit.