WO2021120207A1 - 显示装置、显示面板及其制造方法 - Google Patents

显示装置、显示面板及其制造方法 Download PDF

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Publication number
WO2021120207A1
WO2021120207A1 PCT/CN2019/127146 CN2019127146W WO2021120207A1 WO 2021120207 A1 WO2021120207 A1 WO 2021120207A1 CN 2019127146 W CN2019127146 W CN 2019127146W WO 2021120207 A1 WO2021120207 A1 WO 2021120207A1
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Prior art keywords
layer
electrode layer
substrate
auxiliary electrode
electrode
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Application number
PCT/CN2019/127146
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English (en)
French (fr)
Inventor
吴仲远
李永谦
袁志东
李蒙
袁粲
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980003149.6A priority Critical patent/CN113574678A/zh
Priority to EP19945466.1A priority patent/EP4080576A4/en
Priority to US17/040,606 priority patent/US11844255B2/en
Priority to PCT/CN2019/127146 priority patent/WO2021120207A1/zh
Publication of WO2021120207A1 publication Critical patent/WO2021120207A1/zh
Priority to US18/500,345 priority patent/US20240074266A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/828—Transparent cathodes, e.g. comprising thin metal layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/102—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising tin oxides, e.g. fluorine-doped SnO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/103—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising indium oxides, e.g. ITO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3026—Top emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display device, a display panel, and a manufacturing method of the display panel.
  • the cathode of the transparent material and the anode of the reflective material are usually used.
  • the transparent conductive material such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide)
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • the conductivity is low.
  • the conductivity is generally increased by adding auxiliary cathodes.
  • the auxiliary cathodes usually need to be connected to the pads in the peripheral area of the display panel for signal input.
  • the resistance of the lines connecting the auxiliary electrodes and the pads is usually large, resulting in a voltage drop. (IR Drop) is relatively high, and as the size of the display panel increases, the voltage drop will increase, which will affect signal transmission.
  • the purpose of the present disclosure is to provide a display device, a display panel, and a manufacturing method of the display panel.
  • a display panel including:
  • the substrate has a display area and a peripheral area surrounding the display area;
  • the pad is provided on one side of the substrate and located in the peripheral area;
  • An auxiliary electrode layer which is provided on the same side of the substrate as the pad, and the auxiliary electrode layer includes an auxiliary electrode located in the display area;
  • the data line layer is provided in the same layer as the auxiliary electrode layer, and has a peripheral line portion located in the peripheral area, and the projection of the peripheral line portion on the substrate is located on the pad and the auxiliary electrode layer Between projections on the substrate;
  • the first electrode layer is provided on the side of the auxiliary electrode layer away from the substrate, the first electrode layer has a first electrode and a bus, the first electrode is made of light-shielding metal material and is located in the display area, The bus line is located in the peripheral area and is connected to the pad and the auxiliary electrode layer at the same time;
  • the light-emitting layer is arranged on the side of the first electrode layer away from the substrate;
  • the second electrode layer is arranged on the side of the light-emitting layer away from the substrate and connected to the auxiliary electrode layer, and the second electrode layer is made of a transparent conductive material.
  • the first electrode layer further has an adapter portion, the adapter portion is located in the display area and connected to the auxiliary electrode layer, and the second electrode layer It is connected to the auxiliary electrode layer through the adapter portion.
  • the display panel further includes:
  • the thin film transistor layer is arranged on the side of the first electrode layer close to the substrate, and includes a source-drain layer having a source electrode and a drain electrode, the source-drain layer, the data line layer, and the auxiliary electrode Layers are different areas of the same film layer.
  • the thin film transistor layer further includes:
  • the first electrode layer is provided on a surface of the flat layer facing away from the substrate, and the connecting portion is connected to the auxiliary electrode through a first via hole passing through the flat layer.
  • the source and drain layer, the auxiliary electrode layer, the data line layer, and the pad are different regions of the same film layer, and the pad passes through all areas.
  • the second via hole of the flat layer is connected to the bus.
  • the auxiliary electrode layer further includes a connection part located in the peripheral area, each of the auxiliary electrodes is connected to the connection part, and the bus line passes through the flat layer
  • the third via hole is connected to the connecting portion.
  • the display panel further includes:
  • a pixel definition layer which is provided on the surface of the flat layer facing away from the substrate, and has a pixel area exposing the first electrode and a connecting hole exposing the transition part;
  • the light-emitting layer includes a light-emitting unit located in the pixel area; the second electrode layer covers the pixel defining layer and the light-emitting layer, and the second electrode is connected to the connecting portion through the connection hole .
  • a method of manufacturing a display panel including:
  • the substrate having a display area and a peripheral area surrounding the display area;
  • auxiliary electrode layer and a data line layer arranged in the same layer are formed on one side of the substrate, the auxiliary electrode layer and the pad are located on the same side of the substrate, and the auxiliary electrode layer includes The auxiliary electrode of the area; the data line layer has a peripheral line portion located in the peripheral area, and the projection of the peripheral line portion on the substrate is located on the pad and the auxiliary electrode layer on the substrate Between the projections on the
  • a first electrode layer made of a light-shielding metal material is formed on the side of the auxiliary electrode layer away from the substrate.
  • the first electrode layer has a first electrode and a bus line.
  • the first electrode is located in the display area.
  • the bus is located in the peripheral area and is connected to the pad and the auxiliary electrode layer at the same time;
  • a second electrode layer made of transparent conductive material is formed on the side of the light-emitting layer away from the substrate, and the second electrode layer is connected to the auxiliary electrode layer.
  • the first electrode layer further has an adapter portion, the adapter portion is located in the display area and connected to the auxiliary electrode layer, and the second electrode layer It is connected to the auxiliary electrode layer through the adapter portion.
  • the manufacturing method before forming the first electrode layer, the manufacturing method further includes:
  • the thin film transistor layer including a source and drain layer having a source electrode and a drain electrode;
  • the source drain layer, the data line layer, and the auxiliary electrode layer are formed through a single patterning process.
  • forming a thin film transistor layer on one side of the substrate includes:
  • the first electrode layer is provided on a surface of the flat layer facing away from the substrate, and the connecting portion is connected to the auxiliary electrode through a first via hole passing through the flat layer.
  • the source and drain layer, the auxiliary electrode layer, the data line layer and the pad are formed by a patterning process, and the pad is formed by passing through the flat
  • the second via of the layer is connected to the bus.
  • the auxiliary electrode layer further includes a connection part located in the peripheral area, each of the auxiliary electrodes is connected to the connection part, and the bus line passes through the flat layer
  • the third via hole is connected to the connecting portion.
  • the manufacturing method before forming the second electrode layer and after forming the flat layer, the manufacturing method further includes:
  • the pixel definition layer Forming a pixel definition layer on the surface of the flat layer facing away from the substrate, the pixel definition layer having a pixel area exposing the first electrode and a connecting hole exposing the transition part;
  • the light-emitting layer includes a light-emitting unit located in the pixel area;
  • the second electrode layer covers the pixel definition layer and the light-emitting layer, and the second electrode is connected to the connecting portion through the connection hole.
  • a display device including the display panel described in any one of the above.
  • FIG. 1 is a cross-sectional view of an embodiment of a display panel of the present disclosure.
  • FIG. 2 is a top view of an embodiment of the display panel of the present disclosure.
  • FIG. 3 is a flowchart of an embodiment of a method for manufacturing a display panel of the present disclosure.
  • FIG. 4 is a schematic diagram corresponding to step S170 in an embodiment of the manufacturing method of the present disclosure.
  • FIG. 5 is a schematic diagram corresponding to step S180 in an embodiment of the manufacturing method of the present disclosure.
  • Embodiments of the present disclosure provide a display panel, which is a top-emission OLED display panel.
  • the display panel includes a substrate 1, a pad 2, an auxiliary electrode layer 3, and a first electrode layer 4.
  • the light-emitting layer 5, the second electrode layer 6 and the data line layer 10 wherein:
  • the substrate 1 has a display area S1 and a peripheral area S2 surrounding the display area S1.
  • the pad 2 is provided on the side of the substrate 1 and located in the peripheral area S2.
  • the auxiliary electrode layer 3 and the pad 2 are provided on the same side of the substrate 1, and the auxiliary electrode layer 3 includes an auxiliary electrode 31 located in the display area S1.
  • the data line layer 10 is arranged in the same layer as the auxiliary electrode layer 3, and has a peripheral line portion 101 located in the peripheral area S2.
  • the projection of the peripheral line portion 101 on the substrate 1 is located on the pad 2 and the auxiliary electrode layer 3 is on the substrate 1. Between the projections.
  • the first electrode layer 4 is provided on the side of the auxiliary electrode layer 3 away from the substrate 1.
  • the first electrode layer 4 has a first electrode 41 and a bus line 43.
  • the first electrode 41 is located in the display area S1 and is made of a light-shielding metal material.
  • the bus line 43 is located The peripheral area S2 is connected to the pad 2 and connected to the auxiliary electrode layer 3.
  • the light-emitting layer 5 is provided on the side of the first electrode layer 4 facing away from the substrate 1.
  • the second electrode layer 6 is provided on the side of the light-emitting layer 5 away from the substrate 1 and connected to the auxiliary electrode layer 3, and the second electrode layer 6 is made of a transparent conductive material.
  • the second electrode layer 6 is connected to the auxiliary electrode layer 3, so that the resistance of the second electrode layer 6 is reduced through the auxiliary electrode layer 3.
  • the pad 2 of the peripheral area S2 and the auxiliary electrode layer 3 of the display area S1 can be connected through the first electrode layer 4, avoiding special connection lines, simplifying the structure and process, and because the first electrode layer 4 is located in the data
  • the line layer 10 is on the side away from the substrate 1, so that the bus 43 and the peripheral line portion 101 are arranged in different layers, so that the respective patterns of the bus line 43 and the peripheral line portion 101 have enough space, which is beneficial to reduce the wiring difficulty and avoid the bus line 43 and the periphery.
  • the line parts 101 interfere with each other.
  • the first electrode layer 4 is made of a light-shielding metal material, it has good electrical conductivity, thereby preventing excessive voltage drop and avoiding signal influence.
  • each layer of the display panel only schematically shows the positional relationship of each layer, so that those skilled in the art can understand the solutions and principles of the embodiments of the present disclosure, but it does not constitute a reference to each layer.
  • the substrate 1 has a display area S1 and a peripheral area S2 surrounding the display area S1, the display area S1 corresponds to the display area S1 of the display panel, and the peripheral area S2 corresponds to the peripheral area S2 of the display panel.
  • the material of the substrate 1 may be a hard material such as glass, or a flexible material such as PET (polyethylene terephthalate), which is not specifically limited here.
  • the pad 2 is provided on the side of the substrate 1 and is located in the above-mentioned peripheral area S2, that is, the orthographic projection of the pad 2 on the substrate 1 is located in the peripheral area S2, and is not limited to the pad 2 directly.
  • the pad 2 can be a metal or alloy material, such as aluminum, molybdenum or aluminum neodymium, and the specific structure of the pad 2 is not particularly limited here, and it can be connected to a power supply or other external circuits.
  • any structure is located in the display area S1 or the peripheral area S2 is not limited to that the structure is directly provided on the surface of the substrate 1, but also includes the orthographic projection of the structure on the substrate 1. Located in the display area S1 or the peripheral area S2.
  • the auxiliary electrode layer 3 may be a metal or alloy material, such as aluminum, molybdenum, or aluminum neodymium.
  • the auxiliary electrode layer 3 and the pad 2 are arranged on the same side of the substrate 1, and the two can be arranged in the same layer, that is, the auxiliary electrode layer 3 and the pad 2 are different areas of the same film layer.
  • the materials are the same.
  • the auxiliary electrode layer 3 and the pad 2 can also be arranged in different layers, that is, they belong to different layers.
  • the auxiliary electrode layer 3 includes auxiliary electrodes 31 located in the display area S1.
  • the shape and size of the auxiliary electrodes 31 are not particularly limited here. Further, the number of the auxiliary electrodes 31 may be multiple and distributed in an array.
  • the data line layer 10 can be arranged in the same layer as the auxiliary electrode layer 3 and the pad 2 and located on the same side of the substrate 1.
  • the data line layer 10 can transmit data signals required for displaying images.
  • the data line layer 10 has a peripheral line portion 101, and the peripheral line portion 101 is located in the peripheral area S2.
  • the data line layer 10 may also include a plurality of data lines (not shown in the figure). Each data line is located in the display area S1 and is connected to the peripheral line portion 101.
  • the peripheral line portion 101 can be used as a bus of the data line.
  • the projection of the peripheral line portion 101 on the substrate 1 is located between the projection of the pad 2 and the auxiliary electrode layer 3 on the substrate 1.
  • the first electrode layer 4, the light-emitting layer 5 and the second electrode layer 6 may constitute an OLED light-emitting structure, which may include a plurality of OLED light-emitting devices, wherein:
  • the first electrode layer 4 is provided on the side of the auxiliary electrode layer 3 away from the substrate 1.
  • the material of the first electrode layer 4 is a light-shielding metal material, such as copper, platinum, etc., which will not be listed here.
  • the first electrode layer 4 can extend from the display area S1 to the peripheral area S2. Specifically, the first electrode layer 4 has a first electrode 41 and a bus line 43. The first electrode 41 is located in the display area S1 and the bus line 43 is located in the peripheral area S2. And connect with pad 2. At the same time, the projections of the bus line 43 and the peripheral line portion 101 on the substrate 1 at least partially overlap, so that the bus line 43 can cross the peripheral line portion 101 and be connected to the auxiliary electrode layer 3 without interfering with the pattern of the peripheral line portion 101. , Easy to wire.
  • the first electrodes 41 may be arranged in an array, and each first electrode 41 may be used as an anode of an OLED light-emitting device.
  • the first electrode layer 4 may further include an adapter portion 42 which may be connected to the auxiliary electrode layer 3, and the adapter portion 42 may be located in the space between the first electrodes 41, and Each switching part 42 is connected to the bus 43 so as to input a signal to each switching part 42 at the same time.
  • the number of the connecting portions 42 and the auxiliary electrodes 31 are the same and there are multiple, each connecting portion 42 is connected to each auxiliary electrode 31 in a one-to-one correspondence, and the second electrode layer 6 can be connected to the auxiliary electrode 31 through the connecting portion 42
  • the connection of the electrode 31 is beneficial to shorten the extension path of the second electrode layer 6 to the auxiliary electrode 31 and avoid the situation that the extension path of the second electrode layer 6 to the auxiliary electrode 31 is too long, which is easy to be disconnected during manufacture.
  • the auxiliary electrode layer 3 may further include a connection portion 32, which is located in the peripheral area and is connected to the bus 43.
  • the connecting portion 42 can be connected to the connecting portion 32, so that the bus 43 and the transfer portion 42 are connected through the connecting portion 32 of the auxiliary electrode layer 3, so as to connect the bus 43 with the second electrode layer 6.
  • the transfer portion 42 can also be directly connected to the bus 43 in the first electrode layer 4, that is, the transfer portion 42 is connected by setting a wire for each transfer portion 42 To the bus 43 without passing through the auxiliary electrode 31 and the connecting portion 32 to transfer.
  • the wiring connecting the transfer portion 42 and the bus 43 needs to avoid the first electrode 41, that is, it is not connected to the first electrode 41.
  • the light-emitting layer 5 is provided on the side of the first electrode layer 4 away from the substrate 1. It can emit light under the action of the first electrode layer 4 and the second electrode layer 6, for example, the light-emitting layer 5 It may include a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer sequentially stacked on the first electrode layer 4. The specific light-emitting principle will not be described in detail here.
  • the light-emitting layer 5 may include a plurality of light-emitting units, and each light-emitting unit is located on each first electrode 41 in a one-to-one correspondence, so as to form a plurality of OLED light-emitting devices.
  • the second electrode layer 6 can be used as the cathode of the OLED display structure, and it can use transparent conductive materials, such as ITO and IZO.
  • the second electrode layer 6 is provided on the side of the light-emitting layer 5 away from the substrate 1, and each OLED light-emitting device can share the second electrode layer 6.
  • the second electrode layer 6 is connected to the transition portion 42. Since the transition portion 42 is connected to the auxiliary electrode 31, the second electrode layer 6 can be connected to the auxiliary electrode 31 to increase the first The conductivity of the two electrode layer 6.
  • the pad 2 can be connected to the second electrode layer 6 through the bus 43, the auxiliary electrode layer 3 and the transition portion 42, which is beneficial to improve the electrical conductivity and reduce the voltage drop of the line between the pad 2 and the second electrode layer 6.
  • the display panel of the embodiment of the present disclosure may further include a thin film transistor layer 7.
  • the thin film transistor layer 7 may be provided on the side of the first electrode layer 4 close to the substrate 1.
  • the thin film transistor layer 7 may It includes a plurality of thin film transistors, and each thin film transistor is connected to each first electrode 41 in a one-to-one correspondence, and is used to drive the above-mentioned OLED device to emit light.
  • the thin film transistor may adopt a top gate structure or a bottom gate structure, which is not particularly limited here.
  • the thin film transistor layer 7 may include an active layer 71 and a gate insulating layer laminated in a direction away from the substrate 1. 72.
  • the source-drain layer includes a source 75 and a drain 76 connected to both ends of the active layer 71, and the drain 76 can be connected to the first electrode 41.
  • the source and drain layer, the auxiliary electrode layer 3 and the data line layer 10 can be formed by a patterning process, so that the source and drain layer, the data line layer 10 and the auxiliary electrode layer 3 are different regions of the same film layer, that is, the same Layers are arranged, and the three are arranged at intervals, that is, the film layer is not a continuous film layer.
  • the data line of the data line layer 10 may be connected to the source electrode 75 of the thin film transistor layer 7 in order to transmit data signals.
  • the above-mentioned thin film transistor layer 7 may further include a flat layer 77 covering the source and drain layers and the dielectric layer 74, and may also cover the auxiliary electrode layer 3.
  • the first electrode layer 4 is disposed on the surface of the flat layer 77 away from the substrate 1, and each of the transfer portions 42 can be connected to an opposite auxiliary electrode 31 through a first via 100 passing through the flat layer 77.
  • the above-mentioned pad 2 can also be arranged in the same layer as the data line layer 10, the source drain layer and the auxiliary electrode layer 3.
  • the four are different areas of the same film layer, and the pad 2 can pass through
  • the second via 200 of the flat layer 77 is connected to the bus 43.
  • the pad 2 can also be arranged in the same layer as the gate 73 of the thin film transistor layer 7.
  • the display panel of the embodiment of the present disclosure may further include a pixel definition layer 8.
  • the pixel definition layer 8 is made of a light-shielding material and is provided on the surface of the flat layer 77 facing away from the substrate 1 and has an exposed first
  • the pixel area of the electrode 41 and the connection hole 400 exposing the adapter portion 42 are provided in each pixel area in a one-to-one correspondence with the light-emitting units of the light-emitting layer 5 to form multiple sub-pixels. All sub-pixels can be divided into multiple pixels. Each pixel includes a plurality of sub-pixels.
  • a plurality of OLED light-emitting devices can be defined by the pixel definition layer 8.
  • the second electrode layer 6 covers the pixel definition layer 8 and the light-emitting layer 5, and the second electrode layer 6 is connected to the adapter portion 42 through the connection hole 400, and thus is connected to the auxiliary electrode 31.
  • the bus 43 may be connected to the connection portion 32 of the auxiliary electrode layer 3 through the third via hole 300 passing through the flat layer 77, and the connection portion 32 is connected to each auxiliary electrode. 31 Connected.
  • FIG. 2 is a partial schematic diagram of the display panel, which shows the distribution mode of each auxiliary electrode 31, each sub-pixel 500, and bus 43.
  • the auxiliary electrode 31 and the sub-pixel 500 are all arranged in an array in the display area S1, namely Distributed along the row direction and the column direction; the bus 43 is located in the peripheral area S2, and each column of auxiliary electrodes 31 and each column of sub-pixels 500 are alternately arranged along the row direction.
  • the peripheral area S2 is also provided with a driving circuit board 600 which is connected to the sub-pixel 500 and is used to drive the sub-pixel 500 to emit light.
  • the specific connection mode and circuit structure are not specifically limited here.
  • FIG. 2 only schematically shows The distribution method does not constitute a limitation on the actual structure.
  • the display panel of the embodiment of the present disclosure may further include a buffer layer 9, which may be provided between the thin film transistor layer 7 and the substrate 1.
  • the material of the buffer layer 9 may be an insulating material such as silicon nitride.
  • the embodiments of the present disclosure provide a method for manufacturing a display panel.
  • the display panel can be the display panel of the above-mentioned embodiments, and the structure of the display panel will not be repeated here.
  • the manufacturing method includes step S110-step S160, wherein:
  • Step S110 providing a substrate, the substrate having a display area and a peripheral area surrounding the display area.
  • Step S120 forming a pad located in the peripheral area on one side of the substrate.
  • Step S130 forming an auxiliary electrode layer and a data line layer in the same layer on one side of the substrate, the auxiliary electrode layer, the data line layer and the pad are located on the same side of the substrate, and
  • the auxiliary electrode layer includes an auxiliary electrode located in the display area;
  • the data line layer has a peripheral line portion located in the peripheral area, and the projection of the peripheral line portion on the substrate is located between the pad and the
  • the auxiliary electrode layer is between the projections on the substrate.
  • Step S140 forming a first electrode layer of light-shielding metal material on the side of the auxiliary electrode layer away from the substrate, the first electrode layer having a first electrode and a bus, and the first electrode is located in the display area
  • the bus line is located in the peripheral area and is connected to the pad and the auxiliary electrode layer at the same time.
  • Step S150 forming a light-emitting layer on the side of the first electrode layer away from the substrate.
  • Step S160 forming a second electrode layer of transparent conductive material on the side of the light-emitting layer away from the substrate, and the second electrode layer is connected to the auxiliary electrode layer.
  • the pad 2 in the peripheral area and the auxiliary electrode 31 in the display area can be connected through the first electrode layer 4, avoiding special connection lines and simplifying the structure and process.
  • the first electrode layer 4 is a light-shielding metal material, it has good electrical conductivity, thereby preventing excessive voltage drop and avoiding signal influence.
  • FIG. 1 As shown in FIG. 1, FIG. 4, and FIG. 5, the steps of the manufacturing method of the embodiment of the present disclosure are described below:
  • step S110 the structure of the substrate 1 can refer to the substrate 1 in the above display panel implementation mode, which will not be described in detail here.
  • the structure of the bonding pad 2 can refer to the bonding pad 2 in the above display panel embodiment, which will not be described in detail here.
  • the bonding pad 2 may be a metal or alloy material, such as aluminum, molybdenum, or aluminum neodymium. It can be formed by patterning processes such as photolithography and printing, and the process is not specifically limited here.
  • the structure of the auxiliary electrode layer 3 can refer to the auxiliary electrode layer 3 in the above display panel implementation, which will not be described in detail here. It can also be formed by patterning processes such as photolithography and printing, and will not be described here. The craftsmanship is specially limited. Further, the pad 2, the data line layer 10, and the auxiliary electrode layer 3 can be formed by a patterning process, so that the three are arranged in the same layer to simplify the process, that is, the step S120 and the step S130 can be combined into the same step.
  • the structure of the first electrode layer 4 can refer to the first electrode layer 4 in the above display panel implementation, which will not be described in detail here. It can be formed by patterning processes such as photolithography and printing. The craftsmanship is specially limited.
  • the structure of the light-emitting layer 5 can refer to the light-emitting layer 5 in the above display panel embodiment, which will not be described in detail here. It can be formed by a patterning process such as vapor deposition, and the process is not specifically limited herein.
  • the structure of the second electrode layer 6 can refer to the second electrode layer 6 in the above display panel embodiment, which will not be described in detail here. It can be formed by patterning processes such as photolithography and printing. The craftsmanship is specially limited.
  • the manufacturing method of the embodiment of the present disclosure further includes:
  • Step S170 forming a thin film transistor layer on one side of the substrate, the thin film transistor layer including a source and drain layer having a source electrode and a drain electrode;
  • the source drain layer and the auxiliary electrode layer are formed by a patterning process once.
  • the structure of the thin film transistor layer 7 may refer to the thin film transistor 7 in the above display panel embodiment.
  • the thin film transistor layer 7 may include a thin film transistor layer 7 away from the substrate 1.
  • the active layer 71, the gate insulating layer 72, the gate 73, the dielectric layer 74 and the source-drain layer are sequentially stacked in the direction.
  • the source-drain layer includes a source 75 and a drain 76 connected to both ends of the active layer 71.
  • the source-drain layer, the data line layer 10 and the auxiliary electrode layer 3 can be formed by one patterning process, so that the source-drain layer, the data line layer 10 and the auxiliary electrode layer 3 are in different regions of the same film layer, that is, they are arranged in the same layer.
  • the above-mentioned pad 2 can also be provided in the same layer as the source and drain layer, the data line layer 10 and the auxiliary electrode layer 3. The four are different areas of the same film layer, and the pad 2 can pass through the second layer of the flat layer 77.
  • the via is connected to the bus 43.
  • the pad 2 can also be arranged in the same layer as the gate 73 of the thin film transistor layer 7 and formed by one patterning process.
  • a thin film transistor layer is formed on one side of the substrate, that is, step S170, including steps S1710 and S1720, wherein:
  • Step S1710 forming a source-drain layer having a source electrode and a drain electrode on one side of the substrate.
  • Step S1720 forming a flat layer covering the source drain layer and the auxiliary electrode layer.
  • the first electrode layer is provided on a surface of the flat layer facing away from the substrate, and the connecting portion is connected to the auxiliary electrode through a first via hole passing through the flat layer.
  • step S170 may further include sequentially forming an active layer 71, a gate insulating layer 72, a gate 73, and a dielectric layer on the side of the substrate 1.
  • the layer 74, the source and drain layers may be formed on the surface of the dielectric layer 74 away from the substrate.
  • the flat layer 77 covers the source and drain layers and the dielectric layer 74, and may also cover the auxiliary electrode layer 3.
  • the first electrode layer 4 is disposed on the surface of the flat layer 77 facing away from the substrate 1, and each of the transfer portions 42 can be connected to an opposite auxiliary electrode 31 through a first via hole passing through the flat layer 77.
  • a part of the auxiliary electrode layer 3 extends to the peripheral area, and at least a part of the area extending to the peripheral area is directly opposite to the bus line 43 and is connected through the third via hole passing through the flat layer 77.
  • a buffer layer 9 can also be formed on the substrate 1, and the thin film transistor layer 7 can be formed on the surface of the buffer layer 9 away from the substrate 1.
  • the manufacturing method of the present disclosure may further include:
  • Step S180 forming a pixel definition layer on the surface of the flat layer facing away from the substrate, the pixel definition layer having a pixel area exposing the first electrode and a connecting hole exposing the transition part;
  • the light-emitting layer includes a light-emitting unit located in the pixel area;
  • the second electrode layer covers the pixel definition layer and the light-emitting layer, and the second electrode is connected to the connecting portion through the connection hole.
  • the pixel definition layer 8 is made of light-shielding material, and is provided on the surface of the flat layer 77 away from the substrate 1, and has a pixel area exposing the first electrode 41 and a connection that exposes the transfer portion 42
  • the holes 400 and the light-emitting units of the light-emitting layer 5 are provided in each pixel area in a one-to-one correspondence, that is, a plurality of OLED light-emitting devices can be defined by the pixel definition layer 8.
  • the second electrode layer 6 covers the pixel definition layer 8 and the light-emitting layer 5, and the second electrode layer 6 is connected to the adapter portion 42 through the connection hole 400, and thus is connected to the auxiliary electrode 31.
  • the embodiments of the present disclosure also provide a display device, including the display panel of any of the foregoing embodiments. Since the display device adopts the display panel of the above embodiment, the two can solve the same technical problems and have the same beneficial effects.
  • the display device of the embodiment of the present disclosure can be used in electronic devices such as mobile phones, tablet computers, or electronic paper.

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Abstract

一种显示装置、显示面板及其制造方法，该显示面板包括衬底（1）、焊盘（2）、辅助电极层（3）、数据线层（10）、第一电极层（4）、发光层（5）和第二电极层（6）。衬底（1）具有显示区（S1）和围绕显示区（S1）的外围区（S2）。焊盘（2）设于衬底（1）一侧且位于外围区（S2）。辅助电极层（3）与焊盘（2）设于衬底（1）的同一侧，辅助电极层（3）包括位于显示区（S1）的辅助电极（31）；数据线层（10）与辅助电极层（3）同层设置且具有位于外围区（S2）的外围线部（101），外围线部（101）位于焊盘（2）和辅助电极层（3）在衬底（1）上的投影之间；第一电极层（4）设于辅助电极层（3）背离衬底（1）的一侧且具有第一电极（41）和总线（43），第一电极（41）位于显示区（S1），总线（43）位于外围区（S2）并与焊盘（2）和辅助电极层（3）连接；发光层（5）设于第一电极层（4）背离衬底（1）的一侧；第二电极层（6）设于发光层（5）背离衬底（1）的一侧且与辅助电极层（3）连接。

Description

显示装置、显示面板及其制造方法 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示装置、显示面板及显示面板的制造方法。
背景技术
在顶发射OLED显示面板中，通常采用透明材料的阴极和反射材料的阳极，若选用ITO(氧化铟锡)、IZO(氧化铟锌)等透明导电材料作为阴极，虽然其透过率高，但电导率较低。目前，一般是通过增加辅助阴极的方式增加电导率，辅助阴极通常需要与显示面板外围区的焊盘连接，以便输入信号，但是连接辅助电极和焊盘的线路的电阻通常较大，使得压降(IR Drop)较高，且随着显示面板尺寸的增大，压降也会增大，导致信号传输受到影响。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种显示装置、显示面板及显示面板的制造方法。
根据本公开的一个方面，提供一种显示面板，所述显示面板包括：
衬底，具有显示区和围绕显示区的外围区；
焊盘，设于所述衬底一侧，且位于所述外围区；
辅助电极层，与所述焊盘设于所述衬底的同一侧，所述辅助电极层包括位于所述显示区的辅助电极；
数据线层，与所述辅助电极层同层设置，且具有位于所述外围区的外围线部，所述外围线部在所述衬底上的投影位于所述焊盘和所述辅助电极层在所述衬底上的投影之间；
第一电极层，设于所述辅助电极层背离所述衬底的一侧，所述第一电极层具有第一电极和总线，所述第一电极为遮光金属材料且位于所述显示区，所述总线位于所述外围区并同时与所述焊盘和所述辅助电极层连接；
发光层，设于所述第一电极层背离所述衬底的一侧；
第二电极层，设于所述发光层背离所述衬底的一侧，且与所述辅助电极层连接，所述第二电极层为透明导电材料。
在本公开的一种示例性实施例中，所述第一电极层还具有转接部，所述转接部位于所述显示区，且与所述辅助电极层连接，所述第二电极层通过所述转接部与所述辅助电极层连接。
在本公开的一种示例性实施例中，所述显示面板还包括：
薄膜晶体管层，设于所述第一电极层靠近所述衬底的一侧，且包括具有源极和漏极的源漏层，所述源漏层、所述数据线层和所述辅助电极层为同一膜层的不同区域。
在本公开的一种示例性实施例中，所述薄膜晶体管层还包括：
平坦层，覆盖所述源漏层和所述辅助电极层；
所述第一电极层设于所述平坦层背离所述衬底的表面，所述转接部通过穿过所述平坦层的第一过孔与所述辅助电极连接。
在本公开的一种示例性实施例中，所述源漏层、所述辅助电极层、所述数据线层和所述焊盘为同一膜层的不同区域，所述焊盘通过穿过所述平坦层的第二过孔与所述总线连接。
在本公开的一种示例性实施例中，所述辅助电极层还包括位于所述外围区的连接部，各所述辅助电极与所述连接部连接，所述总线通过穿过所述平坦层的第三过孔与所述连接部连接。
在本公开的一种示例性实施例中，所述显示面板还包括：
像素定义层，设于所述平坦层背离所述衬底的表面，且具有露出所述第一电极的像素区和露出所述转接部的连接孔；
所述发光层包括位于所述像素区内的发光单元；所述第二电极层覆盖所述像素定义层和所述发光层，所述第二电极通过所述连接孔与所述转接部连接。
根据本公开的一个方面，提供一种显示面板的制造方法，包括：
提供一衬底，所述衬底具有显示区和围绕显示区的外围区；
在所述衬底一侧形成位于所述外围区的焊盘；
在所述衬底的一侧形成同层设置的辅助电极层和数据线层，所述辅助电极层与所述焊盘位于所述衬底的同一侧，所述辅助电极层包括位于所述显示区的辅助电极；所述数据线层具有位于所述外围区的外围线部，所述外围线部在所述衬底上的投影位于所述焊盘和所述辅助电极层在所述衬底上的投影之间；
在所述辅助电极层背离所述衬底的一侧形成遮光金属材料的第一电极层，所述第一电极层具有第一电极和总线，所述第一电极位于所述显示区，所述总线位于所述外围区且同时与所述焊盘和所述辅助电极层连接；
在所述第一电极层背离所述衬底的一侧形成发光层；
在所述发光层背离所述衬底的一侧形成透明导电材料的第二电极层，所述第二电极层与所述辅助电极层连接。
在本公开的一种示例性实施例中，所述第一电极层还具有转接部，所述转接部位于所述显示区，且与所述辅助电极层连接，所述第二电极层通过所述转接部与所述辅助电极层连接。
在本公开的一种示例性实施例中，在形成所述第一电极层之前，所述制造方法还包括：
在所述衬底一侧形成薄膜晶体管层，所述薄膜晶体管层包括具有源极和漏极的源漏层；
所述源漏层、所述数据线层和所述辅助电极层通过一次构图工艺形成。
在本公开的一种示例性实施例中，在所述衬底一侧形成薄膜晶体管层，包括：
在所述衬底一侧形成具有源极和漏极的源漏层；
形成覆盖所述源漏层和所述辅助电极层的平坦层；
所述第一电极层设于所述平坦层背离所述衬底的表面，所述转接部通过穿过所述平坦层的第一过孔与所述辅助电极连接。
在本公开的一种示例性实施例中，所述源漏层、所述辅助电极层、所述数据线层和所述焊盘通过一次构图工艺形成，所述焊盘通过穿过所述平坦层的第二过孔与所述总线连接。
在本公开的一种示例性实施例中，所述辅助电极层还包括位于所述外围区的连接部，各所述辅助电极与所述连接部连接，所述总线通过穿过所述平坦层的第三过孔与所述连接部连接。
在本公开的一种示例性实施例中，在形成所述第二电极层之前，形成所述平坦层之后，所述制造方法还包括：
在所述平坦层背离所述衬底的表面形成像素定义层，所述像素定义层具有露出所述第一电极的像素区和露出所述转接部的连接孔；
所述发光层包括位于所述像素区内的发光单元；
所述第二电极层覆盖所述像素定义层和所述发光层，所述第二电极通过所述连接孔与所述转接部连接。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开显示面板一实施方式的截面图。
图2为本公开显示面板一实施方式的俯视图。
图3为本公开显示面板的制造方法一实施方式的流程图。
图4为对应本公开制造方法一实施方式中步骤S170的示意图。
图5为对应本公开制造方法一实施方式中步骤S180的示意图。
附图标记说明：
1、衬底；2、焊盘；3、辅助电极层；31、辅助电极；32、连接部；4、第一电极层；41、第一电极；42、转接部；43、总线；5、发光层；6、第二电极层；7、薄膜晶体管层；71、有源层；72、栅绝缘层；73、栅极；74、介电层；75、源极；76、漏极；77、平坦层；8、像素定义层；9、缓冲层；10、数据线层；101、外围线部；100、第一过孔；200、第二过孔；300、第三过孔；400、连接孔；500、子像素；600、驱动电路。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是 指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开实施方式提供了一种显示面板，该显示面板为顶发射的OLED显示面板，如图1所示，该显示面板包括衬底1、焊盘2、辅助电极层3、第一电极层4、发光层5、第二电极层6和数据线层10，其中：
衬底1具有显示区S1和围绕显示区S1的外围区S2。焊盘2设于衬底1一侧，且位于外围区S2。辅助电极层3与焊盘2设于衬底1的同一侧，辅助电极层3包括位于显示区S1的辅助电极31。
数据线层10与辅助电极层3同层设置，且具有位于外围区S2的外围线部101，外围线部101在衬底1上的投影位于焊盘2和辅助电极层3在衬底1上的投影之间。
第一电极层4设于辅助电极层3背离衬底1的一侧，第一电极层4具有第一电极41和总线43，第一电极41位于显示区S1且为遮光金属材料，总线43位于外围区S2并与焊盘2连接，且与辅助电极层3连接。
发光层5设于第一电极层4背离衬底1的一侧。第二电极层6设于发光层5背离衬底1的一侧，且与辅助电极层3连接，第二电极层6为透明导电材料。
本公开实施方式的显示面板，第二电极层6通过与辅助电极层3连接，从而通过辅助电极层3降低第二电极层6的电阻。同时，可通过第一电极层4将外围区S2的焊盘2和显示区S1的辅助电极层3连接起来，避免专门设置连接线路，可简化结构和工艺，且由于第一电极层4位于数据线层10背离衬底1的一侧，使得总线43与外围线部101异层设置，使总线43与外围线部101各自的图案有足够的空间，有利于降低布线难度，避免总线43和外围线部101互相干涉。此外，由于第一电极层4为遮光金属材料，具有良好的电导率，从而防止压降过大，避免信号受到影响。
需要说明的是，附图中，显示面板的各层，仅示意性示出了各层的位置关系，以使本领域技术人员明了本公开实施方式的方案和原理，但并不构成对各层具体图案的限定。
下面对本公开实施方式显示面板的各部分进行详细说明：
如图1所示，衬底1具有显示区S1和围绕显示区S1的外围区S2，该显示区S1对应于显示面板的显示区S1，该外围区S2对应于该显示面板的外围区S2。衬底1的材料可以是玻璃等硬质材料，也可以是PET(聚对苯二甲酸乙二醇酯)等柔性材料，在此不做特殊限定。
如图1所示，焊盘2设于衬底1一侧，且位于上述的外围区S2，即焊盘2在衬底1上的正投影位于外围区S2，并不限定于焊盘2直接设置在衬底1的表面。焊盘2可为金属或合金材料，例如铝、钼或铝钕等，且焊盘2的具体结构在此不做特殊限定，其可与 电源或其它外接电路连接。
需要说明的是，本公开实施方式中，任一结构位于显示区S1或外围区S2的含义，并不限于该结构直接设于衬底1的表面，也包括该结构在衬底1的正投影位于显示区S1或外围区S2。
如图1所示，辅助电极层3可为金属或合金材料，例如铝、钼或铝钕等。同时，辅助电极层3与焊盘2设于衬底1的同一侧，且二者可以同层设置，即辅助电极层3与焊盘2为同一膜层的不同区域，此时，二者的材料相同。当然，辅助电极层3与焊盘2也可异层设置，即分别属于不同的膜层。
辅助电极层3包括位于显示区S1的辅助电极31，辅助电极31的形状和尺寸在此不做特殊限定，进一步的，辅助电极31的数量可为多个，且阵列分布。
数据线层10可与辅助电极层3和焊盘2同层设置，且位于衬底1的同一侧，通过数据线层10，可传输显示图像所需的数据信号。数据线层10具有外围线部101，且外围线部101位于外围区S2。数据线层10还可包括多个数据线(图中未示出)，各数据线位于显示区S1，且均与外围线部101连接，外围线部101可作为数据线的总线。同时，外围线部101在衬底1上的投影位于焊盘2和辅助电极层3在衬底1上的投影之间。
如图1所示，第一电极层4、发光层5和第二电极层6可构成OLED发光结构，其可包括多个OLED发光器件，其中：
第一电极层4设于辅助电极层3背离衬底1的一侧，第一电极层4的材料为遮光金属材料，例如铜、铂等，在此不再一一列举。
第一电极层4可由显示区S1延伸至外围区S2，具体而言，第一电极层4具有第一电极41和总线43，其中，第一电极41位于显示区S1，总线43位于外围区S2并与焊盘2连接。同时，总线43和外围线部101二者在衬底1的投影至少部分重合，使得总线43可跨过外围线部101而与辅助电极层3连接，而与外围线部101的图案互不干涉，便于布线。
进一步的，如图1所示，第一电极41可阵列分布，每个第一电极41可作为一个OLED发光器件的阳极。在本公开的一些实施方式中，第一电极层4还可包括转接部42，转接部42可与辅助电极层3连接，转接部42可位于第一电极41之间的空间，且各转接部42均与总线43连接，以便同时向各转接部42输入信号。举例而言，转接部42和辅助电极31的数量相同且均为多个，各转接部42一一对应地与各辅助电极31连接，第二电极层6可通过转接部42与辅助电极31连接，有利于缩短第二电极层6向辅助电极31延伸的路径，避免出现因第二电极层6向辅助电极31延伸的路径过长，而在制造时容易断开的情况。
为了将每个转接部42与总线43连接，在本公开的一些实施方式中，辅助电极层3还可包括连接部32，连接部32位于外围区，且与总线43连接，同时，各转接部42可与连接部32连接，从而通过辅助电极层3的连接部32将总线43和转接部42连接起来，以便将总线43与第二电极层6连接。
当然，在本公开的一些实施方式中，也可将转接部42在第一电极层4内直接与总线43连接，即，通过为每个转接部42设置走线将转接部42连接至总线43，而不用通过辅助电极31和连接部32来中转。但连接转接部42和总线43的走线需要避让第一电极41，即与第一电极41不连接。
如图1所示，发光层5设于第一电极层4背离衬底1的一侧，其可在第一电极层4和第二电极层6的作用下发光，举例而言，发光层5可包括依次层叠于第一电极层4上的空穴注入层、空穴传输层、有机发光层、电子传输层和电子注入层，具体发光原理，在此不再详述。发光层5可包括多个发光单元，各发光单元一一对应的位于各第一电极41上，以便形成多个OLED发光器件。
如图1所示，第二电极层6可作为OLED显示结构的阴极，其可采用透明导电材料，例如ITO和IZO等。第二电极层6设于发光层5背离衬底1的一侧，各OLED发光器件可共用第二电极层6。在本公开的一些实施方式中，第二电极层6与转接部42连接，由于转接部42与辅助电极31连接，从而可使第二电极层6与辅助电极31连接，以增大第二电极层6的电导率。同时，焊盘2可通过总线43、辅助电极层3和转接部42与第二电极层6连接，有利于提高电导率，降低焊盘2和第二电极层6之间线路的压降。
进一步的，如图1所示，本公开实施方式的显示面板还可包括薄膜晶体管层7，薄膜晶体管层7可设于第一电极层4靠近衬底1的一侧，该薄膜晶体管层7可包括多个薄膜晶体管，各薄膜晶体管一一对应的与各第一电极41连接，用于驱动上述的OLED器件发光。
薄膜晶体管可采用顶栅结构或底栅结构，在此不做特殊限定，以顶栅结构为例，薄膜晶体管层7可包括向远离衬底1的方向依次层叠的有源层71、栅绝缘层72、栅极73、介电层74和源漏层，其中，源漏层包括连接于有源层71两端的源极75和漏极76，漏极76可与第一电极41连接。为了简化结构和工艺，源漏层、辅助电极层3和数据线层10可通过一次构图工艺形成，使得源漏层、数据线层10和辅助电极层3为同一膜层的不同区域，即同层设置，且三者间隔设置，即该膜层并非连续不断的膜层。此外，数据线层10的数据线可与薄膜晶体管层7的源极75连接，以便传输数据信号。
上述的薄膜晶体管层7还可包括平坦层77，平坦层77覆盖源漏层和介电层74，还可覆盖辅助电极层3。第一电极层4设于平坦层77背离衬底1的表面，每个转接部42 可通过一穿过平坦层77的第一过孔100与正对的一辅助电极31连接。
此外，如图1所示，上述的焊盘2也可与数据线层10、源漏层和辅助电极层3同层设置，四者为同一膜层的不同区域，焊盘2可通过穿过平坦层77的第二过孔200与总线43连接。当然，焊盘2也可与薄膜晶体管层7的栅极73同层设置。
进一步的，如图1所示，本公开实施方式的显示面板还可包括像素定义层8，像素定义层8为遮光材质，且设于平坦层77背离衬底1的表面，且具有露出第一电极41的像素区和露出转接部42的连接孔400，发光层5的各发光单元一一对应的设于各像素区，以形成多个子像素，所有子像素可划分为多个像素，每个像素包括多个子像素。
举例而言，通过像素定义层8可限定出多个OLED发光器件。第二电极层6覆盖像素定义层8和发光层5，第二电极层6通过连接孔400与转接部42连接，从而与辅助电极31连接。此外，如图1所示，在本公开的一些实施方式中，总线43可通过穿过平坦层77的第三过孔300与辅助电极层3的连接部32连接，连接部32与各辅助电极31连接。
如图2所示，图2为显示面板的局部示意图，其示出了各辅助电极31、各子像素500以及总线43的分布方式，辅助电极31和子像素500均阵列分布于显示区S1，即沿行方向和列方向分布；总线43位于外围区S2，各列辅助电极31与各列子像素500沿行方向交替排列。此外，外围区S2还设有驱动电路板600，其与子像素500连接，用于驱动子像素500发光，具体连接方式及线路结构在此不做特殊限定，图2中仅示意性示出了分布方式，并不构成对实际结构的限定。
需要说明的是，本文中的行方向及和列方向仅表示相交的两个不同方向，虽然在各附图中当前的视角它们分别为横向和纵向，但并不代表在实际的产品中，行方向必定为横向，而列方向必定为纵向。
如图1所示，本公开实施方式的显示面板还可包括缓冲层9，其可设于薄膜晶体管层7和衬底1之间，缓冲层9的材料可以是氮化硅等绝缘材料。
本公开实施方式提供一种显示面板的制造方法，该显示面板为可为上述实施方式的显示面板，其结构在此不再赘述。如图3所示，该制造方法包括步骤S110-步骤S160，其中：
步骤S110、提供一衬底，所述衬底具有显示区和围绕显示区的外围区。
步骤S120、在所述衬底一侧形成位于所述外围区的焊盘。
步骤S130、在所述衬底的一侧形成同层设置辅助电极层和数据线层，所述辅助电极层、所述数据线层与所述焊盘位于所述衬底的同一侧，所述辅助电极层包括位于所述显示区的辅助电极；所述数据线层具有位于所述外围区的外围线部，所述外围线部在所述 衬底上的投影位于所述焊盘和所述辅助电极层在所述衬底上的投影之间。
步骤S140、在所述辅助电极层背离所述衬底的一侧形成遮光金属材料的第一电极层，所述第一电极层具有第一电极和总线，所述第一电极位于所述显示区，所述总线位于所述外围区且同时与所述焊盘和所述辅助电极层连接。
步骤S150、在所述第一电极层背离所述衬底的一侧形成发光层。
步骤S160、在所述发光层背离所述衬底的一侧形成透明导电材料的第二电极层，所述第二电极层与所述辅助电极层连接。
本公开实施方式制造方法，可通过第一电极层4将外围区的焊盘2和显示区的辅助电极31连接起来，避免专门设置连接线路，可简化结构和工艺。同时，由于第一电极层4为遮光金属材料，具有良好的电导率，从而防止压降过大，避免信号受到影响。
如图1、图4和图5所示，下面对本公开实施方式制造方法的各步骤进行说明：
在步骤S110中，衬底1的结构可参考上文显示面板实施方式中的衬底1，在此不再详述。
在步骤S120中，焊盘2的结构可参考上文显示面板实施方式中的焊盘2，在此不再详述，焊盘2可为金属或合金材料，例如铝、钼或铝钕等，其可通过光刻、印刷等构图工艺形成，在此不对其工艺做特殊限定。
在步骤S130中，辅助电极层3的结构可参考上文显示面板实施方式中的辅助电极层3，在此不再详述，其也可通过光刻、印刷等构图工艺形成，在此不对其工艺做特殊限定。进一步的，焊盘2、数据线层10和辅助电极层3可通过一次构图工艺形成，使三者同层设置，以简化工艺，即步骤S120和步骤S130可合并为同一步骤。
在步骤S140中，第一电极层4的结构可参考上文显示面板实施方式中的第一电极层4，在此不再详述，其可通过光刻、印刷等构图工艺形成，在此不对其工艺做特殊限定。
在步骤S150中，发光层5的结构可参考上文显示面板实施方式中的发光层5，在此不再详述，其可通过蒸镀等构图工艺形成，在此不对其工艺做特殊限定。
在步骤S160中，第二电极层6的结构可参考上文显示面板实施方式中的第二电极层6，在此不再详述，其可通过光刻、印刷等构图工艺形成，在此不对其工艺做特殊限定。
进一步的，在形成第一电极层4之前，即步骤S140之前，本公开实施方式的制造方法还包括：
步骤S170、在所述衬底一侧形成薄膜晶体管层，所述薄膜晶体管层包括具有源极和漏极的源漏层；
所述源漏层和所述辅助电极层通过一次构图工艺形成。
在步骤S170中，如图4所示，薄膜晶体管层7的结构可参考上文显示面板实施方式 中的薄膜晶体管7，以顶栅结构为例，薄膜晶体管层7可包括向远离衬底1的方向依次层叠的有源层71、栅绝缘层72、栅极73、介电层74和源漏层，源漏层包括连接于有源层71两端的源极75和漏极76。
可通过一次构图工艺形成源漏层、数据线层10和辅助电极层3，使得为源漏层、数据线层10和辅助电极层3为同一膜层的不同区域，即同层设置。此外，上述的焊盘2也可与源漏层、数据线层10和辅助电极层3同层设置，四者为同一膜层的不同区域，焊盘2可通过穿过平坦层77的第二过孔与总线43连接。
当然，焊盘2也可与薄膜晶体管层7的栅极73同层设置，且通过一次构图工艺形成。
在一实施方式中，在所述衬底一侧形成薄膜晶体管层，即步骤S170，包括步骤S1710和步骤S1720，其中：
步骤S1710、在所述衬底一侧形成具有源极和漏极的源漏层。
步骤S1720、形成覆盖所述源漏层和所述辅助电极层的平坦层。
所述第一电极层设于所述平坦层背离所述衬底的表面，所述转接部通过穿过所述平坦层的第一过孔与所述辅助电极连接。
如图4所示，以顶栅结构薄膜晶体管为例，在步骤S1710之前，步骤S170还可包括，在衬底1一侧依次形成有源层71、栅绝缘层72、栅极73、介电层74，源漏层可形成于介电层74背离衬底的表面。
在步骤S1720中，如图4所示，平坦层77覆盖源漏层和介电层74，还可覆盖辅助电极层3。第一电极层4设于平坦层77背离衬底1的表面，每个转接部42可通过一穿过平坦层77的第一过孔与正对的一辅助电极31连接。
在一实施方式中，辅助电极层3的部分区域延伸至外围区，且延伸至外围区的至少部分区域与总线43正对，且通过穿过所述平坦层77的第三过孔连接。
此外，在形成薄膜晶体管层7之前，还可在衬底1上形成缓冲层9，薄膜晶体管层7可形成于缓冲层9背离衬底1的表面。
更进一步的，在形成平坦层77之后，形成第二电极层6之前，即在步骤S1720之后，步骤S160之前，本公开的制造方法还可包括：
步骤S180、在所述平坦层背离所述衬底的表面形成像素定义层，所述像素定义层具有露出所述第一电极的像素区和露出所述转接部的连接孔；
所述发光层包括位于所述像素区内的发光单元；
所述第二电极层覆盖所述像素定义层和所述发光层，所述第二电极通过所述连接孔与所述转接部连接。
在步骤S180中，如图5所示，像素定义层8为遮光材质，且设于平坦层77背离衬 底1的表面，且具有露出第一电极41的像素区和露出转接部42的连接孔400，发光层5的各发光单元一一对应的设于各像素区，也就是说，通过像素定义层8可限定出多个OLED发光器件。第二电极层6覆盖像素定义层8和发光层5，第二电极层6通过连接孔400与转接部42连接，从而与辅助电极31连接。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开实施方式还提供一种显示装置，包括上述任意实施方式的显示面板。由于该显示装置采利用了上述实施方式的显示面板，因而二者能解决相同的技术问题，且具有相同的有益效果。本公开实施方式的显示装置可用于手机、平板电脑或电子纸等电子设备。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (15)

  1. 一种显示面板，其中，所述显示面板包括：
    衬底，具有显示区和围绕显示区的外围区；
    焊盘，设于所述衬底一侧，且位于所述外围区；
    辅助电极层，与所述焊盘设于所述衬底的同一侧，所述辅助电极层包括位于所述显示区的辅助电极；
    数据线层，与所述辅助电极层同层设置，且具有位于所述外围区的外围线部，所述外围线部在所述衬底上的投影位于所述焊盘和所述辅助电极层在所述衬底上的投影之间；
    第一电极层，设于所述辅助电极层背离所述衬底的一侧，所述第一电极层具有第一电极和总线，所述第一电极为遮光金属材料且位于所述显示区，所述总线位于所述外围区并同时与所述焊盘和所述辅助电极层连接；
    发光层，设于所述第一电极层背离所述衬底的一侧；
    第二电极层，设于所述发光层背离所述衬底的一侧，且与所述辅助电极层连接，所述第二电极层为透明导电材料。
  2. 根据权利要求1所述的显示面板，其中，所述第一电极层还具有转接部，所述转接部位于所述显示区，且与所述辅助电极层连接，所述第二电极层通过所述转接部与所述辅助电极层连接。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板还包括：
    薄膜晶体管层，设于所述第一电极层靠近所述衬底的一侧，且包括具有源极和漏极的源漏层，所述源漏层、所述数据线层和所述辅助电极层为同一膜层的不同区域。
  4. 根据权利要求3所述的显示面板，其中，所述薄膜晶体管层还包括：
    平坦层，覆盖所述源漏层和所述辅助电极层；
    所述第一电极层设于所述平坦层背离所述衬底的表面，所述转接部通过穿过所述平坦层的第一过孔与所述辅助电极连接。
  5. 根据权利要求4所述的显示面板，其中，所述源漏层、所述辅助电极层、所述数据线层和所述焊盘为同一膜层的不同区域，所述焊盘通过穿过所述平坦层的第二过孔与所述总线连接。
  6. 根据权利要求4所述的显示面板，其中，所述辅助电极层还包括位于所述外围区的连接部，各所述辅助电极与所述连接部连接，所述总线通过穿过所述平坦层的第三过孔与所述连接部连接。
  7. 根据权利要求4所述的显示面板，其中，所述显示面板还包括：
    像素定义层，设于所述平坦层背离所述衬底的表面，且具有露出所述第一电极的像素区和露出所述转接部的连接孔；
    所述发光层包括位于所述像素区内的发光单元；所述第二电极层覆盖所述像素定义层和所述发光层，所述第二电极通过所述连接孔与所述转接部连接。
  8. 一种显示面板的制造方法，其中，包括：
    提供一衬底，所述衬底具有显示区和围绕显示区的外围区；
    在所述衬底一侧形成位于所述外围区的焊盘；
    在所述衬底的一侧形成同层设置的辅助电极层和数据线层，所述辅助电极层、所述数据线层与所述焊盘位于所述衬底的同一侧，所述辅助电极层包括位于所述显示区的辅助电极；所述数据线层具有位于所述外围区的外围线部，所述外围线部在所述衬底上的投影位于所述焊盘和所述辅助电极层在所述衬底上的投影之间；
    在所述辅助电极层背离所述衬底的一侧形成遮光金属材料的第一电极层，所述第一电极层具有第一电极和总线，所述第一电极位于所述显示区，所述总线位于所述外围区且同时与所述焊盘和所述辅助电极层连接；
    在所述第一电极层背离所述衬底的一侧形成发光层；
    在所述发光层背离所述衬底的一侧形成透明导电材料的第二电极层，所述第二电极层与所述辅助电极层连接。
  9. 根据权利要求8所述的制造方法，其中，所述第一电极层还具有转接部，所述转接部位于所述显示区，且与所述辅助电极层连接，所述第二电极层通过所述转接部与所述辅助电极层连接。
  10. 根据权利要求9所述的制造方法，其中，在形成所述第一电极层之前，所述制造方法还包括：
    在所述衬底一侧形成薄膜晶体管层，所述薄膜晶体管层包括具有源极和漏极的源漏层；
    所述源漏层、所述数据线层和所述辅助电极层通过一次构图工艺形成。
  11. 根据权利要求9所述的制造方法，其中，在所述衬底一侧形成薄膜晶体管层，包括：
    在所述衬底一侧形成具有源极和漏极的源漏层；
    形成覆盖所述源漏层和所述辅助电极层的平坦层；
    所述第一电极层设于所述平坦层背离所述衬底的表面，所述转接部通过穿过 所述平坦层的第一过孔与所述辅助电极连接。
  12. 根据权利要求11所述的制造方法，其中，所述源漏层、所述辅助电极层、所述数据线层和所述焊盘通过一次构图工艺形成，所述焊盘通过穿过所述平坦层的第二过孔与所述总线连接。
  13. 根据权利要求11所述的制造方法，其中，所述辅助电极层还包括位于所述外围区的连接部，各所述辅助电极与所述连接部连接，所述总线通过穿过所述平坦层的第三过孔与所述连接部连接。
  14. 根据权利要求11所述的制造方法，其中，在形成所述第二电极层之前，形成所述平坦层之后，所述制造方法还包括：
    在所述平坦层背离所述衬底的表面形成像素定义层，所述像素定义层具有露出所述第一电极的像素区和露出所述转接部的连接孔；
    所述发光层包括位于所述像素区内的发光单元；
    所述第二电极层覆盖所述像素定义层和所述发光层，所述第二电极通过所述连接孔与所述转接部连接。
  15. 一种显示装置，其中，包括权利要求1-7任一项所述的显示面板。
PCT/CN2019/127146 2019-12-20 2019-12-20 显示装置、显示面板及其制造方法 WO2021120207A1 (zh)

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