WO2021109443A1 - 芯片封装模块及封装方法及具有该模块的电子装置 - Google Patents

芯片封装模块及封装方法及具有该模块的电子装置 Download PDF

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Publication number
WO2021109443A1
WO2021109443A1 PCT/CN2020/088704 CN2020088704W WO2021109443A1 WO 2021109443 A1 WO2021109443 A1 WO 2021109443A1 CN 2020088704 W CN2020088704 W CN 2020088704W WO 2021109443 A1 WO2021109443 A1 WO 2021109443A1
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Prior art keywords
chip
packaging
substrate
module according
upper side
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PCT/CN2020/088704
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English (en)
French (fr)
Inventor
庞慰
王云峰
杨清瑞
张孟伦
Original Assignee
天津大学
诺思(天津)微系统有限责任公司
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Priority to EP20896027.8A priority Critical patent/EP4089917A4/en
Publication of WO2021109443A1 publication Critical patent/WO2021109443A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H03H9/1014—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0504—Holders; Supports for bulk acoustic wave devices
    • H03H9/0514—Holders; Supports for bulk acoustic wave devices consisting of mounting pads or bumps
    • H03H9/0523—Holders; Supports for bulk acoustic wave devices consisting of mounting pads or bumps for flip-chip mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H2003/0071—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks of bulk acoustic wave and surface acoustic wave elements in the same process

Definitions

  • the invention relates to the field of semiconductors, in particular to a chip packaging structure, a chip packaging method, and an electronic device with a chip packaging module.
  • FBAR Film Bulk Acoustic Resonator
  • BAW Bulk Acoustic Wave Resonator
  • film bulk acoustic resonators have specific packaging requirements in different application environments.
  • wafer-level packaging is more common, which not only increases the size of the device, but also has a large number of packaging steps, which increases the packaging cost.
  • wireless communication equipment has gradually developed in the direction of portable, multi-functional, high-performance, and low-cost, prompting electronic components to also move towards miniaturization, high integration, high reliability, and high yield.
  • RF filters are no exception.
  • FIG. 9 is a schematic diagram of a chip packaging structure in the prior art.
  • Figure 9
  • a substrate which can be ceramic or organic materials, and includes three parts: a bottom substrate 101, a conductive layer 103, and an oil filter layer 105;
  • chip bonding structure which can be MBM, solder balls, copper pillars, etc.
  • an unpackaged filter chip which can be an FBAR chip, a SAW chip or a BAW chip;
  • 17 is the adhesive layer between the chips and the outer protective layer
  • 19 is the adhesive layer between the chips and the outer protective layer.
  • the outer protective layer 17 and the substrate 10 are vacuum-pressed, and the contact point is poor in sealing and adhesion.
  • moisture easily penetrates the filter oil layer 105 and damages the cavity structure required by the filter chip 15. Affect device performance.
  • a chip packaging module including:
  • the packaging substrate is opposite to the chip and a cavity is formed between the two;
  • the first packaging layer encapsulates the chip on the packaging substrate
  • the second encapsulation layer is arranged to cover the outside of the first encapsulation layer
  • the first encapsulation layer includes an extension that extends laterally outward along the encapsulation substrate, the lower side of the extension covers the upper side of the encapsulation substrate, and the end of the second encapsulation layer and the upper side of the extension are formed Surface contact.
  • the embodiment of the present invention also provides a chip packaging method, including the steps:
  • a first encapsulation layer is provided so that the first encapsulation layer encapsulates the chip on the encapsulation substrate.
  • the first encapsulation layer has an extension part extending laterally outward along the encapsulation substrate, and the lower side of the extension part covers the Upper side
  • a second encapsulation layer covering the first encapsulation layer is provided, and the end of the second encapsulation layer is in surface contact with the upper side of the extension portion.
  • the embodiment of the present invention also relates to an electronic device including the above-mentioned chip package module or the chip package module manufactured according to the above-mentioned packaging method.
  • Fig. 1 is a schematic cross-sectional view of a chip package module according to an exemplary embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view of a chip package module according to an exemplary embodiment of the present invention
  • FIG. 2A is a partial enlarged schematic view of the contact portion between the first packaging layer and the substrate in FIG. 2;
  • FIG. 3 is a schematic cross-sectional view of a chip package module according to an exemplary embodiment of the present invention.
  • 3A is a partially enlarged schematic diagram of the contact portion between the first packaging layer and the substrate in FIG. 3;
  • FIG. 4 is a schematic top view of a packaging structure of a chip packaging module according to an exemplary embodiment of the present invention.
  • FIG. 4A is an enlarged schematic diagram of part A in FIG. 4;
  • FIG. 5 is a schematic top view of a package structure of a chip package module according to an exemplary embodiment of the present invention.
  • FIG. 5A is an enlarged schematic diagram of part A in FIG. 5;
  • FIG. 5B is an enlarged schematic diagram of part A in FIG. 5;
  • Fig. 6 is a schematic top view of a package structure of a chip package module according to an exemplary embodiment of the present invention.
  • Fig. 6A is an enlarged schematic diagram of part A in Fig. 6;
  • FIG. 7A-7D exemplarily show a process diagram of a chip packaging method according to an embodiment of the present invention
  • FIG. 8 is a schematic cross-sectional view of a chip package module according to an exemplary embodiment of the present invention, which shows two chips;
  • FIG. 9 is a schematic diagram of a chip packaging structure in the prior art.
  • Fig. 1 is a schematic cross-sectional view of a chip package module according to an exemplary embodiment of the present invention.
  • Figure 1 is a schematic cross-sectional view of a chip package module according to an exemplary embodiment of the present invention.
  • Figure 1 :
  • the substrate 10 is a substrate, which may be ceramic or organic material.
  • the substrate 10 includes three parts: a bottom substrate 101, a conductive layer 103, and an oil filter layer 105;
  • chip bonding structure which can be MBM, solder balls, copper pillars, etc.
  • an unpackaged filter chip which can be an FBAR chip, a SAW chip or a BAW chip;
  • 17 is the first packaging layer, that is, the adhesive layer between the chips and the peripheral protection layer;
  • the second encapsulation layer which may also be an adhesive layer between chips and a peripheral protection layer.
  • the first encapsulation layer 17 includes an extension portion extending laterally outward along the package substrate (in FIG. 1 is the lateral portion in contact with the substrate), and the lower side of the extension portion covers the encapsulation substrate. Upper side. As shown in FIG. 1, the end of the second encapsulation layer 19 is in surface contact with the upper side of the extension.
  • the lateral direction refers to the direction parallel to the surface of the chip or the substrate. More specifically, in the drawings, it may correspond to the left and right directions in the drawings.
  • the extension portion increases the contact area between the first packaging layer and the substrate, the adhesion between the first packaging layer and the substrate is increased, and the sealing effect is improved.
  • Fig. 2 is a schematic cross-sectional view of a chip package module according to an exemplary embodiment of the present invention
  • Fig. 2A is a partially enlarged schematic diagram of the contact portion between the first package layer and the substrate in Fig. 2.
  • the substrate is provided with a recess 107 at the position where the extension part contacts, which is beneficial to increase the adhesion between the first packaging layer and the substrate and improve the sealing effect.
  • the height of the cavity is H1, 10 ⁇ m ⁇ H1 ⁇ 150 ⁇ m
  • the depth of the depression is H2, 0.05 ⁇ m ⁇ H2 ⁇ 10 ⁇ m
  • the range of the width W3 of the depression is: W3 ⁇ H2.
  • the first packaging layer 17 includes a vertical portion covering the side surface of the semiconductor chip, and the vertical portion is connected to the extension portion;
  • the angle ⁇ formed between the surface facing the cavity and the upper side of the substrate is: 60 ⁇ 90.
  • the sidewall roughness that is, the roughness of the vertical surface AA' in FIG. 2A is
  • the first width W1 of the first encapsulation layer is smaller than the second width W2 of the second encapsulation layer, and the first width W1 depends on the first encapsulation layer
  • the range of the thickness can be 0 ⁇ W1 ⁇ 50 ⁇ m, the second width W2 ⁇ 15 ⁇ m, and the upper limit of the second width depends on the difference between the package size and the chip size.
  • the specific value of the width of W2 is determined based on the process capability and the difference between the package size and the chip size.
  • FIG. 3 is a schematic cross-sectional view of a chip package module according to an exemplary embodiment of the present invention.
  • the part of the substrate in contact with the extension part is provided with protrusions.
  • FIG. 3A is a partially enlarged schematic diagram of the contact portion between the first packaging layer and the substrate.
  • the size of the protrusion and the depression shown in Figure 2 can be similar, for example, the height of the cavity is H1, 10 ⁇ m ⁇ H1 ⁇ 150 ⁇ m, the height of the protrusion is H2, 0.05 ⁇ m ⁇ H2 ⁇ 10 ⁇ m; the width of the protrusion is W3 The range of is: W3 ⁇ H2.
  • the height of the bumps may be the same as the thickness of the metal layer on the surface of the substrate.
  • FIG. 4 is a schematic top view of the packaging structure of a chip package module according to an exemplary embodiment of the present invention
  • FIG. 4A is an enlarged schematic view of part A in FIG. 4.
  • the structure provided on the substrate for increasing the seal is ring-shaped.
  • the depressions 107 are strip-shaped depressions, and the number of depressions can be multiple.
  • FIG. 5 is a schematic top view of a package structure of a chip package module according to an exemplary embodiment of the present invention
  • FIG. 5A is an enlarged schematic view of part A in FIG. 5
  • FIG. 5B is another embodiment of part A in FIG. 5
  • Magnified schematic diagram of As shown in FIG. 5, the structure provided on the substrate for increasing the seal is ring-shaped (the ring is formed by the intermittent structure).
  • the recess 107 has a long rectangular shape.
  • the discretely distributed rectangular recesses 107 are staggered, so that, in the lateral direction, it is beneficial to enhance the resistance of the gas to pass through.
  • FIG. 6 is a schematic top view of the packaging structure of a chip package module according to an exemplary embodiment of the present invention
  • FIG. 6A is an enlarged schematic view of part A in FIG. 6.
  • the depression 107 is a circular depression.
  • Figures 2-6A show the seal reinforcement formed by protrusions and/or recesses.
  • the sealing reinforcement part is not limited to this.
  • the sealing reinforcement part may include a rough surface structure provided on the upper side of the packaging substrate 10.
  • FIGS. 7A-7D exemplarily show a process diagram of a chip packaging method according to an embodiment of the present invention.
  • the chip packaging method will be exemplarily described below with reference to FIGS. 7A-7D.
  • the oil filter layer 105 of the substrate 10 is etched to expose the required conductive portions 103, protrusions 107, and the subsequent portions of the substrate 101 that need to be pressed and contacted.
  • a plurality of unpackaged filter chips 15 are welded upside down to the substrate 10.
  • a vacuum compression method is used for sealing, after forming the first sealing layer 17 and the second sealing layer 19, an air cavity is provided for the filter chip 15 and then laser cutting (along the vertical dotted line).
  • the multiple chips are spaced apart from each other in the lateral direction, and the width of the extension between two adjacent chips is greater than or equal to 30 ⁇ m and twice as large as Or more than twice the first width.
  • the double is an approximate number, for example, within the range of 1.5 times-2.5 times.
  • a packaged chip is obtained after cutting.
  • FIG. 8 is a schematic cross-sectional view of a chip package module according to an exemplary embodiment of the present invention, which shows two chips.
  • the filter chip includes at least one of a bulk acoustic wave filter or a surface acoustic wave filter.
  • a chip packaging module including:
  • the packaging substrate is opposite to the chip and a cavity is formed between the two;
  • the first packaging layer encapsulates the chip on the packaging substrate
  • the second encapsulation layer is arranged to cover the outside of the first encapsulation layer
  • the first encapsulation layer includes an extension that extends laterally outward along the encapsulation substrate, the lower side of the extension covers the upper side of the encapsulation substrate, and the end of the second encapsulation layer and the upper side of the extension are formed Surface contact.
  • At least a portion of the packaging substrate covered by the extension portion is provided with a sealing reinforcement portion.
  • the sealing reinforcement part includes a concave structure or a convex structure provided on the upper side of the packaging substrate.
  • the recessed structure or the raised structure includes a strip-shaped ring-shaped or rectangular array or a circular array structure formed by recesses or protrusions.
  • the height of the cavity is H1, 10 ⁇ m ⁇ H1 ⁇ 150 ⁇ m;
  • the depth of the concave structure or the height of the convex structure is H2, and 0.05 ⁇ m ⁇ H2 ⁇ 10 ⁇ m;
  • the range of the width W3 of the concave structure or the convex structure is: W3 ⁇ H2.
  • the sealing reinforcement part includes a rough surface structure provided on the upper side of the packaging substrate.
  • the sealing reinforcement part is arranged in a ring shape.
  • the sealing reinforcement part includes an intermittent structure arranged in an annular shape as a whole.
  • the first width W1 of the first packaging layer is smaller than the second width W2 of the second packaging layer.
  • the range of the first width W1 is: 0 ⁇ W1 ⁇ 50 ⁇ m, and the range of the second width W2 is: W2 ⁇ 15 ⁇ m.
  • the first packaging layer includes a vertical portion covering a side surface of the semiconductor chip, and the vertical portion is connected to the extension portion;
  • the angle ⁇ formed between the surface of the vertical portion facing the cavity and the upper side of the substrate is: 60 ⁇ 90.
  • the chip includes at least a filter chip, and the filter chip includes at least one of a bulk acoustic wave filter or a surface acoustic wave filter.
  • the chip is a chipset composed of a plurality of chips arranged in the same layer with each other and spaced apart in a lateral direction;
  • the plurality of chips are spaced apart from each other in the lateral direction by the first packaging layer;
  • the extension part of the first encapsulation layer is arranged on the outside of the chipset.
  • the chipset includes a plurality of filter chips, or the chipset includes a filter chip and an active chip.
  • a chip packaging method including the steps:
  • a first packaging layer is provided so that the first packaging layer encapsulates the chip on the packaging substrate, and the first packaging layer has an extension portion extending laterally outward along the packaging substrate, and the lower side of the extension portion covers the surface of the packaging substrate.
  • a second encapsulation layer covering the first encapsulation layer is provided, and the end of the second encapsulation layer is in surface contact with the upper side of the extension portion.
  • the step of "providing a package substrate” also includes providing a sealing reinforcement part at a predetermined position of the package substrate, the predetermined position being covered by the extension part.
  • the step of "welding the chip upside down to the upper side of the package substrate” includes upside down welding a plurality of chips to the upper side of the package substrate, wherein the plurality of chips are spaced apart from each other in the lateral direction;
  • the first encapsulation layer has a first width W1.
  • the width of the extension between two adjacent chips is not less than 30 ⁇ m, and is twice or more than twice the first width W1 .
  • the step of "welding the chip upside down to the upper side of the package substrate” includes upside down welding a plurality of filter chips to the upper side of the package substrate, or welding the filter chip and the active chip upside down to the upper side of the package substrate.
  • An electronic device comprising the chip packaging module according to any one of 1-14 or the chip packaging module manufactured according to the chip packaging method according to any one of 15-19.

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  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

一种芯片封装模块及其封装方法以及具有该芯片封装模块的电子装置，所述芯片封装模块包括：芯片(15)；封装基板(10)，与所述芯片(15)对置且两者之间形成空腔；第一封装层(17)，将所述芯片(15)封装在封装基板(10)上；第二封装层(19)，覆盖所述第一封装层(17)的外侧设置，其中：第一封装层(17)包括沿封装基板(10)横向向外延伸的延伸部，所述延伸部的下侧覆盖所述封装基板(10)的上侧，所述第二封装层(19)的端部与所述延伸部的上侧形成面接触。

Description

芯片封装模块及封装方法及具有该模块的电子装置 技术领域
本发明涉及半导体领域，尤其涉及一种芯片封装结构，一种芯片封装方法，以及一种具有芯片封装模块的电子装置。
背景技术
电子器件作为电子设备的基本元素，已经被广泛应用，其应用范围包括移动电话、汽车、家电设备等。此外，未来即将改变世界的人工智能、物联网、5G通讯等技术仍然需要依靠电子器件作为基础。
薄膜体声波谐振器(Film Bulk Acoustic Resonator，简称FBAR，又称为体声波谐振器，也称BAW)作为压电器件的重要成员正在通信领域发挥着重要作用，特别是FBAR滤波器在射频滤波器领域市场占有份额越来越大，FBAR具有尺寸小、谐振频率高、品质因数高、功率容量大、滚降效应好等优良特性，其滤波器正在逐步取代传统的声表面波(SAW)滤波器和陶瓷滤波器，在无线通信射频领域发挥巨大作用，其高灵敏度的优势也能应用到生物、物理、医学等传感领域。
通常，薄膜体声波谐振器在不同的应用环境下，具有特定的封装要求。目前，较为常见的为晶圆级封装，此种封装不但会增加器件的尺寸，而且具有大量的封装步骤，增加了封装成本。近年来随着无线移动通讯技术的快速发展，无线通讯设备逐渐向着便携式、多功能、高性能、低成本方向发展，促使电子元器件也朝着小型化、高集成、高可靠性、高良率的方向发展，射频滤波器也不例外。
近年来，在满足封装需求的基础上，工艺简单、成本低廉的封装技术快速发展，然而，封装结构的气密性及可靠性仍待提高。
图9为现有技术中的芯片封装结构的示意图。在图9中：
10为基板，可以为陶瓷和有机材质等，包含三部分：底部基板101，导电层103，滤油层105；
11为芯片焊接结构，可以为MBM，焊球，铜柱等；
13为焊盘(pad)；
15为未封装的滤波芯片，可以为FBAR芯片，SAW芯片或者BAW芯片；
17为芯片间的粘接层及外围保护层；
19为芯片间的粘接层及外围保护层。
在图P所示的结构中，外围保护层17和基板10真空压合，接触处密封性及粘附性差，此外，湿气易穿过滤油层105，破坏滤波芯片15所需的空腔结构，影响器件性能。
发明内容
为解决或缓解现有技术中的存在的技术问题的至少一个方面，提出本发明。
根据本发明的实施例的一个方面，提出了一种芯片封装模块，包括：
芯片；
封装基板，与所述芯片对置且两者之间形成空腔；
第一封装层，将所述芯片封装在封装基板上；
第二封装层，覆盖所述第一封装层的外侧设置，
其中：
第一封装层包括沿封装基板横向向外延伸的延伸部，所述延伸部的下侧覆盖所述封装基板的上侧，所述第二封装层的端部与所述延伸部的上侧形成面接触。
本发明的实施例还提出了一种芯片封装方法，包括步骤：
提供封装基板；
提供未封装芯片；
将芯片倒置焊接到封装基板上侧；
提供第一封装层，使得第一封装层将芯片封装到封装基板上，所述第一封装层具有沿封装基板横向向外延伸的延伸部，所述延伸部的下侧覆盖所述封装基板的上侧；
提供覆盖第一封装层的第二封装层，所述第二封装层的端部与所述延伸部的上侧形成面接触。
本发明的实施例也涉及一种电子装置，包括上述的芯片封装模块或根 据上述封装方法制造的芯片封装模块。
附图说明
以下描述与附图可以更好地帮助理解本发明所公布的各种实施例中的这些和其他特点、优点，图中相同的附图标记始终表示相同的部件，其中：
图1为根据本发明的一个示例性实施例的芯片封装模块的示意性截面图；
图2为根据本发明的一个示例性实施例的芯片封装模块的示意性截面图；
图2A为图2中的第一封装层与基板之间的接触部分的局部放大示意图；
图3为根据本发明的一个示例性实施例的芯片封装模块的示意性截面图；
图3A为图3中的第一封装层与基板之间的接触部分的局部放大示意图；
图4为根据本发明的一个示例性实施例的芯片封装模块的封装结构的俯视示意图；
图4A为图4中的A部分的放大示意图；
图5为根据本发明的一个示例性实施例的芯片封装模块的封装结构的俯视示意图；
图5A为图5中的A部分的放大示意图；
图5B为图5中的A部分的放大示意图；
图6为根据本发明的一个示例性实施例的芯片封装模块的封装结构的俯视示意图；
图6A为图6中的A部分的放大示意图；
图7A-7D示例性示出了根据本发明的一个实施例的芯片封装方法的过程图；
图8为根据本发明的一个示例性实施例的芯片封装模块的示意性截面图，其示出了两颗芯片；
图9为现有技术中的芯片封装结构的示意图。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解为对本发明的一种限制。
图1为根据本发明的一个示例性实施例的芯片封装模块的示意性截面图。在图1中：
10为基板，可以为陶瓷和有机材质等，在一个示例性实施例中，基板10包含三部分：底部基板101，导电层103，滤油层105；
11为芯片焊接结构，可以为MBM，焊球，铜柱等；
13为焊盘；
15为未封装的滤波芯片，可以为FBAR芯片，SAW芯片或者BAW芯片；
17为第一封装层，即芯片间的粘接层及外围保护层；
19为第二封装层，也可以为芯片间的粘接层及外围保护层。
如图1所示，第一封装层17包括沿封装基板横向向外延伸的延伸部(在图1中即为与基板接触的横向部分)，所述延伸部的下侧覆盖所述封装基板的上侧。如图1所示，所述第二封装层19的端部与所述延伸部的上侧形成面接触。
在本发明中，以基板在下而芯片在上的方式，确定“上”与“下”。在本发明中，横向即为平行于芯片或者基板的表面的方向，更具体的，在附图中，可以对应于图中的左右方向。
在图1的结构中，由于延伸部增加了第一封装层与基板的接触面积，从而增加了第一封装层与基板的粘附性，提高了密封效果。
图2为根据本发明的一个示例性实施例的芯片封装模块的示意性截面图，图2A为图2中的第一封装层与基板之间的接触部分的局部放大示 意图。如图2所示，基板在于延伸部接触的位置设置有凹陷107，这有利于增加第一封装层与基板的粘附性，提高了密封效果。
如图2所示，空腔的高度为H1，10μm≤H1≤150μm，凹陷的深度为H2，0.05μm≤H2≤10μm；所述凹陷的宽度W3的范围为：W3≥H2。
在进一步的实施例中，如图2和2A所示，第一封装层17包括覆盖半导体芯片的侧面的竖向部，所述竖向部与所述延伸部连接；且所述竖向部的面对所述空腔的面与基底的上侧之间形成的角度θ为：60<θ<90。如图2A所示，在一个实施例中，侧壁粗糙度即图2A中AA’这个竖向面的粗糙度为
Figure PCTCN2020088704-appb-000001
在本发明的一个进一步的实施例中，如图2所示，第一封装层的第一宽度W1小于所述第二封装层的第二宽度W2，且第一宽度W1取决于第一封装层的厚度，其范围可为0<W1≤50μm，第二宽度W2≥15μm，第二宽度的上限取决于封装尺寸与芯片尺寸的差值。基于工艺能力，以及封装尺寸和芯片尺寸的差值确定W2的宽度的具体值。
图3为根据本发明的一个示例性实施例的芯片封装模块的示意性截面图。其中基板的与延伸部接触的部分设置有凸起。图3A为第一封装层与基板之间的接触部分的局部放大示意图。凸起与图2中所示的凹陷的尺寸可以相似，例如空腔的高度为H1，10μm≤H1≤150μm，凸起的高度为H2，0.05μm≤H2≤10μm；所述凸起的宽度W3的范围为：W3≥H2。此外，在设置凸起的情况下，凸起的高度可以与基板表层的金属层的厚度相同。
图4为根据本发明的一个示例性实施例的芯片封装模块的封装结构的俯视示意图，图4A为图4中的A部分的放大示意图。如图4所示，基板上设置的用于增加密封的结构为环形。如图4A所示，凹陷107为条形凹陷，且凹陷的条数可以有多条。
图5为根据本发明的一个示例性实施例的芯片封装模块的封装结构的俯视示意图，图5A为图5中的A部分的放大示意图，图5B为图5中的A部分的另一个实施例的放大示意图。如图5所示，基板上设置的用于增加密封的结构为环形(由断续结构形成环形)。如图5A所示，凹陷107具有长条矩形的形状。在图5B中，离散分布的矩形凹陷107错开布置， 如此，在横向方向上，有利于增强气体通过的阻力。
图6为根据本发明的一个示例性实施例的芯片封装模块的封装结构的俯视示意图，图6A为图6中的A部分的放大示意图。在图6和6A中，凹陷107为圆形凹陷。
附图2-6A示出了凸起和/或凹陷等形成的密封加强部。但是密封加强部不限于此，例如密封加强部可以包括设置在封装基板10的上侧的粗糙面结构。
图7A-7D示例性示出了根据本发明的一个实施例的芯片封装方法的过程图。下面参照图7A-7D示例性描述芯片封装方法。
如图7A所示，刻蚀基板10的滤油层105，露出所需的导电部分103、凸起107以及基板101后续需要压合接触的部分。
如图7B所示，将未封装的多个滤波芯片15倒置焊接到基板10上。
如图7C所示，采用真空压合的方式进行密封，形成第一密封层17和第二密封层19后，为滤波芯片15提供空气腔，然后进行激光切割(沿竖向虚线)。
需要指出的是，在将多颗芯片倒置焊接到基板上时，所述多颗芯片在横向方向上彼此间隔开，两个相邻芯片之间的延伸部的宽度大于等于30μm，且两倍于或大于两倍的第一宽度。如能理解的，这里的两倍是一个概数，例如1.5倍-2.5倍的范围内，均可。
如图7D所示，切割后得到封装的芯片。
需要指出的是，以上的封装方法也可以用于集成多颗滤波芯片，或者多颗有源芯片与滤波芯片。图8为根据本发明的一个示例性实施例的芯片封装模块的示意性截面图，其示出了两颗芯片。在本发明中，所述滤波器芯片中至少包括体声波滤波器或者表面声波滤波器的一种。
基于以上，本发明提出了如下技术方案：
1、一种芯片封装模块，包括：
芯片；
封装基板，与所述芯片对置且两者之间形成空腔；
第一封装层，将所述芯片封装在封装基板上；
第二封装层，覆盖所述第一封装层的外侧设置，
其中：
第一封装层包括沿封装基板横向向外延伸的延伸部，所述延伸部的下侧覆盖所述封装基板的上侧，所述第二封装层的端部与所述延伸部的上侧形成面接触。
2、根据1所述的芯片封装模块，其中：
所述封装基板的至少被延伸部覆盖的部分设置有密封加强部。
3、根据2所述的芯片封装模块，其中：
所述密封加强部包括设置在封装基板的上侧的凹陷结构或凸起结构。
4、根据3所述的芯片封装模块，其中：
所述凹陷结构或凸起结构包括由凹陷或凸起形成的条形环状或矩形阵列或圆形阵列结构。
5、根据3所述的芯片封装模块，其中：
所述空腔的高度为H1，10μm≤H1≤150μm；
所述凹陷结构的深度或凸起结构的高度为H2，0.05μm≤H2≤10μm；
所述凹陷结构或凸起结构的宽度W3的范围为：W3≥H2。
6、根据2所述的芯片封装模块，其中：
所述密封加强部包括设置在封装基板的上侧的粗糙面结构。
7、根据1-6中任一项所述的芯片封装模块，其中：
所述密封加强部呈环形布置。
8、根据7所述的芯片封装模块，其中：
所述密封加强部包括整体呈环形布置的断续结构。
9、根据1所述的芯片封装模块，其中：
在延伸过芯片且平行于芯片的上表面的截面图中，所述第一封装层的第一宽度W1小于所述第二封装层的第二宽度W2。
10、根据9所述的芯片封装模块，其中：
所述第一宽度W1的范围为：0<W1≤50μm，所述第二宽度W2的范围为：W2≥15μm。
11、根据1-10中任一项所述的芯片封装模块，其中：
所述第一封装层包括覆盖半导体芯片的侧面的竖向部，所述竖向部与所述延伸部连接；且
所述竖向部的面对所述空腔的面与基底的上侧之间形成的角度θ为：60<θ<90。
12、根据1-10中任一项所述的芯片封装模块，其中：
所述芯片至少包括滤波芯片，所述滤波器芯片中至少包括体声波滤波器或者表面声波滤波器的一种。
13、根据12所述的芯片封装模块，其中：
所述芯片为由彼此同层布置且横向方向上间隔开的多颗芯片构成的芯片组；
所述多颗芯片彼此在横向方向上由所述第一封装层彼此间隔开；且
所述第一封装层的延伸部设置在所述芯片组的外侧。
14、根据13所述的芯片封装模块，其中：
所述芯片组包括多个滤波芯片，或者所述芯片组包括滤波芯片以及有源芯片。
15、一种芯片封装方法，包括步骤：
提供封装基板；
提供未封装芯片；
将芯片倒置焊接到封装基板上侧；
提供第一封装层，使得第一封装层将芯片封装到封装基板上，所述第一封装层具有沿封装基板横向向外延伸的延伸部，所述延伸部的下侧覆盖所述封装基板的上侧；
提供覆盖第一封装层的第二封装层，所述第二封装层的端部与所述延伸部的上侧形成面接触。
16、根据15所述的方法，其中：
步骤“提供封装基板”还包括在封装基板的预定位置设置密封加强部，所述预定位置被延伸部覆盖。
17、根据15或16所述的方法，其中：
“将芯片倒置焊接到封装基板上侧”的步骤包括将多颗芯片倒置焊接到封装基板上侧，其中，所述多颗芯片在横向方向上彼此间隔开；
第一封装层具有第一宽度W1，“提供第一封装层”的步骤中，两个相邻芯片之间的延伸部的宽度不小于30μm，且两倍于或大于两倍的第一宽度W1。
18、根据17所述的方法，其中：
“将芯片倒置焊接到封装基板上侧”的步骤包括将多个滤波芯片倒置焊接到封装基板上侧，或者将滤波芯片与有源芯片倒置焊接到封装基板上侧。
19、根据17或18所述的方法，还包括：
切割步骤，在预定的相邻芯片之间切割以形成多个独立的芯片封装模块。
20、一种电子装置，包括根据1-14中任一项所述的芯片封装模块或者根据15-19中任一项所述的芯片封装方法制造的芯片封装模块。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行变化，本发明的范围由所附权利要求及其等同物限定。

Claims (20)

  1. 一种芯片封装模块，包括：
    芯片；
    封装基板，与所述芯片对置且两者之间形成空腔；
    第一封装层，将所述芯片封装在封装基板上；
    第二封装层，覆盖所述第一封装层的外侧设置，
    其中：
    第一封装层包括沿封装基板横向向外延伸的延伸部，所述延伸部的下侧覆盖所述封装基板的上侧，所述第二封装层的端部与所述延伸部的上侧形成面接触。
  2. 根据权利要求1所述的芯片封装模块，其中：
    所述封装基板的至少被延伸部覆盖的部分设置有密封加强部。
  3. 根据权利要求2所述的芯片封装模块，其中：
    所述密封加强部包括设置在封装基板的上侧的凹陷结构或凸起结构。
  4. 根据权利要求3所述的芯片封装模块，其中：
    所述凹陷结构或凸起结构包括由凹陷或凸起形成的条形环状或矩形阵列或圆形阵列结构。
  5. 根据权利要求3所述的芯片封装模块，其中：
    所述空腔的高度为H1，10μm≤H1≤150μm；
    所述凹陷结构的深度或所述凸起结构的高度为H2，0.05μm≤H2≤10μm；
    所述凹陷结构或凸起结构的宽度W3的范围为：W3≥H2。
  6. 根据权利要求2所述的芯片封装模块，其中：
    所述密封加强部包括设置在封装基板的上侧的粗糙面结构。
  7. 根据权利要求1-6中任一项所述的芯片封装模块，其中：
    所述密封加强部呈环形布置。
  8. 根据权利要求7所述的芯片封装模块，其中：
    所述密封加强部包括整体呈环形布置的断续结构。
  9. 根据权利要求1所述的芯片封装模块，其中：
    在延伸过芯片且平行于芯片的上表面的截面图中，所述第一封装层的 第一宽度W1小于所述第二封装层的第二宽度W2。
  10. 根据权利要求9所述的芯片封装模块，其中：
    所述第一宽度W1的范围为：0<W1≤50μm，所述第二宽度W2的范围为：W2≥15μm。
  11. 根据权利要求1-10中任一项所述的芯片封装模块，其中：
    所述第一封装层包括覆盖半导体芯片的侧面的竖向部，所述竖向部与所述延伸部连接；且
    所述竖向部的面对所述空腔的面与基底的上侧之间形成的角度θ为：60<θ<90。
  12. 根据权利要求1-10中任一项所述的芯片封装模块，其中：
    所述芯片至少包括滤波芯片，所述滤波器芯片中至少包括体声波滤波器或者表面声波滤波器的一种。
  13. 根据权利要求12所述的芯片封装模块，其中：
    所述芯片为由彼此同层布置且横向方向上间隔开的多颗芯片构成的芯片组；
    所述多颗芯片彼此在横向方向上由所述第一封装层彼此间隔开；且
    所述第一封装层的延伸部设置在所述芯片组的外侧。
  14. 根据权利要求13所述的芯片封装模块，其中：
    所述芯片组包括多个滤波芯片，或者所述芯片组包括滤波芯片以及有源芯片。
  15. 一种芯片封装方法，包括步骤：
    提供封装基板；
    提供未封装芯片；
    将芯片倒置焊接到封装基板上侧；
    提供第一封装层，使得第一封装层将芯片封装到封装基板上，所述第一封装层具有沿封装基板横向向外延伸的延伸部，所述延伸部的下侧覆盖所述封装基板的上侧；
    提供覆盖第一封装层的第二封装层，所述第二封装层的端部与所述延伸部的上侧形成面接触。
  16. 根据权利要求15所述的方法，其中：
    步骤“提供封装基板”还包括在封装基板的预定位置设置密封加强部，所述预定位置被延伸部覆盖。
  17. 根据权利要求15或16所述的方法，其中：
    “将芯片倒置焊接到封装基板上侧”的步骤包括将多颗芯片倒置焊接到封装基板上侧，其中，所述多颗芯片在横向方向上彼此间隔开；
    第一封装层具有第一宽度W1，“提供第一封装层”的步骤中，两个相邻芯片之间的延伸部的宽度不小于30μm，且两倍于或大于两倍的第一宽度W1。
  18. 根据权利要求17所述的方法，其中：
    “将芯片倒置焊接到封装基板上侧”的步骤包括将多个滤波芯片倒置焊接到封装基板上侧，或者将滤波芯片与有源芯片倒置焊接到封装基板上侧。
  19. 根据权利要求17或18所述的方法，还包括：
    切割步骤，在预定的相邻芯片之间切割以形成多个独立的芯片封装模块。
  20. 一种电子装置，包括根据权利要求1-14中任一项所述的芯片封装模块或者根据权利要求15-19中任一项所述的芯片封装方法制造的芯片封装模块。
PCT/CN2020/088704 2019-12-04 2020-05-06 芯片封装模块及封装方法及具有该模块的电子装置 WO2021109443A1 (zh)

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