WO2021082146A1 - 显示面板及其制造方法 - Google Patents

显示面板及其制造方法 Download PDF

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Publication number
WO2021082146A1
WO2021082146A1 PCT/CN2019/121171 CN2019121171W WO2021082146A1 WO 2021082146 A1 WO2021082146 A1 WO 2021082146A1 CN 2019121171 W CN2019121171 W CN 2019121171W WO 2021082146 A1 WO2021082146 A1 WO 2021082146A1
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Prior art keywords
layer
manufacturing
display panel
nucleation
pixel area
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PCT/CN2019/121171
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English (en)
French (fr)
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谭伟
李金川
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/623,785 priority Critical patent/US11165039B1/en
Publication of WO2021082146A1 publication Critical patent/WO2021082146A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/826—Multilayers, e.g. opaque multilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H10K50/858—Arrangements for extracting light from the devices comprising refractive means, e.g. lenses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • This application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof.
  • OLED Organic Light Emitting Display
  • the light-emitting principle of OLED display devices is that semiconductor materials and organic light-emitting materials are driven by an electric field to cause the organic light-emitting materials to emit light through carrier injection and recombination.
  • the existing OLED display panel usually includes a TFT substrate, an anode provided on the TFT substrate, an organic light emitting layer provided on the anode, and a cathode provided on the organic light emitting layer.
  • the metal cathode Since the top-emitting OLED display panel has a common cathode structure, and the common cathode generally uses a metal or transparent oxide with high transmittance, the metal cathode has the problem of high surface resistance. For large-size OLED display panels, the common cathode surface resistance is high. There will be severe power supply voltage drop (IR-drop), resulting in poor brightness uniformity at different positions of the large-size OLED display panel.
  • IR-drop severe power supply voltage drop
  • the purpose of the present application is to provide a display panel and a manufacturing method thereof, so as to solve the problem of large common cathode resistance voltage drop in a large-size OLED display panel, which causes poor brightness uniformity at different positions of the OLED display panel.
  • a manufacturing method of a display panel includes the following steps:
  • the substrate having a pixel area and a non-pixel area located outside the pixel area, the substrate including a common electrode disposed in the pixel area and the non-pixel area;
  • nucleation inhibiting layer Forming a nucleation inhibiting layer on the common electrode of the pixel area and the non-pixel area, the nucleation inhibiting layer is used to inhibit the formation of a conductive layer on the surface of the nucleation inhibiting layer;
  • Laser ablation is used to remove the nucleation suppression layer in the non-pixel area to form a patterned nucleation suppression layer
  • the thickness of the conductive layer is greater than the thickness of the patterned nucleation suppression layer
  • the thickness of the nucleation inhibiting layer is 25 nanometers to 80 nanometers.
  • the removing the nucleation suppression layer in the non-pixel area by laser ablation includes the following steps:
  • the laser outputs light with a wavelength of 340 nanometers to 370 nanometers, and operates at an output power of 1.5 watts to 2.2 watts and an output frequency of 500 kHz to 2000 kHz, and ablates the nucleation suppression layer in the non-pixel area to form the pattern Chemical nucleation inhibition layer.
  • the manufacturing method further includes the following steps:
  • a capping layer is formed on the surface of the patterned nucleation inhibiting layer away from the substrate, and the thickness of the capping layer is greater than the thickness of the patterned nucleation inhibiting layer.
  • the sum of the thickness of the capping layer and the patterned nucleation suppression layer ranges from 400 nanometers to 600 nanometers.
  • the manufacturing method further includes the following steps:
  • the refractive index of the common electrode is greater than the refractive index of the patterned nucleation inhibiting layer
  • the refractive index of the patterned nucleation inhibiting layer is greater than or equal to the The refractive index of the capping layer is greater than the refractive index of the encapsulation layer.
  • the material for preparing the common electrode is metal or metal oxide.
  • the conductive layer is made of magnesium
  • the nucleation suppression layer is made of 3-(4-biphenyl)-4-phenyl-5-tert-butylbenzene.
  • Group-1,2,4-triazole bis(2-methyl-8-hydroxyquinoline-p-hydroxy)-4-biphenol aluminum, N(biphenyl-4-yl)9,9-dimethyl- At least one of N-(4(9-phenyl-9H-carbazol-3-yl)phenyl)-9H-fluoren-2-amine.
  • the present application provides a method for manufacturing a display panel.
  • the manufacturing method includes the following steps:
  • the substrate having a pixel area and a non-pixel area located outside the pixel area, the substrate including a common electrode disposed in the pixel area and the non-pixel area;
  • nucleation inhibiting layer Forming a nucleation inhibiting layer on the common electrode of the pixel area and the non-pixel area, the nucleation inhibiting layer is used to inhibit the formation of a conductive layer on the surface of the nucleation inhibiting layer;
  • Laser ablation is used to remove the nucleation suppression layer in the non-pixel area to form a patterned nucleation suppression layer
  • the conductive layer is formed on the common electrode in the non-pixel area.
  • the removing the nucleation suppression layer in the non-pixel area by laser ablation includes the following steps:
  • the laser outputs light with a wavelength of 340 nanometers to 370 nanometers, and operates at an output power of 1.5 watts to 2.2 watts and an output frequency of 500 kHz to 2000 kHz, and ablates the nucleation suppression layer in the non-pixel area to form the pattern Chemical nucleation inhibition layer.
  • the laser outputs light with a wavelength of 355 nanometers, and the output power of the laser is 1.7 watts to 2.0 watts.
  • the thickness of the nucleation suppression layer is 25 nm to 80 nm.
  • the manufacturing method further includes the following steps:
  • a capping layer is formed on the surface of the patterned nucleation inhibiting layer away from the substrate, and the thickness of the capping layer is greater than the thickness of the patterned nucleation inhibiting layer.
  • the sum of the thickness of the capping layer and the patterned nucleation suppression layer ranges from 400 nanometers to 600 nanometers.
  • the manufacturing method further includes the following steps:
  • the refractive index of the common electrode is greater than the refractive index of the patterned nucleation inhibiting layer
  • the refractive index of the patterned nucleation inhibiting layer is greater than or equal to the The refractive index of the capping layer is greater than the refractive index of the encapsulation layer.
  • the material for preparing the common electrode is metal or metal oxide.
  • the thickness of the conductive layer is greater than the thickness of the patterned nucleation suppression layer.
  • the conductive layer is made of magnesium
  • the nucleation suppression layer is made of 3-(4-biphenyl)-4-phenyl-5-tert-butylbenzene.
  • Group-1,2,4-triazole bis(2-methyl-8-hydroxyquinoline-p-hydroxy)-4-biphenol aluminum, N(biphenyl-4-yl)9,9-dimethyl- At least one of N-(4(9-phenyl-9H-carbazol-3-yl)phenyl)-9H-fluoren-2-amine.
  • a display panel is manufactured by the above-mentioned manufacturing method.
  • the present application provides a display panel and a manufacturing method thereof.
  • a patterned nucleation suppression layer with good mesh continuity and high precision is formed by using laser ablation, and the nucleation suppression layer is used to suppress the formation of a conductive layer on the surface of the nucleation suppression layer.
  • a conductive layer with good continuity is formed on the common electrode in the non-pixel area to improve the resistance voltage drop of the cathode formed by the common electrode and the conductive layer, and improve the brightness uniformity of the display screen of the display panel.
  • FIG. 1 is a flowchart of a manufacturing method of a display panel according to an embodiment of the application
  • 2A-2F are schematic diagrams of the structure in the process of manufacturing the display panel of the embodiment of the present application.
  • FIG. 1 is a flowchart of a manufacturing method of a display panel according to an embodiment of the present application.
  • the manufacturing method of the display panel includes the following steps:
  • the substrate 10 is an organic light emitting diode array substrate.
  • the substrate 10 has a pixel area 10a and a non-pixel area 10b located outside the pixel area 10a.
  • the substrate 10 includes a substrate 100, a thin film transistor array layer 101, and an organic light emitting diode array layer.
  • the substrate 100 is a glass substrate or a flexible polymer layer, and the flexible polymer layer includes a polyimide layer.
  • the thin film transistor array layer 101 includes a plurality of thin film transistors arranged in an array, and the thin film transistors are used to control the working state of the organic light emitting diodes in the organic light emitting diode array layer.
  • the thin film transistor may be a metal oxide thin film transistor or a polysilicon thin film transistor or the like.
  • the organic light emitting diode array layer includes a plurality of organic light emitting diodes arranged in an array, and the organic light emitting diodes may include red light organic light emitting diodes, blue light organic light emitting diodes, and green light organic light emitting diodes.
  • the organic light-emitting diode is a top-emission organic light-emitting diode, that is, the substrate 10 includes a plurality of independent pixel electrodes 1021, a plurality of independent organic light-emitting layers 1022 located in the pixel area 10a, and a common electrode disposed in the pixel area 10a and the non-pixel area 10b 1023.
  • a plurality of independent pixel electrodes 1021 are respectively electrically connected to the drain electrode in the thin film transistor.
  • the pixel electrode 1021 is an opaque electrode or a transparent electrode.
  • the pixel electrode 1021 is made of metals such as Ag and Mg, or a combination of transparent metal oxides such as indium zinc oxide and indium tin oxide and a metal layer.
  • the preparation material of the common electrode 1023 is metal or metal oxide, for example, the common electrode 1023 is Ag of 10 nm-100 nm, or the common electrode is an indium tin oxide layer or an indium zinc oxide layer.
  • the organic light emitting diode may also include a hole transport layer, a hole injection layer, an electron transport layer, an electron injection layer, etc., to further improve the light emitting effect of the organic light emitting diode.
  • a planarization layer, a passivation layer and a pixel definition layer are arranged between the organic light emitting diode array layer and the thin film transistor array layer.
  • the passivation layer forms the surface of the thin film transistor array layer, and is used to prevent ions in the organic layer such as the planarization layer from entering the thin film transistor array layer to affect the electrical performance of the thin film transistor.
  • the planarization layer is used to make the surface on which the thin film transistor array layer is formed more smooth, and the planarization layer is arranged on the surface of the passivation layer away from the thin film transistor array layer.
  • the pixel definition layer is used to define the pixel area 10a and the non-pixel area 10b of the substrate 100, and the pixel definition layer is disposed on the surface of the passivation layer away from the planarization layer.
  • S11 forming a nucleation suppression layer on the common electrode of the pixel area and the non-pixel area.
  • spin coating, vacuum evaporation, printing, etc. are used to form the entire surface of the nucleation suppression layer 103 on the common electrode 1023 of the pixel region 10a and the non-pixel region 10b.
  • the nucleation suppression layer 103 is used to suppress the formation of the conductive layer 104 on the surface of the nucleation suppression layer 103.
  • the nucleation suppression layer 103 and the conductive layer 104 have a low initial adhesion probability, so that the conductive layer 104 will not adhere to the surface of the nucleation suppression layer 103.
  • the preparation material of the nucleation inhibiting layer 103 is selected from the group consisting of 3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole, bis(2-methyl-8- Hydroxyquinoline p-hydroxy)-4-biphenol aluminum, N(biphenyl-4-yl)9,9-dimethyl-N-(4(9-phenyl-9H-carbazol-3-yl)benzene Group) at least one of -9H-fluoren-2-amine.
  • the thickness of the nucleation inhibiting layer 103 is 25 nanometers to 80 nanometers.
  • the thickness of the nucleation suppression layer 103 is 30 nanometers, 40 nanometers, or 50 nanometers.
  • the thickness of the nucleation suppression layer 103 is greater than or equal to 25 nanometers, which is beneficial to prevent the common electrode 1023 of the non-pixel region 10b from being excessively ablated when the nucleation suppression layer 103 of the non-pixel region 10b is ablated, which affects the normal operation of the common electrode 1023. performance.
  • the thickness of the nucleation suppression layer 103 is less than or equal to 80 nanometers, which is beneficial to avoid that the thickness of the nucleation suppression layer 103 in the pixel region 10a is too large and reduces the light output of the organic light emitting diode.
  • S12 Laser ablation is used to remove the nucleation suppression layer in the non-pixel area to form a patterned nucleation suppression layer.
  • the laser outputs light with a wavelength of 340 nanometers to 370 nanometers, and operates at an output power of 1.5 watts to 2.2 watts and an output frequency of 500 kHz to 2000 kHz.
  • the ablation of the non-pixel area 10b suppresses nucleation Layer 103 to form a patterned nucleation suppression layer 103a.
  • the laser wavelength between 340 nm and 370 nm is beneficial to avoid the ablation thickness of the common electrode 1023 exceeding the allowable value when the laser wavelength is too small to cause the ablation of the nucleation suppression layer 103, and it is also beneficial to avoid the laser wavelength from being too large to cause the formation of the non-pixel area 10b.
  • the laser outputs light with a wavelength of 355 nanometers.
  • the output power of the laser is 1.5 watts to 2.2 watts, to avoid excessively high light energy output by the laser, which may cause the ablation thickness of the common electrode 1023 to exceed the allowable value when the non-pixel area 10b nucleation suppression layer 103 is removed, and also avoid excessive light energy output by the laser.
  • the nucleation suppression layer 103 of the non-pixel region 10b is so low that it cannot be removed.
  • the output power of the laser is 1.7 watts to 2.0 watts.
  • the output frequency of 500kHz-2000kHz is conducive to forming a patterned nucleation suppression layer 103a with better grid continuity and higher precision.
  • the patterned nucleation suppression layer 103a has the advantages of good grid continuity, high precision, and high production efficiency. And by optimizing the process parameters of laser ablation to form the patterned nucleation suppression layer 103a, the patterned nucleation suppression layer 103a has better grid continuity and accuracy, and at the same time, it avoids overshooting the common electrode 1023 of the non-pixel region 10b.
  • the damage in the allowable range is thereby avoided to affect the resistance of the common electrode 1023 in the non-pixel area 10b, and the display effect of the display panel is improved.
  • the patterned nucleation suppression layer 103a formed has good mesh continuity and high precision, which also makes the subsequently formed conductive layer 104 good Continuity and high precision.
  • vacuum evaporation is used to form the conductive layer 104 on the common electrode 1023 of the non-pixel region 10b. Since there is a self-assembly function between the conductive layer 104 and the patterned nucleation suppression layer 103a, the pixel region 10a where the patterned nucleation suppression layer 103a is formed cannot form the conductive layer 104, and the non-pixel region 10b of the nucleation suppression layer 103 is removed. A conductive layer 104 is formed on the common electrode 1023.
  • the conductive layer 104 is in electrical contact with the common electrode 1023, so that the surface resistance of the cathode formed by the conductive layer 104 and the common electrode 1023 is reduced, the resistance voltage drop of the cathode formed by the common electrode 1023 and the conductive layer 104 is improved, and the appearance of large-size display panels is avoided.
  • the non-uniformity of the resistance voltage drop improves the brightness uniformity of the display panel when displaying images.
  • the preparation material of the conductive layer 104 includes magnesium. There is a smaller initial adhesion coefficient between magnesium and the nucleation suppression layer.
  • the thickness of the conductive layer 104 is greater than the thickness of the patterned nucleation suppression layer 103a, so that the conductive layer 104 has a larger thickness to further improve the problem of uneven resistance voltage drop in a large-size display panel.
  • the thickness of the conductive layer 104 is greater than or equal to 150 nanometers and less than 2 microns. For example, the thickness of the conductive layer is 200 nanometers, 300 nanometers, 800 nanometers, or 1 micron.
  • the manufacturing method further includes the following steps:
  • a capping layer 105 (CPL) is formed on the surface of the patterned nucleation suppression layer 103a away from the substrate 10.
  • the capping layer 105 is used to suppress the surface plasmon effect of the light emitted by the organic light emitting diode at the metal/medium interface to improve the light emission efficiency of the light emitted by the organic light emitting diode.
  • the capping layer 105 is made of organic materials, for example, the capping layer 105 is made of aluminum quinolate (Alq3).
  • the thickness of the capping layer 105 is greater than the thickness of the patterning suppression layer 103a, so as to further increase the light transmittance of the light emitted by the organic light emitting diode through the patterning suppression layer 103a and the capping layer 105.
  • the sum of the thickness of the capping layer 105 and the patterning suppression layer 103a ranges from 400 nanometers to 600 nanometers, so as to reduce the thickness of the display panel while increasing the light emitted by the organic light emitting diode to pass through the capping layer 105 and
  • the patterning suppresses the penetration rate of the layer 103a.
  • the thickness of the patterning suppression layer is 50 nanometers, and the thickness of the capping layer is 450 nanometers; or, the thickness of the patterning suppression layer is 80 nanometers, and the thickness of the capping layer is 420 nanometers.
  • the preparation material of the capping layer 105 may also be the same as the preparation material of the patterning suppression layer 103a.
  • the capping layer 105 and the patterning suppression layer 103a are the same film layer and are formed by the same process.
  • the manufacturing method further includes the following steps:
  • the encapsulation layer 106 covering the capping layer 105 and the conductive layer 104 is formed, the refractive index of the common electrode 1023 is greater than the refractive index of the patterned nucleation suppression layer 103a, and the refractive index of the patterned nucleation suppression layer 103a is greater than or equal to the refraction of the capping layer 105
  • the refractive index of the capping layer 105 is greater than that of the encapsulation layer 106, so that the light emitted by the organic light-emitting diode passes through the common electrode 1023, the patterned nucleation suppression layer 103a, the capping layer 105, and the encapsulation layer 106, which have a decreasing refractive index. After that, the light transmittance of the light emitted by the organic light emitting diode increases.
  • the encapsulation layer 106 includes at least two inorganic insulating layers and an organic insulating layer located between the two inorganic layers.
  • the refractive index of the inorganic insulating layer and the organic insulating layer are both smaller than the refractive index of the patterned nucleation suppression layer.
  • the inorganic insulating layer is made of silicon oxide
  • the organic insulating layer is made of polyacrylate.
  • the display panel is a top-emitting organic light-emitting diode display panel, and the display panel may also be a bottom-emitting organic light-emitting diode display panel or a transparent organic light-emitting diode display panel.
  • the present application also provides a display panel, which is manufactured by the above-mentioned manufacturing method.
  • the display panel of the present application uses laser ablation to form a patterned nucleation suppression layer with good mesh continuity and high precision, and the nucleation suppression layer is used to suppress the formation of a conductive layer on the surface of the nucleation suppression layer to serve as a common electrode in the non-pixel area.
  • a conductive layer with good continuity is formed on the surface to improve the resistance voltage drop of the cathode formed by the common electrode and the conductive layer, and improve the brightness uniformity of the display screen of the display panel.

Abstract

一种显示面板及其制造方法，通过采用激光烧蚀以形成网格连续性好以及精度高的图案化成核抑制层(103a)，利用成核抑制层(103a)抑制导电层(104)形成于成核抑制层(103a)的表面，于非像素区(10b)的公共电极(1023)上形成连续性好的导电层(104)，以改善公共电极(1023)和导电层(104)构成的阴极的电阻压降，提高显示面板显示画面的亮度均一性。

Description

显示面板及其制造方法
本申请要求于2019年10月30日提交中国专利局、申请号为201911042322.1、发明名称为“显示面板及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及其制造方法。
 背景技术
有机电致发光(Organic Light Emitting Display，OLED)器件具有自发光、全固态、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角以及使用温度范围宽，可实现柔性显示与大面积全彩显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
目前，小尺寸OLED在移动智能终端和车载领域的应用已经全面超越液晶显示装置（Liquid Crystal Display，LCD），未来大尺寸顶发光型且高解析度的OLED显示面板也会全面应用并取代液晶显示装置。OLED显示器件的发光原理为半导体材料和有机发光材料在电场驱动下，通过载流子注入和复合导致有机发光材料发光。现有OLED显示面板通常包括：TFT基板，设于TFT基板上的阳极、设于阳极上的有机发光层及设于有机发光层上的阴极。由于顶发光OLED显示面板是共阴极的结构，且共阴极一般采用透过率高的金属或者透明氧化物，金属阴极会存在面电阻高的问题，对于大尺寸OLED显示面板共阴极面电阻高，会存在严重的电源电压降(IR-drop)，导致大尺寸OLED显示面板不同位置亮度均一性差。
 技术问题
本申请的目的在于提供一种显示面板及其制造方法，以解决大尺寸OLED显示面板存在共阴极电阻压降大而导致OLED显示面板不同位置亮度均一性差的问题。
 技术解决方案
一种显示面板的制造方法，其中，所述制造方法包括如下步骤：
提供一基板，所述基板具有像素区和位于所述像素区外的非像素区，所述基板包括设置于所述像素区和所述非像素区的公共电极；
于所述像素区和所述非像素区的所述公共电极上形成成核抑制层，所述成核抑制层用于抑制导电层形成于所述成核抑制层的表面；
采用激光烧蚀去除所述非像素区的所述成核抑制层以形成图案化成核抑制层；
于所述非像素区的所述公共电极上形成所述导电层；
所述导电层的厚度大于所述图案化成核抑制层的厚度；
所述成核抑制层的厚度为25纳米-80纳米。
在上述显示面板的制造方法中，所述采用激光烧蚀去除所述非像素区的所述成核抑制层包括如下步骤：
激光器输出波长为340纳米-370纳米的光，且以1.5瓦特-2.2瓦特的输出功率以及500kHz-2000kHz的输出频率工作，烧蚀所述非像素区的所述成核抑制层以形成所述图案化成核抑制层。
在上述显示面板的制造方法中，所述制造方法还包括如下步骤：
于所述图案化成核抑制层远离所述基板的表面形成盖封层，所述盖封层的厚度大于所述图案化成核抑制层的厚度。
在上述显示面板的制造方法中，所述盖封层和所述图案化成核抑制层的厚度之和的取值范围为400纳米-600纳米。
在上述显示面板的制造方法中，所述制造方法还包括如下步骤：
形成覆盖所述盖封层和所述导电层的封装层，所述公共电极的折射率大于所述图案化成核抑制层的折射率，所述图案化成核抑制层的折射率大于或等于所述盖封层的折射率，所述盖封层的折射率大于所述封装层的折射率。
在上述显示面板的制造方法中，所述公共电极的制备材料为金属或者金属氧化物。
在上述显示面板的制造方法中，所述导电层的制备材料包括镁，所述成核抑制层的制备材料选自3-(4-联苯)-4-苯基-5-叔丁基苯基-1，2，4-三唑、双(2-甲基-8-羟基喹啉对羟基)-4-联苯酚铝、N(联苯-4-基)9，9-二甲基-N-(4(9-苯基-9H-咔唑-3-基)苯基)-9H-芴-2-胺中的至少一种。
本申请提供一种显示面板的制造方法，所述制造方法包括如下步骤：
提供一基板，所述基板具有像素区和位于所述像素区外的非像素区，所述基板包括设置于所述像素区和所述非像素区的公共电极；
于所述像素区和所述非像素区的所述公共电极上形成成核抑制层，所述成核抑制层用于抑制导电层形成于所述成核抑制层的表面；
采用激光烧蚀去除所述非像素区的所述成核抑制层以形成图案化成核抑制层；
于所述非像素区的所述公共电极上形成所述导电层。
在上述显示面板的制造方法中，所述采用激光烧蚀去除所述非像素区的所述成核抑制层包括如下步骤：
激光器输出波长为340纳米-370纳米的光，且以1.5瓦特-2.2瓦特的输出功率以及500kHz-2000kHz的输出频率工作，烧蚀所述非像素区的所述成核抑制层以形成所述图案化成核抑制层。
在上述显示面板的制造方法中，所述激光器输出波长为355纳米的光，所述激光器的输出功率为1.7瓦特-2.0瓦特。
在上述显示面板的制造方法中，所述成核抑制层的厚度为25纳米-80纳米。
在上述显示面板的制造方法中，所述制造方法还包括如下步骤：
于所述图案化成核抑制层远离所述基板的表面形成盖封层，所述盖封层的厚度大于所述图案化成核抑制层的厚度。
在上述显示面板的制造方法中，所述盖封层和所述图案化成核抑制层的厚度之和的取值范围为400纳米-600纳米。
在上述显示面板的制造方法中，所述制造方法还包括如下步骤：
形成覆盖所述盖封层和所述导电层的封装层，所述公共电极的折射率大于所述图案化成核抑制层的折射率，所述图案化成核抑制层的折射率大于或等于所述盖封层的折射率，所述盖封层的折射率大于所述封装层的折射率。
在上述显示面板的制造方法中，所述公共电极的制备材料为金属或者金属氧化物。
在上述显示面板的制造方法中，所述导电层的厚度大于所述图案化成核抑制层的厚度。
在上述显示面板的制造方法中，所述导电层的制备材料包括镁，所述成核抑制层的制备材料选自3-(4-联苯)-4-苯基-5-叔丁基苯基-1，2，4-三唑、双(2-甲基-8-羟基喹啉对羟基)-4-联苯酚铝、N(联苯-4-基)9，9-二甲基-N-(4(9-苯基-9H-咔唑-3-基)苯基)-9H-芴-2-胺中的至少一种。
一种显示面板，所述显示面板由上述制造方法制得。
 有益效果
本申请提供一种显示面板及其制造方法，通过采用激光烧蚀以形成网格连续性好以及精度高的图案化成核抑制层，利用成核抑制层抑制导电层形成于成核抑制层的表面以于非像素区的公共电极上形成连续性好的导电层，以改善公共电极和导电层构成的阴极的电阻压降，提高显示面板显示画面的亮度均一性。
 附图说明
图1为本申请实施例显示面板的制造方法的流程图；
图2A-2F为制造本申请实施例显示面板过程中的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，其为本申请实施例显示面板的制造方法的流程图。显示面板的制造方法包括如下步骤：
S10:提供一基板。
具体地，如图2A所示，基板10为有机发光二极管阵列基板。基板10具有像素区10a和位于像素区10a外的非像素区10b。基板10包括衬底100、薄膜晶体管阵列层101以及有机发光二极管阵列层。
衬底100为玻璃基板或者柔性聚合物层，柔性聚合物层包括聚酰亚胺层。
薄膜晶体管阵列层101包括多个阵列排布的薄膜晶体管，薄膜晶体管用于控制有机发光二极管阵列层中的有机发光二极管的工作状态。薄膜晶体管可以为金属氧化物薄膜晶体管或多晶硅薄膜晶体管等。
有机发光二极管阵列层包括多个阵列排布的有机发光二极管，有机发光二极管可以包括红光有机发光二极管、蓝光有机发光二极管以及绿光有机发光二极管。有机发光二极管为顶发光型有机发光二极管，即基板10包括多个独立的像素电极1021、多个独立且位于像素区10a的有机发光层1022以及设置于像素区10a和非像素区10b的公共电极1023。多个独立的像素电极1021分别与薄膜晶体管中的漏电极电性连接。像素电极1021为不透明电极或者透明电极。像素电极1021的制备材料为Ag、Mg等金属，或为氧化铟锌、氧化铟锡等透明金属氧化物与金属层的组合。公共电极1023的制备材料为金属或金属氧化物，例如公共电极1023为10纳米-100纳米的Ag，或者公共电极为氧化铟锡层或氧化铟锌层。有机发光二极管还可以包括空穴传输层、空穴注入层、电子传输层以及电子注入层等，以进一步地提高有机发光二极管的发光效果。
在有机发光二极管阵列层和薄膜晶体管阵列层之间设置有平坦化层、钝化层以及像素定义层。钝化层形成薄膜晶体管阵列层的表面，用于阻止平坦化层等有机层中的离子进入至薄膜晶体管阵列层中而影响薄膜晶体管的电性能。平坦化层用于使形成有薄膜晶体管阵列层的表面更加平整，平坦化层设置于钝化层远离薄膜晶体管阵列层的表面。像素定义层用于定义基板100的像素区10a和非像素区10b，像素定义层设置于钝化层远离平坦化层的表面。
S11:于像素区和非像素区的公共电极上形成成核抑制层。
具体地，如图2B所示，采用旋涂、真空蒸镀以及印刷等在像素区10a和非像素区10b的公共电极1023上形成整面的成核抑制层103。成核抑制层103用于抑制导电层104形成于成核抑制层103的表面。成核抑制层103与导电层104之间具有低的初始粘着概率，使得导电层104不会附着于成核抑制层103的表面。成核抑制层103的制备材料选自3-(4-联苯)-4-苯基-5-叔丁基苯基-1，2，4-三唑、双(2-甲基-8-羟基喹啉对羟基)-4-联苯酚铝、N(联苯-4-基)9，9-二甲基-N-(4(9-苯基-9H-咔唑-3-基)苯基)-9H-芴-2-胺中的至少一种。
成核抑制层103的厚度为25纳米-80纳米。例如成核抑制层103的厚度为30纳米、40纳米或者50纳米。成核抑制层103的厚度大于或等于25纳米，有利于避免烧蚀非像素区10b的成核抑制层103时导致非像素区10b的公共电极1023被过度烧蚀而影响公共电极1023的正常工作性能。成核抑制层103的厚度小于或等于80纳米，有利于避免像素区10a的成核抑制层103的厚度太大而降低有机发光二极管的出光率。
S12:采用激光烧蚀去除非像素区的成核抑制层以形成图案化成核抑制层。
具体地，如图2C所示，激光器输出波长为340纳米-370纳米的光，且以1.5瓦特-2.2瓦特的输出功率以及500kHz-2000kHz的输出频率工作，烧蚀非像素区10b的成核抑制层103以形成图案化成核抑制层103a。激光波长为340纳米-370纳米有利于避免激光波长太小导致烧蚀成核抑制层103时导致公共电极1023烧蚀厚度超过允许值，也有利于避免激光波长太大导致非像素区10b的成核抑制层103无法去除完全导致导电层104无法形成于非像素区10b的公共电极1023上。优选地，激光器输出波长为355纳米的光。激光器的输出功率为1.5瓦特-2.2瓦特，避免激光器输出的光能量过高导致去除非像素区10b成核抑制层103时导致公共电极1023烧蚀厚度超过允许值，也避免激光器输出的光能量过低而无法去除非像素区10b的成核抑制层103。优选地，激光器的输出功率为1.7瓦特-2.0瓦特。500kHz-2000kHz的输出频率有利于形成网格连续性更好且精度更高的图案化成核抑制层103a。
需要说明的是，由于技术原因，目前无法采用掩膜板形成大尺寸显示面板的图案化成核抑制层。而本实施例采用激光烧蚀技术以形成图案化成核抑制层103a，使得图案化成核抑制层103a具有网格连续性好、精度高以及制作效率高的优点。且通过优化激光烧蚀以形成图案化成核抑制层103a的工艺参数，使得图案化成核抑制层103a具有更好的网格连续性以及精度的同时，避免对非像素区10b的公共电极1023造成超过允许范围的损伤，从而避免影响非像素区10b公共电极1023的电阻，提高显示面板的显示效果。此外，相对于传统工艺，例如采用印刷导电银浆等以形成导电层，由于形成的图案化成核抑制层103a具有良好的网格连续性以及高精度，也使得后续形成的导电层104具有良好的连续性以及高精度。
S13: 于非像素区的公共电极上形成导电层。
具体地，如图2D所示，采用真空蒸镀以于非像素区10b的公共电极1023上形成导电层104。由于导电层104和图案化成核抑制层103a之间存在自组装功能，使得形成有图案化成核抑制层103a的像素区10a无法形成导电层104，而去除成核抑制层103的非像素区10b的公共电极1023上形成有导电层104。导电层104与公共电极1023电性接触，使得导电层104与公共电极1023构成的阴极的面电阻减小，改善公共电极1023和导电层104构成的阴极的电阻压降，避免大尺寸显示面板出现电阻压降不均一的问题，提高显示面板显示画面时的亮度均一性。
导电层104的制备材料包括镁。镁与成核抑制层之间具有更小的初始粘着系数。导电层104的厚度大于图案化成核抑制层103a的厚度，使得导电层104厚度较大以进一步地改善大尺寸显示面板出现电阻压降不均一的问题。导电层104的厚度大于或等于150纳米且小于2微米。例如导电层的厚度为200纳米、300纳米、800纳米或者1微米。
进一步地，如图2E所示，制造方法还包括如下步骤：
于图案化成核抑制层103a远离基板10的表面形成盖封层105（Capping Layer，CPL）。盖封层105用于通过压制有机发光二极管发出的光在金属/介质界面处的表面等离子激元效应以提高有机发光二极管发出的光的出射光效率。盖封层105的制备材料为有机材料，例如盖封层105的制备材料为羟基喹啉铝（Alq3）。
盖封层105的厚度大于图案化抑制层103a的厚度，以进一步地提高有机发光二极管发出的光穿过图案化抑制层103a以及盖封层105的透光率。盖封层105和图案化抑制层103a的厚度之和的取值范围为400纳米-600纳米，以实现显示面板的厚度薄化的同时，提高有机发光二极管发出的光穿过盖封层105以及图案化抑制层103a的穿过率。例如图案化抑制层的厚度为50纳米，盖封层的厚度为450纳米；或，图案化抑制层的厚度为80纳米，盖封层的厚度为420纳米。
可以理解的是，盖封层105的制备材料也可以与图案化抑制层103a的制备材料相同。此时，盖封层105与图案化抑制层103a为同一膜层且通过同一制程形成。
进一步地，如图2F所示，制造方法还包括如下步骤：
形成覆盖盖封层105和导电层104的封装层106，公共电极1023的折射率大于图案化成核抑制层103a的折射率，图案化成核抑制层103a的折射率大于或等于盖封层105的折射率，盖封层105的折射率大于封装层106的折射率，以使得有机发光二极管发出的光经过折射率呈递减趋势的公共电极1023、图案化成核抑制层103a盖封层105以及封装层106后，有机发光二极管发出的光的透光率增加。
封装层106至少包括两无机绝缘层以及位于两无机层之间的一有机绝缘层。无机绝缘层和有机绝缘层的折射率均小于图案化成核抑制层的折射率，例如无机绝缘层为氧化硅，有机绝缘层为聚丙烯酸酯等。
需要说明的是，上述描述的是显示面板为顶发光有机发光二极管显示面板，显示面板也可以为底发光有机发光二极管显示面板或者透明有机发光二极管显示面板。
本申请还提供一种显示面板，显示面板通过上述制造方法制得。
本申请显示面板通过采用激光烧蚀以形成网格连续性好以及精度高的图案化成核抑制层，利用成核抑制层抑制导电层形成于成核抑制层的表面以于非像素区的公共电极上形成连续性好的导电层，以改善公共电极和导电层构成的阴极的电阻压降，提高显示面板显示画面的亮度均一性。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (18)

  1. 一种显示面板的制造方法，其中，所述制造方法包括如下步骤：
    提供一基板，所述基板具有像素区和位于所述像素区外的非像素区，所述基板包括设置于所述像素区和所述非像素区的公共电极；
    于所述像素区和所述非像素区的所述公共电极上形成成核抑制层，所述成核抑制层用于抑制导电层形成于所述成核抑制层的表面；
    采用激光烧蚀去除所述非像素区的所述成核抑制层以形成图案化成核抑制层；
    于所述非像素区的所述公共电极上形成所述导电层；
    所述导电层的厚度大于所述图案化成核抑制层的厚度；
    所述成核抑制层的厚度为25纳米-80纳米。
  2. 根据权利要求1所述的显示面板的制造方法，其中，所述采用激光烧蚀去除所述非像素区的所述成核抑制层包括如下步骤：
    激光器输出波长为340纳米-370纳米的光，且以1.5瓦特-2.2瓦特的输出功率以及500kHz-2000kHz的输出频率工作，烧蚀所述非像素区的所述成核抑制层以形成所述图案化成核抑制层。
  3. 根据权利要求1所述的显示面板的制造方法，其中，所述制造方法还包括如下步骤：
    于所述图案化成核抑制层远离所述基板的表面形成盖封层，所述盖封层的厚度大于所述图案化成核抑制层的厚度。
  4. 根据权利要求3所述的显示面板的制造方法，其中，所述盖封层和所述图案化成核抑制层的厚度之和的取值范围为400纳米-600纳米。
  5. 根据权利要求3所述的显示面板的制造方法，其中，所述制造方法还包括如下步骤：
    形成覆盖所述盖封层和所述导电层的封装层，所述公共电极的折射率大于所述图案化成核抑制层的折射率，所述图案化成核抑制层的折射率大于或等于所述盖封层的折射率，所述盖封层的折射率大于所述封装层的折射率。
  6. 根据权利要求1所述的显示面板的制造方法，其中，所述公共电极的制备材料为金属或者金属氧化物。
  7. 根据权利要求1所述的显示面板的制造方法，其中，所述导电层的制备材料包括镁，所述成核抑制层的制备材料选自3-(4-联苯)-4-苯基-5-叔丁基苯基-1，2，4-三唑、双(2-甲基-8-羟基喹啉对羟基)-4-联苯酚铝、N(联苯-4-基)9，9-二甲基-N-(4(9-苯基-9H-咔唑-3-基)苯基)-9H-芴-2-胺中的至少一种。
  8. 一种显示面板的制造方法，其中，所述制造方法包括如下步骤：
    提供一基板，所述基板具有像素区和位于所述像素区外的非像素区，所述基板包括设置于所述像素区和所述非像素区的公共电极；
    于所述像素区和所述非像素区的所述公共电极上形成成核抑制层，所述成核抑制层用于抑制导电层形成于所述成核抑制层的表面；
    采用激光烧蚀去除所述非像素区的所述成核抑制层以形成图案化成核抑制层；
    于所述非像素区的所述公共电极上形成所述导电层。
  9. 根据权利要求8所述的显示面板的制造方法，其中，所述采用激光烧蚀去除所述非像素区的所述成核抑制层包括如下步骤：
    激光器输出波长为340纳米-370纳米的光，且以1.5瓦特-2.2瓦特的输出功率以及500kHz-2000kHz的输出频率工作，烧蚀所述非像素区的所述成核抑制层以形成所述图案化成核抑制层。
  10. 根据权利要求9所述的显示面板的制造方法，其中，所述激光器输出波长为355纳米的光，所述激光器的输出功率为1.7瓦特-2.0瓦特。
  11. 根据权利要求8所述的显示面板的制造方法，其中，所述成核抑制层的厚度为25纳米-80纳米。
  12. 根据权利要求8所述的显示面板的制造方法，其中，所述制造方法还包括如下步骤：
    于所述图案化成核抑制层远离所述基板的表面形成盖封层，所述盖封层的厚度大于所述图案化成核抑制层的厚度。
  13. 根据权利要求12所述的显示面板的制造方法，其中，所述盖封层和所述图案化成核抑制层的厚度之和的取值范围为400纳米-600纳米。
  14. 根据权利要求12所述的显示面板的制造方法，其中，所述制造方法还包括如下步骤：
    形成覆盖所述盖封层和所述导电层的封装层，所述公共电极的折射率大于所述图案化成核抑制层的折射率，所述图案化成核抑制层的折射率大于或等于所述盖封层的折射率，所述盖封层的折射率大于所述封装层的折射率。
  15. 根据权利要求8所述的显示面板的制造方法，其中，所述公共电极的制备材料为金属或者金属氧化物。
  16. 根据权利要求8所述的显示面板的制造方法，其中，所述导电层的厚度大于所述图案化成核抑制层的厚度。
  17. 根据权利要求8所述的显示面板的制造方法，其中，所述导电层的制备材料包括镁，所述成核抑制层的制备材料选自3-(4-联苯)-4-苯基-5-叔丁基苯基-1，2，4-三唑、双(2-甲基-8-羟基喹啉对羟基)-4-联苯酚铝、N(联苯-4-基)9，9-二甲基-N-(4(9-苯基-9H-咔唑-3-基)苯基)-9H-芴-2-胺中的至少一种。
  18. 一种显示面板，其中，所述显示面板由权利要求1所述的制造方法制得。
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