WO2021056887A1 - Dram存储器 - Google Patents

Dram存储器 Download PDF

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Publication number
WO2021056887A1
WO2021056887A1 PCT/CN2019/127862 CN2019127862W WO2021056887A1 WO 2021056887 A1 WO2021056887 A1 WO 2021056887A1 CN 2019127862 W CN2019127862 W CN 2019127862W WO 2021056887 A1 WO2021056887 A1 WO 2021056887A1
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Prior art keywords
memory
storage
block
bank
data transmission
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PCT/CN2019/127862
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English (en)
French (fr)
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冀康灵
尚为兵
李红文
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长鑫存储技术有限公司
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Priority to US17/281,206 priority Critical patent/US11538515B2/en
Priority to EP19946694.7A priority patent/EP3937175B1/en
Publication of WO2021056887A1 publication Critical patent/WO2021056887A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Definitions

  • the present invention relates to the field of memory, in particular to a DRAM memory.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a commonly used semiconductor memory device in computers, and its memory array area is composed of many repeated memory cells. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • DRAM Dynamic Random Access Memory
  • the existing DRAM memory organization structure includes a number of banks (BANK), and each bank (BANK) is divided into two storage blocks of the same size on the left and right.
  • BANK bank
  • the existing organizational structure DRAM memory has problems such as high power consumption and data transmission rate and data transmission accuracy that need to be improved during operation.
  • the technical problem to be solved by the present invention is how to reduce the power consumption of the DRAM memory and how to improve the data transmission rate and data transmission accuracy.
  • the present invention provides a DRAM memory, including:
  • each storage bank is divided into three storage blocks in a column direction, and each storage block has a plurality of storage cells arranged in rows and columns.
  • the three storage blocks include a first storage block, a second storage block, and a third storage block that are sequentially arranged in a column direction.
  • the first storage block, the second storage block, and the third storage block in each storage block are respectively connected to a first column decoding circuit, a second column decoding circuit, and a third column decoding circuit.
  • first storage block, the second storage block, and the third storage block in each storage block are further connected to a first row decoding circuit and a second row decoding circuit.
  • the first row decoding circuit is connected to all the storage units in the first storage block and some storage units in the second storage block, and is used to determine the first storage block in all the storage units and the second storage block.
  • Part of the memory cells in the block are row-addressed
  • the second row decoding circuit is connected to all the memory cells in the third memory block and some memory cells in the second memory block, and is used to address the third memory block in all the memory cells.
  • the storage unit and part of the storage unit in the second storage block perform row addressing.
  • the storage capacities of the first storage block, the second storage block, and the third storage block are equal.
  • the line area has a control line and a data transmission line
  • the control line is used to send control instructions and/or addresses to the corresponding memory bank
  • the data transmission line is used to transmit data to or read data from the corresponding storage unit in the corresponding storage library.
  • the substrate further has a pad area, the pad area has a plurality of first pads and second pads, the first pads are connected to the control circuit, and the second pads Connect with data transmission line.
  • the DRAM memory of the present invention includes: a substrate; a plurality of memory banks arranged in rows and columns on the substrate, each memory bank is divided into three memory blocks in the column direction, and each memory block is There are several storage units arranged in rows and columns.
  • each storage bank is divided into three storage blocks in the column direction, on the one hand, when each storage bank has a certain capacity, each storage bank is divided into three storage blocks in the column direction, and each storage block
  • the length in the row direction will be shorter (as opposed to the solution of dividing each memory bank into two memory blocks in the row direction), so that the length of the control circuit itself will be shorter and the control circuit will be connected to the storage array in each memory block accordingly
  • the distance of the storage unit will be shorter, so there is no need for a large drive, reducing power consumption, and making the length of the data transmission line itself shorter and the data transmission line to the corresponding storage unit in the storage array in each storage block
  • the distance will also be shorter, which reduces the parasitic resistance and capacitance generated by the data
  • first storage block, the second storage block, and the third storage block in each storage block are respectively connected to a first column decoding circuit, a second column decoding circuit, and a third column decoding circuit.
  • the first storage block, the second storage block and the third storage block in one storage block are also connected to the first row decoding circuit and the second row decoding circuit.
  • the first column decoding circuit, the second column decoding circuit, and the third column decoding circuit are used to perform column addressing on corresponding memory cells in the first memory block, the second memory block, and the third memory block, respectively.
  • a row of decoding circuit and a second row of decoding circuit address the storage units of the first storage block, the second storage block and the third storage block, so that the corresponding ones of the three storage blocks in a storage bank can be addressed at the same time.
  • the memory cells are accessed at the same time (including reading, writing or refreshing), which improves the operating efficiency of the DRAM memory.
  • the first row decoding circuit is connected to all the memory cells in the first memory block and some memory cells in the second memory block, and is used to determine the first memory block in all the memory cells and the second memory block. Part of the memory cells in the second memory block are row-addressed, and the second row decoding circuit is connected to all memory cells in the third memory block and some memory cells in the second memory block, and is used for addressing the third memory block in the third memory block. All memory cells and some memory cells in the second memory block are row-addressed. Therefore, the row decoding (decoding) of the memory cells in the three memory blocks in a memory bank can be shared and controlled, and the area of the chip is saved.
  • FIG. 1 is a schematic diagram of the structure of a DRAM memory in an embodiment of the present invention
  • FIG. 2 is a schematic diagram of the structure of a DRAM memory in another embodiment of the present invention.
  • the existing organizational structure DRAM memory has problems such as high power consumption and data transmission rate and data transmission accuracy that need to be improved during operation.
  • FIG. 1 is a schematic structural diagram of a DRAM memory in an embodiment of the present invention.
  • the DRAM memory includes several rows and columns (the row direction is the X-axis direction in FIG. 1, and the column direction is the Y-axis direction in FIG. 1).
  • 8 storage banks BANK are taken as an example for illustration.
  • Each storage bank BANK is divided into two storage blocks of the same size on the left and right, including a first storage block 21 and a second storage block 22.
  • the first storage block 21 and the second storage block 22 include a storage array or a number of storage units arranged in rows and columns.
  • the first storage block 21 and the second storage block 22 are respectively connected to the corresponding row decoding circuit YDEC and column decoding circuit XDEC, A control line and a data transmission line are provided between the storage banks between adjacent rows, the control line is used to transmit control signals to the corresponding bank BANK, and the data transmission line is used to transmit data to the corresponding storage unit .
  • the aforementioned organizational structure DRAM memory has a longer length in the row direction (X-axis direction), and the corresponding control line and data transmission line have a longer length, and the distance between the control line and the data transmission line and each storage unit is also relatively long.
  • the present invention provides a DRAM memory, including: a substrate; a plurality of memory banks arranged in rows and columns on the substrate, each memory bank is divided into three memory blocks in the column direction, the Each storage block has several storage units arranged in rows and columns.
  • each storage bank By dividing each storage bank into three storage blocks in the column direction, on the one hand, when each storage bank has a certain capacity, each storage bank is divided into three storage blocks in the column direction, and each storage block
  • the length in the row direction will be shorter (as opposed to the solution of dividing each memory bank into two memory blocks in the row direction), so that the length of the control circuit itself will be shorter and the control circuit will be connected to the storage array in each memory block accordingly
  • the distance of the storage unit will be shorter, so there is no need for a large drive, reducing power consumption, and making the length of the data transmission line itself shorter and the data transmission line to the corresponding storage unit in the storage array in each storage block
  • the distance will also be shorter, which reduces the parasitic resistance and capacitance generated by the data transmission line, which improves the data transmission rate and data transmission accuracy, and reduces power consumption.
  • the length of the memory block in the memory bank becomes shorter, which can reduce the power consumption.
  • FIG. 2 is a schematic diagram of the structure of a DRAM memory in another embodiment of the present invention.
  • the DRAM memory includes:
  • each memory bank BANK is divided into three memory blocks (31/32/33) in the column direction, each of the memory blocks (31/32 /33) has several storage units arranged in rows and columns.
  • DRAM memory is generally divided into several storage banks BANK.
  • the number of storage banks BANK in a DRAM memory can be 4, 8, 16, or other numbers.
  • Each storage bank BANK has the same storage capacity, for example, the DRAM memory capacity is 8Gb.
  • the capacity of each bank BANK is 1Gb, and each bank BANK in the DRAM memory has its own bank address, which is used to access the DRAM memory (such as reading, writing or refreshing)
  • first find the corresponding storage bank BANK and then find the corresponding storage unit in the storage bank BANK.
  • a DRAM memory having 16 BANKs is taken as an example for description.
  • Each memory bank BANK is divided into three memory blocks in the column direction, and each memory block has a memory array.
  • the memory array includes a number of memory cells arranged in rows and columns.
  • the three memory blocks The block includes a first storage block 31, a second storage block 32, and a third storage block 33 arranged in sequence in the column direction.
  • the first storage block 31, the second storage block 32, and the third storage block 33 are respectively associated with corresponding rows.
  • the decoding circuit XDEC and the column decoding circuit YDEC are connected (it should be noted that, in this embodiment, the column direction refers to the Y axis direction, and the row direction refers to the X axis direction).
  • each storage bank BANK By dividing each storage bank BANK into three storage blocks (the first storage block 31, the second storage block 32, and the third storage block 33) in the column direction, on the one hand, when the capacity of each storage bank BANK is constant , Divide each storage bank BANK into three storage blocks in the column direction, and the length of each storage block in the row direction will be shorter (as opposed to the solution of dividing each storage bank into two storage blocks in the row direction), As a result, the length of the control circuit itself will be shortened and the distance between the control circuit and the corresponding memory cell in the storage array in each memory block will be shortened, so a large drive is not required, power consumption is reduced, and the length of the data transmission circuit itself It will be shorter and the distance between the data transmission line and the corresponding memory cell in the memory array in each memory block will also be shorter, so that the parasitic resistance and parasitic capacitance generated by the data transmission line are reduced, and the data transmission rate and data transmission are accurate.
  • the length of the memory block in the memory bank BANK is shortened, which can optimize the layout of the memory bank BANK in the DRAM memory, so that the length and width comparison of the DRAM memory is optimized, which is conducive to packaging.
  • the storage capacities of the first storage block 31, the second storage block 32, and the third storage block 33 are equal.
  • the first memory block 31, the second memory block 32, and the third memory block 33 in each memory block BANK are respectively connected to the first column decoding circuit (YDEC) 51 and the second column decoding circuit.
  • the circuit (YDEC) 52 is connected to the third column decoding circuit (YDEC) 53, and the first storage block 31, the second storage block 32, and the third storage block 33 in each of the storage blocks BANK are also connected to the first row
  • the decoding circuit (XDEC) 41 and the second row decoding circuit (XDEC) 42 are connected.
  • the first column decoding circuit (YDEC) 51, the second column decoding circuit (YDEC) 52 and the third column decoding circuit (YDEC) 53 are respectively used for the first storage block 31, the second storage block 32 and the third storage
  • the corresponding memory cells in the block 33 perform column addressing.
  • the first row decoding circuit (XDEC) 41 and the second row decoding circuit (XDEC) 42 are the first storage block 31, the second storage block 32, and the third storage block 33. Row addressing of the storage unit of the drink in the storage bank, so that the corresponding storage unit of the three storage blocks in a storage bank BANK can be accessed at the same time (including reading, writing or refreshing), which improves the operating efficiency of the DRAM memory. .
  • the first row decoding circuit 41 is connected to all the storage units in the first storage block 31 and some storage units in the second storage block 32, and is used to compare the storage units in the first storage block 31
  • the storage unit and some storage units in the second storage block 32 perform row addressing
  • the second row decoding circuit 42 and the third storage block 33 are connected to all storage units and some storage units in the second storage block 32, It is used to perform row addressing on all the storage cells in the third storage block 33 and some storage cells in the second storage block 32. Therefore, the row decoding (decoding) of the memory cells in the three memory blocks in one memory bank BANK can be shared and controlled, and the area of the chip is saved.
  • the line area 61 There is a line area 61 between the two adjacent rows of memory banks BANK, and the line area 61 has a control line and a data transmission line, and the control line is used to send control instructions and/or addresses to the corresponding memory bank,
  • the control instructions include instructions such as write instructions, read instructions, and refresh instructions.
  • the addresses include the bank address of each bank BANK and the row address and column address of the corresponding memory cell in the corresponding memory block in the bank BANK.
  • the data transmission line is used to transmit data to or read data from the corresponding storage unit in the corresponding storage bank BANK.
  • the substrate also has a pad area 71.
  • the pad area 71 is generally located around the bank BANK array.
  • the pad area 71 has a plurality of first pad areas and a plurality of second pad areas.
  • a pad area is connected with the control circuit, and the plurality of second pad areas are connected with the data transmission circuit.
  • the process of addressing the DRAM storage is generally to first specify the bank address of the bank BANK, then specify the row address, and then refer to the column address.

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Abstract

一种DRAM存储器，包括：衬底；位于所述衬底上呈行列排布的若干存储库，每一个存储库在列方向上被分为三个存储块，所述每一个存储块中均具有呈行列排布的若干存储单元。通过将每一个存储库列方向上分为三个存储块，一方面，在每一个存储库容量一定的情况下，在列方向上将每一个存储库分为三个存储块，每一个存储块在行方向上的长度会变短，使得控制线路和数据传输线路到每一个存储块中的存储阵列中相应的存储单元的距离会变短，因而可以不需要很大的驱动，并且使得数据传输线路产生的寄生电阻和寄生电容减小，使得数据传输速率和数据传输准确性提升，降低功耗。

Description

DRAM存储器 技术领域
本发明涉及存储器领域，尤其涉及一种DRAM存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，其存储阵列区由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
现有DRAM存储器组织架构包括若干存储库(BANK)，每一个存储库(BANK)均是分成左右两个大小相同的存储块。但是现有的组织架构DRAM存储器在工作时存在功耗较大以及数据传输速率和数据传输准确性仍有待提升的问题。
发明内容
本发明所要解决的技术问题是怎样减小DRAM存储器功耗以及怎样提高数据传输速率和数据传输准确性。
为此，本发明提供了一种DRAM存储器，包括：
衬底；
位于所述衬底上呈行列排布的若干存储库，每一个存储库在列方向上被分为三个存储块，所述每一个存储块中均具有呈行列排布的若干存储单元。
可选的，所述三个存储块包括在列方向上依次排布的第一存储块、第二存储块和第三存储块。
可选的，所述每一个存储块中的所述第一存储块、第二存储块和第三存储块分别与第一列解码电路、第二列解码电路和第三列解码电路连接。
可选的，所述每一个存储块中的所述第一存储块、第二存储块和第三存储块还与第一行解码电路和第二行解码电路连接。
可选的，所述第一行解码电路与所述第一存储块中所有的存储单元以及第二存储块中部分存储单元连接，用于对第一存储块在所有的存储单元以及第二 存储块中部分存储单元进行行寻址，所述第二行解码电路与所述第三存储块在所有的存储单元以及第二存储块中部分存储单元连接，用于对第三存储块在所有的存储单元以及第二存储块中部分存储单元进行行寻址。
可选的，所述第一存储块、第二存储块和第三存储块的存储容量相等。
可选的，两相邻列的存储库之间具有线路区，所述线路区中具有控制线路和数据传输线路，所述控制线路用于向对应的存储库发送控制指令和/或地址，所述数据传输线路用于向对应存储库中对应的存储单元传送数据或者从该存储单元中读取数据。
可选的，所述衬底上还具有焊盘区，所述焊盘区中具有若干第一焊盘和第二焊盘，所述第一焊盘与控制线路连接，所述第二焊盘与数据传输线路连接。
与现有技术相比，本发明技术方案具有以下优点：
本发明的DRAM存储器，包括：衬底；位于所述衬底上呈行列排布的若干存储库，每一个存储库在列方向上被分为三个存储块，所述每一个存储块中均具有呈行列排布的若干存储单元。通过将每一个存储库列方向上分为三个存储块，一方面，在每一个存储库容量一定的情况下，在列方向上将每一个存储库分为三个存储块，每一个存储块在行方向上的长度会变短(相对于在行方向上将每一个存储库分成两个存储块的方案)，使得控制线路本身长度会变短并且控制线路到每一个存储块中的存储阵列中相应的存储单元的距离会变短，因而不需要很大的驱动，降低功耗，并且使得数据传输线路本身长度会变短并且数据传输线路到每一个存储块中的存储阵列中相应的存储单元的距离也会变短，使得数据传输线路产生的寄生电阻和寄生电容减小，使得数据传输速率和数据传输准确性提升，降低功耗；另一方面，存储库中存储块的长度变短，能优化DRAM存储器中存储库的布局，使得DRAM存储器长宽比较为优化，有利于封装的进行。
进一步，所述每一个存储块中的所述第一存储块、第二存储块和第三存储块分别与第一列解码电路、第二列解码电路和第三列解码电路连接，所述每一个存储块中的所述第一存储块、第二存储块和第三存储块还与第一行解码电路和第二行解码电路连接。所述第一列解码电路、第二列解码电路和第三列解码电路分别用于对第一存储块、第二存储块和第三存储块中对应的存储单元进行 列寻址，所述第一行解码电路和第二行解码电路第一存储块、第二存储块和第三存储块中对饮的存储单元进行行寻址，因而可以同时对一个存储库中三个存储块中对应的存储单元同时进行访问(包括读取、写入或刷新)，提高了DRAM存储器的运行效率。
在一实施例中，所述第一行解码电路与所述第一存储块中所有的存储单元以及第二存储块中部分存储单元连接，用于对第一存储块在所有的存储单元以及第二存储块中部分存储单元进行行寻址，所述第二行解码电路与所述第三存储块在所有的存储单元以及第二存储块中部分存储单元连接，用于对第三存储块在所有的存储单元以及第二存储块中部分存储单元进行行寻址。因而使得一个存储库中三个存储块中存储单元的行解码(译码)可以共享控制，节省了芯片的面积。
附图说明
图1为本发明一实施例中DRAM存储器的结构示意图；
图2为本发明另一实施例中DRAM存储器的结构示意图。
具体实施方式
如背景技术所言，现有的组织架构DRAM存储器在工作时时存在功耗较大以及数据传输速率和数据传输准确性仍有待提升的问题。
参考图1，图1为本发明一实施例中DRAM存储器的结构示意图，所述DRAM存储器包括：若干行列(行方向为图1中X轴方向，列方向为图1中Y轴方向)排布的存储库BANK，图1中以8个存储库BANK作为示例进行说明，所述每个存储库BANK均分成左右两个大小相同的存储块，包括第一存储块21和第二存储块22，第一存储块21和第二存储块22中包括存储阵列或行列排布的若干存储单元，第一存储块21和第二存储块22分别与对应的行解码电路YDEC和列解码电路XDEC连接，相邻行之间的存储库之间设置有控制线路和数据传输线路，所述控制线路用于向对应的存储库BANK传输控制信号，所述数据传输线路用于向对应的存储单元中传输数据。前述组织架构DRAM存储器其沿行方向(X轴方向)的长度较长，相应的控制线路和数据传输线路的长度也要较长，且控制线路和数据传输线路到每一个存储单元的距离也较长，因而增加了功耗，并且使得控制线路和数据传输线路产生的寄生电阻 和寄生电容增大，使得数据传输速率和数据传输准确性下降。此外，行方向(X轴方向)长度过长，使得长宽比例不够优化，会直接影响封装，可能无法满足封装要求。
为此，本发明提供了一种DRAM存储器，包括：衬底；位于所述衬底上呈行列排布的若干存储库，每一个存储库在列方向上被分为三个存储块，所述每一个存储块中均具有呈行列排布的若干存储单元。通过将每一个存储库列方向上分为三个存储块，一方面，在每一个存储库容量一定的情况下，在列方向上将每一个存储库分为三个存储块，每一个存储块在行方向上的长度会变短(相对于在行方向上将每一个存储库分成两个存储块的方案)，使得控制线路本身长度会变短并且控制线路到每一个存储块中的存储阵列中相应的存储单元的距离会变短，因而不需要很大的驱动，降低功耗，并且使得数据传输线路本身长度会变短并且数据传输线路到每一个存储块中的存储阵列中相应的存储单元的距离也会变短，使得数据传输线路产生的寄生电阻和寄生电容减小，使得数据传输速率和数据传输准确性提升，降低功耗；另一方面，存储库中存储块的长度变短，能优化DRAM存储器中存储库的布局，使得DRAM存储器长宽比较为优化，有利于封装的进行。
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在详述本发明实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
图2为本发明另一实施例中DRAM存储器的结构示意图。
参考图2，所述DRAM存储器，包括：
衬底(图中未示出)；
位于所述衬底上呈行列排布的若干存储库BANK，每一个存储库BANK在列方向上被分为三个存储块(31/32/33)，所述每一个存储块(31/32/33)中均具有呈行列排布的若干存储单元。
DRAM存储器一般分为若干存储库BANK，一个DRAM存储器中存储库BANK的数量可以为4个、8个、16个或其他数量，每一个存储库BANK的 存储容量相同，比如DRAM存储器容量为8Gb，相应的存在8个存储库BANK时，每一个存储库BANK的容量为1Gb，DRAM存储器中每一个存储库BANK具有各自的库地址，在对DRAM存储器进行访问(比如读取、写入或刷新)时，先找到对应的存储库BANK，然后找到所述存储库BANK中对应的存储单元。本实施例中，参考图2，以DRAM存储器具有16个BANK作为示例进行说明。
每一个存储库BANK在列方向上被分为三个存储块，每一个存储块中具有存储阵列，所述存储阵列包括呈行列排布的若干存储单元，本实施例中，所述三个存储块包括在列方向上依次排布的第一存储块31、第二存储块32和第三存储块33，第一存储块31、第二存储块32和第三存储块33分别与对应的行解码电路XDEC和列解码电路YDEC连接(需要说明的是，本实施例中，所述列方向指Y轴方向，行方向指X轴方向)。通过将每一个存储库BANK列方向上分为三个存储块(第一存储块31、第二存储块32和第三存储块33)，一方面，在每一个存储库BANK容量一定的情况下，在列方向上将每一个存储库BANK分为三个存储块，每一个存储块在行方向上的长度会变短(相对于在行方向上将每一个存储库分成两个存储块的方案)，使得控制线路本身长度会变短并且控制线路到每一个存储块中的存储阵列中相应的存储单元的距离会变短，因而不需要很大的驱动，降低功耗，并且使得数据传输线路本身长度会变短并且数据传输线路到每一个存储块中的存储阵列中相应的存储单元的距离也会变短，使得数据传输线路产生的寄生电阻和寄生电容减小，使得数据传输速率和数据传输准确性提升，降低功耗；另一方面，存储库BANK中存储块的长度变短，能优化DRAM存储器中存储库BANK的布局，使得DRAM存储器长宽比较为优化，有利于封装的进行。
在一实施例中，所述第一存储块31、第二存储块32和第三存储块33的存储容量相等。
在一实施例中，所述每一个存储块BANK中的所述第一存储块31、第二存储块32和第三存储块33分别与第一列解码电路(YDEC)51、第二列解码电路(YDEC)52和第三列解码电路(YDEC)53连接，所述每一个存储块BANK中的所述第一存储块31、第二存储块32和第三存储块33还与第一行 解码电路(XDEC)41和第二行解码电路(XDEC)42连接。所述第一列解码电路(YDEC)51、第二列解码电路(YDEC)52和第三列解码电路(YDEC)53分别用于对第一存储块31、第二存储块32和第三存储块33中对应的存储单元进行列寻址，所述第一行解码电路(XDEC)41和第二行解码电路(XDEC)42第一存储块31、第二存储块32和第三存储块33中对饮的存储单元进行行寻址，因而可以同时对一个存储库BANK中三个存储块中对应的存储单元同时进行访问(包括读取、写入或刷新)，提高了DRAM存储器的运行效率。
在一实施例中，所述第一行解码电路41与所述第一存储块31中所有的存储单元以及第二存储块32中部分存储单元连接，用于对第一存储块31在所有的存储单元以及第二存储块32中部分存储单元进行行寻址，所述第二行解码电路42与所述第三存储块33在所有的存储单元以及第二存储块32中部分存储单元连接，用于对第三存储块33在所有的存储单元以及第二存储块32中部分存储单元进行行寻址。因而使得一个存储库BANK中三个存储块中存储单元的行解码(译码)可以共享控制，节省了芯片的面积。
所述两相邻列的存储库BANK之间具有线路区61，所述线路区61中具有控制线路和数据传输线路，所述控制线路用于向对应的存储库发送控制指令和/或地址，所述控制指令包括写入指令、读取指令和刷新等指令，所述地址包括每个存储库BANK的库地址以及存储库BANK中对应的存储块中相应存储单元的行地址和列地址，所述数据传输线路用于向对应存储库BANK中对应的存储单元传送数据或者从该存储单元中读取数据。
所述衬底上还具有焊盘区71，焊盘区71一般位于存储库BANK阵列周围，所述焊盘区71中具有若干第一焊盘区和若干第二焊盘区，所述若干第一焊盘区与控制线路连接，所述若干第二焊盘区与数据传输线路连接。
在一实施例中，所述DRAM存储进行寻址的流程一般是先指定存储库BANK的库地址，再指定行地址，然后指列地址。
需要说明的是，本实施例中关于存储结构其他限定或描述在本实施例中不再赘述，具体请参考前述存储结构形成过程实施例中的相应限定或描述。
本发明虽然已以较佳实施例公开如上，但其并不是用来限定本发明，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方 法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。

Claims (8)

  1. 一种DRAM存储器，其特征在于，包括：
    衬底；
    位于所述衬底上呈行列排布的若干存储库，每一个存储库在列方向上被分为三个存储块，所述每一个存储块中均具有呈行列排布的若干存储单元。
  2. 如权利要求1所述的DRAM存储器，其特征在于，所述三个存储块包括在列方向上依次排布的第一存储块、第二存储块和第三存储块。
  3. 如权利要求2所述的DRAM存储器，其特征在于，所述每一个存储块中的所述第一存储块、第二存储块和第三存储块分别与第一列解码电路、第二列解码电路和第三列解码电路连接。
  4. 如权利要求3所述的DRAM存储器，其特征在于，所述每一个存储块中的所述第一存储块、第二存储块和第三存储块还与第一行解码电路和第二行解码电路连接。
  5. 如权利要求3所述的DRAM存储器，其特征在于，所述第一行解码电路与所述第一存储块中所有的存储单元以及第二存储块中部分存储单元连接，用于对第一存储块在所有的存储单元以及第二存储块中部分存储单元进行行寻址，所述第二行解码电路与所述第三存储块在所有的存储单元以及第二存储块中部分存储单元连接，用于对第三存储块在所有的存储单元以及第二存储块中部分存储单元进行行寻址。
  6. 如权利要求2所述的DRAM存储器，其特征在于，所述第一存储块、第二存储块和第三存储块的存储容量相等。
  7. 如权利要求1所述的DRAM存储器，其特征在于，两相邻列的存储库之间具有线路区，所述线路区中具有控制线路和数据传输线路，所述控制线路用于向对应的存储库发送控制指令和/或地址，所述数据传输线路用于向对应存储库中对应的存储单元传送数据或者从该存储单元中读取数据。
  8. 如权利要求7所述的DRAM存储器，其特征在于，还具有焊盘区，所述焊盘区中具有若干第一焊盘和第二焊盘，所述第一焊盘与控制线路连接，所述第二焊盘与数据传输线路连接。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11538515B2 (en) 2019-09-24 2022-12-27 Changxin Memory Technologies, Inc. DRAM memory
US11698830B2 (en) 2020-09-14 2023-07-11 Changxin Memory Technologies, Inc. Semiconductor memory

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112992258B (zh) * 2021-04-14 2022-05-31 长鑫存储技术有限公司 含片上ecc的信号处理电路和存储器

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5914907A (en) * 1998-02-03 1999-06-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device capable of increasing chip yields while maintaining rapid operation
US5943285A (en) * 1996-08-05 1999-08-24 Kabushiki Kaisha Toshiba Arrangement of memory blocks and pads
US6069812A (en) * 1997-11-21 2000-05-30 Samsung Electronics Co., Ltd. Integrated circuit memory devices including rows of pads extending parallel to the short sides of the integrated circuit
US6121677A (en) * 1997-12-31 2000-09-19 Samsung Electronics Co. Reduced size integrated circuits and methods using test pads located in scribe regions of integrated circuits wafers
US6329678B1 (en) * 1998-12-04 2001-12-11 Hyundai Electronics Industries Co., Ltd. Semiconductor memory array
US6448602B1 (en) * 1995-09-06 2002-09-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with improved arrangement of memory blocks and peripheral circuits

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10144086A (ja) * 1996-11-14 1998-05-29 Sharp Corp 不揮発性半導体記憶装置
DE10392539T5 (de) * 2002-04-10 2005-06-02 Hynix Semiconductor Inc., Ichon Speicherchiparchitektur mit nichtrechteckigen Speicherbänken und Verfahren zum Anordnen von Speicherbänken
US7990798B2 (en) * 2007-10-15 2011-08-02 Qimonda Ag Integrated circuit including a memory module having a plurality of memory banks
JP5624715B2 (ja) * 2008-10-30 2014-11-12 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置
CN112634955A (zh) 2019-09-24 2021-04-09 长鑫存储技术有限公司 Dram存储器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6448602B1 (en) * 1995-09-06 2002-09-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with improved arrangement of memory blocks and peripheral circuits
US5943285A (en) * 1996-08-05 1999-08-24 Kabushiki Kaisha Toshiba Arrangement of memory blocks and pads
US6069812A (en) * 1997-11-21 2000-05-30 Samsung Electronics Co., Ltd. Integrated circuit memory devices including rows of pads extending parallel to the short sides of the integrated circuit
US6121677A (en) * 1997-12-31 2000-09-19 Samsung Electronics Co. Reduced size integrated circuits and methods using test pads located in scribe regions of integrated circuits wafers
US5914907A (en) * 1998-02-03 1999-06-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device capable of increasing chip yields while maintaining rapid operation
US6329678B1 (en) * 1998-12-04 2001-12-11 Hyundai Electronics Industries Co., Ltd. Semiconductor memory array

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3937175A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11538515B2 (en) 2019-09-24 2022-12-27 Changxin Memory Technologies, Inc. DRAM memory
US11698830B2 (en) 2020-09-14 2023-07-11 Changxin Memory Technologies, Inc. Semiconductor memory

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