WO2021054617A1 - Transistor à couches minces et son procédé de fabrication - Google Patents

Transistor à couches minces et son procédé de fabrication Download PDF

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WO2021054617A1
WO2021054617A1 PCT/KR2020/010874 KR2020010874W WO2021054617A1 WO 2021054617 A1 WO2021054617 A1 WO 2021054617A1 KR 2020010874 W KR2020010874 W KR 2020010874W WO 2021054617 A1 WO2021054617 A1 WO 2021054617A1
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Prior art keywords
layer
insulating layer
film transistor
thin film
interlayer insulating
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PCT/KR2020/010874
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English (en)
Korean (ko)
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지광환
박상희
장기석
이광흠
김도형
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엘지디스플레이 주식회사
한국과학기술원
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Priority claimed from KR1020200059831A external-priority patent/KR20210033878A/ko
Application filed by 엘지디스플레이 주식회사, 한국과학기술원 filed Critical 엘지디스플레이 주식회사
Publication of WO2021054617A1 publication Critical patent/WO2021054617A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present specification relates to a thin film transistor, and more particularly, to provide a thin film transistor having excellent switching characteristics while reducing an area occupied in a plane, and a method of manufacturing the same.
  • the display device includes a display panel in which a plurality of subpixels are arranged, and various driving circuits such as a source driving circuit and a gate driving circuit for driving the display panel.
  • a display panel includes transistors, various electrodes, and various signal wirings formed on a glass substrate, and driving circuits that can be implemented as integrated circuits are mounted on a printed circuit, and electrically connected to the display panel through the printed circuit. Connected.
  • driving circuits that can be implemented as integrated circuits are mounted on a printed circuit, and electrically connected to the display panel through the printed circuit. Connected.
  • such an existing structure is suitable for a large display device, but is not suitable for a small display device.
  • TFTs thin film transistors
  • the etching process for the trench structure extending in the vertical direction is difficult, and when the oxide semiconductor is used as the active layer, the surface is often damaged or etched together during the process of forming the insulating layer. Occurs.
  • the inventors of the present specification invented a thin film transistor having excellent switching characteristics while reducing an occupied area by forming a buffer layer between an interlayer insulating layer and an active layer on a semiconductor substrate, and a method of manufacturing the same.
  • the thin film transistor according to the exemplary embodiment of the present specification includes a semiconductor substrate, an interlayer insulating layer having a trench structure disposed on the semiconductor substrate, a source electrode and a drain electrode disposed spaced apart from the top of the interlayer insulating layer, and an interlayer insulating layer.
  • a buffer layer disposed on the inner sidewall, an active layer having a trench structure disposed above the source electrode and drain electrode, and the buffer layer, a gate insulating layer having a trench structure disposed above the active layer, and a trench structure disposed above the gate insulating layer It consists of a gate electrode.
  • the interlayer insulating layer is made of at least one insulating material of silicon oxide (SiOx), silicon nitride (SiNx), and aluminum oxide (Al 2 O 3 ).
  • the buffer layer is made of an insulating material having excellent interfacial properties.
  • the buffer layer extends to a central portion of the trench structure of the interlayer insulating layer.
  • the active layer is made of an oxide semiconductor or low-temperature polysilicon.
  • the thin film transistor according to the exemplary embodiment of the present specification further includes a protective layer between the active layer and the gate insulating layer.
  • the gate insulating layer is made of at least one insulating material of silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx), and hafnium oxide (HfOx).
  • a vertical channel length from the lower surface of the source electrode or the drain electrode to the lower surface of the active layer has a value of 100 nm to 1,000 nm.
  • a method of manufacturing a thin film transistor includes the steps of sequentially laminating a semiconductor substrate, an interlayer insulating layer, and an electrode metal, and etching a part of the interlayer insulating layer and the electrode metal to obtain a spaced apart source electrode.
  • Forming an interlayer insulating layer having a drain electrode and a trench structure forming a buffer layer on the inner sidewall of the interlayer insulating layer, forming an active layer having a trench structure on top of the source electrode and drain electrode, and the buffer layer, and the active layer And forming a gate insulating layer having a trench structure to cover the trench structure, and forming a gate electrode having a trench structure over the gate insulating layer.
  • the interlayer insulating layer is one of plasma chemical vapor deposition (PECVD), atomic layer deposition (ALD) for depositing a thin film using a surface chemical reaction, and sputtering. Evaporation is carried out in the above manner.
  • PECVD plasma chemical vapor deposition
  • ALD atomic layer deposition
  • the interlayer insulating layer and the electrode metal are etched using the same mask.
  • an interlayer insulating layer and a metal for an electrode are etched by a dry etching method or a wet etching method.
  • the buffer layer is formed by etching a central portion of an insulating material deposited by a plasma chemical vapor deposition (PECVD) or plasma atomic layer deposition (PEALD) method, and an inner sidewall of the interlayer insulating layer. It is formed by leaving only the insulating material.
  • PECVD plasma chemical vapor deposition
  • PEALD plasma atomic layer deposition
  • the buffer layer is a plasma chemical vapor deposition (PECVD) or plasma atomic layer deposition (PEALD) etching a central portion of the deposited insulating material, the inside of the interlayer insulating layer It is formed by leaving an insulating material on the sidewall and the upper part of the interlayer insulating layer.
  • PECVD plasma chemical vapor deposition
  • PEALD plasma atomic layer deposition
  • the active layer is deposited by sputtering or plasma atomic layer deposition (PEALD).
  • PEALD plasma atomic layer deposition
  • the method of manufacturing a thin film transistor according to an exemplary embodiment of the present specification further includes forming a protective layer having a trench structure on an upper portion of the active layer by using a plasma atomic layer deposition (PEALD) method.
  • PEALD plasma atomic layer deposition
  • the gate insulating layer is formed by plasma atomic layer deposition (PEALD) or plasma chemical vapor deposition (PECVD).
  • PEALD plasma atomic layer deposition
  • PECVD plasma chemical vapor deposition
  • the gate electrode is formed by dry etching.
  • a thin film transistor includes a semiconductor substrate, an interlayer insulating layer having a trench structure disposed on the semiconductor substrate, a buffer layer disposed along the inner sidewall of the interlayer insulating layer, and a trench structure disposed to cover the buffer layer. Protection disposed between the active layer of, the source electrode and the drain electrode spaced apart from the top of the active layer, the gate insulating layer and the gate electrode sequentially stacked in the trench structure of the active layer, and the source electrode, the drain electrode, and the gate electrode. Includes layers.
  • the buffer layer is disposed to cover the interlayer insulating layer.
  • the thin film transistor according to the exemplary embodiment of the present specification includes a semiconductor substrate, an interlayer insulating layer having a trench structure disposed on the semiconductor substrate, an active layer having a trench structure disposed above the interlayer insulating layer, and spaced apart from the upper or lower portion of the active layer.
  • the source electrode and the drain electrode are disposed, and the gate insulating layer and the gate electrode disposed between the source electrode and the drain electrode at the upper or lower part of the active layer, and between the interlayer insulating layer and the active layer, along the inner sidewall of the interlayer insulating layer. It includes the arranged buffer layer.
  • 1 is a graph showing a change in a threshold voltage according to a drain voltage in a case where the channel length of a thin film transistor is long (long channel) and short (short channel),
  • DIBL drain induction barrier reduction
  • FIG. 3 is a cross-sectional view of a thin film transistor according to an embodiment of the present specification
  • FIG. 4 is a plan view of a thin film transistor according to an embodiment of the present specification.
  • FIG. 5 is a flowchart illustrating a method of manufacturing a thin film transistor according to an embodiment of the present specification
  • 6A to 6G are cross-sectional views illustrating a manufacturing process of a thin film transistor according to an exemplary embodiment of the present specification
  • FIG. 7 is a cross-sectional view of a thin film transistor according to another embodiment of the present specification.
  • FIG. 8 is a diagram showing a change in resistance values corresponding to a horizontal channel length and a vertical channel length in a thin film transistor according to an embodiment of the present specification
  • FIG. 9 is a graph showing a change in driving current according to a change in a vertical channel length in a thin film transistor according to an embodiment of the present specification
  • FIG. 10 is a graph illustrating a change in driving current according to a change in a horizontal channel length in a thin film transistor according to an exemplary embodiment of the present specification.
  • node A passes through another node
  • it may include a case where a signal is transmitted to the B node.
  • First, second, etc. are used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be a second component within the technical idea of the present specification.
  • the thin film transistor When a thin film transistor is used in a display device, the thin film transistor may play a role of switching a subpixel that is a basic unit for displaying an image.
  • the area occupied by the thin film transistor directly determines the size of the subpixel of the display device, and thus, as the size of the thin film transistor is reduced, the degree of integration and resolution of the display device can be improved.
  • a short channel structure in which a channel between a source electrode and a drain electrode is formed short is used.
  • DIBL Drain Induced Barrier Lowering
  • 1 is a graph showing a change in a threshold voltage according to a drain voltage in a case where the channel length of a thin film transistor is long (long channel) and short (short channel).
  • the threshold voltage Vt is kept constant without being affected by the magnitude of the voltage applied to the drain electrode.
  • the thin film transistor has a threshold voltage (Vt) of about 0.7 V.
  • the barrier between the drain electrode and the source electrode is lowered, so that the thermoelectric current moving from the source electrode to the drain electrode increases.
  • DIBL drain induction barrier reduction
  • FIG 3 is a cross-sectional view of a thin film transistor according to an exemplary embodiment of the present specification.
  • the thin film transistor 100 includes a semiconductor substrate 110, an interlayer insulating layer 120, a source electrode 130 and a drain electrode 140 disposed spaced apart from each other, and an interlayer.
  • a buffer layer 150 positioned on an inner sidewall of the insulating layer 120, an active layer 160 and a protective layer 170 having a trench structure, a gate insulating layer 180 having a trench structure, and a gate electrode 190 may be included. .
  • the semiconductor substrate 110 may be a growth substrate of various types, such as a sapphire substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a silicon (Si) substrate, an aluminum nitride (AlN) substrate, and the like.
  • the interlayer insulating layer 120 is laminated on the semiconductor substrate 110, and is made of an insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (Al 2 O 3 ), or a stacked structure thereof. Can be done.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • Al 2 O 3 aluminum oxide
  • the interlayer insulating layer 120 can be deposited at high speed through a plasma enhanced chemical vapor deposition (PECVD) method, but plasma enhanced atomic layer deposition (PEALD) or sputtering, etc. You could also use the method. In this case, the thickness of the interlayer insulating layer 120 may be adjusted according to the characteristics of the thin film transistor 100.
  • PECVD plasma enhanced chemical vapor deposition
  • PEALD plasma enhanced atomic layer deposition
  • sputtering etc. You could also use the method.
  • the thickness of the interlayer insulating layer 120 may be adjusted according to the characteristics of the thin film transistor 100.
  • the source electrode 130 and the drain electrode 140 disposed on the interlayer insulating layer 120 are indium tin oxide (ITO) and indium zinc oxide according to the structure and performance of the thin film transistor 100.
  • ITO indium tin oxide
  • Zinc Oxide; IZO Zinc Oxide
  • a metal or alloy such as molybdenum (Mo), aluminum (Al), titanium (Ti), titanium nitride (TiN), tungsten titanium (TiW), or a laminated structure thereof Can be done.
  • the source electrode 130 and the drain electrode 140 may be formed by patterning an electrode material stacked on the interlayer insulating layer 120. In this process, a trench structure is formed by etching the center portion of the source electrode 130 and the drain electrode 140 and a part of the interlayer insulating layer 120 positioned therein using the same mask, thereby forming a trench structure. ) To form the buffer layer 150 on the inner sidewall.
  • a dry etching method may be used to remove a part of the interlayer insulating layer 120 positioned between the source electrode 130 and the drain electrode 140, but a wet etch method is used. You could also use it.
  • the buffer layer 150 is disposed in a vertical direction along the inner sidewall of the interlayer insulating layer 120 having a trench structure.
  • the buffer layer 150 improves the surface quality of the interlayer insulating layer 120 damaged in the etching process, and is applied to the drain electrode 140 even if the channel length between the source electrode 130 and the drain electrode 140 is shortened.
  • the effect of reducing the drain induction barrier (DIBL) in which the conductive band of the source electrode 130 is lowered by the voltage may be weakened.
  • DIBL drain induction barrier
  • an insulating material having excellent interfacial properties is deposited on the surface of the interlayer insulating layer 120 formed through etching, and the central portion of the interlayer insulating layer 120 is removed through dry etching. It can be formed only on the inner sidewall.
  • the insulating material for forming the buffer layer 150 may be deposited by a plasma chemical vapor deposition (PECVD) or plasma atomic layer deposition (PEALD) method.
  • interlayer insulation is performed by not removing the central portion of the interlayer insulating layer 120. It may be formed to extend to the central portion as well as the inner sidewall of the layer 120.
  • the active layer 160 is formed to cover partial regions of the source electrode 130 and the drain electrode 140, the buffer layer 150 inside the trench structure, and the interlayer insulating layer 120, and thus the source electrode 130 and the drain electrode A channel between 140 is formed. As such, a vertical channel is formed between the source electrode 130 and the drain electrode 140 due to the active layer 160 formed in a trench structure.
  • the active layer 160 is less affected by the drain-inducing barrier reduction (DIBL) effect, and has excellent operating characteristics indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium gallium zinc tin oxide (IGZTO), and indium zinc. It may be made of an oxide semiconductor such as oxide (IZO), indium oxide (InOx), indium aluminum oxide (InAlOx), indium silicon oxide (InSiOx), and zinc tin oxide (ZTO). Alternatively, low temperature poly-silicon (LTPS) may be used depending on the performance of the thin film transistor 100.
  • DIBL drain-inducing barrier reduction
  • the active layer 160 may be deposited by a sputtering method, but may also be deposited by a plasma atomic layer deposition (PEALD) method.
  • PEALD plasma atomic layer deposition
  • excellent step coverage can be provided to the thin film transistor 100 with a short channel length, and the oxidation effect of the metal electrode can be reduced during the oxide semiconductor formation process. There is an advantage.
  • the protective layer 170 is an active layer 160 in order to minimize damage during a subsequent photolithography, photoresist (PR) peeling process (PR strip), or deposition of the gate insulating layer 180. ) Can be formed on top of.
  • PR photoresist
  • the protective layer 170 may be formed at a level of about 10 nm by a plasma atomic layer deposition (PEALD) method. Alternatively, the protective layer 170 may be omitted.
  • PEALD plasma atomic layer deposition
  • the gate insulating layer 180 is insulated from silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx), and hafnium oxide (HfOx) after patterning the protective layer 170 by a method such as wet etching. It can be formed in a single layer or stacked form using a material.
  • the gate insulating layer 180 may be formed by a plasma atomic layer deposition (PEALD) or plasma chemical vapor deposition (PECVD) method, and the channel length, threshold voltage, leakage current, and drain induction barrier of the thin film transistor 100 are reduced ( The deposition thickness may be determined in consideration of the DIBL) effect.
  • PEALD plasma atomic layer deposition
  • PECVD plasma chemical vapor deposition
  • the gate electrode 190 may be formed of a metal or alloy similar to the source electrode 130 and the drain electrode 140 on the gate insulating layer 180.
  • the thickness of the trench region may be reduced due to poor step coverage of the inner sidewall portion forming the trench structure. Therefore, when the pattern of the gate electrode 190 is formed by wet etching, there is a possibility that a pattern defect or a short circuit may occur on the inner sidewall of the trench structure due to the isotropic etch property, so that the gate electrode 190 is dry-etched. It is preferable to form the pattern.
  • FIG. 4 is a plan view of a thin film transistor according to an exemplary embodiment of the present specification.
  • the thin film transistor 100 includes an interlayer insulating layer 120, an active layer 160 formed between the source electrode 130 and the drain electrode 140, and a gate insulating layer. Since (180) and the gate electrode 190 are formed in a trench structure elongated in the vertical direction, the channel length L between the source electrode 130 and the drain electrode 140 is reduced.
  • DIBL drain induction barrier reduction
  • the buffer layer 150 is formed along the inner sidewall of the interlayer insulating layer 120 formed in a trench structure.
  • the surface quality may be improved and a drain induction barrier reduction (DIBL) effect caused by a short channel length L between the source electrode 130 and the drain electrode 140 may be weakened.
  • DIBL drain induction barrier reduction
  • FIG. 5 is a flowchart illustrating a method of manufacturing a thin film transistor according to an exemplary embodiment of the present specification.
  • 6A to 6G are cross-sectional views illustrating a manufacturing process of a thin film transistor according to an exemplary embodiment of the present specification.
  • a method of manufacturing a thin film transistor includes sequentially stacking a semiconductor substrate 110, an interlayer insulating layer 120, and a metal for an electrode (S100), and interlayer insulation. Etching the layer 120 and the electrode metal to form the source electrode 130 and the drain electrode 140 (S200), forming the buffer layer 150 on the inner sidewall of the interlayer insulating layer 120 (S300) ), forming the active layer 160 and the protective layer 170 having a trench structure (S400), forming the gate insulating layer 180 to cover the active layer 160 and the protective layer 170 (S500), And forming the gate electrode 190 (S600 ).
  • the step of sequentially stacking the semiconductor substrate 110, the interlayer insulating layer 120, and the electrode metal (S100) is, as shown in FIG. 6A, the semiconductor substrate 110 is disposed and the upper portion of the semiconductor substrate 110 After depositing the interlayer insulating layer 120 made of an insulating material on the layer, the electrode metal 135 for forming the source electrode 130 and the drain electrode 140 is stacked thereon.
  • the interlayer insulating layer 120 may be deposited through a method such as plasma chemical vapor deposition (PECVD), plasma atomic layer deposition (PEALD), or sputtering.
  • PECVD plasma chemical vapor deposition
  • PEALD plasma atomic layer deposition
  • sputtering a method such as sputtering.
  • the step of forming the source electrode 130 and the drain electrode 140 by etching the interlayer insulating layer 120 and the electrode metal 135 (S200) is an electrode using a single mask as shown in FIG. 6B. This is a process of forming a trench structure by etching a central portion of the molten metal 135 and a portion of the interlayer insulating layer 120 corresponding thereto.
  • the electrode metal 135 and the interlayer insulating layer 120 may be etched by dry etching or wet etching.
  • an insulating material having excellent interfacial properties is applied to the surface of the interlayer insulating layer 120 formed through etching. After deposition, the central portion of the interlayer insulating layer 120 is removed through dry etching.
  • the insulating material for forming the buffer layer 150 may be deposited by a plasma chemical vapor deposition (PECVD) or plasma atomic layer deposition (PEALD) method.
  • PECVD plasma chemical vapor deposition
  • PEALD plasma atomic layer deposition
  • the interlayer insulating layer 120 When the interlayer insulating layer 120 is formed in a trench structure in order to reduce the channel length between the source electrode 130 and the drain electrode 140 in the thin film transistor 100, the source electrode 130 and the drain electrode 140 There may be a drain induction barrier reduction (DIBL) phenomenon.
  • DIBL drain induction barrier reduction
  • the interlayer insulating layer damaged in the etching process ( 120) can improve the surface quality and weaken the drain induction barrier reduction (DIBL) effect.
  • the buffer layer 150 may be formed not only on the inner sidewall of the interlayer insulating layer 120 but also on the central portion. 6D illustrates a case where the buffer layer 150 extends to the central portion of the interlayer insulating layer 120 as described above.
  • step S400 of forming the active layer 160 and the protective layer 170 having a trench structure as shown in FIG. 6E, a partial region of the source electrode 130 and the drain electrode 140 and the buffer layer inside the trench structure ( 150) and the trench-structured active layer 160 and the protective layer 170 to cover the interlayer insulating layer 120 in sequence.
  • the active layer 160 may be deposited using an oxide semiconductor or low-temperature polysilicon (LTPS) by sputtering or plasma atomic layer deposition (PEALD).
  • LTPS oxide semiconductor or low-temperature polysilicon
  • PEALD plasma atomic layer deposition
  • the protective layer 170 may be deposited by a plasma atomic layer deposition (PEALD) method, or may be omitted.
  • PEALD plasma atomic layer deposition
  • Forming the gate insulating layer 180 to cover the active layer 160 and the passivation layer 170 (S500) is a single layer on the passivation layer 170 using an insulating material, as shown in FIG. 6F. Alternatively, it is a process of forming the gate insulating layer 180 having a trench structure in a stacked form.
  • the gate insulating layer 180 may be formed by plasma atomic layer deposition (PEALD) or plasma chemical vapor deposition (PECVD).
  • PEALD plasma atomic layer deposition
  • PECVD plasma chemical vapor deposition
  • Forming the gate electrode 190 is a process of forming a trench structure by dry etching after depositing an electrode metal on the gate insulating layer 180, as shown in FIG. 6G.
  • a step coverage defect may occur in an inner sidewall portion of the trench structure, and thus a trench structure is formed by dry etching.
  • the thin film transistor 100 manufactured through this process improves the surface quality of the interlayer insulating layer 120 by forming the buffer layer 150 along the inner sidewall of the interlayer insulating layer 120 having a trench structure. Even in the case of a vertical channel in which the channel length L between the source electrode 130 and the drain electrode 140 is shortened due to the active layer 160 having a trench structure formed as a long length, the effect of reducing the drain induction barrier (DIBL) may be weakened. You will be able to.
  • DIBL drain induction barrier
  • the top gate structure in which the gate electrode 190 is formed on the channel layer 160 and the gate insulating layer 180 has been described as an example, but the source electrode 130 and the drain electrode 140 ), and a coplanar structure in which the gate electrode 190 is positioned on the same plane, or a bottom gate in which the gate electrode 190 is positioned below the channel layer 160 and the gate insulating layer 180 ) Structure, and a self-align structure using an etch stopper. The same may be applied to various thin film transistor structures.
  • FIG. 7 is a cross-sectional view of a thin film transistor according to another exemplary embodiment of the present specification.
  • a thin film transistor 100 includes a semiconductor substrate 110, an interlayer insulating layer 120 having a trench structure, a buffer layer 150, an active layer 160, and an active layer ( The source electrode 130 and the drain electrode 140 are spaced apart from the top of the 160, the gate insulating layer 180 and the gate electrode 190, and the source electrode 130 disposed inside the trench structure of the active layer 160. ), the drain electrode 140, and the passivation layer 170 disposed between the gate electrode 190.
  • the gate electrode 190 is disposed inside the trench structure, the source electrode 130 and the drain electrode 140 are disposed at a higher position than the gate electrode 190.
  • the buffer layer 150 and the channel layer 160 having a predetermined thickness may be formed on the interlayer insulating layer 120 in a trench structure.
  • the buffer layer 150 may be formed on a vertical sidewall inside the trench structure in which the gate electrode 190 is disposed, or may extend to a central portion of the trench structure including the vertical sidewall inside the trench structure as shown here. .
  • a gate insulating layer 180 and a gate electrode 190 are sequentially stacked inside the trench structure.
  • the source electrode 130 and the drain electrode 140 may be formed on the left and right upper portions of the trench structure, respectively.
  • the source electrode 130 and the drain electrode 140 use an etch stopper to form the source electrode 130. It may be formed in a self-aligned structure so that no overlap between the and the drain electrode 140 occurs.
  • a protective layer 170 made of an Inter Layer Dielectric (ILD) may be disposed.
  • a vertical channel is formed between the source electrode 130 and the drain electrode 140 due to the active layer 160 having a trench structure that is elongated in the vertical direction. It may mean that a channel is formed so that charges moving from 130) to the drain electrode 140 move in a direction including an up-down direction.
  • the vertical channel means not only the case where the active layer 160 is formed perpendicular to the same reference plane as the semiconductor substrate 110, but also the case where the active layer 160 is inclined at a predetermined angle with respect to the reference plane. Can be used.
  • the inclination varies depending on the etching process, but may have a gradient of about 30 to 90 degrees depending on the lattice surface.
  • the thin film transistor 100 forms the buffer layer 150 along the inner sidewall of the interlayer insulating layer 120 formed in a trench structure, so that the interlayer insulating layer 120 damaged in the etching process. Even if the surface quality of is improved and the channel length L between the source electrode 130 and the drain electrode 140 is shortened, the effect of reducing the drain induction barrier (DIBL) may be weakened.
  • DIBL drain induction barrier
  • the resistance value between the source electrode 130 and the drain electrode 140 varies according to the horizontal channel length in the horizontal direction and the vertical channel length in the vertical direction.
  • the transistor 100 It may affect the driving current flowing in the turned-on state.
  • FIG. 8 is a diagram illustrating a change in resistance values corresponding to a horizontal channel length and a vertical channel length in a thin film transistor according to an exemplary embodiment of the present specification.
  • a channel having a trench structure has a vertical channel length L1 formed in a vertical direction and a horizontal channel length L2 formed in the trench in a horizontal direction. ).
  • the vertical channel length L1 may be defined as a length from the lower surface of the source electrode 130 or the drain electrode 140 to the lower surface of the active layer 160 located inside the trench.
  • the horizontal channel length L2 may be defined as a length between the source electrode 130 and the drain electrode 140.
  • the length between the buffer layers 150 formed inside the trench may be defined as the horizontal channel length L2, but here, the source electrode 130 and the drain electrode 140 may correspond to the channel length L disclosed in FIG. 4. ) Is represented by the horizontal channel length (L2).
  • the driving current Id flowing through the source electrode 130 and the drain electrode 140 is influenced by the vertical channel length L1 and the horizontal channel length L2. Can be received.
  • the horizontal channel length L2 maintains a distance that can minimize the drain induction barrier reduction (DIBL) phenomenon, while maintaining a constant vertical channel length L1. It can be effective to reduce to within range.
  • DIBL drain induction barrier reduction
  • FIG. 9 is a graph showing a change in driving current according to a change in a vertical channel length in a thin film transistor according to an exemplary embodiment of the present specification
  • FIG. 10 is a graph showing a change in driving current according to a change in a horizontal channel length.
  • the vertical channel length L1 of the trench structure in the thin film transistor 100 is 420 nm (in the case of (a)) and in the case of 210 nm ((b) In the case of ), it can be seen that the driving current Id of the thin film transistor 100 increases when the vertical channel length L1 is 210 nm.
  • the vertical channel length L1 may vary depending on the material or size of each layer constituting the thin film transistor 100, but may be formed in the range of 100 nm to 1,000 nm, more preferably 100 nm to 300 nm. It can be formed in a range.
  • the vertical channel length L1 of the trench structure is formed to have the same value (eg, 210 nm), and the horizontal channel length L2 Even if) is changed to the case of 10 ⁇ m (in the case of (a)) and the case of 15 ⁇ m (in the case of (b)), it can be seen that the driving current Id of the driving transistor 100 hardly changes.
  • the thin film transistor 100 having a trench structure it will be effective to form the horizontal channel length L2 to have a sufficient size within a range that can minimize the drain induction barrier reduction (DIBL) phenomenon.
  • DIBL drain induction barrier reduction

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un transistor à couches minces comprenant : un substrat semi-conducteur ; une couche d'isolation inter-couche d'une structure de tranchée ; une électrode de source et une électrode de drain espacées l'une de l'autre ; une couche tampon positionnée sur une paroi latérale interne de la couche d'isolation inter-couche ; une couche d'activation et une couche de protection de la structure de tranchée ; et une couche d'isolation de grille et une électrode de grille de la structure de tranchée.
PCT/KR2020/010874 2019-09-19 2020-08-14 Transistor à couches minces et son procédé de fabrication WO2021054617A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2019-0115605 2019-09-19
KR20190115605 2019-09-19
KR10-2020-0059831 2020-05-19
KR1020200059831A KR20210033878A (ko) 2019-09-19 2020-05-19 박막 트랜지스터 및 그 제조 방법

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11832486B2 (en) 2021-09-14 2023-11-28 Electronics And Telecommunications Research Institute Semiconductor device, display panel, and display device including the same

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Publication number Priority date Publication date Assignee Title
KR20060109376A (ko) * 2005-04-15 2006-10-20 삼성전자주식회사 트렌치 소자 분리 방법
KR20080012084A (ko) * 2006-08-02 2008-02-11 삼성전자주식회사 반도체 소자 및 그 제조 방법
US20090261420A1 (en) * 2008-04-17 2009-10-22 Samsung Electronics Co., Ltd. Recess gate transistor
KR20130075359A (ko) * 2011-12-27 2013-07-05 삼성전자주식회사 게이트 절연층의 형성 방법
KR101339271B1 (ko) * 2012-12-18 2013-12-09 현대자동차 주식회사 반도체 소자의 제조 방법

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Publication number Priority date Publication date Assignee Title
KR20060109376A (ko) * 2005-04-15 2006-10-20 삼성전자주식회사 트렌치 소자 분리 방법
KR20080012084A (ko) * 2006-08-02 2008-02-11 삼성전자주식회사 반도체 소자 및 그 제조 방법
US20090261420A1 (en) * 2008-04-17 2009-10-22 Samsung Electronics Co., Ltd. Recess gate transistor
KR20130075359A (ko) * 2011-12-27 2013-07-05 삼성전자주식회사 게이트 절연층의 형성 방법
KR101339271B1 (ko) * 2012-12-18 2013-12-09 현대자동차 주식회사 반도체 소자의 제조 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11832486B2 (en) 2021-09-14 2023-11-28 Electronics And Telecommunications Research Institute Semiconductor device, display panel, and display device including the same

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