WO2020036327A1 - Procédé de fabrication de tft à canal court et structure tft à canal court - Google Patents

Procédé de fabrication de tft à canal court et structure tft à canal court Download PDF

Info

Publication number
WO2020036327A1
WO2020036327A1 PCT/KR2019/009029 KR2019009029W WO2020036327A1 WO 2020036327 A1 WO2020036327 A1 WO 2020036327A1 KR 2019009029 W KR2019009029 W KR 2019009029W WO 2020036327 A1 WO2020036327 A1 WO 2020036327A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
source
drain
gate
forming
Prior art date
Application number
PCT/KR2019/009029
Other languages
English (en)
Korean (ko)
Inventor
이현준
Original Assignee
재단법인대구경북과학기술원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 재단법인대구경북과학기술원 filed Critical 재단법인대구경북과학기술원
Publication of WO2020036327A1 publication Critical patent/WO2020036327A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to a short channel TFT, and more particularly, to a structure that substantially increases the length of a channel while reducing the width between the source S and the drain D for high integration.
  • the present invention relates to a short channel TFT fabrication method which enables high integration by having a short channel TFT structure manufactured thereby.
  • FIG. 1 is a diagram showing a structure (a) and a gate voltage-channel current characteristic (b) of a TFT having a bottom gate structure.
  • a TFT having a bottom gate structure has a gate insulator (GI) positioned on the gate G, and an active layer (A) positioned thereon, as shown in FIG. It has a structure in which source / drain (S / D) is located at both sides.
  • GI gate insulator
  • A active layer
  • S / D source / drain
  • Examples of the conventional TFT fabrication technology having the above-described structure is a method of manufacturing a polycrystalline silicon thin film transistor having a trench-shaped copper bottom gate structure of Korean Patent Publication No. 10-1283008, Korean Patent Publication No. 10-2017- 0032642 discloses a nitride-based transistor that implements a normally-off state and a method of manufacturing the same.
  • the present invention is to solve the above-mentioned problems of the prior art, to form a trench or bump under the active layer (Thin Film Transistor) of the TFT (Thin Film Transistor) for high integration, the length of the active layer
  • the width between the source and the drain can be reduced while increasing the length of the actual channel formed in the active layer, thereby enabling the fabrication of highly integrated TFTs. It is an object to provide a short channel TFT fabrication method and a short channel TFT structure produced thereby.
  • Short channel TFT fabrication method of the present invention for achieving the above object
  • the trench is configured to fabricate an etch stopper bottom gate TFT that increases the length of the active layer to reduce the width between the source and drain within the normal operating range of the channel. do.
  • a mask having a structure for forming a trench is applied to expose, develop, etch, and peel off the photoresist layer. And forming a trench in the gate layer.
  • the photoresist is coated on the source drain metal layer (S / D) to form a photoresist layer (PR), and then source and drain formation It is characterized in that the process for generating a source (S and drain (D) separated by the trench region to form a channel by the active layer by applying a mask for the exposure, development, etching and peeling.
  • Forming a gate insulating layer by depositing a gate insulating layer on the bumped gate layer;
  • the bump is configured to fabricate a bottom gate bottom bump TFT that increases the length of the active layer to reduce the width between the source and drain within the normal operating range of the channel. do.
  • the photoresist is coated on the gate layer to form a photoresist layer, and a mask having a structure for bump formation is applied to perform exposure, development, etching and peeling on the photoresist layer. By forming a bump on the gate layer.
  • the photoresist is coated on the source drain metal layer (S / D) to form a photoresist layer (PR), and then source and drain formation It is characterized in that the process of generating a source (S and drain (D) separated by the bump region to form a channel by the active layer by applying a mask for the exposure, development, etching and peeling.
  • Forming an insulating gate layer by depositing an insulating gate layer over the active layer exposed between the source and drain and the source and drain;
  • the trench is configured to fabricate a top gate bottom trench TFT structure that increases the length of the active layer to reduce the width between the source and drain within the normal operating range of the channel. It is done.
  • the photoresist is coated on the insulating layer to form a photoresist layer, and a mask having a structure for forming a trench is applied to perform exposure, development, etching, and peeling on the photoresist layer. By forming a trench in the insulating layer.
  • the photoresist is coated on the source drain metal layer (S / D) to form a photoresist layer (PR), and then source and drain formation It is characterized in that the process for generating a source (S and drain (D) separated by the trench region to form a channel by the active layer by applying a mask for the exposure, development, etching and peeling.
  • Forming an insulating gate layer by depositing an insulating gate layer over the active layer exposed between the source and drain and the source and drain;
  • the bump is configured to fabricate a top gate bottom bump TFT to increase the length of the active layer to reduce the width between the source and drain within the normal operating range of the channel. do.
  • the photoresist is coated on the insulating layer to form a photoresist layer, and a mask having a structure for bump formation is applied to perform exposure, development, etching, and peeling on the photoresist layer.
  • a bump on the insulating layer characterized in that the process.
  • the photoresist is coated on the source drain metal layer (S / D) to form a photoresist layer (PR), and then source and drain formation It is characterized in that the process of generating a source (S and drain (D) separated by the bump region to form a channel by the active layer by applying a mask for the exposure, development, etching and peeling.
  • the short channel TFT structure of the present invention for achieving the above object is
  • a gate insulating layer stacked on the gate layer and having a trench shape
  • An active layer stacked in an upper region of the gate insulating layer in the shape of the trench;
  • Source and drain stacked on top of the active layer so as to be positioned at both sides of the trench, respectively.
  • the trench may be an etch stopper bottom gate short channel TFT structure that increases the length of the active layer to reduce the width between the source and the drain within the normal operating range of the channel.
  • a gate insulating layer stacked on the gate layer and having a bump shape
  • a source and a drain which are divided on both sides of the bump and stacked on top of the active layer
  • a protective layer stacked on the source and drain and an active layer between the source and the drain.
  • the bump may be a bottom gate short channel TFT structure in which a length of the active layer is increased to reduce the width between the source and the drain within the normal operating range of the channel. .
  • a source and a drain which are divided on both sides of an upper region of the trench and stacked on top of the active layer;
  • a gate insulating layer stacked over the active layer between the source and drain and the source and drain;
  • the trench may have a top gate bottom trench short channel TFT structure in which the length of the active layer is increased to reduce the width between the source and the drain within the normal operating range of the channel.
  • a gate insulating layer stacked on the source, the drain, and an upper region of the active layer between the source and the drain;
  • the bump may have a top gate bottom bump short channel TFT structure that increases the length of the active layer to reduce the width between the source and the drain within the normal operating range of the channel.
  • the present invention having the above-described configuration, by forming a trench or a bump under an active layer of a TFT (Thin Film Transistor), such as the length of the concave surface of the trench or the convex surface of the bump Since the length of the active layer can be increased in three dimensions, it is possible to increase the actual channel length while reducing the width between the source and drain in one dimension, thereby reducing the overall size of the TFT. It provides the effect of achieving high integration without performing.
  • TFT Thin Film Transistor
  • Fig. 1 is a diagram showing the structure (a) and gate voltage-current characteristics (b) of a TFT having a bottom gate structure of the prior art.
  • FIG. 2 is a cross-sectional view of an etch stopper bottom trench TFT in accordance with an embodiment of the present invention.
  • FIG. 3 is a process diagram for fabricating the etching stopper bottom trench TFT of FIG.
  • FIG. 4 is a cross-sectional view of a top gate bottom trench TFT in accordance with an embodiment of the present invention.
  • FIG. 5 is a process diagram for fabricating the top gate bottom trench TFT of FIG. 4.
  • FIG. 6 is a cross-sectional view of a TFT having a bottom gate bottom bump structure in accordance with an embodiment of the present invention.
  • FIG. 7 is a process diagram for fabricating the bottom gate bottom bump TFT of FIG. 6.
  • FIG. 8 is a cross-sectional view of a top gate bottom bump TFT in accordance with an embodiment of the present invention.
  • FIG. 9 is a process diagram for fabricating the top gate bottom bump TFT of FIG. 8.
  • FIG. 9 is a process diagram for fabricating the top gate bottom bump TFT of FIG. 8.
  • Figure 10 is a comparison of the gate voltage and channel current characteristics of the conventional TFT fabricated in the size of 2um and the short channel TFT having the trench of the present invention.
  • FIG. 2 is a cross-sectional view of an etch stopper bottom trench TFT according to an embodiment of the present invention
  • FIG. 3 is a process diagram for fabricating an etch stopper bottom trench TFT of FIG. 2.
  • a trench 10 is formed in the center of a bottom gate layer G, which is a metal conductive layer, by performing a photoresist and etching process.
  • a gate insulator (GI) is stacked on the layer G, and an active layer A is stacked in an area including the trench 10 in the upper center of the gate insulating layer GI, and the active layer Insulator layer (I) is stacked on top of (A), and source (S :) and drain (D :) are in contact with both sides of active layer (A) with insulating layer (I) in between. It has a structure that is formed.
  • a passivation layer (P: passivation) laminated on the source S and the drain D is omitted.
  • a gate metal layer (GM) is laminated on a substrate, followed by photoresist coating and exposure.
  • the concave trench 10 is formed at the center by performing the process of exposing, developing, wet etching and wet etching, and stripping and removing the photoresist layer PR.
  • the bottom gate layer G is formed.
  • a gate insulator (GI) is laminated by stacking a metal oxide such as SiNx on the gate layer G.
  • the photoresist coating, mask applied exposure, wet etching and Stripping is performed to form the active layer A on the gate insulating layer GI including the trench.
  • the source drain metal layer S / D to be formed as the source S and the drain D is stacked on the gate insulating layer GI and the active layer A, and then the source in the upper region of the active layer A Photoresist coating, masked exposure and development, etching and stripping to remove the drain metal layer S / D, so that each side of the active layer A is independently contacted
  • the etching stopper bottom trench TFT 100 of FIG. 2 is fabricated by forming (S) and the drain D and laminating a SiO 2 protective layer P thereon.
  • the etching stopper bottom trench TFT 100 manufactured as described above has a concave trench 10 structure below the active layer A, and thus the length of the active layer A increases in three dimensions. Even when the width between S) and the drain D is narrowed, the length of the entire channel formed by the active layer A is increased, so that a TFT device having a size of 2 ⁇ m or less can be manufactured.
  • FIG. 4 is a cross-sectional view of the top gate bottom trench TFT 200 according to the embodiment of the present invention
  • FIG. 5 is a process diagram for fabricating the top gate bottom trench TFT of FIG. 4.
  • the top gate bottom trench TFT 200 may include an insulating layer I having a trench 10 formed therein, an active layer A deposited on the insulating layer I, and upper sides of the active layer A, respectively.
  • the top gate bottom trench TFT 200 having the above-described structure is formed by depositing an insulating layer on a substrate, coating the photoresist, and forming a photoresist layer PR to expose and develop
  • the insulating layer on which the trenches 10 are formed is formed by performing development, etching, and stripping and removing the photoresist layer PR.
  • the active layer A is deposited on the insulating layer on which the above-described trench 10 is formed, and then the source drain metal layer S / D, which is to be the source S and the drain D, is stacked.
  • a mask for forming the source and the drain is applied to perform exposure, development, etching and peeling. As a result, a source S and a drain D are separated to form a channel by the active layer.
  • the trench 10 structure is formed under the active layer A by sequentially depositing the gate insulating layer GI and the gate layer G on the source S and the drain D and the active layer A.
  • the top gate bottom trench TFT 200 has a concave trench 10 structure below the active layer A, so that the entire length of the active layer A becomes three-dimensionally longer, and thus the source S While narrowing the width between the drain and the drain D, the length of the entire channel formed by the active layer A can be increased to fabricate a TFT device having a size of 2 ⁇ m or less.
  • FIG. 6 is a cross-sectional view of a bottom gate bottom bump TFT 300 according to an embodiment of the present invention
  • FIG. 7 illustrates fabrication of the bottom gate bottom bump TFT 300 of FIG. 6. It is a process chart for.
  • the bottom gate bottom bump TFT 300 has a structure in which the bottom width of the active layer A is increased while increasing the overall length by having the bump 20 structure below the active layer A.
  • the bottom gate bottom bump TFT 300 may include a gate layer G having bumps 20 formed thereon, a gate insulating layer GI having a bump structure, and a gate insulating layer GI stacked on top of the gate layer G, and a gate insulating layer GI.
  • Active layer (A) stacked on top of the active layer (A), the source (S) and drain (D) and the source (S) and drain (D) and the source (S) which are formed to be laminated insulated from each other on the active layer (A) It comprises a protective layer (P) deposited on top of the active layer (A) between the drain (D).
  • the above-described bottom gate bottom bump TFT 300 of FIG. 6 is manufactured by the process of FIG. 7, and will be described with reference to FIG. 7.
  • a gate metal layer (G deposition) is deposited on a substrate.
  • the central region is formed so thick that the ultraviolet ray is not transmitted, and the regions on both sides using a thinly formed mask (M) to transmit some ultraviolet rays
  • M thinly formed mask
  • the gate insulating layer GI and the active layer A are sequentially deposited on the gate layer G to be stacked.
  • a source drain metal layer S / D to be a source S and a drain D electrode is deposited on the active layer A, and then a photoresist layer PR is deposited thereon.
  • the bottom gate bottom bump TFT 300 is fabricated by performing stripping and depositing the protective layer P.
  • the bottom gate bottom bump TFT 300 has the structure of the bump 20 to narrow the width between the source S and the drain D, while reducing the length of the entire channel formed by the active layer A. It is possible to manufacture a TFT device having a size of 2 ⁇ m or less.
  • FIG. 8 is a cross-sectional view of a top gate bottom bump TFT 400 according to an embodiment of the present invention
  • FIG. 9 is a fabrication of the top gate bottom bump TFT 400 of FIG. 8. It is a process chart for.
  • the top gate bottom bump TFT 400 forms a bump 20 by performing photoresist etching on an insulating layer on an upper substrate, and an active layer A on the substrate and the bump 20.
  • the gate insulating layer GI and the gate insulating layer GI are formed on the gate insulating layer GI.
  • the above-mentioned top gate bottom bump TFT 400 is manufactured by the process of FIG. 9, and first, deposits an insulating layer on the substrate.
  • the photoresist is coated on the insulating layer to form the photoresist layer PR, and then exposed by using a mask M that blocks ultraviolet rays emitted to the region where the bump 20 is to be formed. Subsequently, development is performed to perform etching and stripping to form a bump 20 formed as an insulating layer on the substrate.
  • the active layer A and the source drain metal layer S / D are sequentially deposited and stacked on the substrate and the bump 20, and the photoresist is coated on the source drain metal layer S / D.
  • the resistor layer PR is formed.
  • the bump 20 region is opened and the other regions are subjected to exposure, development, and etching by applying the shielded mask M, and then the remaining photoresist PR is removed.
  • the source S and the drain D are formed in the upper part of the active layer A of both sides of the bump 20, respectively.
  • the top gate bottom bump TFT 400 is fabricated by depositing and forming the gate insulating layer GI and the gate layer G.
  • the top gate bottom bump TFT 400 has the structure of the bump 20 so that the length of the entire channel formed by the active layer A is increased three-dimensionally without changing the overall TFT size.
  • the width between S) and the drain D can be narrowed, so that a TFT element having a size of 2 ⁇ m or less can be manufactured.
  • the present invention even when the gap between the source S and the drain D is reduced by forming the trench 10 or bump 20 structure under the active layer A of the TFT,
  • the outer surface of the concave portion of the trench 10 or the protrusion of the bump 20 can increase the length of the active layer A, which forms an electron transfer channel between the source S and the drain D, thereby increasing the length of 2um. It is possible to manufacture a TFT element having the following size.
  • FIG. 10 is a comparison diagram of gate voltage and channel current characteristics of a conventional TFT fabricated in a size of 2 ⁇ m and a short channel TFT having a trench of the present invention.
  • the length of the active layer forming the channel c is increased by the three-dimensional structure of the trench 10, so that the source S and the drain D
  • the length of the active layer for channel formation is secured even though the gap between them is reduced, so that even when the active layer A of the TFT of the prior art has a gap between the source S and the drain D operating as a conductor.
  • the gate voltage is 0V
  • the insulator has the characteristics of the insulator, thereby enabling the function of the TFT, thereby enabling high integration.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne un procédé de fabrication de TFT à canal court qui permet une intégration élevée au moyen de la réduction de la largeur entre une source (S) et un drain (D) pour une intégration élevée et également pour une augmentation réelle de la longueur d'un canal, et une structure de TFT à canal court fabriquée au moyen de ce dernier. Le procédé de fabrication de TFT à canal court de la présente invention comprend : en une étape de formation de couche de grille consistant à former une couche de grille; en une étape de formation de tranchée consistant à former une tranchée sur la couche de grille; en une étape de formation de couche d'isolation de grille consistant à déposer une couche d'isolation de grille sur la couche de grille ayant la tranchée; en une étape de dépôt de couche active consistant à déposer une couche active sur la couche d'isolation de grille; en une étape de formation de source/drain consistant à former une source et un drain, qui sont déposés des deux côtés de la tranchée, sur la couche active; et en une étape de formation de couche de protection consistant à déposer une couche de protection sur la source, le drain et la couche active. Le procédé est caractérisé par la fabrication d'un TFT à grille inférieure d'arrêt de gravure dont la longueur de la couche active est augmentée au moyen de la tranchée et qui réduit la largeur entre la source et le drain dans une plage de fonctionnement normal d'un canal.
PCT/KR2019/009029 2018-08-17 2019-07-22 Procédé de fabrication de tft à canal court et structure tft à canal court WO2020036327A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020180096067A KR102172878B1 (ko) 2018-08-17 2018-08-17 쇼트 채널 tft 제작 방법 및 쇼트채널 tft 구조
KR10-2018-0096067 2018-08-17

Publications (1)

Publication Number Publication Date
WO2020036327A1 true WO2020036327A1 (fr) 2020-02-20

Family

ID=69524780

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2019/009029 WO2020036327A1 (fr) 2018-08-17 2019-07-22 Procédé de fabrication de tft à canal court et structure tft à canal court

Country Status (2)

Country Link
KR (1) KR102172878B1 (fr)
WO (1) WO2020036327A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11296289B2 (en) * 2018-06-01 2022-04-05 Samsung Electronics Co., Ltd. Thin film transistor and method of manufacturing the same and thin film transistor panel and electronic device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677487A (ja) * 1992-07-01 1994-03-18 Hyundai Electron Ind Co Ltd 薄膜トランジスター及びその製造方法
KR960036145A (ko) * 1995-03-24 1996-10-28 김주용 고집적 박막 트랜지스터 및 그 제조 방법
JP2001133804A (ja) * 1999-10-29 2001-05-18 Fujitsu Ltd 液晶表示装置の製造方法
KR20130036136A (ko) * 2010-05-10 2013-04-11 파나소닉 액정 디스플레이 주식회사 박막 트랜지스터 장치 및 그 제조 방법
KR20170090995A (ko) * 2016-01-29 2017-08-08 히타치 긴조쿠 가부시키가이샤 반도체 장치 및 반도체 장치의 제조 방법

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5739257B2 (ja) * 2010-08-05 2015-06-24 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR101283008B1 (ko) 2010-12-23 2013-07-05 주승기 트렌치형상의 구리 하부 게이트 구조를 갖는 다결정 실리콘 박막 트랜지스터의 제조방법
KR20170032642A (ko) 2015-09-15 2017-03-23 서울반도체 주식회사 노멀리-오프 상태를 구현하는 질화물계 트랜지스터 및 이의 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677487A (ja) * 1992-07-01 1994-03-18 Hyundai Electron Ind Co Ltd 薄膜トランジスター及びその製造方法
KR960036145A (ko) * 1995-03-24 1996-10-28 김주용 고집적 박막 트랜지스터 및 그 제조 방법
JP2001133804A (ja) * 1999-10-29 2001-05-18 Fujitsu Ltd 液晶表示装置の製造方法
KR20130036136A (ko) * 2010-05-10 2013-04-11 파나소닉 액정 디스플레이 주식회사 박막 트랜지스터 장치 및 그 제조 방법
KR20170090995A (ko) * 2016-01-29 2017-08-08 히타치 긴조쿠 가부시키가이샤 반도체 장치 및 반도체 장치의 제조 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11296289B2 (en) * 2018-06-01 2022-04-05 Samsung Electronics Co., Ltd. Thin film transistor and method of manufacturing the same and thin film transistor panel and electronic device

Also Published As

Publication number Publication date
KR102172878B1 (ko) 2020-11-02
KR20200020394A (ko) 2020-02-26

Similar Documents

Publication Publication Date Title
WO2018056694A2 (fr) Dispositif à semi-conducteur logique
WO2020017746A1 (fr) Dispositif d'affichage et son procédé de fabrication
WO2019041543A1 (fr) Structure de transistor à couches minces et circuit d'attaque amoled
WO2020184777A1 (fr) Procédé de fabrication de transistor à couches minces à semi-conducteur à oxyde
WO2019056517A1 (fr) Structure de transistor à couches minces et son procédé de fabrication
WO2019198907A1 (fr) Dispositif d'affichage et procédé de fabrication de dispositif d'affichage
WO2020036327A1 (fr) Procédé de fabrication de tft à canal court et structure tft à canal court
WO2013176519A1 (fr) Substrat de boîtier de semi-conducteurs, système de boîtier utilisant un tel substrat et son procédé de fabrication
WO2020111452A1 (fr) Dispositif d'affichage
WO2022045698A1 (fr) Dispositif d'affichage
WO2016206033A1 (fr) Substrat de matrice de transistor à couche mince et son procédé de fabrication
WO2021101242A1 (fr) Transistor à couches minces multi-canal et son procédé de fabrication
WO2017156808A1 (fr) Procédé de fabrication de transistor en couches minces
WO2018218712A1 (fr) Substrat de transistor à couches minces (tft) en polysilicium basse température et son procédé de fabrication
WO2016115727A1 (fr) Panneau d'affichage à cristaux liquides et son procédé de fabrication
WO2017152451A1 (fr) Substrat de matrice en mode ffs et procédé de fabrication associé
WO2018012868A1 (fr) Transistor atomique de commutation et procédé de fonctionnement associé
WO2020004747A1 (fr) Procédé de fabrication d'un dispositif d'affichage électroluminescent organique
WO2021054617A1 (fr) Transistor à couches minces et son procédé de fabrication
WO2020130244A1 (fr) Dispositif d'affichage électroluminescent organique et procédé de fabrication du dispositif d'affichage électroluminescent organique
WO2021261783A1 (fr) Transistor à couches minces et son procédé de fabrication
WO2020056906A1 (fr) Substrat de réseau, son procédé de fabrication et panneau d'affichage
WO2020045850A1 (fr) Dispositif d'affichage souple et son procédé de fabrication
WO2021101288A1 (fr) Transistor, son procédé de fabrication et onduleur ternaire le comprenant
WO2017015981A1 (fr) Procédé de fabrication de transistor à couches minces de polysilicium

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19849607

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19849607

Country of ref document: EP

Kind code of ref document: A1