WO2021052125A1 - Multiplexeur - Google Patents

Multiplexeur Download PDF

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Publication number
WO2021052125A1
WO2021052125A1 PCT/CN2020/111339 CN2020111339W WO2021052125A1 WO 2021052125 A1 WO2021052125 A1 WO 2021052125A1 CN 2020111339 W CN2020111339 W CN 2020111339W WO 2021052125 A1 WO2021052125 A1 WO 2021052125A1
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WO
WIPO (PCT)
Prior art keywords
carrier board
carrier
cross
multiplexer
metal layer
Prior art date
Application number
PCT/CN2020/111339
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English (en)
Chinese (zh)
Inventor
庞慰
梁新红
Original Assignee
天津大学
诺思(天津)微系统有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 天津大学, 诺思(天津)微系统有限责任公司 filed Critical 天津大学
Publication of WO2021052125A1 publication Critical patent/WO2021052125A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00—Auxiliary devices
    • H01P1/20—Frequency-selective devices, e.g. filters

Definitions

  • the present invention relates to the field of communication technology, in particular to a multiplexer.
  • FBAR filters and multiplexers have become more and more popular in the market due to their small size, good insertion loss, high frequency selectivity, and ease of integration.
  • the quadruple is integrated by four separate chips.
  • the four individual chips are flip-chip connected to the multi-layer carrier through metal balls. Due to the increasing miniaturization of chips, the quadruple The spacing between the four chips in the device is further reduced, which leads to unfavorable coupling, which in turn worsens the isolation.
  • a common method to improve isolation is to increase the spatial distance of the channels of the multiplexer, but this will inevitably increase the size of the chip; another method is phase cancellation, but this will not only increase the complexity of the design, but also Increase the size of the multiplexer integrated chip. Therefore, designing a FBAR quadruplexer that can improve isolation without increasing the size has become one of the urgent problems in this field.
  • the present invention provides a multiplexer that forms an isolation wall by arranging a cross-shaped metal layer and a through hole on the first carrier of the carrier assembly, so that each chip is in a separate isolation cavity In order to eliminate the unfavorable coupling between the chips.
  • a multiplexer is provided.
  • the multiplexer provided by the present invention includes a carrier board assembly and a chip, the chip is arranged on the carrier board assembly, and the carrier board assembly includes a multilayered first carrier board and a second carrier board.
  • the second carrier board is arranged below the first carrier board, and a dielectric layer is arranged between the first carrier board and the second carrier board, and a dielectric layer is arranged between adjacent first carrier boards
  • One or more layers of the first carrier plate have a cross-shaped metal layer, and the cross-shaped metal layer is provided with a through hole penetrating the first carrier plate and the dielectric layer.
  • the carrier assembly is a rectangular parallelepiped plate structure, a cross-shaped metal layer on the surface of the carrier assembly divides the surface of the carrier assembly into four compartments, and the chip is located in the compartment Inside.
  • a metal band gap is provided along the periphery of the cross-shaped metal layer, and the metal band gap includes a plurality of metal strips arranged at intervals.
  • the number of the through holes is at least two, and a plurality of the through holes are arranged at intervals.
  • the cross-shaped metal layer includes four metal strips, the four metal strips form a cross-shaped structure, and each metal strip includes two metal sheets arranged in parallel and spaced apart.
  • a through hole penetrating the first carrier board and the dielectric layer is provided in the middle of the cross-shaped metal layer.
  • a plurality of through holes are arranged on the metal sheet at intervals, and the first through holes on two parallel and adjacent metal sheets are arranged in parallel.
  • the first carrier board and the second carrier board are made of metallic copper.
  • the cross-shaped metal layer is made of metallic copper.
  • the carrier board assembly includes three layers of the first carrier board and the second carrier that are stacked.
  • the carrier assembly includes successively stacked multiple layers of a first carrier, a second carrier, and a dielectric layer.
  • the multiplexer passes through the cross-shaped metal layer on the first carrier and penetrates the The first carrier board and the through hole of the dielectric layer form an isolation wall, so that each chip is in a separate isolation cavity, and the electromagnetic radiation of each chip is limited in its own isolation cavity, thereby eliminating electromagnetic radiation between each chip The unfavorable coupling.
  • FIG. 1 is a schematic diagram of the structure of a multiplexer in the prior art
  • Fig. 2 is a first structural diagram of a multiplexer according to an embodiment of the present invention.
  • Fig. 3 is a second structural schematic diagram of a multiplexer according to an embodiment of the present invention.
  • Fig. 4 is a third structural schematic diagram of a multiplexer according to an embodiment of the present invention.
  • Figure 5 is an A-A' cross-sectional view of the multiplexer according to the embodiment of the present invention.
  • Fig. 6 is a comparison diagram of isolation performance curves between the multiplexer of the present invention and the multiplexer of the prior art
  • Fig. 7 is a comparison diagram of isolation performance curves between the multiplexer of the present invention and the multiplexer of the prior art.
  • 1- carrier board assembly 2- chip; 3- cross-shaped metal layer; 4- through hole, 5- metal strip, 6-second carrier, 7-first carrier, 8-dielectric layer, 9- Metal sheets.
  • the present invention discloses a multiplexer, a carrier assembly 1 and a chip 2.
  • the chip 2 is arranged on the carrier assembly 1 (the chip 2 can be arranged in two ways, one is the chip 2.
  • the chip 2 is set upside down, and the chip 2 is connected to the carrier board assembly 1 through a metal ball; the other is that the chip 2 is arranged in the forward direction, and the chip 2 is connected to the carrier board assembly 1 through wire bonding)
  • the carrier board assembly 1 includes a stack of multiple Layers of the first carrier board 7 and the second carrier board 6, the second carrier board 6 is arranged below the first carrier board 7, and a dielectric layer 8 is arranged between the first carrier board 7 and the second carrier board 6, adjacent to each other
  • a dielectric layer 8 is provided between the first carrier board 7;
  • the first carrier board 7 has a cross-shaped metal layer 3, and the cross-shaped metal layer 3 is provided with a through hole 4 penetrating the first carrier board 7 and the dielectric layer 8.
  • the cross-shaped metal layer 3 on each first carrier board 7 may be the same or different. At least one first carrier board 7 is provided with a cross-shaped metal layer 3. If space permits, a cross-shaped metal layer 3 may be provided on multiple first carrier boards 7.
  • the multiplexer forms an isolation wall through the cross-shaped metal layer 3 on the first carrier board 7 and the through holes 4 through the first carrier board 7 and the dielectric layer 8, so that each chip 2 is in a separate isolation cavity.
  • the electromagnetic radiation of each chip 2 is confined in the respective isolation cavity, thereby eliminating the unfavorable coupling of electromagnetic radiation between the chips 2 and improving the mutual isolation.
  • the carrier assembly 1 includes three layers of a first carrier plate 7 and a second carrier plate 6 which are stacked, and the three layers of the first carrier plate 7 and the dielectric layer 8 are stacked in sequence, and are located at the first layer of the third layer.
  • the carrier board 7 and the second carrier board 6 are laminated together through a dielectric layer 8.
  • the carrier assembly 1 is a rectangular parallelepiped plate structure, and its size may be, for example, 2500 ⁇ m ⁇ 2000 ⁇ m.
  • the cross-shaped metal layer 3 on the surface of the carrier assembly 1 divides the surface of the carrier assembly 1 into four compartments, and the chip 2 is located in the compartment.
  • the cross-shaped metal layer 3 divides the surface of the carrier assembly 1 into four compartments of the same size, and each compartment is provided with a chip 2. Therefore, the electromagnetic radiation generated by the four chips 2 does not affect each other, so that the mutual isolation between the respective chips 2 can be improved.
  • the four chips 2 are Band3 Tx (1710 ⁇ 1785MHZ), Band Rx (1805 ⁇ 1880MHZ), Band1 Tx (1920 ⁇ 1980MHZ), Band1 Rx (2110 ⁇ 2170MHZ).
  • a metal band gap is provided along the periphery of the cross-shaped metal layer 3, and the metal band gap includes a plurality of metal strips 5 arranged at intervals.
  • the metal strips 5 may be arranged at equal intervals or may be arranged at different intervals.
  • the cross-shaped metal layer 3 on the first carrier board 7 of each layer is different, and the cross-shaped metal layer 3 of the first carrier board 7 of the middle layer has a smaller horizontal and vertical dimension than the cross-shaped metal layer of the first carrier board 7 of the top layer At 3 o'clock, the electromagnetic radiation of the chip 2 cannot be completely shielded. At this time, the metal band gap can form a second shielding wall to further shield the electromagnetic radiation, thereby improving the mutual isolation between the four chips 2.
  • the number of through holes 4 is at least two, and a plurality of through holes 4 are arranged at intervals.
  • the plurality of through holes 4 may be arranged at equal intervals, or may be arranged at non-equal intervals.
  • the cross-shaped metal layer 3 includes four metal strips, and the four metal strips form a cross-shaped structure, and each metal strip includes two metal sheets 9 arranged in parallel and spaced apart. Further, the cross-shaped metal layer 3 is deformed into a cross-shaped metal layer.
  • a through hole 4 penetrating the first carrier 7 and the dielectric layer 8 is provided in the middle of the cross-shaped metal layer 3.
  • a plurality of through holes 4 are arranged on the metal sheet 9 at intervals, and the through holes 4 on two parallel and adjacent metal sheets 9 are arranged in parallel, forming two holes on the metal layer in the shape of a square.
  • the shielding wall further improves the mutual isolation between the four chips 2.
  • the first carrier board 7 and the second carrier board 6 are made of metal copper, and the cross-shaped metal layer 3 is made of metal copper. Copper has good conductivity, so the shielding cavity formed by using metallic copper as the raw material of the first carrier board 7 and the second carrier board 6 has a good shielding effect.
  • Figure 6 is a comparison diagram of isolation performance curves, in which the black dashed line is the isolation curve of the multiplexer in the prior art of Figure 1, the gray solid line is the isolation curve of the multiplexer shown in Figure 2, and the black solid line is the graph 3 shows the isolation curve of the multiplexer.
  • Figure 6A shows the isolation between Band3Rx (1805 ⁇ 1880MHz) and Band1Tx (1920 ⁇ 1980MHz); the isolation at Band3Rx (1805 ⁇ 1880MHz) frequency band is compared with the multiplexer of Figure 1, the multiplexer of Figure 2 The improvement is about 8dB, and the multiplexer of Figure 3 is improved by about 6dB.
  • Figure 6B shows the isolation between Band3Tx (1710 ⁇ 1785MHz) and Band3Rx (1805 ⁇ 1880MHz); among them, the isolation in Band3Tx (1710 ⁇ 1785MHz) frequency band is compared with the multiplexer in Figure 1.
  • the isolation of the frequency band, the multiplexer of Fig. 2 and the multiplexer of Fig. 3 are both improved by about 4dB.
  • Figure 6C shows the isolation between Band1Tx (1920 ⁇ 1980MHz) and Band1Rx (2110 ⁇ 2170MHz); the isolation in Band1Tx (1920 ⁇ 1980MHz) frequency band is compared with the multiplexer in Figure 1, the multiplexer in Figure 2 The increase is about 3dB, and the multiplexers in Figure 3 are all improved by about 1dB.
  • Figure 6D shows the isolation between Band3Tx (1710 ⁇ 1785MHz) and Band1Rx (2110 ⁇ 2170MHz); the isolation in Band3Tx (1710 ⁇ 1785MHz) frequency band is compared with the multiplexer in Figure 1, the multiplexer in Figure 2 With an increase of about 2dB, the multiplexers in Figure 3 are all improved by about 1dB; in the Band1Rx (2110-2170MHz) frequency band, the multiplexers in Figure 2 are improved by about 2dB, and the multiplexers in Figure 3 are all improved by about 1dB.
  • FIG. 7 is a comparison diagram of isolation curves of the multiplexers of FIG. 1 and FIG. 4.
  • Figure 7A shows the isolation between Band3Rx (1805 ⁇ 1880MHz) and Band1Tx (1920 ⁇ 1980MHz); the isolation in Band3Rx (1805 ⁇ 1880MHz) frequency band is compared with the multiplexer of Figure 1, the multiplexer of Figure 4 The improvement is about 11dB; in Band1Tx (1920 ⁇ 1980MHz) frequency band isolation, the multiplexer of Fig. 4 has no improvement.
  • Figure 7B shows the isolation between Band3Tx (1710 ⁇ 1785MHz) and Band3Rx (1805 ⁇ 1880MHz); the isolation in the Band3Tx (1710 ⁇ 1785MHz) frequency band is compared with the multiplexer of Figure 1, the multiplexer of Figure 4 No improvement; In Band3Rx (1805-1880MHz) frequency band isolation, the multiplexer in Figure 4 improves about 3dB.
  • Figure 7C shows the isolation between Band1Tx (1920 ⁇ 1980MHz) and Band1Rx (2110 ⁇ 2170MHz); the isolation in Band1Tx (1920 ⁇ 1980MHz) frequency band is compared with the multiplexer of Figure 1, the multiplexer of Figure 4 The improvement is about 9dB; in the Band1Rx (2110 ⁇ 2170MHz) frequency band, the multiplexer in Figure 4 improves about 5dB.
  • Figure 7D shows the isolation between Band3Tx (1710 ⁇ 1785MHz) and Band1Rx (2110 ⁇ 2170MHz); the isolation in Band3Tx (1710 ⁇ 1785MHz) frequency band is compared with the multiplexer in Figure 1, the multiplexer in Figure 4 The improvement is about 5dB; in the Band1Rx (2110 ⁇ 2170MHz) frequency band, the multiplexer in Figure 4 improves about 3dB.

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  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

La présente invention concerne un multiplexeur, comprenant un ensemble plaque de support et des puces, les puces étant disposées sur l'ensemble plaque de support ; l'ensemble plaque de support comprend une pluralité de premières plaques de support et une seconde plaque de support qui sont empilées, la seconde plaque de support est disposée sous les premières plaques de support, et une couche intermédiaire est disposée entre les premières plaques de support et la seconde plaque de support, et une couche intermédiaire est disposée entre des premières plaques de support adjacentes ; une ou plusieurs plaques des premières plaques de support comportent une couche métallique en forme de croix, et la couche métallique en forme de croix est pourvue de trous traversants pénétrant à travers les premières plaques de support et la couche intermédiaire. Selon le multiplexeur décrit par la présente invention, le multiplexeur forme une paroi d'isolation en fournissant la couche métallique en forme de croix et les trous traversants sur les premières plaques de support de l'ensemble plaque de support, de sorte que chaque puce est située dans une cavité d'isolation individuelle, ce qui permet d'éliminer un couplage indésirable entre les puces.
PCT/CN2020/111339 2019-09-20 2020-08-26 Multiplexeur WO2021052125A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910891645.1A CN110707400B (zh) 2019-09-20 2019-09-20 一种多工器
CN201910891645.1 2019-09-20

Publications (1)

Publication Number Publication Date
WO2021052125A1 true WO2021052125A1 (fr) 2021-03-25

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PCT/CN2020/111339 WO2021052125A1 (fr) 2019-09-20 2020-08-26 Multiplexeur

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WO (1) WO2021052125A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110707400B (zh) * 2019-09-20 2021-09-21 天津大学 一种多工器

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CN204067349U (zh) * 2014-08-04 2014-12-31 中芯国际集成电路制造(北京)有限公司 一种芯片保护结构
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WO2018221427A1 (fr) * 2017-05-30 2018-12-06 株式会社村田製作所 Multiplexeur, dispositif de transmission et dispositif de réception
CN109686721A (zh) * 2019-01-31 2019-04-26 中国电子科技集团公司第四十三研究所 一种低热阻的厚膜多层布线结构及其制备方法
CN110707400A (zh) * 2019-09-20 2020-01-17 天津大学 一种多工器

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JP4381113B2 (ja) * 2003-11-27 2009-12-09 三洋電機株式会社 アンテナ共用器
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JP5583612B2 (ja) * 2011-01-31 2014-09-03 太陽誘電株式会社 分波器
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654590A (en) * 1993-12-27 1997-08-05 Fujitsu Limited Multichip-module having an HDI and a temporary supporting substrate
CN103582302A (zh) * 2012-07-25 2014-02-12 纬创资通股份有限公司 印刷电路板及印刷电路板的制造方法
CN104218317A (zh) * 2013-06-03 2014-12-17 中兴通讯股份有限公司 一种印刷电路板及采用多入多出天线技术的无线终端
CN204067349U (zh) * 2014-08-04 2014-12-31 中芯国际集成电路制造(北京)有限公司 一种芯片保护结构
CN206992298U (zh) * 2017-05-08 2018-02-09 江苏亨鑫科技有限公司 一种极化和方向图各异的四单元mimo天线
WO2018221427A1 (fr) * 2017-05-30 2018-12-06 株式会社村田製作所 Multiplexeur, dispositif de transmission et dispositif de réception
CN109686721A (zh) * 2019-01-31 2019-04-26 中国电子科技集团公司第四十三研究所 一种低热阻的厚膜多层布线结构及其制备方法
CN110707400A (zh) * 2019-09-20 2020-01-17 天津大学 一种多工器

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