WO2021035707A1 - Régulateur à faible perte - Google Patents

Régulateur à faible perte Download PDF

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Publication number
WO2021035707A1
WO2021035707A1 PCT/CN2019/103781 CN2019103781W WO2021035707A1 WO 2021035707 A1 WO2021035707 A1 WO 2021035707A1 CN 2019103781 W CN2019103781 W CN 2019103781W WO 2021035707 A1 WO2021035707 A1 WO 2021035707A1
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WO
WIPO (PCT)
Prior art keywords
power tube
coupled
source
voltage
drain
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PCT/CN2019/103781
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English (en)
Chinese (zh)
Inventor
熊付荣
康超健
马壮
石玉楠
宋伟
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2019/103781 priority Critical patent/WO2021035707A1/fr
Priority to CN201980098699.0A priority patent/CN114144741A/zh
Publication of WO2021035707A1 publication Critical patent/WO2021035707A1/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers

Definitions

  • This application relates to the field of integrated circuits, and in particular to a low-dropout voltage regulator.
  • the low dropout regulator (low dropout regulator, usually referred to as LDO) is used to provide a stable DC voltage power supply.
  • LDOs can be applied to work with a smaller output and input voltage difference, can provide a lower voltage difference, and are often used for power supply voltage stabilization.
  • a typical LDO includes four modules: a reference voltage source, an error amplifier (EA), a power tube circuit, and a feedback circuit.
  • EA error amplifier
  • the working principle of the LDO is that the feedback circuit samples the output voltage, makes a difference with the reference voltage (VREF) generated by the reference voltage source, and then is amplified by the error amplifier circuit to control the gate voltage of the power tube circuit and provide the output current to drive the load. Adjust the load current according to the output voltage so that the output voltage remains stable.
  • VREF reference voltage
  • the LDO When the LDO supplies power to the active terminal, when the load current changes, there may be a sink current output to the LDO.
  • the sink current will cause the output voltage of the LDO to be higher than the nominal value, resulting in unstable output voltage.
  • the first aspect of the embodiments of the present application provides a low dropout voltage regulator, including: a voltage source, a ground terminal, an error amplifying circuit, a control circuit, a power tube circuit, and an output node; wherein the power tube circuit includes a first power tube and A second power tube, the first power tube and the second power tube are connected in series between the voltage source and the ground, and the common connection point of the first power tube and the second power tube is coupled to the output node; the The error amplifying circuit is used to provide a control voltage to the gates of the first power tube and the second power tube based on the voltage of the output node, the error amplifying circuit includes a first output terminal and a second output terminal, the first output terminal Is coupled to the gate of the first power tube, the second output terminal is coupled to the gate of the second power tube; the control circuit includes a third power tube and a fourth power tube, the source of the third power tube The pole and the drain are connected in series between the first output terminal and the second output terminal, and the source and
  • the low dropout voltage regulator provided by the embodiment of the present application is used in the case of source current and sink current.
  • the first power tube is turned on and the second power tube is turned on when the source current is selected.
  • the power tube is turned off.
  • the sink current is turned on, the second power tube is turned on and the first power tube is turned off.
  • the setting of the control circuit can avoid the power loss caused by the simultaneous turning on of the first power tube and the second power tube.
  • the low dropout voltage regulator further includes control logic for turning on the fourth power tube and turning off the third power tube when the first power tube is turned on. Tube; and when the second power tube is turned on, the third power tube is turned on, and the fourth power tube is turned off.
  • the control logic can be realized through the parameter setting of each power tube and the circuit connection mode, which is not specifically limited here.
  • the gates of the third power tube and the fourth power tube are coupled to a stable bias voltage.
  • the low dropout voltage regulator may further include a bias voltage circuit for providing a stable bias voltage for the third power tube and the fourth power tube.
  • the first power tube is a PMOS tube
  • the second power tube is an NMOS tube
  • the source of the first power tube is coupled to the voltage source
  • the second power tube is The source of the tube is coupled to the ground
  • the drains of the first power tube and the second power tube are coupled to the output node.
  • the low dropout voltage regulator provided in the embodiment of the present application provides a specific composition and connection mode of a power tube circuit.
  • the third power tube is a PMOS tube
  • the fourth power tube is an NMOS tube
  • the first output terminal of the error amplifier circuit is coupled to the source of the third power tube , The drain of the fourth power tube, and the gate of the first power tube
  • the second output terminal of the error amplifier circuit is coupled to the drain of the third power tube, the source of the fourth power tube, and The grid of the second power tube.
  • the low dropout voltage regulator provided by the embodiment of the application provides a specific composition and connection method of the control circuit.
  • the source of the third power tube is coupled to the gate of the first power tube.
  • the gate voltage of the first power tube is controlled
  • the source of the fourth power tube is coupled to the gate of the second power tube.
  • the gate voltage of the second power tube can be controlled.
  • the low dropout voltage regulator further includes: a bias voltage circuit for providing a stable first bias voltage to the gate of the third power tube, and The grid of the four power tube provides a stable second bias voltage.
  • the error amplifying circuit includes a differential pair circuit, a current signal enhancer and a current mirror, and the differential pair circuit is used for the first input terminal and the second input terminal of the error amplifying circuit.
  • the voltage difference at the input terminal is converted into a current signal
  • the current signal enhancer includes at least one current signal enhancement unit, the current signal enhancement unit is used to amplify the current signal output by the differential pair circuit; the current mirror is used to amplify the current signal enhancer
  • the output current signal drives the power tube circuit.
  • the current signal enhancement unit includes three PMOS transistors MP1, MP2, and MP3, and three NMOS transistors MN1, MN2, and MN3; the drain of the MP1 is coupled to the differential pair circuit
  • the first output terminal the gate of the MP1 is coupled to the gate of the MP2 and the gate of the MP3, the gate and the drain of the MP1 are short-circuited, the source of the MP1, the source of the MP2 and the gate of the MP3
  • the source is coupled to the LDO input power
  • the drain of MP2 is coupled to the drain of MN3, the drain of MP3 is coupled to the drain of MN2, and the drain of MN1 is coupled to the second output terminal of the differential pair circuit
  • the gate of the MN1 is coupled to the gate of the MN2 and the gate of the MN3, and the source of the MN1, the source of the MN2 and the source of the MN3 are coupled to the ground.
  • the common node of the MP3 and the MN2 is coupled to the first output terminal of
  • the current signal enhancer includes: a first current signal enhancement unit and a second current signal enhancement unit, and the first current signal enhancement unit and the second current signal enhancement unit are cascaded .
  • the feedback circuit includes: a first resistor and a second resistor connected in series, and a common node of the first resistor and the second resistor is coupled to the first input of the error amplifying circuit The second resistor is grounded, and the first resistor is coupled to the output end of the power tube circuit; the low dropout voltage regulator further includes a compensation capacitor CF, which is coupled to both ends of the first resistor.
  • a second aspect of the embodiments of the present application provides a power supply voltage stabilizing system, which is characterized in that it includes the low dropout voltage stabilizer as provided in the above first aspect and various implementation manners, and a voltage coupled to the low dropout voltage stabilizer. Source and load.
  • the third aspect of the embodiments of the present application provides a chip system, which is characterized by the low dropout voltage regulator provided in the above-mentioned first aspect and various implementation manners.
  • the control circuit connected between the first output terminal and the second output terminal of the error amplifier can adjust the gate voltage of the first power tube and the second power tube to prevent the first power tube and the second power tube from turning on at the same time. Reduce power consumption.
  • Figure 1 is a schematic diagram of a typical LDO
  • Figure 2 is a schematic diagram of the SCSI active terminal power supply structure
  • FIG. 3 is a schematic diagram of the structure of an LDO in an embodiment of the application.
  • FIG. 4 is a schematic diagram of another LDO structure in an embodiment of the application.
  • Figure 5-a is a schematic diagram of an LDO in source current mode in an embodiment of the application.
  • Figure 5-b is a schematic diagram of the LDO in the sink current mode in an embodiment of the application.
  • FIG. 6 is a schematic diagram of another LDO structure in an embodiment of the application.
  • FIG. 7 is a schematic structural diagram of a current signal enhancement unit in an embodiment of the application.
  • the LDO provided in the embodiments of the present application can provide a lower voltage drop, and is often used for power supply stabilization. When the LDO is input and sinks current, the output voltage stability can be maintained.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; It can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; It can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • Source current refers to actively outputting current from the output port. In this embodiment, it specifically refers to the LDO outputting current to the load.
  • Sink current refers to passively inputting current from the output, and in this embodiment specifically refers to the load sinking current into the LDO.
  • the error amplifier circuit usually includes an error amplifier (error amplifier, EA).
  • EA error amplifier
  • the first input terminal of the error amplifier circuit 120 is coupled to the reference voltage source 110, the output terminal is coupled to the gate of the power tube circuit 130, the source of the power tube circuit 130 is coupled to the voltage source Vin, and the drain is coupled to the output node
  • the feedback circuit 140 the other end of the feedback circuit 140 is coupled to the second input end of the error amplifying circuit 120.
  • the input voltage VREG is provided for the SCSI active terminal through the LDO.
  • the bus endpoints B1 to BN in the figure are all coupled to the voltage node VOH through the MOS transistors MP_1 to MP_2N-1.
  • an embodiment of the present application provides a low-dropout voltage stabilizer, which will be described in detail below.
  • FIG. 3 is a schematic diagram of an LDO structure in an embodiment of this application.
  • the power tube circuit 330 includes a first power tube 331 and a second power tube 332.
  • the first power tube and the second power tube are connected in series between the voltage source and the ground, and the common connection point of the first power tube and the second power tube is coupled to the output node.
  • the first power transistor may be a p-channel metal oxide semiconductor (PMOS) or an N-channel metal oxide semiconductor (NMOS),
  • the second power tube may be PMOS or NMOS, which is not limited here.
  • the type of the first power tube is not necessarily related to the type of the second power tube.
  • the type of the first power tube and the type of the second power tube may be the same or different, which is not limited here.
  • One input terminal of the error amplifier circuit 320 is coupled to the reference voltage source 310, and the other input terminal is coupled to the feedback circuit 340, the first input terminal is input VREF, the second input terminal is based on the voltage of the output node, and the feedback circuit is input through the feedback circuit.
  • the voltage, the voltage difference between the first input terminal and the second input terminal is amplified by the error amplifier circuit and used to drive the power tube circuit 330.
  • the error amplifying circuit 320 includes a first output terminal and a second output terminal. The first output terminal is coupled to the gate of the first power tube 331, and the second output terminal is coupled to the gate of the second power tube 332. .
  • the error amplifier circuit 320 controls the gate voltage of the power tube circuit 330 to stabilize the voltage Vout output by the LDO through the output node when the circuit is balanced.
  • the control circuit 350 includes a third power tube 351 and a fourth power tube 352.
  • the third power tube 351 may be PMOS or NMOS, which is not limited here
  • the fourth power tube 352 may be PMOS or NMOS, which is not limited here.
  • the source and drain of the third power tube are connected in series between the first output terminal and the second output terminal, and the source and drain of the fourth power tube are connected in series with the first output terminal and the second output terminal. Between ends.
  • the control circuit is used to control when the first power tube is turned on, the second power tube is turned off; when the second power tube is turned on, the first power tube is turned off.
  • the bias voltage circuit 360 includes a first current source IB1 and a second current source IB2, the IB1 is coupled to the gate of the fourth power tube, and the IB2 is coupled to the gate of the third power tube.
  • the bias voltage circuit is used to provide a preset bias voltage.
  • the fourth power tube 352 can be controlled to turn on or off, and the third power tube 351 can be controlled to turn on or off.
  • one end of IB1 is coupled to the power input terminal VIN of the LDO, the other end is grounded, one end of IB2 is coupled to the power input terminal VIN of the LDO, and the other end is grounded.
  • the LDO working state includes source current mode and sink current mode.
  • the source current mode the LDO source current
  • the sink current mode the LDO sink current.
  • the low dropout voltage regulator also includes control logic for turning on the fourth power tube and turning off the third power tube when the first power tube is turned on; and when the second power tube is turned on , The third power tube is turned on, and the fourth power tube is turned off.
  • the control logic can be specifically implemented by the configuration of specific types, parameters, and circuit connection modes of the first power tube, the second power tube, the third power tube, and the fourth power tube. The following is a specific introduction.
  • the output voltage of the error amplifier circuit 320 is low, the first power tube is turned on, and the third power tube is controlled to be turned off through the preset IB1 and IB2, and the fourth power tube is turned on, and the fourth power tube is in working current.
  • the resistance changes as the voltage output by the error amplifier circuit fluctuates.
  • the gate voltage of the second power tube can be controlled to prevent the second power tube from being turned on. As a result, the first power tube is turned on and the second power tube is turned off.
  • the output voltage of the error amplifier circuit 320 is higher, the second power tube is turned on, and the third power tube is controlled to be turned on through the preset IB1 and IB2, and the fourth power tube is turned off, and the third power tube is in working current.
  • the resistance changes as the voltage output by the error amplifier circuit fluctuates.
  • the gate voltage of the first power tube can be controlled to prevent the first power tube from being turned on.
  • the second power tube is turned on and the first power tube is turned off.
  • One end of the second power tube is grounded. Therefore, when the sink current is applied, the voltage at the power output terminal of the LDO can be prevented from rising, and the output voltage can be kept stable.
  • the LDO provided in the embodiment of the application can be used for power supply stabilization to provide a stable voltage output for the load.
  • the LDO power tube circuit controls the gates of the first power tube and the second power tube through the output voltage signal of the error amplifier circuit, and controls the turning on or off of the third power tube and the fourth power tube in the control circuit, thereby controlling the first power tube
  • the second power tube is turned on or off, thus, in the source current mode, the first power tube is turned on and the second power tube is turned off; in the sink current mode, the second power tube is turned on, because the second power tube is grounded
  • the LDO output voltage can be kept stable, so that the LDO can keep the output voltage stable in the presence of sink and source currents.
  • FIG. 4 is a schematic diagram of another LDO structure in an embodiment of the present application.
  • the LDO provided by the embodiment of the present application includes: a reference voltage source 410, an error amplifier circuit 420, a power tube circuit 430, and a feedback circuit 440.
  • the LDO also includes a control circuit 450 and a bias voltage circuit 460.
  • the power tube circuit 430 includes a first power tube MPP, which is a PMOS tube, and a second power tube MNN, which is an NMOS tube.
  • the error amplifying circuit 420 includes a pair of transconductance amplifying units, including a first transconductance amplifying unit Gm (UP) and a second transconductance amplifying unit Gm (DN), and the error amplifying circuit 420 also includes a pair of 1:m currents.
  • m is the mirror ratio coefficient, which is related to the channel size of the transistor parameter inside the current mirror, m is greater than 1, for example, it can be 5, and the specific value is not limited here.
  • the current mirror specifically includes two PMOS transistors MPO1 and MPO2, and two NMOS transistors MNO1 and MNO2.
  • the gate of MPO1 is coupled to the gate of MPO2, and the gate and drain of MPO1 are short-circuited and coupled to the first transconductor.
  • the output of the amplifying unit Gm(UP), the source of MPO1 and the source of MPO2 are coupled to the LDO input voltage source Vin, and the drain of MPO2 is the first output terminal of the error amplifier circuit, which is coupled to the first input terminal of the control circuit .
  • the gate of MNO1 is coupled to the gate of MNO2.
  • the gate and drain of MNO1 are short-circuited and coupled to the output of the second transconductance amplifying unit Gm(DN).
  • the source of MNO1 is grounded, and the drain of MNO2 is the error amplifier.
  • the second output terminal is coupled to the second input terminal of the control circuit, and the source is grounded.
  • the control circuit includes a third power tube MPO3 and a fourth power tube MNO3.
  • MPO3 is a PMOS tube
  • MNO3 is an NMOS tube.
  • the source and drain of the third power tube are connected in series between the first output terminal and the second output terminal of the error amplifier, and the source and drain of the fourth power tube are connected in series with the first output terminal of the error amplifier.
  • the first output terminal of the error amplifier circuit 420 that is, the drain of MPO2
  • the second output terminal of the error amplifier circuit 420 that is, the drain of MNO2, is coupled to the source of MNO3, the drain of MPO3, and the gate of the second power tube MNN.
  • the source of the first power tube is coupled to the voltage source Vin
  • the drain of the first power tube MPP is coupled to the drain of the second power tube MNN
  • the source of the second power tube is coupled to the ground.
  • the common node of the first power tube MPP and the second power tube MNN is the output node of the LDO, and the output voltage Vout of the output node can be used to provide a stable voltage for the load.
  • the bias voltage circuit includes a PMOS tube MPO4, an NMOS tube MNO4, and a first bias current IB1 and a second bias current IB2.
  • the source of MNO4 is grounded, the gate is shorted to the drain, the drain and the gate of MNO3 are coupled to one end of the first bias current, and the other end of the first bias current is coupled to the input voltage source Vin of the LDO. Therefore, it can be determined that the first bias voltage VBN provided to the gate of MNO3 is the gate source voltage VGS of MNO4.
  • the second bias current IB2 is coupled to the gate of MPO3 and the drain of MPO4, the other end of IB2 is grounded, the source of MPO4 is coupled to the input voltage source Vin of LDO, and the gate of MPO4 is shorted to the drain Therefore, it can be determined that the second bias voltage provided to the gate of MPO3 is VIN minus the source gate voltage VSG of MPO4.
  • the first bias current can be connected in series with multiple power transistors between VIN and ground, for example, IB1 can be connected in series with the NMOS transistor MNO4-1 and the NMOS transistor MNO4-2; similarly, the second bias current can be connected in series with the NMOS transistor MNO4-1 and the NMOS transistor MNO4-2.
  • Multiple power tubes are connected in series between VIN and ground, for example, IB2 is connected in series with PMOS tube MPO4-1 and PMOS tube MPO4-2, which is not specifically limited here.
  • the drain of MIN1 is coupled to the first input terminal of the current signal booster, the drain of MIN2 is coupled to the drain of MIN3, the gate of MON3 is coupled to the gate of MIN4, the gate and drain of MIN3 are short-circuited, MIN3 and MIN4
  • the source of is coupled to the operating voltage VDD inside the LDO, and the drain of MIN4 is coupled to the second input of the current signal booster.
  • the drain of MP1 is coupled to the drain of MIN1 in the differential pair circuit
  • the gate of MP1 is coupled to the gate of MP2 and the gate of MP3, the gate of MP1 and the drain are short-circuited
  • MP1 The source of MP2 and MP3 is coupled to the internal operating voltage VDD of the LDO
  • the drain of MP2 is coupled to the drain of MN3
  • the drain of MP3 is coupled to the drain of MN2
  • the drain of MN1 is coupled to the drain of MIN4 in the differential pair circuit.
  • the gate of MN1 is coupled to the gate of MN2 and the gate of MN3, and the sources of MN1, MN2, and MN3 are grounded.
  • the drain of MP4 is coupled to the common node of MP3 and MN2, the drain and gate of MP4 are short-circuited, the gate of MP4 is coupled to the gate of MP5 and the gate of MP6, the source of MP4, the source of MP5 and MP6
  • the sources of are all coupled to the internal operating voltage VDD of the LDO, the drain of MP5 is coupled to the drain of MN6, and the drain of MP6 is coupled to the drain of MN5.
  • the drain of MN4 is coupled to the common node of MP2 and MN3, the drain and gate of MN4 are short-circuited, the gate of MN4 is coupled to the gates of MN5, MN6, the source of MN4, the source of MN5, and the source of MN6 Ground, the common node of MN6 and MP5 is coupled to the first input terminal of the current mirror, and the common node of MN5 and MP6 is coupled to the second input terminal of the current mirror.
  • the current mirror includes two PMOS transistors MPO1, MPO2, and two NMOS transistors MNO1, MNO2, MN5 and MP6.
  • the common node is coupled to the drain of MPO1, the gate and drain of MPO1 are short-circuited, and the gate of MPO1 is coupled to MPO2.
  • the gate of MPO1 and the source of MPO2 are coupled to the LDO operating voltage VDD, and the drain of MPO2 is coupled to the first input terminal of the control circuit.
  • the control circuit includes a third power tube MPO3 and a fourth power tube MNO3.
  • MPO3 is a PMOS tube
  • MNO3 is an NMOS tube.
  • the first output terminal of the error amplifier circuit 420 that is, the drain of MPO2, is coupled to the drain of MNO3, the source of MPO3, and the gate of the first power tube MPP.
  • the second output terminal of the error amplifier circuit 420 that is, the drain of MNO2, is coupled to the source of MNO3, the drain of MPO3, and the gate of the second power tube MNN.
  • the bias voltage circuit includes a PMOS tube MPO4, an NMOS tube MNO4, and a first bias current IB1 and a second bias current IB2.
  • the source of MNO4 is grounded, the gate is shorted to the drain, the drain and the gate of MNO3 are coupled to one end of the first bias current, and the other end of the first bias current is coupled to the input voltage source Vin of the LDO.
  • One end of the second bias current IB2 is coupled to the gate of MPO3 and the drain of MPO4, the other end of IB2 is grounded, the source of MPO4 is coupled to the input voltage source Vin of the LDO, and the gate of MPO4 is shorted to the drain .
  • the drain of the first power tube MPP is coupled to the drain of the second power tube MNN.
  • the common node of the first power tube MPP and the second power tube MNN is the output node of the LDO, and the output voltage Vout of the output node can be used to provide a stable voltage for the load.
  • the feedback circuit of the LDO includes a first resistor R1 and a second resistor R2 connected in series, the common node of R1 and R2 is coupled to the non-inverting input end of the error amplifier circuit, the other end of R2 is grounded, and the other end of R1 is coupled To the output terminal and voltage output terminal of the power tube circuit.
  • the LDO further includes a compensation capacitor CF, which is coupled to both ends of R1 to form feedforward compensation.
  • the present application provides a power supply voltage stabilizing system, including the low dropout voltage regulator provided in the above-mentioned embodiment, and a voltage source and load coupled to the low dropout voltage regulator.

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Abstract

Régulateur à faible perte qui est appliqué à un système d'alimentation électrique, comprend : une source de tension, une borne de masse, un circuit amplificateur d'erreur (320), un circuit de commande (350), un circuit de tube de puissance (330) et un noeud de sortie. Le circuit de tube de puissance (330) comprend un premier tube de puissance (331) et un deuxième tube de puissance (332) connectés en série entre la source de tension et la borne de masse. Un point de connexion commun du premier tube de puissance (331) et du deuxième tube de puissance (332) est couplé au noeud de sortie. Le circuit amplificateur d'erreur (320) est utilisé pour fournir une tension de commande aux grilles du premier tube de puissance (331) et du deuxième tube de puissance (332) sur la base de la tension du noeud de sortie. Le circuit amplificateur d'erreur (320) comprend une première borne de sortie et une seconde borne de sortie. La première borne de sortie est couplée à la grille du premier tube de puissance (331), et la seconde borne de sortie est couplée à la grille du deuxième tube de puissance (332). Le circuit de commande (350) comprend un troisième tube de puissance (351) et un quatrième tube de puissance (352). Une source et un drain du troisième tube de puissance (351) sont connectés en série entre la première borne de sortie et la seconde borne de sortie. Une source et un drain du quatrième tube de puissance (352) sont connectés en série entre la première borne de sortie et la seconde borne de sortie.
PCT/CN2019/103781 2019-08-30 2019-08-30 Régulateur à faible perte WO2021035707A1 (fr)

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Application Number Priority Date Filing Date Title
PCT/CN2019/103781 WO2021035707A1 (fr) 2019-08-30 2019-08-30 Régulateur à faible perte
CN201980098699.0A CN114144741A (zh) 2019-08-30 2019-08-30 一种低压差稳压器

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PCT/CN2019/103781 WO2021035707A1 (fr) 2019-08-30 2019-08-30 Régulateur à faible perte

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CN113885633A (zh) * 2021-11-02 2022-01-04 中微半导体(深圳)股份有限公司 一种低压差nmos型稳压器及迟滞控制方法
CN114337226A (zh) * 2021-12-31 2022-04-12 上海艾为微电子技术有限公司 功率管的保护电路、电源保护芯片以及设备
CN115202427A (zh) * 2021-04-09 2022-10-18 上海艾为电子技术股份有限公司 一种稳压电路及电源管理芯片
TWI811974B (zh) * 2022-01-26 2023-08-11 大陸商星宸科技股份有限公司 具有雙向電流調整的低壓差穩壓器
CN117539318A (zh) * 2024-01-09 2024-02-09 龙骧鑫睿(厦门)科技有限公司 一种高电源抑制比的无片外电容ldo电路

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116954297B (zh) * 2023-09-19 2023-12-15 深圳市思远半导体有限公司 一种电源选择电路和电源

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101127510A (zh) * 2006-08-17 2008-02-20 松下电器产业株式会社 差分输入d类放大器
CN101552841A (zh) * 2008-03-31 2009-10-07 恩益禧电子股份有限公司 输出放大电路及使用该电路的显示装置的数据驱动器
CN101893908A (zh) * 2010-07-08 2010-11-24 西安启芯微电子有限公司 灌入/拉出电流快速响应线性电压调节器及调节方法
CN102163399A (zh) * 2010-02-18 2011-08-24 瑞萨电子株式会社 输出电路、数据驱动器及显示装置
CN103092241A (zh) * 2011-10-27 2013-05-08 厦门立昂电子科技有限公司 一种混合补偿式高稳定性ldo芯片电路
CN103383581A (zh) * 2012-05-04 2013-11-06 瑞昱半导体股份有限公司 一种具暂态响应增强机制的电压调节装置
US20140062594A1 (en) * 2012-08-30 2014-03-06 Infineon Technologies Ag Chip card

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7589507B2 (en) * 2005-12-30 2009-09-15 St-Ericsson Sa Low dropout regulator with stability compensation
CN103324237B (zh) * 2013-06-09 2015-05-06 中山大学 一种基于电压感应的ldo瞬态响应增强电路
US9488999B2 (en) * 2014-07-25 2016-11-08 Aeroflex Colorado Springs Inc. Voltage regulator for systems with a high dynamic current range
CN110058632A (zh) * 2014-12-29 2019-07-26 意法半导体研发(深圳)有限公司 低压差放大器

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101127510A (zh) * 2006-08-17 2008-02-20 松下电器产业株式会社 差分输入d类放大器
CN101552841A (zh) * 2008-03-31 2009-10-07 恩益禧电子股份有限公司 输出放大电路及使用该电路的显示装置的数据驱动器
CN102163399A (zh) * 2010-02-18 2011-08-24 瑞萨电子株式会社 输出电路、数据驱动器及显示装置
CN101893908A (zh) * 2010-07-08 2010-11-24 西安启芯微电子有限公司 灌入/拉出电流快速响应线性电压调节器及调节方法
CN103092241A (zh) * 2011-10-27 2013-05-08 厦门立昂电子科技有限公司 一种混合补偿式高稳定性ldo芯片电路
CN103383581A (zh) * 2012-05-04 2013-11-06 瑞昱半导体股份有限公司 一种具暂态响应增强机制的电压调节装置
US20140062594A1 (en) * 2012-08-30 2014-03-06 Infineon Technologies Ag Chip card

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115202427A (zh) * 2021-04-09 2022-10-18 上海艾为电子技术股份有限公司 一种稳压电路及电源管理芯片
CN115202427B (zh) * 2021-04-09 2023-12-12 上海艾为电子技术股份有限公司 一种稳压电路及电源管理芯片
CN113885633A (zh) * 2021-11-02 2022-01-04 中微半导体(深圳)股份有限公司 一种低压差nmos型稳压器及迟滞控制方法
CN114337226A (zh) * 2021-12-31 2022-04-12 上海艾为微电子技术有限公司 功率管的保护电路、电源保护芯片以及设备
TWI811974B (zh) * 2022-01-26 2023-08-11 大陸商星宸科技股份有限公司 具有雙向電流調整的低壓差穩壓器
CN117539318A (zh) * 2024-01-09 2024-02-09 龙骧鑫睿(厦门)科技有限公司 一种高电源抑制比的无片外电容ldo电路
CN117539318B (zh) * 2024-01-09 2024-03-26 龙骧鑫睿(厦门)科技有限公司 一种高电源抑制比的无片外电容ldo电路

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