WO2021027242A1 - 具有Г型栅的 GaN 基 MIS-HEMT 器件及制备方法 - Google Patents

具有Г型栅的 GaN 基 MIS-HEMT 器件及制备方法 Download PDF

Info

Publication number
WO2021027242A1
WO2021027242A1 PCT/CN2019/130993 CN2019130993W WO2021027242A1 WO 2021027242 A1 WO2021027242 A1 WO 2021027242A1 CN 2019130993 W CN2019130993 W CN 2019130993W WO 2021027242 A1 WO2021027242 A1 WO 2021027242A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gate
source
gan
drain electrodes
Prior art date
Application number
PCT/CN2019/130993
Other languages
English (en)
French (fr)
Inventor
王洪
陈竟雄
刘晓艺
Original Assignee
中山市华南理工大学现代产业技术研究院
华南理工大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中山市华南理工大学现代产业技术研究院, 华南理工大学 filed Critical 中山市华南理工大学现代产业技术研究院
Publication of WO2021027242A1 publication Critical patent/WO2021027242A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Definitions

  • the invention belongs to the field of semiconductor technology, and particularly relates to a GaN-based MIS-HEMT device with a ⁇ gate structure and a preparation method.
  • GaN gallium nitride
  • GaN gallium nitride
  • the wide-gap group III nitride material represented by gallium nitride (GaN) is called the third-generation semiconductor material, and the wide-gap semiconductor materials and devices based on GaN are developing very rapidly.
  • GaN is a III-V direct bandgap semiconductor with wide band gap, high breakdown field strength, high saturated electron drift speed and high temperature resistance.
  • the band gap of 3.4ev makes GaN very suitable for microwave/millimeter wave Application of power devices.
  • GaN can be modulated with AlGaN
  • the hybrid AlGaN/GaN heterojunction structure, the two-dimensional electron gas conduction channel formed at room temperature has the characteristics of high electron concentration and high electron mobility. Compared with the bulk electron channel of silicon devices, the switching rate is greatly Improved and lower cooling requirements compared to silicon devices. Therefore, GaN HEMT devices have broad application prospects in the field of microwave power.
  • the gate line width of GaN-based MIS-HEMT devices is determined by photolithography.
  • the most commonly used methods are mainly G-line, I-line, deep ultraviolet and extreme ultraviolet lithography with shorter wavelengths, and electron beam lithography.
  • the G-line and I-line lithography technology has the advantages of simple process, low cost and high efficiency. However, the minimum line width is limited by the wavelength of the light source.
  • General G-line and I-line lithography machines can only achieve grid lines of 0.5 ⁇ m or more. The grid lines below 0.5 ⁇ m require a stepping lithography machine or some special skills, the process is complicated, the consistency is not high, and the requirements for the mask are higher than that of the contact lithography machine.
  • the gate length produced by the electron beam direct writing method can reach the nanometer level, and the consistency is very good.
  • the production efficiency is low, the equipment is expensive and the maintenance cost is high, and it is generally only used for experimental research.
  • the deep ultraviolet or extreme ultraviolet lithography machine adopts a shorter wavelength light source, and the resolution can reach 0.05-0.25 ⁇ m.
  • the cost is higher and the efficiency is low.
  • the purpose of the present invention is to overcome the limitations of the gate photolithography process and low power density of the existing GaN-based MIS-HEMT device, and propose a GaN-based MIS- with a ⁇ gate structure from the perspective of the gate process and device structure.
  • the HEMT device and the preparation method thereof can effectively improve the frequency characteristics and power characteristics of the device, so as to meet the requirements of large-scale production with high efficiency and high yield.
  • the present invention provides a GaN-based MIS-HEMT device with a ⁇ -type gate, which includes an AlGaN/GaN heterojunction epitaxial layer, the AlGaN/GaN heterojunction epitaxial layer is a boss structure, and the upper part of the boss is active
  • the two ends of the upper surface of the active area are respectively connected to the source and drain electrodes.
  • the areas on the source and drain electrodes and the upper surface of the active area are connected to the source and drain electrodes, and are covered with a gate dielectric layer and a passivation layer from bottom to top.
  • the passivation layer and the passivation layer are provided with first openings on the upper surface of the source and drain electrodes, respectively exposing part of the upper surface of the source and drain electrodes, and the passivation layer is provided with a second opening on the gate dielectric layer between the source and drain electrodes, The upper surface of the gate dielectric layer is exposed, and the second opening is also connected to a ⁇ -shaped gate electrode.
  • the ⁇ -shaped gate electrode includes a gate cap and a gate foot. The vertical side part of the ⁇ -shaped side is the gate foot, and the horizontal side part is the gate cap.
  • One end of the pin is connected to a part of the lower surface of the gate cap, the other end is connected to the upper surface of the gate dielectric layer partially exposed at the second opening, and the remaining lower surface of the gate cap is connected to the upper surface of the passivation layer.
  • the material layer of the gate electrode is more than three metal layers or metal nitride layers; the top material layer is more than one of Ni, TiN, WN, Cr, and TiW; the material layer of the middle layer is Au or Al; The bottom material layer is more than one of TiN, WN, Cr, and TiW; the total thickness of the gate electrode is 200-300 nm; the left and right width of the gate foot is 0.2-0.5 ⁇ m; the left and right width of the gate cap is 0.4-1 ⁇ m.
  • the thickness of the AlGaN/GaN heterojunction epitaxial layer is 500-1000 ⁇ m, and the thickness of the active region is 100-300 nm.
  • the source and drain electrodes are Ti layer, Al layer, Ni layer and Au layer deposited sequentially from bottom to top on the upper surface of the active region, the thickness of the source and drain electrodes is 200-300nm; Ti layer, Al layer, Ni layer and The thickness of the Au layer is 10-30nm, 80-120nm, 5-15nm, 80-120nm, respectively.
  • the gate dielectric layer is SiN; the thickness of the gate dielectric layer is 5-15 nm; the passivation layer is SiN or SiO 2 , and the thickness of the passivation layer is 65-150 nm.
  • the left and right width of the second opening is 0.35-1 ⁇ m.
  • the present invention also provides a method for preparing a GaN-based MIS-HEMT device with a ⁇ -shaped gate as described above, which includes the following steps:
  • AlGaN/GaN heterojunction epitaxial layer preparation and cleaning AlGaN/GaN heterojunction epitaxial layer is prepared by metal organic vapor deposition MOCVD, and then the AlGaN/GaN heterojunction epitaxial layer is soaked in an acid solution to remove surface oxidation Layer, and then use an organic solvent to remove the organic matter on the AlGaN/GaN heterojunction epitaxial layer;
  • Annealing of the source and drain electrodes to form ohmic contacts define the metal positions and patterns of the source and drain electrodes on the isolated active area through a negative photolithography process, and deposit the source and drain electrodes; annealing in a nitrogen atmosphere at a temperature above 800°C 30-90s, make the source and drain electrodes form an ohmic contact with the AlGaN barrier layer;
  • the gate electrode by optical lithography combined with stripping or etching: use the I-line or G-line lithography machine to expose the gate electrode pattern at the second opening, and then use electron beam evaporation or magnetron sputtering on the source and drain electrodes
  • the material layer of the gate electrode is deposited between, and the ⁇ -shaped gate electrode is prepared by stripping; or the material layer of the gate electrode is deposited by electron beam evaporation or magnetron sputtering, and the gate electrode pattern area is exposed at the second opening, and then
  • the ⁇ -shaped gate electrode is prepared by reducing the left and right widths of the gate cap and the gate foot by anisotropic etching of the photoresist and etching the gate electrode material layer outside the gate electrode pattern area by inductively coupled plasma;
  • Source and drain electrode openings Expose the area outside the first opening protected by the photoresist by optical lithography, and remove the passivation layer and gate dielectric layer at the first opening on the source and drain electrodes by inductively coupled plasma etching ;
  • Isolation and etching to form an independent active area define the active area on the AlGaN/GaN epitaxial layer, and use photoresist to cover the active area; use inductively coupled plasma etching ICP or reactive ion etching RIE The AlGaN/GaN heterojunction epitaxial layer outside the active area is removed, and the etching depth is 100-300nm.
  • the method of depositing the source and drain electrodes is electron beam evaporation or magnetron sputtering.
  • the method of gate dielectric layer deposition is metal organic chemical vapor deposition MOCVD or low pressure chemical vapor deposition method LPCVD.
  • the deposition method of the passivation layer is a plasma enhanced chemical vapor deposition method PECVD.
  • the present invention has the following beneficial effects and advantages:
  • the gate dielectric layer of the present invention adopts SiN grown by low-pressure chemical vapor deposition LPCVD, which has high compactness and is chemically much slower than SiN grown by plasma-enhanced chemical vapor deposition PECVD to react with hydrofluoric acid. Opening the passivation layer through a combination of physical etching and chemical etching to reduce damage to the gate dielectric layer caused by physical etching, thereby reducing gate leakage and improving device performance;
  • LPCVD Low-pressure chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • the first advantage is that G-line and I-line lithography, including contact lithography and stepping lithography, can be combined with metal stripping process or metal etching process, and passivation By aligning the layer opening, part of the gate metal is in contact with the gate dielectric layer, and the other part is in contact with the passivation layer, so that the gate foot line width is greatly reduced under the limit line width of photolithography; the second advantage
  • This ⁇ gate structure introduces a field plate to modulate the electric field intensity distribution of the conductive channel on the drain side of the gate.
  • FIG. 1 is a flowchart of a method for preparing a GaN-based MIS-HEMT device with a ⁇ gate structure provided by an embodiment
  • FIGS. 2 to 10 are schematic diagrams during the manufacturing process of the GaN-based MIS-HEMT device with the ⁇ gate structure provided by the embodiment;
  • the figure shows: 1-AlGaN/GaN heterojunction epitaxial layer; 2-active area; 3-source and drain electrode; 4-gate dielectric layer; 5-passivation layer; 6-gate electrode; 7-photoresist Layer; 8-gate electrode material layer.
  • This embodiment provides a GaN-based MIS-HEMT device with a ⁇ -type gate, as shown in FIG. 10, comprising an AlGaN/GaN heterojunction epitaxial layer 1, and the AlGaN/GaN heterojunction epitaxial layer 1 is a boss Structure, the upper part of the boss is the active area 2, the two ends of the upper surface of the active area 2 are respectively connected to the source and drain electrodes 3, the source and drain electrodes 3 and the upper surface of the active area 2 are connected to the area other than the source and drain electrodes 3 from below The upper surface is sequentially covered with a gate dielectric layer 4 and a passivation layer 5.
  • the gate dielectric layer 4 and the passivation layer 5 are provided with first openings on the upper surface of the source and drain electrodes 3, respectively exposing part of the upper surface of the source and drain electrodes 3
  • the passivation layer 5 is provided with a second opening on the gate dielectric layer 4 between the source and drain electrodes 3, exposing the upper surface of the gate dielectric layer 4, and the second opening is also connected to a ⁇ -shaped gate electrode 6.
  • the electrode 6 includes a grid cap and a grid foot.
  • the vertical side part of the ⁇ shape is a grid foot, and the horizontal side part is a grid cap.
  • One end of the grid foot is connected to a part of the bottom surface of the grid cap, and the other end is partially exposed at the second opening.
  • the upper surface of the dielectric layer 4 is connected, and the remaining lower surface of the gate cap is connected to the upper surface of the passivation layer 5.
  • the gate dielectric layer 4 and the AlGaN/GaN heterojunction epitaxial layer 1 form an MIS structure.
  • the material layers of the gate electrode 6 are the lower TiN metal layer, the middle Au metal layer, and the upper TiN gold metal layer.
  • the thickness of the upper TiN metal layer and the lower TiN metal layer is 50 nm, and the thickness of the middle Au metal layer is 200 nm.
  • the total thickness of the electrode 6 is 300 nm; the left and right width of the gate foot is 0.5 ⁇ m; the left and right width of the gate cap is 1 ⁇ m.
  • the thickness of the AlGaN/GaN heterojunction epitaxial layer 1 is 500 ⁇ m.
  • the thickness of the active region 2 is 300 nm.
  • the source and drain electrodes 3 are Ti layer, Al layer, Ni layer and Au layer deposited sequentially from bottom to top on the upper surface of active region 2.
  • the thickness of Ti layer, Al layer, Ni layer and Au layer are respectively 20nm, 100nm, 10nm and 100nm.
  • the gate dielectric layer 4 is SiN; the thickness of the gate dielectric layer 4 is 10 nm; the passivation layer 5 is SiO 2 , and the thickness of the passivation layer 5 is 100 nm.
  • the left and right width of the second opening is 0.7 ⁇ m.
  • This embodiment provides a method for preparing a GaN-based MIS-HEMT device with a ⁇ -shaped gate as described above, as shown in FIG. 1, including the following steps:
  • Annealing the source and drain electrodes to form ohmic contacts define the metal positions and patterns of the source and drain electrodes on the isolated active region 2 through a negative photolithography process, and deposit Ti/Al/Ni/ from bottom to top through electron beam evaporation. Au, forming the source and drain electrodes 3 through a lift-off process; annealing in a nitrogen atmosphere at a temperature of 830° C. for 60 s to make the source and drain electrodes 3 and the AlGaN barrier layer form an ohmic contact, as shown in FIG. 3;
  • the gate dielectric layer 4 is deposited on the upper surface of the source and drain electrodes 3 and the AlGaN/GaN heterojunction epitaxial layer 1 except for the source and drain electrodes 3 by low pressure chemical vapor deposition method LPCVD. ; On the gate dielectric layer 4, the passivation layer 5 is deposited by plasma enhanced chemical vapor deposition method PECVD; as shown in Figure 4;
  • a photoresist layer 7 is deposited on the upper surface of the passivation layer 5 and the upper surface of the exposed gate dielectric layer, which is defined by a photolithography process
  • the gate electrode pattern is exposed at the second opening, then TiN is deposited by magnetron sputtering, Au is evaporated by electron beam, and a ⁇ -shaped gate electrode 6 is prepared by stripping, as shown in FIG. 8;
  • Source and drain electrode openings expose the area outside the first opening protected by the photoresist by optical lithography, and remove the passivation layer 5 and gate dielectric at the first opening on the source and drain electrodes by inductively coupled plasma etching Layer 4, as shown in Figure 9;
  • the active area 2 is defined on the AlGaN/GaN epitaxial layer by a positive photolithography process, and the active area 2 is covered and protected by photoresist; using inductively coupled plasma etching Etching ICP or reactive ion etching RIE removes the AlGaN/GaN heterojunction epitaxial layer outside the active area, and the etching depth is 300 nm, as shown in Figure 10.
  • the device uses low-pressure chemical vapor deposition LPCVD to form the gate dielectric layer SiN, and uses plasma-enhanced chemical vapor deposition PECVD to deposit the Si02 passivation layer on the gate dielectric layer, using the difference in the reaction speed between the two and hydrofluoric acid.
  • the combination of physical etching and chemical etching opens the passivation layer and greatly reduces the ion damage caused by physical etching to the gate dielectric layer.
  • the GaN-based MIS-HEMT device with a ⁇ gate structure was realized by lithography alignment and stripping of the gate metal at the opening of the passivation layer. This structure makes the gate foot line width break the limit of G line or I line lithography.
  • the line width is greatly reduced, and the electric field intensity distribution of the conductive channel on the drain side of the gate is modulated, and the breakdown voltage of the device is improved.
  • Plasma-enhanced chemical vapor deposition PECVD and low-pressure chemical vapor deposition LPCVD are both mature processes for the industrial production of semiconductors.
  • the above-mentioned GaN-based MIS-HEMT device with a ⁇ gate structure is suitable for large-scale production to reduce the gate leakage of the device and improve the device Breakdown characteristics, frequency and power characteristics.
  • This embodiment provides a GaN-based MIS-HEMT device with a ⁇ -type gate, as shown in FIG. 10, comprising an AlGaN/GaN heterojunction epitaxial layer 1, and the AlGaN/GaN heterojunction epitaxial layer 1 is a boss Structure, the upper part of the boss is the active area 2, the two ends of the upper surface of the active area 2 are respectively connected to the source and drain electrodes 3, the source and drain electrodes 3 and the upper surface of the active area 2 are connected to the area other than the source and drain electrodes 3 from below The upper surface is sequentially covered with a gate dielectric layer 4 and a passivation layer 5.
  • the gate dielectric layer 4 and the passivation layer 5 are provided with first openings on the upper surface of the source and drain electrodes 3, respectively exposing part of the upper surface of the source and drain electrodes 3
  • the passivation layer 5 is provided with a second opening on the gate dielectric layer 4 between the source and drain electrodes 3, exposing the upper surface of the gate dielectric layer 4, and the second opening is also connected to a ⁇ -shaped gate electrode 6.
  • the electrode 6 includes a grid cap and a grid foot.
  • the vertical side part of the ⁇ shape is a grid foot, and the horizontal side part is a grid cap.
  • One end of the grid foot is connected to a part of the bottom surface of the grid cap, and the other end is partially exposed at the second opening.
  • the upper surface of the dielectric layer 4 is connected, and the remaining lower surface of the gate cap is connected to the upper surface of the passivation layer 5.
  • the gate dielectric layer 4 and the AlGaN/GaN heterojunction epitaxial layer 1 form an MIS structure.
  • the material layer of the gate electrode 6 is a three-layer metal layer of Cr, Al and Cr deposited sequentially from bottom to top.
  • the thickness of the metal layer is 50nm, 200nm and 50nm, and the total thickness is 300nm; the left and right width of the gate foot is 0.5 ⁇ m; The left and right width of the cap is 1 ⁇ m.
  • the thickness of the AlGaN/GaN heterojunction epitaxial layer 1 is 500 ⁇ m, and the thickness of the active region 2 is 300 nm.
  • the source and drain electrodes 3 are Ti layer, Al layer, Ni layer and Au layer deposited sequentially from bottom to top on the upper surface of active region 2.
  • the thickness of Ti layer, Al layer, Ni layer and Au layer are respectively 20nm, 100nm, 10nm and 100nm.
  • the gate dielectric layer 4 is SiN; the thickness of the gate dielectric layer 4 is 10 nm; the passivation layer 5 is SiO 2 , and the thickness of the passivation layer 5 is 100 nm.
  • the left and right width of the second opening is 0.7 ⁇ m.
  • This embodiment provides a method for preparing a GaN-based MIS-HEMT device with a ⁇ -shaped gate as described above, as shown in FIG. 1, including the following steps:
  • Annealing the source and drain electrodes to form ohmic contacts define the metal positions and patterns of the source and drain electrodes on the isolated active region 2 through a negative photolithography process, and deposit Ti/Al/Ni/ from bottom to top through electron beam evaporation. Au, forming the source and drain electrodes 3 through a lift-off process; annealing in a nitrogen atmosphere at a temperature of 830° C. for 60 s to make the source and drain electrodes 3 and the AlGaN barrier layer form an ohmic contact, as shown in FIG. 3;
  • the gate dielectric layer is deposited on the upper surface of the source and drain electrodes 3 and the AlGaN/GaN heterojunction epitaxial layer 1 except for the source and drain electrodes 3 through the metal organic chemical vapor deposition method (MOCVD) 4; Using plasma-enhanced chemical vapor deposition method PECVD to deposit the passivation layer 5 on the gate dielectric layer 4; as shown in Figure 4;
  • MOCVD metal organic chemical vapor deposition method
  • Source and drain electrode openings expose the area outside the first opening protected by the photoresist by optical lithography, and remove the passivation layer 5 and gate dielectric at the first opening on the source and drain electrodes by inductively coupled plasma etching Layer 4, as shown in Figure 9;
  • the active area 2 is defined on the AlGaN/GaN epitaxial layer by a positive photolithography process, and the active area 2 is covered and protected by photoresist; using inductively coupled plasma etching Etching ICP or reactive ion etching RIE removes the AlGaN/GaN heterojunction epitaxial layer outside the active area, and the etching depth is 300 nm, as shown in Figure 10.
  • the gate dielectric layer adopts metal organic vapor deposition (MOCVD) to deposit SiN gate dielectric film, and the special gate process adopts an etching process instead of a stripping process.
  • MOCVD metal organic vapor deposition
  • the advantage of the gate etching process is that compared with the lift-off process, the yield is higher, and the gate line width can be further reduced by anisotropic etching of the photoresist. Under the same optical lithography precision, the gate etching process can achieve a smaller gate line width, higher efficiency and better consistency.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

一种具有Γ型栅的GaN基MIS-HEMT器件及其制备方法，所述器件包括AlGaN/GaN异质结外延层（1）等结构，所述器件还包括一Γ型栅电极（6），所述Γ型栅电极（6）包括栅帽和栅脚，栅脚的一端和栅帽的部分下表面连接，另一端和第二开口处部分暴露的栅介质层（4）上表面连接，栅帽的其余下表面和钝化层（5）上表面连接。利用G线、I线光刻包括接触式光刻和步进式光刻与金属剥离工艺或金属刻蚀工艺结合，通过在钝化层（5）开口处通过对准的方式，使一部分的栅极（6）与栅介质层（4）接触，另一部分与钝化层（5）接触，使栅极（6）线宽在光刻的极限线宽下大大减小；所述Γ栅结构（6），引入了场板，场板调制了栅（6）靠漏（3）侧导电沟道的电场强度分布，提高了器件的击穿电压。

Description

具有Γ型栅的GaN基MIS-HEMT器件及制备方法 技术领域
本发明属于半导体技术领域，特别涉及一种具有Γ栅结构的GaN基MIS-HEMT器件及制备方法。
背景技术
以氮化镓(GaN)为代表的宽禁带III族氮化物材料其合金被称为第三代半导体材料，基于GaN的宽禁带半导体材料与器件发展的十分迅猛。GaN是III-V族直接带隙半导体，具有宽禁带、高击穿场强、高的饱和电子漂移速度和耐高温的特性，其中3.4ev的禁带宽度让GaN十分适合微波/毫米波大功率器件的应用。另外，GaN可以与AlGaN形成调制
Figure PCTCN2019130993-appb-000001
杂的AlGaN/GaN异质结结构，在室温下形成的二维电子气导电沟道具有高电子浓度与高电子迁移率的特性，相比于硅器件的体电子沟道而言，开关速率大大提高，并且相比于硅器件降温要求更低。因此氮化镓HEMT器件在微波功率领域具有广泛的应用前景。
近年来微波放大器领域迫切需要具有高频率和高功率密度的器件。由HEMT器件的小信号特性和大信号特性可知，栅长越短器件的截止频率和最大震荡频率越高，而器件的栅压摆幅和击穿电压越高，功率密度越高。这就要求在工艺的限制下，尽可能缩小栅长，并通过在栅电极和AlGaN势垒层之间插入绝缘介质层形成MIS结构提高栅压摆幅，以及通过场板结构如Γ栅结构调制沟道电场分布提高器件的击穿电压。
目前GaN基MIS-HEMT器件的栅极线宽由光刻决定，最常用的手段主要有G线、I线、波长更短的深紫外和极紫外光刻、以及电子束光刻技术。
G线和I线光刻技术具有工艺简单、成本低、效率高的优点。但其最小线宽被光源的波长所限制，一般的G线、I线光刻机只能做到0.5μm以上的栅线条。而0.5μm以下的栅线条则需要步进式光刻机或者一些特殊的技巧，工艺复杂，一致性不高，对掩膜的要求相比于接触式光刻机更高。
电子束直写的方法制作的栅长可以达到纳米水平，且一致性非常好。但生产效 率低下，设备昂贵维护成本高，一般只能用于实验研究。另外深紫外或极紫外光刻机由于采用了波长更短的光源，分辨率更高可以达到0.05-0.25μm，但相比于G线、I线光刻技术成本更高、效率低。
因此，寻找一种工艺简单、高效率、低成本的深亚微米栅长的Γ栅结构的GaN基MIS-HEMT器件制备方法是本行业亟待解决的问题。
发明概述
技术问题
问题的解决方案
技术解决方案
本发明的目的在于克服已有的GaN基MIS-HEMT器件栅极光刻工艺的限制和功率密度不高的不足，从栅极工艺与器件结构的角度提出一种具有Γ栅结构的GaN基MIS-HEMT器件及其制备方法，可以有效的提高器件频率特性和功率特性，以满足高效率、高成品率的规模化生产的需求。
本发明的目的是通过以下技术方案之一实现的。
本发明提供了一种具有Γ型栅的GaN基MIS-HEMT器件，包括AlGaN/GaN异质结外延层，所述AlGaN/GaN异质结外延层为凸台结构，凸台上部分为有源区，有源区上表面的两端分别连接源漏电极，源漏电极上和有源区上表面连接源漏电极以外的区域从下到上依次覆盖有栅介质层和钝化层，栅介质层和钝化层在源漏电极的上表面均设有第一开口，分别暴露出源漏电极的部分上表面，钝化层在源漏电极之间的栅介质层上设有第二开口，暴露出栅介质层上表面，第二开口处还连接Γ型栅电极，所述Γ型栅电极包括栅帽和栅脚，Γ型的竖边部分为栅脚，横边部分为栅帽，栅脚的一端和栅帽的部分下表面连接，另一端和第二开口处部分暴露的栅介质层上表面连接，栅帽的其余下表面和钝化层上表面连接。
优选地，栅电极的材料层为三层以上的金属层或金属氮化物层；顶层材料层为Ni、TiN、WN、Cr、TiW中的一种以上；中间层的材料层为Au或Al；底层材料层为TiN、WN、Cr、TiW中的一种以上；栅电极的总厚度为200-300nm；栅脚的左右宽度为0.2-0.5μm；栅帽的左右宽度为0.4-1μm。
优选地，AlGaN/GaN异质结外延层的厚度为500-1000μm，有源区的厚度为100-300nm。
优选地，源漏电极为在有源区上表面从下到上依次沉积的Ti层、Al层、Ni层和Au层，源漏电极的厚度为200-300nm；Ti层、Al层、Ni层和Au层的厚度分别为10-30nm、80-120nm、5-15nm、80-120nm。
优选地，栅介质层为SiN；栅介质层的厚度为5-15nm；钝化层为SiN或SiO 2，钝化层的厚度为65-150nm。
优选地，第二开口的左右宽度为0.35-1μm。
本发明还提供了一种制备如上所述的具有Γ型栅的GaN基MIS-HEMT器件的方法，包括以下步骤：
(1)AlGaN/GaN异质结外延层准备及清洗：通过金属有机气相沉积MOCVD制备AlGaN/GaN异质结外延层，然后将AlGaN/GaN异质结外延层浸泡于酸性溶液中，去除表面氧化层，再采用有机溶剂去除AlGaN/GaN异质结外延层上的有机物；
(2)源漏电极退火形成欧姆接触：通过负胶光刻工艺实现隔离的有源区上界定源漏电极金属位置及图形，沉积源漏电极；在氮气氛围下，800℃以上的温度中退火30-90s，使源漏电极与AlGaN势垒层形成欧姆接触；
(3)沉积栅介质层及钝化层：在源漏电极和AlGaN/GaN异质结外延层上表面连接源漏电极以外的区域上沉积栅介质层；在栅介质层上沉积钝化层；
(4)去除源电极和漏电极间的部分钝化层：通过光刻方法曝光光刻胶，保护第二开口以外的区域，再通过物理刻蚀的方法去除60-140nm厚度的钝化层，剩余5-10nm的钝化层利用化学刻蚀的方法去除，暴露栅介质层上表面；
(5)通过光学光刻结合剥离或刻蚀制备栅电极：利用I线或G线光刻机，在第二开口处曝光栅电极图形，然后通过电子束蒸发或磁控溅射在源漏电极之间沉积栅电极的材料层，通过剥离的方式制备出Γ型栅电极；或者先通过电子束蒸发或磁控溅射沉积栅电极的材料层，在第二开口处曝光栅电极图形区域，再通过各向异性刻蚀光刻胶缩小栅帽和栅脚的左右宽度及感应耦合等离子体刻蚀刻蚀栅电极图形区域外的栅电极材料层制备出Γ型栅电极；
(6)源漏电极开口：通过光学光刻曝光光刻胶保护的第一开口以外的区域，通过感应耦合等离子体刻蚀去除掉源漏电极上的第一开口处钝化层和栅介质层；
(7)隔离刻蚀形成独立有源区：在AlGaN/GaN外延层上界定有源区，采用光刻胶对有源区进行覆盖保护；利用感应耦合等离子体刻蚀ICP或者反应离子刻蚀RIE对有源区以外的AlGaN/GaN异质结外延层进行去除，刻蚀深度为100-300nm。
优选地，沉积源漏电极的方法为电子束蒸发或磁控溅射。
优选地，栅介质层沉积的方法为金属有机化学气相沉积MOCVD或低压化学气相沉积法LPCVD。
优选地，钝化层的沉积方法为等离子体增强化学的气相沉积法PECVD。
发明的有益效果
有益效果
和现有技术相比，本发明具有以下有益效果和优点：
1)本发明栅介质层采用低压化学气相沉积LPCVD生长的SiN，致密性高，且化学性质上相比于等离子增强型化学气相沉积PECVD生长的SiN与氢氟酸反应慢的多，使之可以通过物理刻蚀和化学刻蚀结合的方法对钝化层开口，降低物理刻蚀对栅介质层的损伤，从而降低栅极漏电，提高器件性能；
2)低压化学气相沉积LPCVD或金属有机化学气相沉积MOCVD均属于半导体工业化生产的成熟工艺，可用于规模化生产中，另外这种方法可以引入栅介质层，改善器件的性能；
3)本发明通过引入Γ栅结构，第一个优点在于可以利用G线、I线光刻包括接触式光刻和步进式光刻与金属剥离工艺或金属刻蚀工艺结合，通过在钝化层开口处通过对准的方式，使一部分的栅极金属与栅介质层接触，另一部分与钝化层接触，使栅足线宽在光刻的极限线宽下大大减小；第二个优点在于通过这种Γ栅结构，引入了场板，调制了栅靠漏侧导电沟道的电场强度分布。
对附图的简要说明
附图说明
图1是实施例提供的具有Γ栅结构的GaN基MIS-HEMT器件制备方法流程图；
图2-图10是实施例提供的具有Γ栅结构的GaN基MIS-HEMT器件的制备过程中的示意图；
图中示出：1-AlGaN/GaN异质结外延层；2-有源区；3-源漏电极；4-栅介质层；5-钝化层；6-栅电极；7-光刻胶层；8-栅电极材料层。
发明实施例
本发明的实施方式
以下结合附图和实施例对本发明的具体实施作进一步说明，但本发明实施和保护不限于此，需要指出的是，以下若有为特别详细说明的过程或工艺参数均属本领域技术人员可参照现有技术实现的。
实施例1
本实施例提供了一种具有Γ型栅的GaN基MIS-HEMT器件，如图10所示，包括AlGaN/GaN异质结外延层1，所述AlGaN/GaN异质结外延层1为凸台结构，凸台上部分为有源区2，有源区2上表面的两端分别连接源漏电极3，源漏电极3上和有源区2上表面连接源漏电极3以外的区域从下到上依次覆盖有栅介质层4和钝化层5，栅介质层4和钝化层5在源漏电极3的上表面均设有第一开口，分别暴露出源漏电极3的部分上表面，钝化层5在源漏电极3之间的栅介质层4上设有第二开口，暴露出栅介质层4上表面，第二开口处还连接Γ型栅电极6，所述Γ型栅电极6包括栅帽和栅脚，Γ型的竖边部分为栅脚，横边部分为栅帽，栅脚的一端和栅帽的部分下表面连接，另一端和第二开口处部分暴露的栅介质层4上表面连接，栅帽的其余下表面和钝化层5上表面连接。
栅介质层4与AlGaN/GaN异质结外延层1形成MIS结构。
栅电极6的材料层为下层的TiN金属层、中层的Au金属层和上层的TiN金金属层，上层TiN金属层和下层TiN金属层的厚度为50nm，中层Au金属层的厚度为200nm，栅电极6的总厚度为300nm；栅脚的左右宽度为0.5μm；栅帽的左右宽度为1μm。
AlGaN/GaN异质结外延层1的厚度为500μm。
有源区2的厚度为300nm。
源漏电极3为在有源区2上表面从下到上依次沉积的Ti层、Al层、Ni层和Au层，Ti层、Al层、Ni层和Au层的厚度分别为20nm、100nm、10nm和100nm。
栅介质层4为SiN；栅介质层4的厚度为10nm；钝化层5为SiO 2，钝化层5的厚度为100nm。
第二开口的左右宽度为0.7μm。
本实施例提供了一种制备如上所述的具有Γ型栅的GaN基MIS-HEMT器件的方法，如图1所示，包括以下步骤：
(1)AlGaN/GaN异质结外延层准备及清洗：通过金属有机气相沉积MOCVD制备AlGaN/GaN异质结外延层1，然后将AlGaN/GaN异质结外延层1浸泡于H 2SO 4∶H 2O 2＝6∶1(质量比)溶液中20分钟(H 2SO 4和H 2O 2均为市售)，去除表面氧化层，再采用丙酮和异丙醇去除AlGaN/GaN异质结外延层1上的有机物，如图2所示；
(2)源漏电极退火形成欧姆接触：通过负胶光刻工艺实现隔离的有源区2上界定源漏电极金属位置及图形，通过电子束蒸发从下到上依次沉积Ti/Al/Ni/Au，通过剥离工艺形成源漏电极3；在氮气氛围下，830℃的温度中退火60s，使源漏电极3与AlGaN势垒层形成欧姆接触，如图3所示；
(3)沉积栅介质层及钝化层：在源漏电极3和AlGaN/GaN异质结外延层1上表面连接源漏电极3以外的区域上通过低压化学气相沉积法LPCVD沉积栅介质层4；在栅介质层4上采用等离子体增强化学的气相沉积法PECVD沉积钝化层5；如图4所示；
(4)去除源电极和漏电极间的部分钝化层：通过光刻方法曝光光刻胶，保护第二开口以外的区域，再通过感应耦合等离子刻蚀ICP工艺刻蚀掉90nm厚的SiO 2，再用氢氟酸(市售)腐蚀掉剩下的10nm厚的SiO 2，暴露栅介质层4上表面；如图5所示；
(5)通过光学光刻结合剥离制备栅电极：如图6所示，在钝化层5的上表面和暴露的栅介质层上表面沉积一层光刻胶层7，通过光刻工艺定义在第二开口处曝光栅电极图形，然后通过磁控溅射沉积TiN，电子束蒸发Au，通过剥离的方式制备出Γ型栅电极6，如图8所示；
(6)源漏电极开口：通过光学光刻曝光光刻胶保护的第一开口以外的区域，通过感应耦合等离子体刻蚀去除掉源漏电极上的第一开口处钝化层5和栅介质层4，如图9所示；
(7)隔离刻蚀形成独立有源区：通过正胶光刻工艺在AlGaN/GaN外延层上界定有源区2，采用光刻胶对有源区2进行覆盖保护；利用感应耦合等离子体刻蚀ICP或者反应离子刻蚀RIE对有源区以外的AlGaN/GaN异质结外延层进行去除，刻蚀深度为300nm，如图10所示。
该器件通过采用低压化学气相沉积LPCVD形成栅介质层SiN，并在栅介质层上采用等离子体增强化学的气相沉积法PECVD沉积Si02钝化层，利用两者与氢氟酸反应快慢的差异，通过物理刻蚀和化学刻蚀结合的办法，对钝化层开口并大大减小了物理刻蚀对栅介质层造成的离子损伤。接着在钝化层开口处通过光刻对准和剥离栅金属的办法实现了Γ栅结构的GaN基MIS-HEMT器件，这种结构使得栅足线宽突破G线或I线光刻的极限，线宽大大减小，并调制了栅靠漏侧导电沟道的电场强度分布，提高了器件的击穿电压。等离子增强型化学气相沉积PECVD和低压化学气相沉积LPCVD均属于半导体工业化生产的成熟工艺，上述Γ栅结构的GaN基MIS-HEMT器件适用于规模化生产中，减小器件的栅漏电，提高器件的击穿特性、频率及功率特性。
实施例2
本实施例提供了一种具有Γ型栅的GaN基MIS-HEMT器件，如图10所示，包括AlGaN/GaN异质结外延层1，所述AlGaN/GaN异质结外延层1为凸台结构，凸台上部分为有源区2，有源区2上表面的两端分别连接源漏电极3，源漏电极3上和有源区2上表面连接源漏电极3以外的区域从下到上依次覆盖有栅介质层4和钝化层5，栅介质层4和钝化层5在源漏电极3的上表面均设有第一开口，分别暴露出源漏电极3的部分上表面，钝化层5在源漏电极3之间的栅介质层4上设有第二开口，暴露出栅介质层4上表面，第二开口处还连接Γ型栅电极6，所述Γ型栅电极6包括栅帽和栅脚，Γ型的竖边部分为栅脚，横边部分为栅帽，栅脚的一端和栅帽的部分下表面连接，另一端和第二开口处部分暴露的栅介质层4上表面连接，栅帽的其余下表面和钝化层5上表面连接。
栅介质层4与AlGaN/GaN异质结外延层1形成MIS结构。
栅电极6的材料层为从下到上依次沉积的Cr、Al和Cr三层金属层，金属层的厚度依次为50nm、200nm和50nm，总厚度300nm；栅脚的左右宽度为0.5μm；栅帽的左右宽度为1μm。
AlGaN/GaN异质结外延层1的厚度为500μm，有源区2的厚度为300nm。
源漏电极3为在有源区2上表面从下到上依次沉积的Ti层、Al层、Ni层和Au层，Ti层、Al层、Ni层和Au层的厚度分别为20nm、100nm、10nm和100nm。
栅介质层4为SiN；栅介质层4的厚度为10nm；钝化层5为SiO 2，钝化层5的厚度为100nm。
第二开口的左右宽度为0.7μm。
本实施例提供了一种制备如上所述的具有Γ型栅的GaN基MIS-HEMT器件的方法，如图1所示，包括以下步骤：
(1)AlGaN/GaN异质结外延层准备及清洗：通过金属有机气相沉积MOCVD制备AlGaN/GaN异质结外延层1，然后将AlGaN/GaN异质结外延层1浸泡于H 2SO 4∶H 2O 2＝6∶1(质量比)溶液中20分钟(H 2SO 4和H 2O 2均为市售)，去除表面氧化层，再采用丙酮和异丙醇去除AlGaN/GaN异质结外延层1上的有机物，如图2所示；
(2)源漏电极退火形成欧姆接触：通过负胶光刻工艺实现隔离的有源区2上界定源漏电极金属位置及图形，通过电子束蒸发从下到上依次沉积Ti/Al/Ni/Au，通过剥离工艺形成源漏电极3；在氮气氛围下，830℃的温度中退火60s，使源漏电极3与AlGaN势垒层形成欧姆接触，如图3所示；
(3)沉积栅介质层及钝化层：在源漏电极3和AlGaN/GaN异质结外延层1上表面连接源漏电极3以外的区域上通过金属有机化学气相沉积法MOCVD沉积栅介质层4；在栅介质层4上采用等离子体增强化学的气相沉积法PECVD沉积钝化层5；如图4所示；
(4)去除源电极和漏电极间的部分钝化层：通过光刻方法曝光光刻胶，保护第二开口以外的区域，再通过感应耦合等离子刻蚀ICP工艺刻蚀掉90nm厚的SiO 2，再用氢氟酸(市售)腐蚀掉剩下的10nm厚的SiO 2，暴露栅介质层4上表面； 如图5所示；
(5)通过光学光刻结合刻蚀制备栅电极：如图7所示，通过电子束蒸发工艺在钝化层5的上表面和暴露的栅介质层上表面从下到上依次沉积依次沉积铬Cr、铝Al、铬Cr金属，这三层金属的厚度依次为50nm、100nm和50nm，通过光刻工艺定义在第二开口处曝光栅电极6图形区域，在栅电极6图形区域上覆盖一层光刻胶层7，再通过各向异性刻蚀光刻胶缩小栅帽和栅脚的左右宽度及氯基等离子体刻去除掉栅电极图形区域外的栅电极材料层制备出Γ型栅电极，如图8所示；
(6)源漏电极开口：通过光学光刻曝光光刻胶保护的第一开口以外的区域，通过感应耦合等离子体刻蚀去除掉源漏电极上的第一开口处钝化层5和栅介质层4，如图9所示；
(7)隔离刻蚀形成独立有源区：通过正胶光刻工艺在AlGaN/GaN外延层上界定有源区2，采用光刻胶对有源区2进行覆盖保护；利用感应耦合等离子体刻蚀ICP或者反应离子刻蚀RIE对有源区以外的AlGaN/GaN异质结外延层进行去除，刻蚀深度为300nm，如图10所示。
该实例相比于实例1，栅介质层采用了金属有机气相沉积MOCVD沉积SiN栅介质薄膜，特别的栅极工艺采用刻蚀工艺而非剥离工艺。栅极刻蚀工艺的优点在于相比于剥离工艺，成品率更高，并且能够通过各向异性刻蚀光刻胶进一步缩小栅极线宽。在同样的光学光刻刻精度下，栅极刻蚀工艺能实现更小的栅极线宽并且效率更高、一致性更好。
上述实施例仅为本发明的优选实例，不构成对本发明的任何限制，显然对于本领域的专业人员来说，在了解本发明的内容及原理后，能够在不背离本发明的原理和范围的情况下，根据本发明的方法进行形式和细节上的各种修正和改变，但是这些基于本发明的修正和改变仍在本发明的权利要求保护范围内。

Claims (10)

  1. 具有Γ型栅的GaN基MIS-HEMT器件，其特征在于，包括AlGaN/GaN异质结外延层，所述AlGaN/GaN异质结外延层为凸台结构，凸台上部分为有源区，有源区上表面的两端分别连接源漏电极，源漏电极上和有源区上表面连接源漏电极以外的区域从下到上依次覆盖有栅介质层和钝化层，栅介质层和钝化层在源漏电极的上表面均设有第一开口，分别暴露出源漏电极的部分上表面，钝化层在源漏电极之间的栅介质层上设有第二开口，暴露出栅介质层上表面，第二开口处还连接Γ型栅电极，所述Γ型栅电极包括栅帽和栅脚，Γ型的竖边部分为栅脚，横边部分为栅帽，栅脚的一端和栅帽的部分下表面连接，另一端和第二开口处部分暴露的栅介质层上表面连接，栅帽的其余下表面和钝化层上表面连接。
  2. 根据权利要求1所述的具有Γ型栅的GaN基MIS-HEMT器件，其特征在于，栅电极的材料层为三层以上的金属层或金属氮化物层；顶层材料层为TiN、WN、Cr、TiW中的一种以上；中间层的材料层为Au或Al；底层材料层为TiN、WN、Cr、TiW中的一种以上；栅电极的总厚度为200-300nm；栅脚的左右宽度为0.2-0.5μm；栅帽的左右宽度为0.4-1μm。
  3. 根据权利要求1所述的具有Γ型栅的GaN基MIS-HEMT器件，其特征在于，AlGaN/GaN异质结外延层的厚度为500-1000μm，有源区的厚度为100-300nm。
  4. 根据权利要求1所述的具有Γ型栅的GaN基MIS-HEMT器件，其特征在于，源漏电极为在有源区上表面从下到上依次沉积的Ti层、Al层、Ni层和Au层，源漏电极的厚度为200-300nm；Ti层、Al层、Ni层和Au层的厚度分别为10-30nm、80-120nm、5-15nm、80-120nm。
  5. 根据权利要求1所述的具有Γ型栅的GaN基MIS-HEMT器件，其特征在于，栅介质层为SiN；栅介质层的厚度为5-15nm；钝化层为Si N或SiO 2，钝化层的厚度为65-150nm。
  6. 根据权利要求1所述的具有Γ型栅的GaN基MIS-HEMT器件，其特征在于，第二开口的左右宽度为0.35-1μm。
  7. 制备如权利要求1至6任一项所述的具有Γ型栅的GaN基MIS-HEMT器件的方法，其特征在于，包括以下步骤：
    (1)AlGaN/GaN异质结外延层准备及清洗：通过金属有机气相沉积MOCVD制备AlGaN/GaN异质结外延层，然后将AlGaN/GaN异质结外延层浸泡于酸性溶液中，去除表面氧化层，再采用有机溶剂去除AlGaN/GaN异质结外延层上的有机物；
    (2)源漏电极退火形成欧姆接触：通过负胶光刻工艺实现隔离的有源区上界定源漏电极金属位置及图形，沉积源漏电极；在氮气氛围下，800℃以上的温度中退火30-90s，使源漏电极与AlGaN势垒层形成欧姆接触；
    (3)沉积栅介质层及钝化层：在源漏电极和AlGaN/GaN异质结外延层上表面连接源漏电极以外的区域上沉积栅介质层；在栅介质层上沉积钝化层；
    (4)去除源电极和漏电极间的部分钝化层：通过光刻方法曝光光刻胶，保护第二开口以外的区域，再通过物理刻蚀的方法去除60-140nm厚度的钝化层，剩余5-10nm厚度的钝化层利用化学刻蚀的方法去除，暴露栅介质层上表面；
    (5)通过光学光刻结合剥离或刻蚀制备栅电极：利用I线或G线光刻机，在第二开口处曝光栅电极图形，然后通过电子束蒸发或磁控溅射在源漏电极之间沉积栅电极的材料层，通过剥离的方式制备出Γ型栅电极；或者先通过电子束蒸发或磁控溅射沉积栅电极的材料层，在第二开口处曝光栅电极图形区域，再通过各向异性刻蚀光刻胶缩小栅帽和栅脚的左右宽度及感应耦合等离子体刻蚀刻蚀栅电极图形区域外的栅电极材料层制备出Γ型栅电极；
    (6)源漏电极开口：通过光学光刻曝光光刻胶保护的第一开口以 外的区域，通过感应耦合等离子体刻蚀去除掉源漏电极上的第一开口处钝化层和栅介质层；
    (7)隔离刻蚀形成独立有源区：在AlGaN/GaN外延层上界定有源区，采用光刻胶对有源区进行覆盖保护；利用感应耦合等离子体刻蚀ICP或者反应离子刻蚀RIE对有源区以外的AlGaN/GaN异质结外延层进行去除，刻蚀深度为100-300nm。
  8. 根据权利要求7所述的制备具有Γ型栅的GaN基MIS-HEMT器件的方法，其特征在于，沉积源漏电极的方法为电子束蒸发或磁控溅射。
  9. 根据权利要求7所述的制备具有Γ型栅的GaN基MIS-HEMT器件的方法，其特征在于，栅介质层沉积的方法为金属有机化学气相沉积MOCVD或低压化学气相沉积法LPCVD。
  10. 根据权利要求7所述的制备具有Γ型栅的GaN基MIS-HEMT器件的方法，其特征在于，钝化层的沉积方法为等离子体增强化学的气相沉积法PECVD。
PCT/CN2019/130993 2019-08-13 2019-12-31 具有Г型栅的 GaN 基 MIS-HEMT 器件及制备方法 WO2021027242A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910746035.2A CN110581170A (zh) 2019-08-13 2019-08-13 具有Г型栅的GaN基MIS-HEMT器件及制备方法
CN201910746035.2 2019-08-13

Publications (1)

Publication Number Publication Date
WO2021027242A1 true WO2021027242A1 (zh) 2021-02-18

Family

ID=68811166

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/130993 WO2021027242A1 (zh) 2019-08-13 2019-12-31 具有Г型栅的 GaN 基 MIS-HEMT 器件及制备方法

Country Status (2)

Country Link
CN (1) CN110581170A (zh)
WO (1) WO2021027242A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110581170A (zh) * 2019-08-13 2019-12-17 中山市华南理工大学现代产业技术研究院 具有Г型栅的GaN基MIS-HEMT器件及制备方法
CN111952355B (zh) * 2020-08-21 2021-03-12 浙江大学 基于多漏指结构的GaN HEMT器件及其制备方法
CN112802802B (zh) * 2021-01-15 2022-04-15 王琮 基于su-8光阻胶的半导体功率器件及其制备方法和包括其的功率模块

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5470767A (en) * 1992-08-06 1995-11-28 Mitsubishi Denki Kabushiki Kaisha Method of making field effect transistor
CN1700421A (zh) * 2004-05-21 2005-11-23 中国科学院微电子研究所 一种纳米线宽多晶硅栅刻蚀掩膜图形的形成方法
CN103779208A (zh) * 2014-01-02 2014-05-07 中国电子科技集团公司第五十五研究所 一种低噪声GaN HEMT器件的制备方法
CN105355659A (zh) * 2015-11-06 2016-02-24 西安电子科技大学 槽栅AlGaN/GaN HEMT器件结构及制作方法
CN105977147A (zh) * 2016-07-29 2016-09-28 中国电子科技集团公司第十三研究所 一种用于纳米栅制备的无损伤自终止刻蚀方法
CN110581170A (zh) * 2019-08-13 2019-12-17 中山市华南理工大学现代产业技术研究院 具有Г型栅的GaN基MIS-HEMT器件及制备方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7501669B2 (en) * 2003-09-09 2009-03-10 Cree, Inc. Wide bandgap transistor devices with field plates
CN101414624B (zh) * 2008-12-01 2010-06-30 西安电子科技大学 Г栅异质结场效应晶体管及其制作方法
CN104022151B (zh) * 2014-06-20 2018-03-02 苏州捷芯威半导体有限公司 半导体器件及其制造方法
CN105118774B (zh) * 2015-07-22 2018-03-30 中国电子科技集团公司第十三研究所 纳米t型栅的制作方法
CN105185714B (zh) * 2015-09-22 2018-09-11 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示基板和显示装置
CN107293482B (zh) * 2017-06-14 2021-03-23 成都海威华芯科技有限公司 一种氮化镓高电子迁移率晶体管栅电极的制作方法
CN211929496U (zh) * 2019-08-13 2020-11-13 中山市华南理工大学现代产业技术研究院 具有Г型栅的GaN基MIS-HEMT器件

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5470767A (en) * 1992-08-06 1995-11-28 Mitsubishi Denki Kabushiki Kaisha Method of making field effect transistor
CN1700421A (zh) * 2004-05-21 2005-11-23 中国科学院微电子研究所 一种纳米线宽多晶硅栅刻蚀掩膜图形的形成方法
CN103779208A (zh) * 2014-01-02 2014-05-07 中国电子科技集团公司第五十五研究所 一种低噪声GaN HEMT器件的制备方法
CN105355659A (zh) * 2015-11-06 2016-02-24 西安电子科技大学 槽栅AlGaN/GaN HEMT器件结构及制作方法
CN105977147A (zh) * 2016-07-29 2016-09-28 中国电子科技集团公司第十三研究所 一种用于纳米栅制备的无损伤自终止刻蚀方法
CN110581170A (zh) * 2019-08-13 2019-12-17 中山市华南理工大学现代产业技术研究院 具有Г型栅的GaN基MIS-HEMT器件及制备方法

Also Published As

Publication number Publication date
CN110581170A (zh) 2019-12-17

Similar Documents

Publication Publication Date Title
US8803199B2 (en) III-nitride semiconductor device with stepped gate
WO2021027242A1 (zh) 具有Г型栅的 GaN 基 MIS-HEMT 器件及制备方法
WO2021027241A1 (zh) 一种具有П型栅的 GaN 基射频器件及其制备方法
CN106887454B (zh) GaN基鳍栅增强型器件及其制作方法
CN107742644A (zh) 一种高性能常关型的GaN场效应晶体管及其制备方法
CN105762078A (zh) GaN基纳米沟道高电子迁移率晶体管及制作方法
CN112635544B (zh) 具有偶极子层的增强型AlGaN-GaN垂直型超结HEMT及其制备方法
KR102208076B1 (ko) 고전자 이동도 트랜지스터 및 그 제조방법
CN113690132B (zh) 一种基于双层钝化精准刻蚀的双t型栅的制备方法
EP0855748A1 (en) Heterojunction field effect transistor and method of fabricating the same
CN211929496U (zh) 具有Г型栅的GaN基MIS-HEMT器件
CN107706232A (zh) 一种原位MIS栅结构常关型GaN基晶体管及制备方法
CN114883407B (zh) 基于Fin-FET栅结构HEMT及其制作方法
CN116169169A (zh) 一种低栅泄漏电流的增强型GaN HEMTs及其制备方法
KR20110025500A (ko) 반도체 소자 및 그 형성 방법
JP2004119820A (ja) 電界効果トランジスタおよびその製造方法
CN207664047U (zh) 一种高性能常关型的GaN场效应晶体管
CN112768508B (zh) 背栅全控型AlGaN/GaN异质结增强型功率HEMT器件及制备方法
CN111129138B (zh) 基于自对准场板结构的氮化镓增强型垂直功率晶体管
CN113540229B (zh) 半导体器件及其制作方法
CN209104156U (zh) 集成增强型与耗尽型场效应管的结构
CN115274845B (zh) 一种凹陷式Fin-MESFET栅结构HEMT及制作方法
TWI813489B (zh) 電晶體結構及其製造方法
KR20140079091A (ko) 트랜지스터 및 그 제조 방법
CN111129139B (zh) 一种基于悬浮场板的自对准栅氮化镓增强型垂直功率器件

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19941692

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19941692

Country of ref document: EP

Kind code of ref document: A1