WO2021007946A1 - 一种液晶显示面板及其驱动方法 - Google Patents

一种液晶显示面板及其驱动方法 Download PDF

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Publication number
WO2021007946A1
WO2021007946A1 PCT/CN2019/106222 CN2019106222W WO2021007946A1 WO 2021007946 A1 WO2021007946 A1 WO 2021007946A1 CN 2019106222 W CN2019106222 W CN 2019106222W WO 2021007946 A1 WO2021007946 A1 WO 2021007946A1
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WO
WIPO (PCT)
Prior art keywords
data
driving circuit
lines
liquid crystal
crystal display
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PCT/CN2019/106222
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English (en)
French (fr)
Inventor
王珊
温亦谦
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/618,368 priority Critical patent/US11308908B2/en
Publication of WO2021007946A1 publication Critical patent/WO2021007946A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • This application relates to the display field, and in particular to a liquid crystal display panel and a driving method thereof.
  • the various performance requirements of the panel have increased, and the resolution requirements of the panel have also been continuously improved.
  • the refresh frequency of the panel has been increased, which has shortened the charging time of the panel.
  • the panel has more Large RC loading results in inconsistent gate opening times, further shortening the charging time. If the charging time of the panel is too short, it will cause insufficient charging, which will result in a decrease in the display effect and uniformity of the panel.
  • the main technical problem solved by this application is to provide a liquid crystal display panel and a driving method thereof, which can improve the uniformity of the liquid crystal display panel and improve the display effect.
  • a technical solution adopted in this application is to provide a liquid crystal display panel, including: a pixel unit group, including a plurality of pixel units, the plurality of pixel units are arranged in a matrix; a plurality of scan lines, Each of the scan lines is connected to at least two of the pixel units in the same row; a gate driving circuit is connected to the plurality of scan lines, and is used to provide gate signals on the scan lines to control the scan lines
  • the connected pixel units are turned on; a plurality of data lines are respectively connected to the plurality of pixel units in different columns; a data driving circuit is connected to the plurality of data lines for supplying The data line provides a data signal to charge the pixel unit connected to the data line and in the open state; wherein, the data signal provided by the data driving circuit to the plurality of data lines is sequentially delayed, so that all The opening time of the plurality of pixel units in the liquid crystal display panel matches the charging time.
  • another technical solution adopted in this application is to provide a liquid crystal display device including the liquid crystal display panel described above.
  • the data signal provided by the data driving circuit of the liquid crystal display panel in the present application to multiple data lines is sequentially delayed along the direction of the principle gate driving circuit, so that the liquid crystal display panel
  • the turn-on time of the multiple pixel units matches the charging time, so that the charging time of the data signal is sufficient, thereby solving the phenomenon of insufficient charging of the data signal due to the delay of the gate signal, causing uneven light emission of the panel, and improving the display quality of the panel.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a liquid crystal display panel provided by the present application
  • FIG. 2 is a schematic structural diagram of a second embodiment of the liquid crystal display panel provided by the present application.
  • FIG. 3 is a schematic structural diagram of a third embodiment of the liquid crystal display panel provided by the present application.
  • FIG. 4 is a schematic diagram of various signal timings of the liquid crystal display panel after the logic board is shifted provided by the present application;
  • FIG. 5 is a schematic structural diagram of a fourth embodiment of a liquid crystal display panel provided by the present application.
  • FIG. 6 is a schematic structural diagram of an embodiment of the liquid crystal display device provided by the present application.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a liquid crystal display panel provided by the present application.
  • the liquid crystal display panel 10 includes a plurality of pixel unit groups 11 such as a pixel unit 111 and a pixel unit 112, a scan line 12, a gate driving circuit 13, data lines 141 and 142, and a data driving circuit 15. Wherein, multiple pixel units in the pixel unit group 11 are arranged in a matrix.
  • Each scan line 12 connects at least two pixel units in the same row (for example, the pixel unit 111 and the pixel unit 112).
  • the gate driving circuit 13 is connected to the scan line 12 to provide a gate signal on the scan line 12 to control the pixel unit (for example, the pixel unit 111 or the pixel unit 112) connected to the scan line 12 to turn on.
  • the data line 141 and the data line 142 are respectively connected to pixel units of different columns (for example, the data line 141 is connected to the pixel unit 111, and the data line 142 is connected to the pixel unit 112).
  • the data driving circuit 15 is connected to the data lines 141 and 142, and is used to provide data signals to the data lines 141 and 142, so as to connect the data line 141 and the data line 142 and open the pixel units (ie, the pixel units 111 and 111).
  • the pixel unit 112) is charged.
  • the pixel unit 111 that is closer to the gate drive circuit 13 receives the gate signal very close to the original signal, but is farther from the gate drive circuit 13
  • the gate signal received by the pixel unit 112 is a signal that gradually increases from low to a standard value, and the pixel unit 111 is in the open state faster than the pixel unit 112.
  • the pixel circuit 111 and the pixel unit 112 are in different columns, so different data lines (data line 141 and data line 142) provide data signals.
  • the data driving circuit 15 provides data signals to the data lines 141 and 142 along the distance away from each other.
  • the direction of the gate driving circuit 13 is delayed in sequence, that is, the data signal provided to the data line 142 is delayed than the data signal provided to the data line 141, so that the data signal received by the pixel unit 112 is delayed compared with the data signal received by the pixel unit 111.
  • the turn-on time of 112 is later than that of the pixel unit 111, so the turn-on time of the pixel unit 112 matches the charging time. In this way, the charging time of the data signal is sufficient, which effectively solves the phenomenon of uneven light emission of the panel and improves the display quality of the panel.
  • the data signals provided by the data driving circuit to the multiple data lines are sequentially delayed along the direction away from the gate driving circuit, so that the opening time and the charging time of the multiple pixel units in the liquid crystal display panel By matching, the charging time of the data signal is sufficient, thereby solving the phenomenon of insufficient charging of the data signal due to the delay of the gate signal, causing the panel to emit light unevenly, and improving the display quality of the panel.
  • FIG. 2 is a schematic structural diagram of a second embodiment of the liquid crystal display panel provided by the present application.
  • the liquid crystal display panel 20 includes a plurality of pixel unit groups 21 such as a pixel unit 211 and a pixel unit 212, a scan line 22, a gate driving circuit 23, data lines 241 and 242, a data driving circuit 25, monitoring lines 261 and 262, Logic board 27.
  • a plurality of pixel units in the pixel unit group 21 are arranged in a matrix.
  • Each scan line 22 connects at least two pixel units (for example, the pixel unit 211 and the pixel unit 212) in the same row.
  • the gate driving circuit 23 is connected to the scan line 22 to provide a gate signal on the scan line 22 to control the pixel unit (for example, the pixel unit 211 or the pixel unit 212) connected to the scan line 22 to turn on.
  • the data line 241 and the data line 242 are respectively connected to pixel units of different columns (for example, the data line 241 is connected to the pixel unit 211, and the data line 242 is connected to the pixel unit 212).
  • the data driving circuit 25 is connected to the data lines 241 and 242, and is used to provide data signals to the data lines 241 and 242, so as to connect the data line 241 and the data line 242 and open the pixel units (that is, the pixel units 211 and 242).
  • the pixel unit 212) is charged.
  • the monitoring line 261 is connected to the pixel unit 211, and the monitoring line 262 is connected to the pixel unit 212, and the pixel unit 211 and the pixel unit 212 are located in the same row.
  • the monitoring line 261 and the monitoring line 262 are used to monitor the opening time of the pixel units 211 and 212, respectively.
  • the turn-on time of the pixel unit is the time when the gate signal voltage of the pixel unit reaches 90% of the standard value.
  • the standard value is the voltage value of the start pulse (STV) provided by the gate drive circuit 23.
  • the pixel unit 211 is closest to the gate drive circuit 23, the value of the STV at which the gate signal received by the pixel unit 211 is instantaneous, that is, the pixel unit 211 is instantly turned on, and the time at this time is recorded as 0 o'clock, and If the pixel unit 212 is far away from the gate driving circuit 23, the received gate signal gradually rises from low. Therefore, after a period of time t, the voltage of the gate signal received by the pixel unit 212 reaches 90 of STV. %, that is, the pixel unit 212 is turned on at time t. In other implementation scenarios, other voltage values can also be set as the judgment basis for judging that the pixel unit is turned on, such as 80% of STV, or 70% of STV.
  • the logic board 27 connects the monitoring line 261 and the monitoring line 262 to obtain the open time of the monitoring line 261 and the monitoring line 262 through the pixel units 211 and 212, and calculates the pixel units 211 and 212 according to the obtained open time of the pixel units 211 and 212 The opening time difference.
  • the time difference is t.
  • the logic board 27 is connected to the data driving circuit 25 and sends the calculated time difference t to the data driving circuit 25 so that the data driving circuit controls the delay time between the data signals provided to the data line 241 and the data line 242 according to the time difference t. That is, the data signal provided by the data line 242 is delayed by t from the data signal provided by the data line 241.
  • the time difference between the opening of the pixel unit can be accurately calculated through the monitoring line and the logic board, so that the data signal provided by the data driving circuit to the multiple data lines can be accurately obtained along the distance away from the gate driving circuit.
  • the time difference of the direction delay makes the opening time of the multiple pixel units in the LCD panel match the charging time, so that the charging time of the data signal is sufficient, so as to solve the problem of insufficient charging of the data signal due to the gate signal delay and uneven panel light emission This phenomenon improves the display quality of the panel.
  • FIG. 3 is a schematic structural diagram of a third embodiment of the liquid crystal display panel provided by the present application.
  • the liquid crystal display panel 30 includes a plurality of pixel unit groups 31 such as a pixel unit 311 and a pixel unit 312, a scan line 32, a gate driving circuit 33, data lines 341 and 342, a data driving circuit 35, monitoring lines 361 and 362, Logic board 37.
  • the pixel unit group 31 such as the pixel unit 311 and the pixel unit 312, the scan line 32, the gate drive circuit 33, the data lines 341 and 342, the data drive circuit 35, the monitoring lines 361 and 362, the logic board 37 and those provided by the present application
  • the pixel unit group 21 such as the pixel unit 211 and the pixel unit 212, the scan line 22, the gate drive circuit 23, the data lines 241 and 242, the data drive circuit 25, the monitor line 261 and 262.
  • the structure and connection relationship of the logic board 27 are consistent, and the details are not repeated here.
  • the data driving circuit 35 includes data driving chips 351 and 352, the data driving chip 351 is connected to the data line 341, and the data driving chip 352 is connected to the data line 342.
  • the data chips 351 and 352 are also connected to the logic board 37.
  • the data signal provided by the data driving chip 351 to the data line 341 is delayed from the data signal provided by the data chip 352 to the data line 352.
  • the data driving chips 351 and 352 are COF (Chip On Film, chip on film) chips.
  • the logic board 27 controls the data signal provided by the data driving circuit to be delayed sequentially by offsetting the data signal (TP) provided by the data driving chip in the data driving circuit 25.
  • TP data signal
  • FIG. 4 is a schematic diagram of various signal timings of the liquid crystal display panel 30 after the logic board 27 is offset according to the present application.
  • Gp1 is the gate signal received by the pixel unit 311
  • Gp2 is the gate signal received by the pixel unit 312
  • TP1 is the drive signal provided by the data drive chip 351
  • TP2 is the drive signal provided by the data drive chip 352
  • Data1 is The data circuit 35 provides a data signal to the pixel unit 311 through the data line 341
  • Data2 is a data signal provided by the data circuit 35 to the pixel unit 312 through the data line 342.
  • the pixel unit 312 is delayed by a time t from the opening time of the pixel unit 311, and the driving signal provided by the data driving chip 352 is delayed by a time t from the driving signal provided by the data driving chip 351, and the data circuit 35 passes through the data line 342
  • the data signal provided to the pixel unit 312 is delayed by a time t from the data signal provided by the data circuit 35 to the pixel unit 311 through the data line 341. Therefore, the time when the pixel units 311 and 312 are turned on matches the time for charging.
  • the data signal provided by the data drive circuit to the pixel unit through the data line is delayed by offsetting the drive signal provided by the data drive chip, so that the opening time of the multiple pixel units in the liquid crystal display panel is related to the charging time. Matching the time of the data signal to make the charging time of the data signal sufficient, thereby solving the phenomenon of insufficient charging of the data signal due to the delay of the gate signal, causing the panel to emit light unevenly, and improving the display quality of the panel.
  • FIG. 5 is a schematic structural diagram of a third embodiment of the liquid crystal display panel provided by the present application.
  • the liquid crystal display panel 50 includes a plurality of pixel unit groups 51 such as a pixel unit 511 and a pixel unit 512, a scan line 52, a gate driving circuit 53, data lines 541 and 542, a data driving circuit 55, and monitoring lines 561 and 562,
  • the logic board 57 and the timing controller 58, the data driving circuit 55 includes data driving chips 551 and 552, the data driving chip 551 is connected to the data line 541, and the data driving chip 5352 is connected to the data line 542.
  • the pixel unit 511 and the pixel unit 512, the scan line 52, the gate driving circuit 53, the data lines 541 and 542, the data driving circuit 55, the monitoring lines 561 and 562, the logic board 57, and the liquid crystal display panel provided by this application
  • the pixel unit group 21 such as the pixel unit 211 and the pixel unit 212, the scan line 22, the gate drive circuit 23, the data lines 241 and 242, the data drive circuit 25, the monitoring lines 261 and 262, and the logic board 27
  • the structure and connection relationship are the same, so I won’t repeat them here.
  • the timing controller 58 is connected to the gate driving circuit 53 and the data driving circuit 55 for controlling the operation of the gate driving circuit 53 and the data driving circuit 55.
  • the timing controller 58 provides a clock signal to the gate driving circuit 53 and the data driving circuit 55, so that the gate driving circuit 53 and the data driving circuit 55 drive and operate according to the clock signal.
  • timing controller in this embodiment makes the gate driving circuit and the data driving circuit work more accurately.
  • FIG. 6 is a schematic structural diagram of an embodiment of the liquid crystal display device provided by the present application.
  • the liquid crystal display device 60 includes a liquid crystal display panel 61, and the liquid crystal display panel 61 is the liquid crystal display panel shown in any one of FIGS. 1 to 3 and 5.
  • this embodiment can effectively enhance the display effect and improve the user experience by using the liquid crystal display panel described in the above content.
  • the data signals provided by the data drive circuit of the present application to multiple data lines are sequentially delayed along the direction of the principle gate drive circuit, so that the time when the multiple pixel units in the liquid crystal display panel are turned on Matching with the charging time, the charging time of the data signal is sufficient, thereby solving the phenomenon of insufficient charging of the data signal due to the delay of the gate signal, causing the panel to emit light unevenly, and improving the display quality of the panel.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Nonlinear Science (AREA)
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Abstract

一种液晶显示面板（10,20,30,50,61）及其驱动方法。液晶显示面板（10,20,30,50,61）包括：像素单元组（11,21,31,51），包括以矩阵方式排列的多个像素单元（111,112,211,212,311,312,511,512）；扫描线（12,22,32,52），每条扫描线（12,22,32,52）连接同一行至少两个像素单元（111,112,211,212,311,312,511,512）；栅极驱动电路（13,23,33,53），与扫描线（12,22,32,52）连接，用于在扫描线（12,22,32,52）上提供栅极信号，以控制扫描线（12,22,32,52）所连接的像素单元（111,112,211,212,311,312,511,512）打开；数据线（141,142,241,242,341,342,541,542），分别连接不同列的至少一个像素单元（111,112,211,212,311,312,511,512）；数据驱动电路（15,25,35,55），与数据线（141,142,241,242,341,342,541,542）连接，用于给数据线（141,142,241,242,341,342,541,542）提供数据信号，以对数据线（141,142,241,242,341,342,541,542）所连接的且处于打开状态的像素单元（111,112,211,212,311,312,511,512）进行充电；其中，数据驱动电路（15,25,35,55）给多条数据线（141,142,241,242,341,342,541,542）提供的数据信号沿着远离栅极驱动电路（13,23,33,53）的方向依次延迟，使得液晶显示面板（10,20,30,50,61）中多个像素单元（111,112,211,212,311,312,511,512）打开的时间与充电的时间相匹配。通过上述方式，能够提升液晶显示面板（10,20,30,50,61）的均匀性，改善显示效果。

Description

一种液晶显示面板及其驱动方法 技术领域
本申请涉及显示领域，特别是涉及一种液晶显示面板及其驱动方法。
 背景技术
随着显示行业的发展，对于面板的各种性能要求提高，对面板的分辨率要求也不断提升，面板的刷新频率提高，使得面板充电时间不断缩短，又由于面板制程工艺的影响，面板有较大的RC loading，导致gate打开时间不一致，进一步缩短充电时间。面板充电时间过短会造成充电不足，从而导致了面板显示效果与均匀性下降。
 技术问题
面板充电时间过短会造成充电不足，从而导致了面板显示效果与均匀性下降。
 技术解决方案
本申请主要解决的技术问题是提供一种液晶显示面板及其驱动方法，能够提升液晶显示面板的均匀性，改善显示效果。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种液晶显示面板，包括：像素单元组，包括多个像素单元，所述多个像素单元以矩阵方式排列；多条扫描线，每条所述扫描线连接同一行至少两个所述像素单元；栅极驱动电路，与所述多条扫描线连接，用于在所述扫描线上提供栅极信号，以控制所述扫描线所连接的所述像素单元打开；多条数据线，所述多条数据线分别连接不同列的所述多个像素单元；数据驱动电路，与所述多条数据线连接，用于给所述数据线提供数据信号，以对所述数据线所连接的且处于打开状态的所述像素单元进行充电；其中，数据驱动电路给所述多条数据线提供的所述数据信号依次延迟，使得所述液晶显示面板中所述多个像素单元打开的时间与充电的时间相匹配。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种液晶显示装置，包括如上所述的液晶显示面板。
 有益效果
区别于现有技术的情况，本申请中液晶显示面板的数据驱动电路给多条数据线提供的所述数据信号沿着原理栅极驱动电路的方向依次延迟，使得所述液晶显示面板中所述多个像素单元打开的时间与充电的时间相匹配，使数据信号的充电时间充足，从而解决因栅极信号延迟导致数据信号充电不足，使面板发光不均匀的现象，改善面板的显示质量。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的液晶显示面板的第一实施例的结构示意图；
图2是本申请提供的液晶显示面板的第二实施例的结构示意图；
图3是本申请提供的液晶显示面板的第三实施例的结构示意图；
图4是本申请提供的经过逻辑板偏移后的液晶显示面板的各信号时序示意图；
图5是本申请提供的液晶显示面板的第四实施例的结构示意图；
图6是本申请提供的液晶显示装置的一实施例的结构示意图。
本申请的最佳实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，图1是本申请提供的液晶显示面板的第一实施例的结构示意图。液晶显示面板10包括多个诸如像素单元111和像素单元112之类的像素单元组11、扫描线12、栅极驱动电路13、数据线141和142、数据驱动电路15。其中，该像素单元组11中的多个像素单元以矩阵方式排列。每条扫描线12连接同一行至少两个像素单元（例如，像素单元111和像素单元112）。栅极驱动电路13与扫描线12连接，用于在扫描线12上提供栅极信号，以控制扫描线12所连接的像素单元（例如，像素单元111或像素单元112）打开。数据线141和数据线142分别连接不同列的像素单元（例如，数据线141连接像素单元111，数据线142连接像素单元112）。数据驱动电路15与数据线141和142连接，用于给数据线141和142提供数据信号，以对数据线141和数据线142所连接的且处于打开状态的像素单元（即，像素单元111和像素单元112）进行充电。
在液晶显示面板10的面积较大时，由于RC延迟等原因，距离栅极驱动电路13较近的像素单元111，接收到的栅极信号十分接近原始信号，而距离栅极驱动电路13较远的像素单元112接收到的栅极信号则是由低逐渐升高至标准值的信号，像素单元111比像素单元112更快处于打开状态。而像素电路111和像素单元112处于不同列，因此由不同的数据线（数据线141和数据线142）提供数据信号，数据驱动电路15给数据线141和数据线142提供的数据信号沿着远离栅极驱动电路13的方向依次延迟，即提供给数据线142的数据信号比提供给数据线141的数据信号延迟，这样像素单元112接收的数据信号比像素单元111接收数据信号延迟，由于像素单元112打开的时间比像素单元111延迟，因此像素单元112的打开时间与充电时间相匹配。这样数据信号的充电时间充足，有效解决了面板发光不均匀的现象，改善面板的显示质量。
需要说明的是，在本实施场景中，仅列举了一条驱动线、两个像素单元和两条数据线，在其他实施场景中，可以设置更多的驱动线、像素单元和数据线。
通过上述描述可知，在本实施例中数据驱动电路给多条数据线提供的数据信号沿着远离栅极驱动电路的方向依次延迟，使得液晶显示面板中多个像素单元打开的时间与充电的时间相匹配，使数据信号的充电时间充足，从而解决因栅极信号延迟导致数据信号充电不足，使面板发光不均匀的现象，改善面板的显示质量。
请参阅图2，图2是本申请提供的液晶显示面板的第二实施例的结构示意图。液晶显示面板20包括多个诸如像素单元211和像素单元212之类的像素单元组21、扫描线22、栅极驱动电路23、数据线241和242、数据驱动电路25、监测线261和262、逻辑板27。
其中，该像素单元组21中的多个像素单元以矩阵方式排列。每条扫描线22连接同一行至少两个像素单元（例如，像素单元211和像素单元212）。栅极驱动电路23与扫描线22连接，用于在扫描线22上提供栅极信号，以控制扫描线22所连接的像素单元（例如，像素单元211或像素单元212）打开。数据线241和数据线242分别连接不同列的像素单元（例如，数据线241连接像素单元211，数据线242连接像素单元212）。数据驱动电路25与数据线241和242连接，用于给数据线241和242提供数据信号，以对数据线241和数据线242所连接的且处于打开状态的像素单元（即，像素单元211和像素单元212）进行充电。
监测线261与像素单元211连接，监测线262与像素单元212连接，像素单元211和像素单元212位于同一行。监测线261和监测线262用于分别用于监测像素单元211和212的打开时间。在本实施场景中，像素单元的打开时间为像素单元栅极信号电压达到标准值的90%的时间。该标准值为栅极驱动电路23提供的起始脉冲（STV）的电压值。例如，像素单元211最靠近栅极驱动电路23，则像素单元211接收到的栅极信号瞬间到的STV的值，即像素单元211瞬间处于打开状态，将此时的时间记为0点，而像素单元212距离栅极驱动电路23较远，则接收到的栅极信号是由低逐渐升高的，因此，在一段时间t后，像素单元212接收到的栅极信号的电压达到STV的90%，即为，像素单元212在时间t时打开。在其他实施场景中，还可以设置其他的电压值作为判断像素单元打开的评判依据，例如STV的80%、或者STV的70%等。
逻辑板27连接监测线261和监测线262，获取监测线261和监测线262通过像素单元211和212的打开时间，并根据获取到的像素单元211和212的打开时间计算出像素单元211和212的打开时间差。例如，在本实施场景中，时间差为t。逻辑板27与数据驱动电路25连接，将计算出的时间差t发送给数据驱动电路25，使得数据驱动电路根据该时间差t控制给数据线241和数据线242提供的数据信号之间的延迟时间。即数据线242提供的数据信号比数据线241提供的数据信号延迟了t。
需要说明的是，在本实施场景中，仅列举了一条驱动线、两个像素单元、两条数据线、两条监测线和一个逻辑板，在其他实施场景中，可以设置更多的驱动线、像素单元、数据线、监测线和逻辑板。
通过上述描述可知，在本实施例中通过监测线和逻辑板可以准确计算出像素单元打开的时间差，从而可以准确获取数据驱动电路给多条数据线提供的数据信号沿着远离栅极驱动电路的方向延迟的时间差，使得液晶显示面板中多个像素单元打开的时间与充电的时间相匹配，使数据信号的充电时间充足，从而解决因栅极信号延迟导致数据信号充电不足，使面板发光不均匀的现象，改善面板的显示质量。
请参阅图3，图3是本申请提供的液晶显示面板的第三实施例的结构示意图。液晶显示面板30包括多个诸如像素单元311和像素单元312之类的像素单元组31、扫描线32、栅极驱动电路33、数据线341和342、数据驱动电路35、监测线361和362、逻辑板37。像素单元311和像素单元312之类的像素单元组31、扫描线32、栅极驱动电路33、数据线341和342、数据驱动电路35、监测线361和362、逻辑板37与本申请提供的液晶显示面板的第二实施例中的像素单元211和像素单元212之类的像素单元组21、扫描线22、栅极驱动电路23、数据线241和242、数据驱动电路25、监测线261和262、逻辑板27的结构和连接关系一致，此处不在进行赘述。
数据驱动电路35包括数据驱动芯片351和352，数据驱动芯片351和数据线341连接，数据驱动芯片352和数据线342连接。数据芯片351和352还与逻辑板37连接。数据驱动芯片351提供给数据线341的数据信号比数据芯片352提供该数据线352的数据信号延迟。在本实施场景中数据驱动芯片351和352为COF（Chip On Film，覆晶薄膜）芯片。
在本实施场景中，逻辑板27通过偏移数据驱动电路25中由数据驱动芯片提供的数据信号（TP）来控制数据驱动电路给多条数据线提供的数据信号依次延迟。请结合参阅图4，图4是本申请提供经过逻辑板27偏移后的液晶显示面板30的各信号时序示意图。
其中，Gp1是像素单元311接收到的栅极信号，Gp2是像素单元312接收到的栅极信号，TP1是数据驱动芯片351提供的驱动信号，TP2是数据驱动芯片352提供的驱动信号，Data1是数据电路35通过数据线341向像素单元311提供的数据信号，Data2是数据电路35通过数据线342向像素单元312提供的数据信号。
根据图4可知，像素单元312比像素单元311的打开时间延迟了时间t，则数据驱动芯片352提供的驱动信号比数据驱动芯片351提供的驱动信号延迟了时间t，数据电路35通过数据线342向像素单元312提供的数据信号比数据电路35通过数据线341向像素单元311提供的数据信号延迟了时间t。于是像素单元311和312打开的时间与充电的时间相匹配。
通过上述描述可知，在本实施例中通过偏移数据驱动芯片提供的驱动信号来延迟数据驱动电路通过数据线向像素单元提供的数据信号，使得液晶显示面板中多个像素单元打开的时间与充电的时间相匹配，使数据信号的充电时间充足，从而解决因栅极信号延迟导致数据信号充电不足，使面板发光不均匀的现象，改善面板的显示质量。
请参阅图5，本申请提供的液晶显示面板的第三实施例的结构示意图。液晶显示面板50包括多个诸如像素单元511和像素单元512之类的像素单元组51、扫描线52、栅极驱动电路53、数据线541和542、数据驱动电路55、监测线561和562、逻辑板57和定时控制器58，数据驱动电路55包括数据驱动芯片551和552，数据驱动芯片551和数据线541连接，数据驱动芯片5352和数据线542连接。
其中，像素单元511和像素单元512、扫描线52、栅极驱动电路53、数据线541和542、数据驱动电路55、监测线561和562、逻辑板57与本申请提供的液晶显示面板的第二实施例中的像素单元211和像素单元212之类的像素单元组21、扫描线22、栅极驱动电路23、数据线241和242、数据驱动电路25、监测线261和262、逻辑板27的结构和连接关系一致，此处不在进行赘述。
定时控制器58连接栅极驱动电路53和数据驱动电路55，用于控制栅极驱动电路53和数据驱动电路55工作。定时控制器58向栅极驱动电路53和数据驱动电路55提供时钟信号，使得栅极驱动电路53和数据驱动电路55根据时钟信号驱动工作。
通过上述描述可知，本实施例中通过定时控制器使得栅极驱动电路和数据驱动电路工作更加精准。
请参阅图6，图6是本申请提供的液晶显示装置的一实施例的结构示意图。液晶显示装置60包括液晶显示面板61，液晶显示面板61为图1-图3以及图5任一幅所示的液晶显示面板。
通过上述描述可知，本实施例通过采用上述内容所述的液晶显示面板，可以有效提升显示效果，改善用户体验。
区别于现有技术，本申请数据驱动电路给多条数据线提供的所述数据信号沿着原理栅极驱动电路的方向依次延迟，使得所述液晶显示面板中所述多个像素单元打开的时间与充电的时间相匹配，使数据信号的充电时间充足，从而解决因栅极信号延迟导致数据信号充电不足，使面板发光不均匀的现象，改善面板的显示质量。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (19)

  1. 一种液晶显示面板，其中，包括：
    像素单元组，包括多个像素单元，所述多个像素单元以矩阵方式排列；
    多条扫描线，每条所述扫描线连接同一行至少两个所述像素单元；
    栅极驱动电路，与所述多条扫描线连接，用于在所述扫描线上提供栅极信号，以控制所述扫描线所连接的所述像素单元打开；
    多条数据线，所述多条数据线分别连接不同列的所述至少一个像素单元；
    数据驱动电路，与所述多条数据线连接，用于给所述数据线提供数据信号，以对所述数据线所连接的且处于打开状态的所述像素单元进行充电；其中，所述数据驱动电路给所述多条数据线提供的所述数据信号沿着远离所述栅极驱动电路的方向依次延迟，使得所述液晶显示面板中所述多个像素单元打开的时间与充电的时间相匹配；
    多条监测线，每条所述监测线分别与同一行不同的像素单元连接，用于监测所连接的所述像素单元打开的时间；
    栅极信号偏移检测电路，连接所述多条监测线，用于通过所述多条监测线监测到每个所述像素单元打开的时间，并计算出同一所述栅极线连接的至少两个所述像素单元的打开时间的时间差；
    逻辑板，连接所述栅极信号偏移检测电路，并与所述数据驱动电路连接，用于将所述时间差发送给所述数据驱动电路，使得所述数据驱动电路根据所述时间差给所述多条数据线提供的所述数据信号沿着远离所述栅极驱动电路的方向依次延迟；
    定时控制器，所述定时控制器连接所述栅极驱动电路和所述数据驱动电路，所述定时控制器用于控制所述栅极驱动电路和所述数据驱动电路工作。
  2. 一种液晶显示面板，其中，包括：
    像素单元组，包括多个像素单元，所述多个像素单元以矩阵方式排列；
    多条扫描线，每条所述扫描线连接同一行至少两个所述像素单元；
    栅极驱动电路，与所述多条扫描线连接，用于在所述扫描线上提供栅极信号，以控制所述扫描线所连接的所述像素单元打开；
    多条数据线，所述多条数据线分别连接不同列的所述至少一个像素单元；
    数据驱动电路，与所述多条数据线连接，用于给所述数据线提供数据信号，以对所述数据线所连接的且处于打开状态的所述像素单元进行充电；
    其中，数据驱动电路给所述多条数据线提供的所述数据信号沿着远离所述栅极驱动电路的方向依次延迟，使得所述液晶显示面板中所述多个像素单元打开的时间与充电的时间相匹配。
  3. 根据权利要求2所述的液晶显示面板，其中，所述显示面板进一步包括：
    多条监测线，每条所述监测线分别与同一行不同的像素单元连接，用于监测所连接的所述像素单元打开的时间；
    栅极信号偏移检测电路，连接所述多条监测线，用于通过所述多条监测线监测到每个所述像素单元打开的时间，并计算出同一所述栅极线连接的至少两个所述像素单元的打开时间的时间差；
    逻辑板，连接所述栅极信号偏移检测电路，并与所述数据驱动电路连接，用于将所述时间差发送给所述数据驱动电路，使得所述数据驱动电路根据所述时间差给所述多条数据线提供的所述数据信号沿着远离所述栅极驱动电路的方向依次延迟。
  4. 根据权利要求3所述的液晶显示面板，其中，
    数据驱动电路向所述至少两个像素单元所在列对应的数据线提供的驱动信号延迟时间为所述时间差的绝对值。
  5. 根据权利要求3所述的液晶显示面板，其中，
    所述像素单元的打开时间为所述像素单元栅极信号电压达到标准值的90%的时间。
  6. 根据权利要求5所述的液晶显示面板，其中，
    所述标准值为所述栅极驱动电路的起始脉冲电压值。
  7. 根据权利要求3所述的液晶显示面板，其中，
    所述逻辑板通过偏移所述数据驱动电路中的驱动信号来控制数据驱动电路给所述多条数据线提供的所述数据信号依次延迟。
  8. 根据权利要求3所述的液晶显示面板，其中，所述数据驱动电路包括多个数据驱动芯片，每个所述驱动芯片与一条所述数据线连接；
    其中，所述驱动芯片用于提供所述驱动信号。
  9. 根据权利要求8所述的液晶显示面板，其中，
    所述多个驱动芯片和所述逻辑板连接，根据所述逻辑板计算出的所述时间差依次延迟所述驱动信号。
  10. 根据权利要求2所述的液晶显示面板，其中，所述液晶显示面板进一步包括：
    定时控制器，所述定时控制器连接所述栅极驱动电路和所述数据驱动电路，用于控制所述栅极驱动电路和所述数据驱动电路工作。
  11. 一种液晶显示装置，其中，包括液晶显示面板，所述液晶显示面板包括：
    像素单元组，包括多个像素单元，所述多个像素单元以矩阵方式排列；
    多条扫描线，每条所述扫描线连接同一行至少两个所述像素单元；
    栅极驱动电路，与所述多条扫描线连接，用于在所述扫描线上提供栅极信号，以控制所述扫描线所连接的所述像素单元打开；
    多条数据线，所述多条数据线分别连接不同列的所述至少一个像素单元；
    数据驱动电路，与所述多条数据线连接，用于给所述数据线提供数据信号，以对所述数据线所连接的且处于打开状态的所述像素单元进行充电；
    其中，所述数据驱动电路给所述多条数据线提供的所述数据信号沿着远离所述栅极驱动电路的方向依次延迟，使得所述液晶显示面板中所述多个像素单元打开的时间与充电的时间相匹配。
  12. 根据权利要求11所述的液晶显示装置，其中，所述显示面板进一步包括：
    多条监测线，每条所述监测线分别与同一行不同的像素单元连接，用于监测所连接的所述像素单元打开的时间；
    栅极信号偏移检测电路，连接所述多条监测线，用于通过所述多条监测线监测到每个所述像素单元打开的时间，并计算出同一所述栅极线连接的至少两个所述像素单元的打开时间的时间差；
    逻辑板，连接所述栅极信号偏移检测电路，并与所述数据驱动电路连接，用于将所述时间差发送给所述数据驱动电路，使得所述数据驱动电路根据所述时间差给所述多条数据线提供的所述数据信号沿着远离所述栅极驱动电路的方向依次延迟。
  13. 根据权利要求12所述的液晶显示装置，其中，
    数据驱动电路向所述至少两个像素单元所在列对应的数据线提供的驱动信号延迟时间为所述时间差的绝对值。
  14. 根据权利要求12所述的液晶显示装置，其中，
    所述像素单元的打开时间为所述像素单元栅极信号电压达到标准值的90%的时间。
  15. 根据权利要求14所述的液晶显示装置，其中，
    所述标准值为所述栅极驱动电路的起始脉冲电压值。
  16. 根据权利要求12所述的液晶显示装置，其中，
    所述逻辑板通过偏移所述数据驱动电路中的驱动信号来控制数据驱动电路给所述多条数据线提供的所述数据信号依次延迟。
  17. 根据权利要求12所述的液晶显示装置，其中，所述数据驱动电路包括多个数据驱动芯片，每个所述驱动芯片与一条所述数据线连接；
    其中，所述驱动芯片用于提供所述驱动信号。
  18. 根据权利要求17所述的液晶显示装置，其中，
    所述多个驱动芯片和所述逻辑板连接，根据所述逻辑板计算出的所述时间差依次延迟所述驱动信号。
  19. 根据权利要求11所述的液晶显示装置，其中，所述液晶显示面板进一步包括：
    定时控制器，所述定时控制器连接所述栅极驱动电路和所述数据驱动电路，用于控制所述栅极驱动电路和所述数据驱动电路工作。
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