WO2020151115A1 - 一种像素驱动电路及其驱动方法 - Google Patents

一种像素驱动电路及其驱动方法 Download PDF

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WO2020151115A1
WO2020151115A1 PCT/CN2019/084244 CN2019084244W WO2020151115A1 WO 2020151115 A1 WO2020151115 A1 WO 2020151115A1 CN 2019084244 W CN2019084244 W CN 2019084244W WO 2020151115 A1 WO2020151115 A1 WO 2020151115A1
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potential
pull
scan line
row
thin film
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PCT/CN2019/084244
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English (en)
French (fr)
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陈江川
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020151115A1 publication Critical patent/WO2020151115A1/zh

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3696Generation of voltages supplied to electrode drivers

Definitions

  • the present invention relates to the field of display technology, in particular to a pixel driving circuit and a driving method thereof.
  • a pixel driving circuit includes:
  • the scan lines are electrically connected to the gate of the thin film transistor
  • the data lines are electrically connected to the source of the thin film transistor
  • a scan driver electrically connected to the scan line
  • a data driver electrically connected to the data line
  • the scan driver provides a first pull-down potential and a second pull-down potential for the scan line, the first pull-down potential is lower than the turn-off potential of the thin film transistor, and the second pull-down potential is low At the first pull-down potential; the first pull-down potential is -4 to -10 volts; and the second pull-down potential is -10.1 to -20 volts.
  • the pull-down target potential of the gate connected to the scan line of the i-th row is set to the second pull-down potential, and i is a positive integer greater than or equal to 1.
  • the target potential of the gate connected to the scan line of the i-th row is set to the first pull-down Potential.
  • the potential of the gate connected to the scan line of the i-th row is adjusted to the first pull-down potential.
  • a pixel driving circuit includes:
  • the scan lines are electrically connected to the gate of the thin film transistor
  • the data lines are electrically connected to the source of the thin film transistor
  • a scan driver electrically connected to the scan line
  • a data driver electrically connected to the data line
  • the scan driver provides a first pull-down potential and a second pull-down potential for the scan line, the first pull-down potential is lower than the turn-off potential of the thin film transistor, and the second pull-down potential is low In the first pull down the potential.
  • the pull-down target potential of the gate connected to the scan line of the i-th row is set to the second pull-down potential, and i is a positive integer greater than or equal to 1.
  • the target potential of the gate connected to the scan line of the i-th row is set to the first pull-down Potential.
  • the potential of the gate connected to the scan line of the i-th row is adjusted to the first pull-down potential.
  • the first pull-down potential is -4 to -10 volts.
  • the second pull-down potential is -10.1 to -20 volts.
  • the present invention also provides a pixel driving method for driving multiple scan lines.
  • the scan driver sets the pull-down target potential of the i-th scan line to the second pull-down potential.
  • the target potential of the gate connected to the scan line in the i-th row is set to the first pulled-down potential; where i is greater than or A positive integer equal to 1, the first pull-down potential is lower than the turn-off potential of the thin film transistor, and the second pull-down potential is lower than the first pull-down potential.
  • the potential of the gate connected to the scan line of the i-th row is adjusted to the first pulled-down potential.
  • the first pull-down potential is -4 to -10 volts.
  • the second pull-down potential is -10.1 to -20 volts.
  • the target potential of the scan line is set to a lower potential in advance, that is, the second pull-down potential VGL2, thereby reducing the scan signal off time.
  • the potential of the scan line of the i-th row is slowly raised to a higher potential, that is, the first pull-down potential VGL1, Therefore, the potential rise time of the scan line during the pull-up phase is not affected, and the pixel charging rate is improved.
  • FIG. 1 is a schematic diagram of a pixel driving circuit in a specific embodiment of the present invention
  • FIG. 2 is a potential waveform diagram of scan lines in a specific embodiment of the present invention.
  • the present invention addresses the technical problem that in the existing liquid crystal display panel, since the gate signal voltage drops for a long time, it is easy to cause mischarging and affect the display quality.
  • the present invention can solve the above-mentioned problems.
  • the pixel drive circuit includes a plurality of sub-pixels 40 distributed in an array, thin film transistors 30 corresponding to the sub-pixels 40 one-to-one, and multiple scan lines (as shown in the figure). Shown Gi, Gi+1, Gm) and multiple columns of data lines (Di, Di+1, Di+2, Dn as shown in the figure); the sub-pixel 40 and the drain electrode of the thin film transistor 30 The scan line is electrically connected to the gate of the thin film transistor 30, and the data line is electrically connected to the source of the thin film transistor 30.
  • the pixel driving circuit further includes a scan driver 10 electrically connected to the scan line and a data driver 20 electrically connected to the data line.
  • the scan driver 10 provides a first pull-down potential, a second pull-down potential, and a high potential for the scan line
  • the data driver 20 provides a data drive signal potential for the data line
  • the first pull-down The potential is lower than the turn-off potential of the thin film transistor 30, and the second pull-down potential is lower than the first pull-down potential.
  • the first pull-down potential is VGL1
  • the second pull-down potential is VGL2
  • the high potential is VGH.
  • the scan driver 10 sets two low levels for scan lines. When the potential of the scan line is turned off from the high potential VGH to the low potential, the target potential of the scan line is set to a lower potential first, thereby reducing the scan signal off time.
  • the pull-down target potential of the gate connected to the i-th scan line is set to the second pull-down potential VGL2, where i is A positive integer greater than or equal to 1.
  • the target low potential of the scan line is set to the first pull-down potential VGL1, the time for the scan line to be pulled down to the off potential is Tf1;
  • the target low potential of is set to the second pull-down potential VGL2, and the time for the scan line's potential to be pulled down to the off potential is Tf2; from theory, Tf2 ⁇ Tf1, and when the VGL2 potential is lower, Tf2 is smaller, that is, it drops The shorter the time to turn-off potential is, so as to prevent mischarging from affecting the display quality.
  • the target potential of the gate connected to the scan line of the i-th row is set to the first pull Low potential VGL1.
  • the potential of the i-th scan line is slowly raised to a higher potential, so as not to affect the pull-up phase
  • the pixel charging rate is improved.
  • the potential of the gate connected to the scan line of the i-th row is adjusted to the first pull-down potential VGL1.
  • the turn-off voltage is -2 volts
  • the first pull-down potential is -4 to -10 volts
  • the second pull-down potential VGL2 is -10.1 to -20 volts. While reducing the potential pull-down time of the scan line, it is ensured that the potential pull-up time of the scan line is not affected.
  • the present invention also provides a pixel driving method for driving multiple rows of scan lines.
  • the scan driver 10 sets the pull-down target potential of the scan line of the i-th row to the second pull-down potential VGL2, and the potential of the gate connected to the scan line of the i-th row is pulled down to the corresponding
  • the scan driver 10 sets the target potential of the gate connected to the scan line of the ith row to the first pull-down potential VGL1; where i is a positive integer greater than or equal to 1, and the first pull The low potential VGL1 is lower than the turn-off potential of the thin film transistor 30, and the second pull-down potential VGL2 is lower than the first pull-down potential VGL1.
  • the target potential of the scan line is set to a lower potential in advance, that is, the second pull-down potential VGL2, thereby reducing the scan signal off time.
  • the potential of the i-th row scan line is slowly raised to a higher potential, so as not to affect the pull-up phase
  • the pixel charging rate is improved.
  • the potential of the gate connected to the scan line of the i-th row is adjusted to the first pulled-down potential VGL1.
  • the turn-off voltage is -2 volts
  • the first pull-down potential VGL1 is -4 to -10 volts
  • the second pull-down potential VGL2 is -10.1 to -20 volts. While reducing the potential pull-down time of the scan line, it is ensured that the potential pull-up time of the scan line is not affected.
  • the beneficial effect of the present invention is: when the potential of the scan line is turned off from the high potential VGH to the low potential, the target potential of the scan line is set to a lower potential first, that is, the second pull-down potential VGL2, thereby reducing the scan signal off. Off time.
  • the target potential of the scan line is set to a lower potential first, that is, the second pull-down potential VGL2, thereby reducing the scan signal off. Off time.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种像素驱动电路,包括子像素(40)、薄膜晶体管(30)、与薄膜晶体管(30)电性连接的多行扫描线(Gi,Gi+1,Gm)和多列数据线(Di,Di+1,Di+2,Dn);像素驱动电路还包括与扫描线(Gi,Gi+1,Gm)电性连接的扫描驱动器(10)以及与数据线(Di,Di+1,Di+2,Dn)电性连接的数据驱动器(20),其中,扫描驱动器(10)为扫描线(Gi,Gi+1,Gm)提供第一拉低电位(VGL1)和第二拉低电位(VGL2),第一拉低电位(VGL1)低于薄膜晶体管(30)的关断电位,第二拉低电位(VGL2)低于第一拉低电位(VGL1)。

Description

一种像素驱动电路及其驱动方法 技术领域
本发明涉及显示技术领域,尤其涉及一种像素驱动电路及其驱动方法。
背景技术
目前多数液晶显示面板均采用逐行扫描的方式实现画面刷新,像素驱动电路中,在栅极信号下拉阶段,需在数据线的数据信号跳变前将栅极信号下拉至关断所需电位。
然而,随着显示面板分辨率的提高,特别是大尺寸高分辨率产品中,由于栅极信号电压下降时间较长,容易导致发生误充电,影响显示品质。
技术问题
随着显示面板分辨率的提高,特别是大尺寸高分辨率产品中,由于栅极信号电压下降时间较长,容易导致发生误充电,影响显示品质。
技术解决方案
一种像素驱动电路,包括:
呈阵列分布的多个子像素;
与所述子像素一一对应的薄膜晶体管,所述薄膜晶体管的漏极与所述子像素电性连接;
多行扫描线,所述扫描线与所述薄膜晶体管的栅极电性连接;
多列数据线,所述数据线与所述薄膜晶体管的源极电性连接;
与所述扫描线电性连接的扫描驱动器;
与所述数据线电性连接的数据驱动器;
其中,所述扫描驱动器为所述扫描线提供第一拉低电位和第二拉低电位,所述第一拉低电位低于所述薄膜晶体管的关断电位,所述第二拉低电位低于所述第一拉低电位;所述第一拉低电位为-4~-10伏特;所述第二拉低电位为-10.1~-20伏特。
进一步的,在第i行扫描线处于下拉阶段时,将与第i行扫描线连接的栅极的下拉目标电位设置为所述第二拉低电位,i为大于或等于1的正整数。
进一步的,在与第i行扫描线连接的栅极的电位下拉至对应的所述薄膜晶体管关断后,将与第i行扫描线连接的栅极的目标电位设置为所述第一拉低电位。
进一步的,在下一帧第i行扫描线重新启动前,将与第i行扫描线连接的栅极的电位调整至所述第一拉低电位。
一种像素驱动电路,包括:
呈阵列分布的多个子像素;
与所述子像素一一对应的薄膜晶体管,所述薄膜晶体管的漏极与所述子像素电性连接;
多行扫描线,所述扫描线与所述薄膜晶体管的栅极电性连接;
多列数据线,所述数据线与所述薄膜晶体管的源极电性连接;
与所述扫描线电性连接的扫描驱动器;
与所述数据线电性连接的数据驱动器;
其中,所述扫描驱动器为所述扫描线提供第一拉低电位和第二拉低电位,所述第一拉低电位低于所述薄膜晶体管的关断电位,所述第二拉低电位低于所述第一拉低电位。
进一步的,在第i行扫描线处于下拉阶段时,将与第i行扫描线连接的栅极的下拉目标电位设置为所述第二拉低电位,i为大于或等于1的正整数。
进一步的,在与第i行扫描线连接的栅极的电位下拉至对应的所述薄膜晶体管关断后,将与第i行扫描线连接的栅极的目标电位设置为所述第一拉低电位。
进一步的,在下一帧第i行扫描线重新启动前,将与第i行扫描线连接的栅极的电位调整至所述第一拉低电位。
进一步的,所述第一拉低电位为-4~-10伏特。
进一步的,所述第二拉低电位为-10.1~-20伏特。
本发明还提供一种像素驱动方法,用于驱动多行扫描线,在第i行扫描线处于下拉阶段时,扫描驱动器将第i行扫描线的下拉目标电位设置为第二拉低电位,在第i行扫描线所连接的栅极的电位下拉至对应的薄膜晶体管关断后,将与第i行扫描线连接的栅极的目标电位设置为第一拉低电位;其中,i为大于或等于1的正整数,所述第一拉低电位低于所述薄膜晶体管的关断电位,所述第二拉低电位低于所述第一拉低电位。
进一步的,将与第i行扫描线连接的栅极的电位调整至所述第一拉低电位。
进一步的,所述第一拉低电位为-4~-10伏特。
进一步的,所述第二拉低电位为-10.1~-20伏特。
有益效果
在扫描线的电位由高电位VGH往低电位关断时,将扫描线的目标电位先行设置为较低的电位,即第二拉低电位VGL2,从而降低扫描信号关断时间。对应的薄膜晶体管关断后,在第i行扫描线连接的薄膜晶体管处于关断状态的前提下,将第i行扫描线的电位缓慢抬升至较高的电位,即第一拉低电位VGL1,从而不影响上拉阶段时扫描线的电位上升时间,提高像素充电率。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍,显而易见地,下面描述中的附图仅仅是发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明具体实施方式中像素驱动电路的示意图;
图2为本发明具体实施方式中扫描线的电位波形图。
本发明的实施方式
以下各实施例的说明是参考附加的图示,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。在图中,结构相似的单元是用以相同标号表示。
本发明针对现有的液晶显示面板中,由于栅极信号电压下降时间较长,容易导致发生误充电,影响显示品质的技术问题。本发明可以解决上述问题。
一种像素驱动电路,如图1所示,所述像素驱动电路包括呈阵列分布的多个子像素40、与所述子像素40一一对应的薄膜晶体管30、多行扫描线(如图中所示的Gi、Gi+1、Gm)和多列数据线(如图中所示的Di、Di+1、Di+2、Dn);所述子像素40与所述薄膜晶体管30的漏极电性连接,所述扫描线与所述薄膜晶体管30的栅极电性连接,所述数据线与所述薄膜晶体管30的源极电性连接。
所述像素驱动电路还包括与所述扫描线电性连接的扫描驱动器10以及与所述数据线电性连接的数据驱动器20。
其中,所述扫描驱动器10为所述扫描线提供第一拉低电位、第二拉低电位和高电位,所述数据驱动器20为所述数据线提供数据驱动信号电位;所述第一拉低电位低于所述薄膜晶体管30的关断电位,所述第二拉低电位低于所述第一拉低电位。
如图2所示,所述第一拉低电位为VGL1,所述第二拉低电位为VGL2,所述高电位为VGH,在液晶面板驱动过程中,扫描驱动器10为扫描线设置两个低电位,在扫描线的电位由高电位VGH往低电位关断时,将扫描线的目标电位先行设置为较低的电位,从而降低扫描信号关断时间。
具体的,第i行扫描线启动后,在第i行扫描线处于下拉阶段时,将与第i行扫描线连接的栅极的下拉目标电位设置为所述第二拉低电位VGL2,i为大于或等于1的正整数。
对于本领域技术人员可知,在扫描线的下拉阶段,若将扫描线的目标低电位设置为第一拉低电位VGL1,则扫描线的电位下拉至关断电位的时间为Tf1;若将扫描线的目标低电位设置为第二拉低电位VGL2,则扫描线的电位下拉至关断电位的时间为Tf2;由理论可知,Tf2<Tf1,且当VGL2电位越低时,Tf2越小,即下降至关断电位的时间越短,从而防止发生误充电导致影响显示品质。
具体的,在与第i行扫描线连接的栅极的电位下拉至对应的所述薄膜晶体管30关断后,将与第i行扫描线连接的栅极的目标电位设置为所述第一拉低电位VGL1。
对应的薄膜晶体管30关断后,在第i行扫描线连接的薄膜晶体管30处于关断状态的前提下,将第i行扫描线的电位缓慢抬升至较高的电位,从而不影响上拉阶段时扫描线的电位上升时间,提高像素充电率。
进一步的,在下一帧第i行扫描线重新启动前,将与第i行扫描线连接的栅极的电位调整至所述第一拉低电位VGL1。
在一实施方式中,关断电压为-2伏特,所述第一拉低电位为-4~-10伏特,所述第二拉低电位VGL2为-10.1~-20伏特。降低扫描线的电位下拉时间的同时,保证不影响扫描线的电位上拉时间。
基于上述像素驱动电路,本发明还提供一种像素驱动方法,用于驱动多行扫描线。
在第i行扫描线处于下拉阶段时,扫描驱动器10将第i行扫描线的下拉目标电位设置为第二拉低电位VGL2,在第i行扫描线所连接的栅极的电位下拉至对应的薄膜晶体管30关断后,扫描驱动器10将与第i行扫描线连接的栅极的目标电位设置为第一拉低电位VGL1;其中,i为大于或等于1的正整数,所述第一拉低电位VGL1低于所述薄膜晶体管30的关断电位,所述第二拉低电位VGL2低于所述第一拉低电位VGL1。
在扫描线的电位由高电位VGH往低电位关断时,将扫描线的目标电位先行设置为较低的电位,即第二拉低电位VGL2,从而降低扫描信号关断时间。对应的薄膜晶体管30关断后,在第i行扫描线连接的薄膜晶体管30处于关断状态的前提下,将第i行扫描线的电位缓慢抬升至较高的电位,从而不影响上拉阶段时扫描线的电位上升时间,提高像素充电率。
进一步的,将与第i行扫描线连接的栅极的电位调整至所述第一拉低电位VGL1。
在一实施方式中,关断电压为-2伏特,所述第一拉低电位VGL1为-4~-10伏特,所述第二拉低电位VGL2为-10.1~-20伏特。降低扫描线的电位下拉时间的同时,保证不影响扫描线的电位上拉时间。
本发明的有益效果为:在扫描线的电位由高电位VGH往低电位关断时,将扫描线的目标电位先行设置为较低的电位,即第二拉低电位VGL2,从而降低扫描信号关断时间。对应的薄膜晶体管30关断后,在第i行扫描线连接的薄膜晶体管30处于关断状态的前提下,将第i行扫描线的电位缓慢抬升至较高的电位,即第一拉低电位VGL1,从而不影响上拉阶段时扫描线的电位上升时间,提高像素充电率。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。

Claims (14)

  1. 一种像素驱动电路,其中,所述像素驱动电路包括:
    呈阵列分布的多个子像素;
    与所述子像素一一对应的薄膜晶体管,所述薄膜晶体管的漏极与所述子像素电性连接;
    多行扫描线,所述扫描线与所述薄膜晶体管的栅极电性连接;
    多列数据线,所述数据线与所述薄膜晶体管的源极电性连接;
    与所述扫描线电性连接的扫描驱动器;
    与所述数据线电性连接的数据驱动器;
    其中,所述扫描驱动器为所述扫描线提供第一拉低电位和第二拉低电位,所述第一拉低电位低于所述薄膜晶体管的关断电位,所述第二拉低电位低于所述第一拉低电位;所述第一拉低电位为-4~-10伏特;所述第二拉低电位为-10.1~-20伏特。
  2. 根据权利要求1所述的像素驱动电路,其中,在第i行扫描线处于下拉阶段时,将与第i行扫描线连接的栅极的下拉目标电位设置为所述第二拉低电位,i为大于或等于1的正整数。
  3. 根据权利要求2所述的像素驱动电路,其中,在与第i行扫描线连接的栅极的电位下拉至对应的所述薄膜晶体管关断后,将与第i行扫描线连接的栅极的目标电位设置为所述第一拉低电位。
  4. 根据权利要求3所述的像素驱动电路,其中,在下一帧第i行扫描线重新启动前,将与第i行扫描线连接的栅极的电位调整至所述第一拉低电位。
  5. 一种像素驱动电路,其中,所述像素驱动电路包括:
    呈阵列分布的多个子像素;
    与所述子像素一一对应的薄膜晶体管,所述薄膜晶体管的漏极与所述子像素电性连接;
    多行扫描线,所述扫描线与所述薄膜晶体管的栅极电性连接;
    多列数据线,所述数据线与所述薄膜晶体管的源极电性连接;
    与所述扫描线电性连接的扫描驱动器;
    与所述数据线电性连接的数据驱动器;
    其中,所述扫描驱动器为所述扫描线提供第一拉低电位和第二拉低电位,所述第一拉低电位低于所述薄膜晶体管的关断电位,所述第二拉低电位低于所述第一拉低电位。
  6. 根据权利要求5所述的像素驱动电路,其中,在第i行扫描线处于下拉阶段时,将与第i行扫描线连接的栅极的下拉目标电位设置为所述第二拉低电位,i为大于或等于1的正整数。
  7. 根据权利要求6所述的像素驱动电路,其中,在与第i行扫描线连接的栅极的电位下拉至对应的所述薄膜晶体管关断后,将与第i行扫描线连接的栅极的目标电位设置为所述第一拉低电位。
  8. 根据权利要求7所述的像素驱动电路,其中,在下一帧第i行扫描线重新启动前,将与第i行扫描线连接的栅极的电位调整至所述第一拉低电位。
  9. 根据权利要求5所述的像素驱动电路,其中,所述第一拉低电位为-4~-10伏特。
  10. 根据权利要求5所述的像素驱动电路,其中,所述第二拉低电位为-10.1~-20伏特。
  11. 一种像素驱动方法,其中,用于驱动多行扫描线,在第i行扫描线处于下拉阶段时,扫描驱动器将第i行扫描线的下拉目标电位设置为第二拉低电位,在第i行扫描线所连接的栅极的电位下拉至对应的薄膜晶体管关断后,将与第i行扫描线连接的栅极的目标电位设置为第一拉低电位;其中,i为大于或等于1的正整数,所述第一拉低电位低于所述薄膜晶体管的关断电位,所述第二拉低电位低于所述第一拉低电位。
  12. 根据权利要求11所述的像素驱动方法,其中,将与第i行扫描线连接的栅极的电位调整至所述第一拉低电位。
  13. 根据权利要求11所述的像素驱动方法,其中,所述第一拉低电位为-4~-10伏特。
  14. 根据权利要求11所述的像素驱动方法,其中,所述第二拉低电位为-10.1~-20伏特。
PCT/CN2019/084244 2019-01-22 2019-04-25 一种像素驱动电路及其驱动方法 WO2020151115A1 (zh)

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