WO2018157447A1 - 像素单元及其驱动方法 - Google Patents

像素单元及其驱动方法 Download PDF

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Publication number
WO2018157447A1
WO2018157447A1 PCT/CN2017/080068 CN2017080068W WO2018157447A1 WO 2018157447 A1 WO2018157447 A1 WO 2018157447A1 CN 2017080068 W CN2017080068 W CN 2017080068W WO 2018157447 A1 WO2018157447 A1 WO 2018157447A1
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Prior art keywords
sub
region
thin film
film transistor
liquid crystal
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PCT/CN2017/080068
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English (en)
French (fr)
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张蒙蒙
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深圳市华星光电技术有限公司
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Priority to US15/539,689 priority Critical patent/US10247994B2/en
Publication of WO2018157447A1 publication Critical patent/WO2018157447A1/zh

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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel unit and a driving method thereof.
  • Liquid crystal display is one of the most widely used flat panel displays.
  • the liquid crystal panel is a core component of liquid crystal displays.
  • the liquid crystal panel is generally composed of a color filter substrate (CF), a thin film transistor array substrate (TFT Array Substrate), and a liquid crystal layer disposed between the two substrates.
  • a pixel electrode and a common electrode are respectively disposed on the array substrate and the color filter substrate.
  • the prior art In order to increase the viewing angle, the prior art generally designs the pixel electrode as a "m" shaped structure.
  • the pixel electrode comprises a strip-shaped vertical stem and a strip-shaped horizontal stem, and the vertical stem and the horizontal stem center intersect perpendicularly.
  • the so-called center-vertical intersection means that the vertical stem and the horizontal stem are perpendicular to each other, and both will have the entire pixel electrode area.
  • the average is divided into 4 domains.
  • Each pixel electrode region is composed of strips of slits (Slit) at an angle of ⁇ 45° and ⁇ 135° to the vertical stem or horizontal stem, and each strip branch is on the same plane as the vertical stem and the horizontal stem.
  • a pixel electrode structure of a "meter" shape in which the upper and lower sides and the left and right are mirror-symmetrical is formed.
  • the pixel structure of the "meter” type has a certain visual chromatic aberration or visual color shift due to the same angle between the strip branches in each pixel electrode region and the vertical trunk and the horizontal trunk, and the liquid crystal panel is worn. The penetration rate will also drop.
  • the prior art divides a pixel unit into a main area and a sub-area, and sets an independent main area pixel electrode in the main area and an independent sub-area pixel electrode in the sub-area. Both the main area pixel electrode and the sub-area pixel electrode are designed using the above-mentioned "m" shape structure. As shown in FIG.
  • each pixel unit includes: a main area thin film transistor T100, a sub-region thin film transistor T200, a charge sharing thin film transistor T300, a main area liquid crystal capacitor C100, and a sub-region liquid crystal capacitor C200, and the main area thin film
  • the gate of the transistor T100 is electrically connected to the scan line Gate corresponding to the pixel unit
  • the source is electrically connected to the data line Data corresponding to the pixel unit
  • the drain is electrically connected to one end of the main area liquid crystal capacitor C100
  • the sub-region thin film transistor is electrically connected.
  • the gate of the T200 is electrically connected to the scan line Gate corresponding to the pixel unit, the source is electrically connected to the data line Data corresponding to the pixel unit, and the drain is electrically connected to one end of the sub-region liquid crystal capacitor C200.
  • the gate of the charge sharing thin film transistor T300 is electrically connected to the scan line Gate corresponding to the pixel unit, the source is electrically connected to the array substrate common voltage Acom, and the drain is electrically connected to one end of the sub-region liquid crystal capacitor C200.
  • the other end of the liquid crystal capacitor C100 and the sub-region liquid crystal capacitor C200 are electrically connected to the common voltage Ccom of the color filter substrate.
  • the main-region thin film transistor T100 charges the pixel electrode of the main region
  • the sub-region thin film transistor T200 charges the pixel electrode of the sub-region.
  • the charge sharing thin film transistor T300 discharges the sub-region pixel electrode such that the main region and the sub-region generate different potentials to increase the viewing angle, but the pixel unit electrically connects the source of the charge-sharing thin film transistor T300 to the array substrate.
  • the voltage Acom needs to set the array substrate common voltage trace on the array substrate, which reduces the aperture ratio of the liquid crystal display panel and increases the frame width of the liquid crystal display panel.
  • An object of the present invention is to provide a pixel unit capable of increasing an aperture ratio of a liquid crystal display panel and reducing a frame width of the liquid crystal display panel.
  • Another object of the present invention is to provide a driving method of a pixel unit, which can increase the aperture ratio of the liquid crystal display panel and reduce the frame width of the liquid crystal display panel.
  • the present invention provides a pixel unit comprising: a plurality of sub-pixels arranged in an array, a plurality of horizontally arranged scanning lines arranged in parallel, and a plurality of vertical data lines arranged in parallel;
  • Each row of sub-pixels corresponds to one scan line, and each column of sub-pixels corresponds to one data line, and each of the sub-pixels includes: a main-region thin film transistor, a sub-region thin film transistor, and a charge sharing thin film transistor;
  • n and m be positive integers, in the nth row and mth column sub-pixels: the gate of the main-region thin film transistor is electrically connected to the nth scan line, the source is electrically connected to the mth data line, and the drain Electrically connecting the pixel electrode of the main area;
  • the gate of the sub-region thin film transistor is electrically connected to the nth scan line, the source is electrically connected to the mth data line, and the drain is electrically connected to the sub-region pixel electrode;
  • the gate of the charge sharing thin film transistor is electrically connected to the nth scan line, the source is electrically connected to the n+1th scan line, and the drain is electrically connected to the sub-region pixel electrode;
  • the nth scan line When the nth scan line provides a high potential, the n+1th scan line provides a common voltage of the array substrate, and the remaining scan lines provide a low potential.
  • the main area pixel electrode and the sub-area pixel electrode are both of a m-shaped structure, and the materials are all ITO.
  • the gate of the main-region thin film transistor, the gate of the sub-region thin film transistor, and the charge sharing film a gate of the transistor and a scan line are located in the first metal layer, a source and a drain of the main-region thin film transistor, a source and a drain of the sub-region thin film transistor, a source and a drain of the charge sharing thin film transistor, and
  • the data line is located in a second metal layer that is insulatively laminated with the first metal layer.
  • the scanning direction of the pixel unit when driving is scanning from the first row of sub-pixels to the last row of sub-pixels.
  • the invention also provides a driving method of a pixel unit, comprising the following steps:
  • Step 1 Providing a pixel unit, comprising: a plurality of sub-pixels arranged in an array, a plurality of horizontal scanning lines arranged in parallel, and a plurality of vertical data lines arranged in parallel;
  • Each row of sub-pixels corresponds to one scan line, and each column of sub-pixels corresponds to one data line, and each sub-pixel includes: a main-region thin film transistor, a sub-region thin film transistor, a charge sharing thin film transistor, a main-area liquid crystal capacitor, and a sub-region liquid crystal capacitor;
  • n and m be positive integers, in the nth row and mth column sub-pixels: the gate of the main-region thin film transistor is electrically connected to the nth scan line, the source is electrically connected to the mth data line, and the drain Electrically connecting one end of the main area liquid crystal capacitor;
  • the gate of the sub-region thin film transistor is electrically connected to the nth scan line, the source is electrically connected to the mth data line, and the drain is electrically connected to one end of the sub-region liquid crystal capacitor;
  • the gate of the charge sharing thin film transistor is electrically connected to the nth scan line, the source is electrically connected to the n+1th scan line, and the drain is electrically connected to one end of the sub-region liquid crystal capacitor;
  • the liquid crystal capacitor of the main area and the other end of the sub-region liquid crystal capacitor are electrically connected to the common voltage of the color filter substrate;
  • Step 2 sequentially scanning each row of sub-pixels
  • the scanning process of each row of sub-pixels is: the current scanning sub-pixel row number is the n-th row, the n-th scanning line provides a high potential, the n+1th scanning line provides the array substrate common voltage, and the rest
  • the scan lines each provide a low potential, and the main-region thin film transistor, the sub-region thin film transistor, and the charge-sharing thin film transistor are both turned on, the main-region thin film transistor is charged as a main-region liquid crystal capacitor, and the sub-region thin film transistor is a sub-region The liquid crystal capacitor is charged, and the charge sharing thin film transistor discharges the sub-region liquid crystal capacitor, so that the voltage across the liquid crystal capacitor of the sub-region is lower than the voltage across the liquid crystal capacitor of the main region.
  • One end of the liquid crystal capacitor of the main area is a pixel electrode of a main area, and the other end is a common electrode;
  • One end of the sub-region liquid crystal capacitor is a sub-region pixel electrode, and the other end is a common electrode.
  • the main area pixel electrode and the sub-area pixel electrode are both of a m-shaped structure, and the materials are all ITO.
  • a gate of the main-region thin film transistor, a gate of the sub-region thin film transistor, a gate of the charge sharing thin film transistor, and a scan line are located in the first metal layer, and a source and a drain and a sub-region of the main-region thin film transistor Source and drain of thin film transistor, source and drain of charge sharing thin film transistor The poles and the data lines are located in a second metal layer that is insulatively laminated with the first metal layer.
  • the scanning direction of the pixel unit is scanning from the first row of sub-pixels to the last row of sub-pixels.
  • the invention also provides a driving method of a pixel unit, comprising the following steps:
  • Step 1 Providing a pixel unit, comprising: a plurality of sub-pixels arranged in an array, a plurality of horizontal scanning lines arranged in parallel, and a plurality of vertical data lines arranged in parallel;
  • Each row of sub-pixels corresponds to one scan line, and each column of sub-pixels corresponds to one data line, and each sub-pixel includes: a main-region thin film transistor, a sub-region thin film transistor, a charge sharing thin film transistor, a main-area liquid crystal capacitor, and a sub-region liquid crystal capacitor;
  • n and m be positive integers, in the nth row and mth column sub-pixels: the gate of the main-region thin film transistor is electrically connected to the nth scan line, the source is electrically connected to the mth data line, and the drain Electrically connecting one end of the main area liquid crystal capacitor;
  • the gate of the sub-region thin film transistor is electrically connected to the nth scan line, the source is electrically connected to the mth data line, and the drain is electrically connected to one end of the sub-region liquid crystal capacitor;
  • the gate of the charge sharing thin film transistor is electrically connected to the nth scan line, the source is electrically connected to the n+1th scan line, and the drain is electrically connected to one end of the sub-region liquid crystal capacitor;
  • the liquid crystal capacitor of the main area and the other end of the sub-region liquid crystal capacitor are electrically connected to the common voltage of the color filter substrate;
  • Step 2 sequentially scanning each row of sub-pixels
  • the scanning process of each row of sub-pixels is: the current scanning sub-pixel row number is the n-th row, the n-th scanning line provides a high potential, the n+1th scanning line provides the array substrate common voltage, and the rest
  • the scan lines each provide a low potential, and the main-region thin film transistor, the sub-region thin film transistor, and the charge-sharing thin film transistor are both turned on, the main-region thin film transistor is charged as a main-region liquid crystal capacitor, and the sub-region thin film transistor is a sub-region The liquid crystal capacitor is charged, and the charge sharing thin film transistor discharges the sub-region liquid crystal capacitor, so that the voltage across the liquid crystal capacitor of the sub-region is lower than the voltage across the liquid crystal capacitor of the main region;
  • one end of the liquid crystal capacitor of the main area is a pixel electrode of the main area, and the other end is a common electrode of the color filter substrate;
  • One end of the sub-region liquid crystal capacitor is a sub-region pixel electrode, and the other end is a color film substrate common electrode;
  • the scanning direction of the pixel unit during driving is scanning from the first row of subpixels to the last row of subpixels.
  • the present invention provides a pixel unit electrically connecting a source of a charge sharing thin film transistor to a scan line corresponding to a next row of sub-pixels of a sub-pixel in which the sub-pixel is located, And setting the potential of the scan line corresponding to the next row of sub-pixels to the common voltage of the array substrate, so that the main area and the sub-area of the sub-pixel have different potentials, and the array substrate common voltage trace is not required to be additionally disposed.
  • the present invention also provides a driving method of a pixel unit, which can reduce the number of wirings and the width of the frame in the array substrate, and increase the aperture ratio of the liquid crystal display panel.
  • 1 is a circuit diagram of a conventional pixel unit
  • FIG. 2 is a circuit diagram of a sub-pixel in a pixel unit of the present invention.
  • FIG. 3 is a timing diagram of a pixel unit of the present invention.
  • FIG. 4 is a structural diagram of a pixel unit of the present invention.
  • FIG. 5 is a flowchart of a method of driving a pixel unit of the present invention.
  • the present invention provides a pixel unit including: a plurality of sub-pixels 10 arranged in an array, a plurality of horizontally spaced horizontal scanning lines 20, and a plurality of vertically spaced parallel data. Line 30;
  • each row of sub-pixels 10 corresponds to one scan line 20, and each column of sub-pixels 10 corresponds to one data line 30.
  • each of the sub-pixels 10 includes: a main-region thin film transistor T1, a sub-region thin film transistor T2, and a charge. Sharing thin film transistor T3;
  • n and m are positive integers.
  • the gate of the main-region thin film transistor T1 is electrically connected to the n-th scan line G(n), and the source is electrically
  • the mth data line Data(m) is connected, and the drain is electrically connected to the main area pixel electrode 100; the gate of the sub-region thin film transistor T2 is electrically connected to the nth scan line G(n), and the source is electrically connected.
  • the mth data line Data(m) the drain is electrically connected to the sub-region pixel electrode 200; the gate of the charge sharing thin film transistor T3 is electrically connected to the nth scan line G(n), and the source is electrically connected.
  • n+1 scan lines G(n+1) the drain is electrically connected to the sub-region pixel electrode 200; the nth scan line G(n) provides a high potential VGH The n+1th scan line G(n+1) provides the array substrate common voltage Acom, and the remaining scan lines 20 each provide a low potential VGL.
  • each sub-pixel 10 is divided into a main area and a sub-area, and an independent main-area pixel electrode 100 is disposed in the main area in the sub-region.
  • An independent sub-region pixel electrode 200 is disposed.
  • the main-region pixel electrode 100 and the common electrode (not shown) on the color filter substrate together form a main-region liquid crystal capacitor C1, and the sub-region pixel electrode 200 and the color filter substrate.
  • the common electrode forms a sub-region liquid crystal capacitor C1, that is, one end of the main-region liquid crystal capacitor C1 is a main-region pixel electrode 100, and the other end is a color film substrate common electrode, and one end of the sub-region liquid crystal capacitor C2 is a sub-region pixel.
  • the other end of the electrode 200 is a common electrode of the color filter substrate, and the common electrode of the color filter substrate is connected to the common voltage Ccom of the color filter substrate, that is, the other end of the liquid crystal capacitor C1 of the main area and the liquid crystal capacitor C2 of the sub-area are electrically connected.
  • Color film substrate common voltage Ccom is a common electrode of the color filter substrate, and the common electrode of the color filter substrate is connected to the common voltage Ccom of the color filter substrate, that is, the other end of the liquid crystal capacitor C1 of the main area and the liquid crystal capacitor C2 of the sub-area are electrically connected.
  • the main-region pixel electrode 100 and the sub-region pixel electrode 200 are both of a Mi-shaped structure, and the materials are preferably Indium tin oxide (ITO).
  • ITO Indium tin oxide
  • the gate of the main-region thin film transistor T1, the gate of the sub-region thin film transistor T2, the gate of the charge-sharing thin film transistor T3, and the scan line 20 are all located in the first metal layer.
  • the source and drain of the main-region thin film transistor T1, the source and drain of the sub-region thin film transistor T2, the source and drain of the charge-sharing thin film transistor T3, and the data line 30 are both located at the same first metal layer Insulating the laminated second metal layer.
  • the scanning direction of the pixel unit is to scan from the first row of sub-pixels 10 to the last row of sub-pixels 10, that is, the n+1th row of sub-pixels 10 are performed after the n-th sub-pixel 10 scanning.
  • the operation of the pixel unit of the present invention is: first, the nth scan line G(n) provides a high potential VGH, and the n+1th scan line G(n+ 1) providing an array substrate common voltage Acom, and the remaining scan lines 20 each providing a low potential VGL, so that the main-region thin film transistor T1, the sub-region thin film transistor T2, and the charge sharing thin film transistor T3 in the n-th row sub-pixel 10 are both turned on,
  • the main-region thin film transistor T1 charges the liquid crystal capacitor C1 of the main region
  • the sub-region thin film transistor T2 charges the sub-region liquid crystal capacitor C1
  • the charge-sharing thin film transistor T3 discharges the sub-region liquid crystal capacitor C1, so that the sub-region liquid crystal capacitor
  • the voltage across C1 is lower than the voltage across the main area liquid crystal capacitor C1
  • the n+1th scan line G(n) provides a high potential VGH
  • the n+2th scan line G(n+2) provides the array substrate
  • the charge sharing TFT T3 is a liquid crystal capacitor C1 discharge time zone, such that the secondary fluid zone
  • the voltage across the crystal capacitor C1 is lower than the voltage across the main area liquid crystal capacitor C1, and so on to the last row of sub-pixels 10.
  • the array substrate common voltage Acom may be disposed near the color film substrate common voltage Ccom, and the specific voltage value needs to be specifically adjusted according to the product, and the array substrate common voltage Acom is greater than the low potential VGL and less than the high potential VGH.
  • the present invention electrically connects the source of the charge-sharing thin film transistor T3 to the scan line 20 corresponding to the next row of sub-pixels 10 of the sub-pixel 10 in which it is located, and scans the sub-pixel 10 for the scan line 20 corresponding to the next row of sub-pixels 10
  • the potential is set to the common voltage Acom of the array substrate, so that the main area and the sub-area of the sub-pixel 10 have different potentials.
  • there is no need to additionally set the common voltage trace of the array substrate thereby effectively reducing the wiring in the array substrate.
  • the increase in the aperture ratio of the liquid crystal display panel facilitates the realization of a narrow bezel of the liquid crystal display panel.
  • the present invention further provides a driving method of a pixel unit, including the following steps:
  • Step 1 please refer to FIG. 2 and FIG. 4, and a pixel unit is provided. The specific structure is not described herein again.
  • Step 2 sequentially scanning each row of sub-pixels 10;
  • the scanning process of each row of sub-pixels 10 is: the current scanning sub-pixel 10 rows are the n-th row, the n-th scanning line G(n) provides a high potential VGH, the n+1th scanning line G(n+1) provides the array substrate common voltage Acom, and the remaining scan lines 20 each provide a low potential VGL, and the main-region thin film transistor T1, the sub-region thin film transistor T2, and the charge sharing thin film transistor T3 are both turned on, the main The thin film transistor T1 is charged in the main area liquid crystal capacitor C1, and the sub-region thin film transistor T2 charges the sub-region liquid crystal capacitor C1, and the charge sharing thin film transistor T3 discharges the sub-region liquid crystal capacitor C1, so that the sub-region liquid crystal capacitor C1 is at both ends The voltage is lower than the voltage across the main area liquid crystal capacitor C1.
  • scanning is performed in a direction from the first row of sub-pixels 10 to the last row of sub-pixels 10, that is, the (n+1)th row of sub-pixels 10 is scanned after the nth sub-pixel 10, that is, at the nth row.
  • the potential of the scan line G(n+1) corresponding to the n+1th row of sub-pixels 10 is the array substrate common voltage Acom, so that the main region and the sub-region of the n-th row of sub-pixels 10 have different potentials.
  • there is no need to additionally set the common voltage trace of the array substrate effectively reducing the number of wires in the array substrate, increasing the aperture ratio of the liquid crystal display panel, and facilitating the narrow border of the liquid crystal display panel.
  • the array substrate common voltage Acom may be disposed near the color film substrate common voltage Ccom, and the specific voltage value needs to be specifically adjusted according to the product, and the array substrate common voltage Acom is greater than the low potential VGL and less than the high potential VGH.
  • the present invention provides a pixel unit by using a charge sharing thin film transistor
  • the source is electrically connected to the scan line corresponding to the next row of sub-pixels of the sub-pixel, and the potential of the scan line corresponding to the next row of sub-pixels is set to the common voltage of the array substrate, so that the main area of the sub-pixel It has different potentials from the sub-region, and does not need to additionally set the common voltage trace of the array substrate.
  • the present invention also provides a driving method of a pixel unit, which can reduce the number of wirings and the width of the frame in the array substrate, and increase the aperture ratio of the liquid crystal display panel.

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Abstract

一种像素单元及其驱动方法，通过将电荷共享薄膜晶体管（T3）的源极与其所在子像素（10）的下一行子像素（10）对应的扫描线（G(n+1)）电性连接，并将该子像素（10）扫描时下一行子像素（10）对应的扫描线（G(n+1)）的电位设置为阵列基板公共电压（Acom），使得该子像素（10）的主区与次区具有不同电位，且不需要额外设置阵列基板公共电压走线，相比现有技术，减少了阵列基板中的布线数量，增大液晶显示面板的开口率，有利于实现液晶显示面板的窄边框。

Description

像素单元及其驱动方法 技术领域
本发明涉及显示技术领域，尤其涉及一种像素单元及其驱动方法。
背景技术
液晶显示器(Liquid Crystal Display，LCD)是目前最广泛使用的平板显示器之一，液晶面板是液晶显示器的核心组成部分。液晶面板通常是由一彩膜基板(Color Filter，CF)、一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成。一般阵列基板、彩膜基板上分别设置像素电极、公共电极。当电压被施加到像素电极与公共电极便会在液晶层中产生电场，该电场决定了液晶分子的取向，从而调整入射到液晶层的光的偏振，使液晶面板显示图像。
为了增大视角，现有技术通常将像素电极设计为“米”字型结构。像素电极包含条状的竖直主干和条状的水平主干，且竖直主干和水平主干中心垂直相交，所谓中心垂直相交是指竖直主干和水平主干相互垂直，且二者将整个像素电极面积平均分成4个区域(domain)。每个像素电极区域都由与竖直主干或水平主干呈±45°、±135°角度的条状分支(Slit)平铺组成，各条状分支与竖直主干和水平主干位于同一平面上，形成上下和左右均镜像对称的“米”字型的像素电极结构。
这种“米”字型的像素电极结构，因每一像素电极区域内的条状分支与竖直主干和水平主干的夹角相同，会存在一定的视觉色差或视觉色偏，液晶面板的穿透率也会下降。为了改善视觉色差或视觉色偏，现有技术会将一个像素单元分成主区和次区，在主区内设置一个独立的主区像素电极、在次区内设置一个独立的次区像素电极，主区像素电极与次区像素电极均采用上述的“米”字型结构设计。如图1所示，每一个像素单元内均包括：主区薄膜晶体管T100、次区薄膜晶体管T200、电荷共享薄膜晶体管T300、主区液晶电容C100、以及次区液晶电容C200,所述主区薄膜晶体管T100的栅极电性连接该像素单元对应的扫描线Gate，源极电性连接该像素单元对应的数据线Data，漏极电性连接主区液晶电容C100的一端，所述次区薄膜晶体管T200的栅极电性连接该像素单元对应的扫描线Gate，源极电性连接该像素单元对应的数据线Data，漏极电性连接次区液晶电容C200的一端， 所述电荷共享薄膜晶体管T300的栅极电性连接该像素单元对应的扫描线Gate，源极电性连接阵列基板公共电压Acom，漏极电性连接次区液晶电容C200的一端，所述主区液晶电容C100与次区液晶电容C200的另一端均电性连接彩膜基板公共电压Ccom，工作时，主区薄膜晶体管T100为主区像素电极充电、次区薄膜晶体管T200为次区像素电极充电、电荷共享薄膜晶体管T300为次区像素电极放电，从而使得主区与次区产生不同的电位，以增大视角，但该像素单元为了将电荷共享薄膜晶体管T300的源极电性连接至阵列基板公共电压Acom，需要在阵列基板上设置阵列基板公共电压走线，这会降低液晶显示面板的开口率，增加液晶显示面板的边框宽度。
发明内容
本发明的目的在于提供一种像素单元，能够增大液晶显示面板的开口率，减小液晶显示面板的边框宽度。
本发明的目的还在于提供一种像素单元的驱动方法，能够增大液晶显示面板的开口率，减小液晶显示面板的边框宽度。
为实现上述目的，本发明提供一种像素单元，包括：阵列排布的多个子像素、多条平行间隔排列的水平的扫描线、以及多条平行间隔排列的竖直的数据线；
每一行子像素对应一条扫描线，每一列子像素对应一条数据线，每一个子像素均包括：主区薄膜晶体管、次区薄膜晶体管和电荷共享薄膜晶体管；
设n和m均为正整数，在第n行第m列子像素中：所述主区薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第m条数据线，漏极电性连接主区像素电极；
所述次区薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第m条数据线，漏极电性连接次区像素电极；
所述电荷共享薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第n+1条扫描线，漏极电性连接次区像素电极；
所述第n条扫描线提供高电位时，所述第n+1条扫描线提供阵列基板公共电压，其余的扫描线均提供低电位。
所述主区像素电极和彩膜基板公共电极共同组成主区液晶电容；
所示次区像素电极和彩膜基板公共电极共同组成次区液晶电容。
所述主区像素电极与次区像素电极均为米字型结构，材料均为ITO。
所述主区薄膜晶体管的栅极、次区薄膜晶体管的栅极、电荷共享薄膜 晶体管的栅极、以及扫描线位于第一金属层，所述主区薄膜晶体管的源极和漏极、次区薄膜晶体管的源极和漏极、电荷共享薄膜晶体管的源极和漏极、以及数据线位于与所述第一金属层绝缘层叠的第二金属层。
所述像素单元在驱动时的扫描方向为从第一行子像素向最后一行子像素进行扫描。
本发明还提供一种像素单元的驱动方法，包括如下步骤：
步骤1、提供一像素单元，包括：阵列排布的多个子像素、多条平行间隔排列的水平的扫描线、以及多条平行间隔排列的竖直的数据线；
每一行子像素对应一条扫描线，每一列子像素对应一条数据线，每一个子像素均包括：主区薄膜晶体管、次区薄膜晶体管、电荷共享薄膜晶体管、主区液晶电容以及次区液晶电容；
设n和m均为正整数，在第n行第m列子像素中：所述主区薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第m条数据线，漏极电性连接主区液晶电容的一端；
所述次区薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第m条数据线，漏极电性连接次区液晶电容的一端；
所述电荷共享薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第n+1条扫描线，漏极电性连接次区液晶电容的一端；
所述主区液晶电容与次区液晶电容的另一端均电性连接彩膜基板公共电压；
步骤2、依次对各行子像素进行扫描；
每一行子像素的扫描过程均为：设当前扫描的子像素行数为第n行，所述第n条扫描线提供高电位，所述第n+1条扫描线提供阵列基板公共电压，其余的扫描线均提供低电位，所述主区薄膜晶体管、次区薄膜晶体管、以及电荷共享薄膜晶体管均打开，所述主区薄膜晶体管为主区液晶电容充电，所述次区薄膜晶体管为次区液晶电容充电，所述电荷共享薄膜晶体管为次区液晶电容放电，使得次区液晶电容两端的电压低于所述主区液晶电容两端的电压。
所述主区液晶电容的一端为主区像素电极，另一端为公共电极；
所述次区液晶电容的一端为次区像素电极，另一端为公共电极。
所述主区像素电极与次区像素电极均为米字型结构，材料均为ITO。
所述主区薄膜晶体管的栅极、次区薄膜晶体管的栅极、电荷共享薄膜晶体管的栅极、以及扫描线位于第一金属层，所述主区薄膜晶体管的源极和漏极、次区薄膜晶体管的源极和漏极、电荷共享薄膜晶体管的源极和漏 极、以及数据线位于与所述第一金属层绝缘层叠的第二金属层。
所述像素单元的扫描方向为从第一行子像素向最后一行子像素进行扫描。
本发明还提供一种像素单元的驱动方法，包括如下步骤：
步骤1、提供一像素单元，包括：阵列排布的多个子像素、多条平行间隔排列的水平的扫描线、以及多条平行间隔排列的竖直的数据线；
每一行子像素对应一条扫描线，每一列子像素对应一条数据线，每一个子像素均包括：主区薄膜晶体管、次区薄膜晶体管、电荷共享薄膜晶体管、主区液晶电容以及次区液晶电容；
设n和m均为正整数，在第n行第m列子像素中：所述主区薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第m条数据线，漏极电性连接主区液晶电容的一端；
所述次区薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第m条数据线，漏极电性连接次区液晶电容的一端；
所述电荷共享薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第n+1条扫描线，漏极电性连接次区液晶电容的一端；
所述主区液晶电容与次区液晶电容的另一端均电性连接彩膜基板公共电压；
步骤2、依次对各行子像素进行扫描；
每一行子像素的扫描过程均为：设当前扫描的子像素行数为第n行，所述第n条扫描线提供高电位，所述第n+1条扫描线提供阵列基板公共电压，其余的扫描线均提供低电位，所述主区薄膜晶体管、次区薄膜晶体管、以及电荷共享薄膜晶体管均打开，所述主区薄膜晶体管为主区液晶电容充电，所述次区薄膜晶体管为次区液晶电容充电，所述电荷共享薄膜晶体管为次区液晶电容放电，使得次区液晶电容两端的电压低于所述主区液晶电容两端的电压；
其中，所述主区液晶电容的一端为主区像素电极，另一端为彩膜基板公共电极；
所述次区液晶电容的一端为次区像素电极，另一端为彩膜基板公共电极；
其中，所述像素单元在驱动时的扫描方向为从第一行子像素向最后一行子像素进行扫描。
本发明的有益效果：本发明提供一种像素单元，其通过将电荷共享薄膜晶体管的源极与其所在子像素的下一行子像素对应的扫描线电性连接， 并将该子像素扫描时下一行子像素对应的扫描线的电位设置为阵列基板公共电压，使得该子像素的主区与次区具有不同电位，且不需要额外设置阵列基板公共电压走线，相比现有技术，减少了阵列基板中的布线数量，增大液晶显示面板的开口率，有利于实现液晶显示面板的窄边框。本发明还提供一种像素单元的驱动方法，能够减少阵列基板中的布线数量和边框宽度，增大液晶显示面板的开口率。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的像素单元的电路图；
图2为本发明的像素单元中一个子像素的电路图；
图3为本发明的像素单元的时序图；
图4为本发明的像素单元的结构图；
图5为本发明的像素单元的驱动方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2及图4，本发明提供一种像素单元，包括：阵列排布的多个子像素10、多条平行间隔排列的水平的扫描线20、以及多条平行间隔排列的竖直的数据线30；
其中，每一行子像素10对应一条扫描线20，每一列子像素10对应一条数据线30，请参阅图2，每一个子像素10均包括：主区薄膜晶体管T1、次区薄膜晶体管T2和电荷共享薄膜晶体管T3；
具体地，设n和m均为正整数，在第n行第m列子像素10中：所述主区薄膜晶体管T1的栅极电性连接第n条扫描线G(n)，源极电性连接第m条数据线Data(m)，漏极电性连接主区像素电极100；所述次区薄膜晶体管T2的栅极电性连接第n条扫描线G(n)，源极电性连接第m条数据线Data(m)，漏极电性连接次区像素电极200；所述电荷共享薄膜晶体管T3的栅极电性连接第n条扫描线G(n)，源极电性连接第n+1条扫描线G(n+1)，漏极电性连接次区像素电极200；所述第n条扫描线G(n)提供高电位VGH 时，所述第n+1条扫描线G(n+1)提供阵列基板公共电压Acom，其余的扫描线20均提供低电位VGL。
需要说明的是，如图4所示，每一个子像素10均分为主区(main)和次区(sub)，在主区内设置有一个独立的主区像素电极100，在次区内设置有一个独立的次区像素电极200，所述主区像素电极100与彩膜基板上的公共电极(未图示)共同形成主区液晶电容C1，所述次区像素电极200与彩膜基板公共电极共同形成次区液晶电容C1，也即所述主区液晶电容C1的一端为主区像素电极100，另一端为彩膜基板公共电极，所述次区液晶电容C2的一端为次区像素电极200，另一端为彩膜基板公共电极，所述彩膜基板公共电极接入彩膜基板公共电压Ccom，也即所述主区液晶电容C1与次区液晶电容C2的另一端均电性连接彩膜基板公共电压Ccom。
优选地，所述主区像素电极100与次区像素电极200均为米字型结构，材料均优选氧化铟锡(Indium tin oxide，ITO)。
进一步地，如图4所示，所述主区薄膜晶体管T1的栅极、次区薄膜晶体管T2的栅极、电荷共享薄膜晶体管T3的栅极、以及扫描线20均位于第一金属层，所述主区薄膜晶体管T1的源极和漏极、次区薄膜晶体管T2的源极和漏极、电荷共享薄膜晶体管T3的源极和漏极、以及数据线30均位于与所述第一金属层绝缘层叠的第二金属层。
值得一提的是，所述像素单元在驱动时的扫描方向为从第一行子像素10向最后一行子像素10进行扫描，即第n+1行子像素10在第n子像素10之后进行扫描。
请同时参阅图2及图3，本发明的像素单元的工作过程为：首先，所述第n条扫描线G(n)提供高电位VGH，所述第n+1条扫描线G(n+1)提供阵列基板公共电压Acom，其余的扫描线20均提供低电位VGL，使得第n行子像素10中的主区薄膜晶体管T1、次区薄膜晶体管T2、以及电荷共享薄膜晶体管T3均打开，所述主区薄膜晶体管T1为主区液晶电容C1充电，所述次区薄膜晶体管T2为次区液晶电容C1充电，所述电荷共享薄膜晶体管T3为次区液晶电容C1放电，使得次区液晶电容C1两端的电压低于所述主区液晶电容C1两端的电压，接着第n+1条扫描线G(n)提供高电位VGH，第n+2条扫描线G(n+2)提供阵列基板公共电压Acom，其余的扫描线20均提供低电位VGL，使得第n+1行子像素10中的主区薄膜晶体管T1、次区薄膜晶体管T2、以及电荷共享薄膜晶体管T3均打开，所述主区薄膜晶体管T1为主区液晶电容C1充电，所述次区薄膜晶体管T2为次区液晶电容C1充电，所述电荷共享薄膜晶体管T3为次区液晶电容C1放电，使得次区液 晶电容C1两端的电压低于所述主区液晶电容C1两端的电压，依次类推直至最后一行子像素10。
具体地，所述阵列基板公共电压Acom可设置在彩膜基板公共电压Ccom附近，具体电压值需根据产品具体调节，同时所述阵列基板公共电压Acom大于低电位VGL且小于高电位VGH。
本发明通过将电荷共享薄膜晶体管T3的源极与其所在子像素10的下一行子像素10对应的扫描线20电性连接，并将该子像素10扫描时下一行子像素10对应的扫描线20的电位设置为阵列基板公共电压Acom，使得该子像素10的主区与次区具有不同电位，相比于现有技术，不需要额外设置阵列基板公共电压走线，有效减少了阵列基板中的布线数量，增大液晶显示面板的开口率，有利于实现液晶显示面板的窄边框。
请参阅图5，本发明还提供一种像素单元的驱动方法，包括如下步骤：
步骤1、请参阅图2及图4，提供一上述像素单元，具体结构在此不再赘述。
步骤2、依次对各行子像素10进行扫描；
每一行子像素10的扫描过程均为：设当前扫描的子像素10行数为第n行，所述第n条扫描线G(n)提供高电位VGH，所述第n+1条扫描线G(n+1)提供阵列基板公共电压Acom，其余的扫描线20均提供低电位VGL，所述主区薄膜晶体管T1、次区薄膜晶体管T2、以及电荷共享薄膜晶体管T3均打开，所述主区薄膜晶体管T1为主区液晶电容C1充电，所述次区薄膜晶体管T2为次区液晶电容C1充电，所述电荷共享薄膜晶体管T3为次区液晶电容C1放电，使得次区液晶电容C1两端的电压低于所述主区液晶电容C1两端的电压。
具体地，扫描时，按照从第一行子像素10向最后一行子像素10的方向进行扫描，即第n+1行子像素10在第n子像素10之后进行扫描，也即在第n行子像素10扫描时第n+1行子像素10对应的扫描线G(n+1)的电位为阵列基板公共电压Acom，使得第n行子像素10的主区与次区具有不同电位，相比于现有技术，不需要额外设置阵列基板公共电压走线，有效减少了阵列基板中的布线数量，增大液晶显示面板的开口率，有利于实现液晶显示面板的窄边框。
具体地，所述阵列基板公共电压Acom可设置在彩膜基板公共电压Ccom附近，具体电压值需根据产品具体调节，同时所述阵列基板公共电压Acom大于低电位VGL且小于高电位VGH。
综上所述，本发明提供一种像素单元，其通过将电荷共享薄膜晶体管 的源极与其所在子像素的下一行子像素对应的扫描线电性连接，并将该子像素扫描时下一行子像素对应的扫描线的电位设置为阵列基板公共电压，使得该子像素的主区与次区具有不同电位，且不需要额外设置阵列基板公共电压走线，相比现有技术，减少了阵列基板中的布线数量，增大液晶显示面板的开口率，有利于实现液晶显示面板的窄边框。本发明还提供一种像素单元的驱动方法，能够减少阵列基板中的布线数量和边框宽度，增大液晶显示面板的开口率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种像素单元，包括：阵列排布的多个子像素、多条平行间隔排列的水平的扫描线、以及多条平行间隔排列的竖直的数据线；
    每一行子像素对应一条扫描线，每一列子像素对应一条数据线，每一个子像素均包括：主区薄膜晶体管、次区薄膜晶体管和电荷共享薄膜晶体管；
    设n和m均为正整数，在第n行第m列子像素中：所述主区薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第m条数据线，漏极电性连接主区像素电极；
    所述次区薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第m条数据线，漏极电性连接次区像素电极；
    所述电荷共享薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第n+1条扫描线，漏极电性连接次区像素电极；
    所述第n条扫描线提供高电位时，所述第n+1条扫描线提供阵列基板公共电压，其余的扫描线均提供低电位。
  2. 如权利要求1所述的像素单元，其中，所述主区像素电极和彩膜基板公共电极共同组成主区液晶电容；
    所示次区像素电极和彩膜基板公共电极共同组成次区液晶电容。
  3. 如权利要求1所述的像素单元，其中，所述主区像素电极与次区像素电极均为米字型结构，材料均为ITO。
  4. 如权利要求1所述的像素单元，其中，所述主区薄膜晶体管的栅极、次区薄膜晶体管的栅极、电荷共享薄膜晶体管的栅极、以及扫描线位于第一金属层，所述主区薄膜晶体管的源极和漏极、次区薄膜晶体管的源极和漏极、电荷共享薄膜晶体管的源极和漏极、以及数据线位于与所述第一金属层绝缘层叠的第二金属层。
  5. 如权利要求1所述的像素单元，其中，所述像素单元在驱动时的扫描方向为从第一行子像素向最后一行子像素进行扫描。
  6. 一种像素单元的驱动方法，包括如下步骤：
    步骤1、提供一像素单元，包括：阵列排布的多个子像素、多条平行间隔排列的水平的扫描线、以及多条平行间隔排列的竖直的数据线；
    每一行子像素对应一条扫描线，每一列子像素对应一条数据线，每一个子像素均包括：主区薄膜晶体管、次区薄膜晶体管、电荷共享薄膜晶体 管、主区液晶电容以及次区液晶电容；
    设n和m均为正整数，在第n行第m列子像素中：所述主区薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第m条数据线，漏极电性连接主区液晶电容的一端；
    所述次区薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第m条数据线，漏极电性连接次区液晶电容的一端；
    所述电荷共享薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第n+1条扫描线，漏极电性连接次区液晶电容的一端；
    所述主区液晶电容与次区液晶电容的另一端均电性连接彩膜基板公共电压；
    步骤2、依次对各行子像素进行扫描；
    每一行子像素的扫描过程均为：设当前扫描的子像素行数为第n行，所述第n条扫描线提供高电位，所述第n+1条扫描线提供阵列基板公共电压，其余的扫描线均提供低电位，所述主区薄膜晶体管、次区薄膜晶体管、以及电荷共享薄膜晶体管均打开，所述主区薄膜晶体管为主区液晶电容充电，所述次区薄膜晶体管为次区液晶电容充电，所述电荷共享薄膜晶体管为次区液晶电容放电，使得次区液晶电容两端的电压低于所述主区液晶电容两端的电压。
  7. 如权利要求6所述的像素单元的驱动方法，其中，所述主区液晶电容的一端为主区像素电极，另一端为彩膜基板公共电极；
    所述次区液晶电容的一端为次区像素电极，另一端为彩膜基板公共电极。
  8. 如权利要求7所述的像素单元的驱动方法，其中，所述主区像素电极与次区像素电极均为米字型结构，材料均为ITO。
  9. 如权利要求6所述的像素单元的驱动方法，其中，所述主区薄膜晶体管的栅极、次区薄膜晶体管的栅极、电荷共享薄膜晶体管的栅极、以及扫描线位于第一金属层，所述主区薄膜晶体管的源极和漏极、次区薄膜晶体管的源极和漏极、电荷共享薄膜晶体管的源极和漏极、以及数据线位于与所述第一金属层绝缘层叠的第二金属层。
  10. 如权利要求6所述的像素单元的驱动方法，其中，所述像素单元在驱动时的扫描方向为从第一行子像素向最后一行子像素进行扫描。
  11. 一种像素单元的驱动方法，包括如下步骤：
    步骤1、提供一像素单元，包括：阵列排布的多个子像素、多条平行间隔排列的水平的扫描线、以及多条平行间隔排列的竖直的数据线；
    每一行子像素对应一条扫描线，每一列子像素对应一条数据线，每一个子像素均包括：主区薄膜晶体管、次区薄膜晶体管、电荷共享薄膜晶体管、主区液晶电容以及次区液晶电容；
    设n和m均为正整数，在第n行第m列子像素中：所述主区薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第m条数据线，漏极电性连接主区液晶电容的一端；
    所述次区薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第m条数据线，漏极电性连接次区液晶电容的一端；
    所述电荷共享薄膜晶体管的栅极电性连接第n条扫描线，源极电性连接第n+1条扫描线，漏极电性连接次区液晶电容的一端；
    所述主区液晶电容与次区液晶电容的另一端均电性连接彩膜基板公共电压；
    步骤2、依次对各行子像素进行扫描；
    每一行子像素的扫描过程均为：设当前扫描的子像素行数为第n行，所述第n条扫描线提供高电位，所述第n+1条扫描线提供阵列基板公共电压，其余的扫描线均提供低电位，所述主区薄膜晶体管、次区薄膜晶体管、以及电荷共享薄膜晶体管均打开，所述主区薄膜晶体管为主区液晶电容充电，所述次区薄膜晶体管为次区液晶电容充电，所述电荷共享薄膜晶体管为次区液晶电容放电，使得次区液晶电容两端的电压低于所述主区液晶电容两端的电压；
    其中，所述主区液晶电容的一端为主区像素电极，另一端为彩膜基板公共电极；
    所述次区液晶电容的一端为次区像素电极，另一端为彩膜基板公共电极；
    其中，所述像素单元在驱动时的扫描方向为从第一行子像素向最后一行子像素进行扫描。
  12. 如权利要求11所述的像素单元的驱动方法，其中，所述主区像素电极与次区像素电极均为米字型结构，材料均为ITO。
  13. 如权利要求11所述的像素单元的驱动方法，其中，所述主区薄膜晶体管的栅极、次区薄膜晶体管的栅极、电荷共享薄膜晶体管的栅极、以及扫描线位于第一金属层，所述主区薄膜晶体管的源极和漏极、次区薄膜晶体管的源极和漏极、电荷共享薄膜晶体管的源极和漏极、以及数据线位于与所述第一金属层绝缘层叠的第二金属层。
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