WO2021000304A1 - 电容器及其制作方法 - Google Patents

电容器及其制作方法 Download PDF

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Publication number
WO2021000304A1
WO2021000304A1 PCT/CN2019/094619 CN2019094619W WO2021000304A1 WO 2021000304 A1 WO2021000304 A1 WO 2021000304A1 CN 2019094619 W CN2019094619 W CN 2019094619W WO 2021000304 A1 WO2021000304 A1 WO 2021000304A1
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WIPO (PCT)
Prior art keywords
conductive layer
layer
conductive
trench
substrate
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PCT/CN2019/094619
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English (en)
French (fr)
Inventor
陆斌
沈健
Original Assignee
深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2019/094619 priority Critical patent/WO2021000304A1/zh
Priority to EP19920625.1A priority patent/EP3783647B1/en
Priority to CN201980001219.4A priority patent/CN112449725B/zh
Priority to US17/027,184 priority patent/US11362171B2/en
Publication of WO2021000304A1 publication Critical patent/WO2021000304A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945—Trench capacitors

Definitions

  • This application relates to the field of capacitors, and more specifically, to capacitors and methods of making them.
  • Capacitors can play the role of bypassing, filtering, decoupling, etc. in the circuit, and are an indispensable part of ensuring the normal operation of the circuit.
  • MLCC Multi-layer Ceramic Capacitors
  • the embodiments of the present application provide a capacitor and a manufacturing method thereof, which can manufacture a capacitor with a small volume and a high capacitance value density.
  • a capacitor in a first aspect, includes:
  • the semiconductor substrate includes at least one substrate trench group, the substrate trench group enters the semiconductor substrate downward from the upper surface of the semiconductor substrate;
  • each stacked structure including n conductive layers and m dielectric layers, the first conductive layer of the n conductive layers is disposed above the semiconductor substrate and the substrate trench
  • the i-th conductive layer in the n-layer conductive layer is formed with an i-th conductive layer trench group
  • the i+1-th conductive layer in the n-layer conductive layer is disposed on the i-th conductive layer
  • the n-layer conductive layer and the m-layer dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, m, n, i are positive integers, and n ⁇ 2, 1 ⁇ i ⁇ n-1;
  • At least one first external electrode the first external electrode is electrically connected to a part of the conductive layer in the n-layer conductive layer;
  • At least one second external electrode is electrically connected to another part of the conductive layer in the n-layer conductive layer, and each conductive layer in the part of the conductive layer is adjacent to each other in the laminated structure
  • the conductive layer includes at least one conductive layer in the other part of the conductive layer.
  • the i-th conductive layer includes a film layer portion and a trench portion, and the i-th conductive layer trench group is disposed in the film portion of the i-th conductive layer without Into the trench portion of the i-th conductive layer.
  • the thickness of the film portion of the first conductive layer ranges from 10 nm to 20 ⁇ m.
  • the number and/or size of conductive layer trenches included in different conductive layers in the n-layer conductive layer are the same.
  • the number and/or size of the conductive layer trenches included in different conductive layers in the n-layer conductive layer are different.
  • multiple substrate trenches included in the substrate trench group are distributed in an array, and/or, multiple conductive layer trenches included in the i-th conductive layer trench group Distributed in an array.
  • the size of the plurality of substrate trenches included in the substrate trench group is smaller than a first threshold, and/or, the plurality of conductive layers included in the i-th conductive layer trench group The size of the layer trench is smaller than the second threshold.
  • the first threshold is equal to the second threshold.
  • each of the stacked structures includes a first conductive layer, a second conductive layer, a first dielectric layer, and a second dielectric layer; wherein,
  • the first dielectric layer is disposed between the semiconductor substrate and the first conductive layer, and the second dielectric layer is disposed between the first conductive layer and the second conductive layer between;
  • the first conductive layer includes the film layer portion and the groove portion, the first conductive layer is formed with a first conductive layer groove group, and the first conductive layer groove group is disposed in the The film portion of the first conductive layer does not enter the groove portion of the first conductive layer, and the second conductive layer is disposed above the first conductive layer and the first conductive layer Within a conductive layer trench group.
  • each of the laminated structures includes a first conductive layer, a second conductive layer, a third conductive layer, a first dielectric layer, a second dielectric layer, and a third dielectric layer.
  • Layer where,
  • the first dielectric layer is disposed between the semiconductor substrate and the first conductive layer, and the second dielectric layer is disposed between the first conductive layer and the second conductive layer In between, the third dielectric layer is disposed between the second conductive layer and the third conductive layer;
  • the first conductive layer includes the film layer portion and the groove portion, the first conductive layer is formed with a first conductive layer groove group, and the first conductive layer groove group is disposed in the The film portion of the first conductive layer does not enter the groove portion of the first conductive layer, and the second conductive layer is disposed above the first conductive layer and the first conductive layer In a conductive layer groove group;
  • the second conductive layer includes a film layer portion and a groove portion, the second conductive layer is formed with a second conductive layer groove group, and the second conductive layer groove group is disposed on the second layer conductive layer.
  • the film portion of the layer does not enter the trench portion of the second conductive layer, and the third conductive layer is disposed above the second conductive layer and in the trench group of the second conductive layer.
  • the i-th conductive layer includes a film layer portion and a trench portion, and the i-th conductive layer trench group is disposed on the film portion of the i-th conductive layer and the The groove part.
  • the set of substrate trenches includes at least one first substrate trench, and the second conductive layer of the n-layer conductive layer is also disposed in the first substrate trench .
  • the size of the first substrate trench is greater than the third threshold.
  • the set of substrate trenches further includes at least one second substrate trench disposed around the first substrate trench, and only the first substrate trench in the n-layer conductive layer A conductive layer is arranged in the second substrate trench.
  • the size of the second substrate trench is smaller than the size of the first substrate trench, and/or the depth of the second substrate trench is smaller than the first substrate trench. The depth of the bottom groove.
  • each of the stacked structures includes a first conductive layer, a second conductive layer, a first dielectric layer, and a second dielectric layer; wherein,
  • the first dielectric layer is disposed between the semiconductor substrate and the first conductive layer, and the second dielectric layer is disposed between the first conductive layer and the second conductive layer between;
  • the first conductive layer includes the film layer portion and the groove portion, the first conductive layer is formed with a first conductive layer groove group, and the first conductive layer groove group is disposed in the The film layer portion of the first conductive layer and the groove portion of the first conductive layer, the second conductive layer is disposed above the first conductive layer and the first conductive layer Layer groove group.
  • a stepped structure is provided in the laminated structure, and an etch stop layer formed of an insulating material is provided on the stepped structure, or an edge of the stepped structure is formed of an insulating material. Side wall.
  • the semiconductor substrate is formed of a material with a resistivity less than a threshold, or a heavily doped conductive layer or a conductive region with a resistivity less than the threshold is formed on the surface of the semiconductor substrate.
  • the conductive layer closest to the semiconductor substrate in the laminated structure is electrically connected to the first external electrode, and the semiconductor substrate is electrically connected to the second external electrode;
  • the conductive layer closest to the semiconductor substrate in the laminated structure is electrically connected to the second external electrode, and the semiconductor substrate is electrically connected to the first external electrode.
  • the capacitor further includes: an electrode layer disposed above the laminated structure, the electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other, so The first conductive area forms the first external electrode, and the second conductive area forms the second external electrode.
  • the first external electrode and/or the second external electrode are electrically connected to the conductive layer of the n-layer conductive layer through an interconnection structure.
  • the interconnection structure includes at least one insulating layer and a conductive via structure, and the conductive via structure penetrates the at least one insulating layer to electrically connect to the n-layer conductive layer. Conductive layer.
  • the first external electrode is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer
  • the second external electrode is electrically connected to all even-numbered conductive layers in the n-layer conductive layer.
  • Layer conductive layer is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer
  • different stacked structures in the at least one stacked structure share the same first external electrode, and/or different stacked structures share the same second external electrode.
  • the conductive layer includes at least one of the following:
  • the dielectric layer includes at least one of the following:
  • Silicon oxide layer silicon nitride layer, silicon oxynitride layer, metal oxide layer, metal nitride layer, metal oxynitride layer.
  • a method for manufacturing a capacitor including:
  • the substrate trench group Preparing at least one substrate trench group on the semiconductor substrate, the substrate trench group entering the semiconductor substrate downward from the upper surface of the semiconductor substrate;
  • each laminated structure includes n conductive layers and m dielectric layers, and the first conductive layer of the n conductive layers is disposed above the semiconductor substrate and the substrate trench In the groove group, the i-th conductive layer in the n-layer conductive layer is formed with an i-th conductive layer groove group, and the i+1-th conductive layer in the n-layer conductive layer is disposed on the i-th conductive layer.
  • the n-layer conductive layer and the m-layer dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, and m, n, and i are positive integers, and n ⁇ 2, 1 ⁇ i ⁇ n-1;
  • At least one first external electrode and at least one second external electrode are prepared, wherein the first external electrode is electrically connected to a portion of the n-layer conductive layer, and the second external electrode is electrically connected to the n
  • the other part of the conductive layer in the conductive layer, and the adjacent conductive layer of each conductive layer in the part of the conductive layer in the laminated structure includes at least one conductive layer in the other part of the conductive layer.
  • the i-th conductive layer includes a film layer portion and a trench portion, and the i-th conductive layer trench group is disposed in the film portion of the i-th conductive layer without Into the trench portion of the i-th conductive layer.
  • the thickness of the film portion of the first conductive layer ranges from 10 nm to 20 ⁇ m.
  • the number and/or size of conductive layer trenches included in different conductive layers in the n-layer conductive layer are the same.
  • the number and/or size of the conductive layer trenches included in different conductive layers in the n-layer conductive layer are different.
  • multiple substrate trenches included in the substrate trench group are distributed in an array, and/or, multiple conductive layer trenches included in the i-th conductive layer trench group Distributed in an array.
  • the size of the plurality of substrate trenches included in the substrate trench group is smaller than a first threshold, and/or, the plurality of conductive layers included in the i-th conductive layer trench group The size of the layer trench is smaller than the second threshold.
  • the first threshold is equal to the second threshold.
  • the laminated structure includes a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer;
  • the preparation of the laminated structure includes:
  • the first conductive layer is etched to form a first conductive layer trench group in the first conductive layer, and the first conductive layer trench group is disposed on the first conductive layer The portion of the film layer that does not enter the groove portion of the first conductive layer;
  • the second conductive layer is deposited on the upper surface and the inner surface of the second dielectric layer.
  • the i-th conductive layer includes a film layer portion and a trench portion, and the i-th conductive layer trench group is disposed on the film portion of the i-th conductive layer and the The groove part.
  • the set of substrate trenches includes at least one first substrate trench, and the second conductive layer of the n-layer conductive layer is also disposed in the first substrate trench .
  • the size of the first substrate trench is greater than the third threshold.
  • the set of substrate trenches further includes at least one second substrate trench disposed around the first substrate trench, and only the first substrate trench in the n-layer conductive layer A conductive layer is arranged in the second substrate trench.
  • the size of the second substrate trench is smaller than the size of the first substrate trench, and/or the depth of the second substrate trench is smaller than the first substrate trench. The depth of the bottom groove.
  • the laminated structure includes a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer;
  • the preparation of the laminated structure includes:
  • the first conductive layer is etched to form a first conductive layer trench group in the first conductive layer, and the first conductive layer trench group is disposed on the first conductive layer The film portion and the groove portion;
  • the second conductive layer is deposited on the upper surface and the inner surface of the second dielectric layer.
  • a stepped structure is provided in the laminated structure, and an etch stop layer formed of an insulating material is provided on the stepped structure, or an edge of the stepped structure is formed of an insulating material. Side wall.
  • the semiconductor substrate is formed of a material with a resistivity less than a threshold, or the surface of the semiconductor substrate is formed with a heavily doped conductive layer or a conductive region with a resistivity less than the threshold.
  • the conductive layer closest to the semiconductor substrate in the laminated structure is electrically connected to the first external electrode, and the semiconductor substrate is electrically connected to the second external electrode;
  • the conductive layer closest to the semiconductor substrate in the laminated structure is electrically connected to the second external electrode, and the semiconductor substrate is electrically connected to the first external electrode.
  • the preparing at least one first external electrode and at least one second external electrode includes:
  • An electrode layer is prepared above the laminated structure, the electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other, the first conductive region forms the first external electrode, and the second conductive region Two conductive regions form the second external electrode.
  • the method further includes:
  • An interconnection structure is prepared so that the first external electrode and/or the second external electrode are electrically connected to the conductive layer in the n-layer conductive layer through the interconnection structure.
  • the interconnection structure includes at least one insulating layer and a conductive via structure, and the conductive via structure penetrates the at least one insulating layer to be electrically connected to the n-layer conductive layer The conductive layer.
  • the first external electrode is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer
  • the second external electrode is electrically connected to all even-numbered conductive layers in the n-layer conductive layer.
  • Layer conductive layer is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer
  • different stacked structures in the at least one stacked structure share the same first external electrode, and/or different stacked structures share the same second external electrode.
  • trench capacitors are fabricated separately in the semiconductor substrate and the conductive layer, and the process of fabricating a single capacitor can be reused, which reduces the alignment accuracy requirements of the multilayer conductive layer, and can reduce the difficulty of the process. In this case, the capacitance density of the capacitor is further improved.
  • Fig. 1 is a schematic structural diagram of a capacitor provided by the present application.
  • Fig. 2 is a schematic structural diagram of a capacitor according to an embodiment of the present application.
  • Fig. 3 is a schematic structural diagram of another capacitor according to an embodiment of the present application.
  • Fig. 4 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 5 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 6 is a schematic structural diagram of a semiconductor substrate according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of yet another semiconductor substrate according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of still another semiconductor substrate according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of still another semiconductor substrate according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of an etching stop layer according to an embodiment of the present application.
  • Fig. 11 is a schematic structural diagram of a side wall according to an embodiment of the present application.
  • Fig. 12 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 13 is a schematic flowchart of a method for manufacturing a capacitor according to an embodiment of the present application.
  • FIGS. 14a to 14n are schematic diagrams of a manufacturing method of a capacitor according to an embodiment of the present application.
  • capacitors in the embodiments of the present application can perform functions such as bypassing, filtering, and decoupling in the circuit.
  • the capacitor described in the embodiments of the present application may be a 3D silicon capacitor, which is a new type of capacitor based on semiconductor wafer processing technology. Compared with traditional MLCC (Multilayer Ceramic Capacitors), 3D silicon capacitors have the advantages of small size, high precision, high stability, and long life.
  • the basic processing flow requires processing high-aspect-ratio deep holes (Via), trenches (Trench), pillars (Pillar), wall (Wall) and other 3D structures on the wafer or substrate first, and then in the 3D structure An insulating film and a low-resistivity conductive material are deposited on the surface to make the lower electrode, the dielectric layer and the upper electrode of the capacitor in sequence.
  • the existing 3D silicon capacitor generally adopts a multi-layer stacking technical solution, as shown in FIG. 1.
  • the capacitance density can be effectively improved.
  • the substrate 110 is a low-resistivity substrate
  • a trench 1 and a trench 2 are formed on the substrate 110
  • a first dielectric is deposited on the upper surface of the substrate 110, the trench 1 and the trench 2 Layer 120
  • a first conductive layer 130 is deposited on the upper and inner surfaces of the first dielectric layer 120
  • a second dielectric layer 140 is deposited on the upper and inner surfaces of the first conductive layer 130
  • the upper and inner surfaces of the second dielectric layer 140 are deposited
  • the capacitance of the capacitor formed by the substrate 110 and the first conductive layer 130 is C 1
  • the capacitance of the capacitor formed by the first conductive layer 130 and the second conductive layer 150 is C 2
  • the capacitor C 1 and the capacitor C 2 are formed in parallel.
  • the capacitance of the capacitor is C total , where,
  • the trench opening is relatively large, which results in a small number of trenches per unit area, thereby limiting the capacitance.
  • the capacitance of the vertically stacked capacitors gradually decreases, and the capacitance density gain brought by the multilayer conductive layer stack is actually limited.
  • the existing solutions are difficult to process, requiring strict control over the uniformity of deposition and etching, and precise multilayer alignment. As a result, the product yield is reduced.
  • this application proposes a new type of capacitor structure and manufacturing method, which can improve the capacitance density of the capacitor.
  • the capacitors in FIGS. 2 to 12 are only examples, and the number of laminated structures included in the capacitor is not limited to that shown in the capacitors in FIGS. 2 to 12, and can be determined according to actual needs.
  • the number of conductive layers and the number of dielectrics included in the laminated structure are just examples, and the number of conductive layers and the number of dielectric layers included in the laminated structure are not limited to those shown in the capacitors in FIGS. 2 to 12, Set flexibly according to actual needs.
  • FIG. 2 is a possible structure diagram of a capacitor 200 according to an embodiment of the present application.
  • the capacitor 200 includes a semiconductor substrate 210, at least one stacked structure 220, at least one first external electrode 230, and at least one second external electrode 240.
  • the semiconductor substrate 210 includes at least one substrate trench group 10, and the substrate trench group 10 enters the semiconductor substrate 210 downward from the upper surface of the semiconductor substrate 210.
  • a semiconductor substrate 210; the laminated structure 220 includes an n-layer conductive layer and an m-layer dielectric layer, and the first conductive layer of the n-layer conductive layer is disposed above the semiconductor substrate 210 and in the substrate trench group 10 ,
  • the i-th conductive layer in the n-layer conductive layer is formed with the i-th conductive layer trench group 20, and the i+1-th conductive layer in the n-layer conductive layer is disposed above the i-th conductive layer and the In the i-th conductive layer trench group 20, the n-layer conductive layer and the m-layer dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, m, n, and i are positive integers, and n ⁇ 2, 1 ⁇ i ⁇ n
  • the substrate trench group 10 may include multiple substrate trenches, and the i-th conductive layer trench group 20 may include multiple conductive layer trenches.
  • the cross-sectional shapes of different substrate trenches in the plurality of substrate trenches in the substrate trench group 10 may be the same or different.
  • FIG. 2 in the embodiment of the present application is a cross section along the longitudinal direction of the substrate.
  • the depth and width of the substrate trench included in the substrate trench group 10 can be flexibly set according to actual needs.
  • the substrate trenches included in the substrate trench group 10 have a high aspect ratio (High aspect ratio).
  • the depth and width of the plurality of conductive layer trenches included in the i-th conductive layer trench group 20 can be flexibly set according to actual needs.
  • the plurality of conductive layer trenches included in the i-th conductive layer trench group 20 have a high aspect ratio.
  • the substrate trenches included in the substrate trench group 10 may be holes with a small difference in cross-sectional length and width, or may also have a difference in length and width. Larger grooves, or may also be columnar (Pillar) or wall (Wall) 3D structure.
  • the plurality of conductive layer trenches included in the i-th conductive layer trench group 20 may be holes with a small difference in cross-sectional length and width, or may also be trenches with a large difference in length and width. , Or can also be columnar or wall-shaped 3D structure.
  • the cross-section can be understood as a cross-section parallel to the surface of the semiconductor substrate 210, while in FIG. 2 it is a cross-section along the longitudinal direction of the semiconductor substrate 210.
  • two adjacent conductive layers in the n-layer conductive layer are electrically isolated by a dielectric layer, and the specific values of m and n can be flexibly configured according to actual needs.
  • the two adjacent conductive layers are electrically isolated.
  • a dielectric layer needs to be provided between the first conductive layer in the stacked structure 220 and the semiconductor substrate 210 to isolate the first conductive layer.
  • external electrodes in the embodiments of the present application may also be referred to as pads or external pads.
  • trench capacitors are fabricated separately in the semiconductor substrate and the conductive layer, and the process of fabricating a single capacitor can be reused, reducing the alignment accuracy requirements of the multilayer conductive layer, and can without increasing the process difficulty. Further improve the capacitance density of the capacitor.
  • the semiconductor substrate 210 may be a silicon wafer, including monocrystalline silicon, polycrystalline silicon, and amorphous silicon.
  • the semiconductor substrate 210 may also be other semiconductor substrates, including SOI wafers, silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs) and other III-V compound semiconductor wafers; Or a glass substrate; or an organic polymer substrate; or a substrate with an epitaxial layer, an oxide layer, a doped layer, or a bonding layer on the surface.
  • the thickness of the semiconductor substrate 210 can also be flexibly set according to actual needs.
  • the semiconductor substrate 210 can be The substrate 210 is thinned.
  • the material of the first external electrode 230 and the second external electrode 240 may be metal, such as copper, aluminum, or the like.
  • the first external electrode 230 and the second external electrode 240 may also include low resistivity Ti, TiN, Ta, TaN layers as adhesion layers and/or barrier layers; they may also include some metal layers on the surface of the external electrodes, such as Ni, Pd (palladium), Au, Sn (tin), Ag are used for subsequent wire bonding or welding processes.
  • the conductive layer includes at least one of the following:
  • the material of the conductive layer in the laminated structure 220 may be heavily doped polysilicon, silicide, carbon, conductive polymer, aluminum (Al), tungsten (W), copper (Cu) , Titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh), nickel (Ni) and other metals, tantalum nitride (TaN), titanium nitride (TiN) ), titanium aluminum nitride (TiAlN), tantalum silicon nitride (TaSiN), tantalum carbon nitride (TaCN) and other low-resistivity compounds, or a combination of the above materials, and a laminated structure.
  • the conductive layer in the laminated structure 220 may also include some other conductive materials, which is not limited in the embodiment of the present application.
  • the dielectric layer includes at least one of the following:
  • Silicon oxide layer silicon nitride layer, silicon oxynitride layer, metal oxide layer, metal nitride layer and metal oxynitride layer.
  • the specific insulation material and layer thickness can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor.
  • the dielectric layer in the stacked structure 220 may also include some other insulating materials, which is not limited in the embodiment of the present application.
  • the order of the m-layer dielectric layer is as follows: on the semiconductor substrate 210, the distance from the semiconductor substrate 210 is ascending.
  • the order of the n-layer conductive layer is as follows: on the semiconductor substrate 210, the distance from the semiconductor substrate 210 is from small to large.
  • each of the at least one stacked structure 220 may correspond to at least one first external electrode 230 and at least one second external electrode 240.
  • the first external electrode 230 is electrically connected to a part of the conductive layer in the n-layer conductive layer; the second external electrode 240 is electrically connected to another conductive layer in the n-layer conductive layer.
  • a part of the conductive layer, and each conductive layer of the part of the conductive layer adjacent to the conductive layer in the laminated structure 220 includes at least one conductive layer of the other part of the conductive layer. Therefore, for different first external electrodes 230 and second external electrodes 240, the stacked structure 220 can form capacitors with different capacitances.
  • the capacitor 200 includes a laminated structure, denoted as laminated structure 1, and includes two first external electrodes and two second external electrodes, and the two first external electrodes are respectively referred to as first external electrodes.
  • a and the first external electrode B, the two second external electrodes are respectively denoted as the second external electrode C and the second external electrode D
  • the laminated structure 1 includes 5 conductive layers, 4 dielectric layers, and 5 conductive layers They are denoted as conductive layer 1, conductive layer 2, conductive layer 3, conductive layer 4, and conductive layer 5, respectively.
  • the four dielectric layers are denoted as dielectric layer 1, dielectric layer 2, dielectric layer 3, and dielectric layer 4, respectively.
  • first external electrode A is electrically connected to the conductive layer 1 and the conductive layer 3
  • first external electrode B is electrically connected to the conductive layer 1
  • second external electrode C is electrically connected
  • the second external electrode D is also electrically connected to the conductive layer 2 and the conductive layer 4.
  • the conductive Layer 1 and the conductive layer 2 form a capacitor 1
  • the capacitance value is denoted as C1
  • the conductive layer 2 and the conductive layer 3 form a capacitor 2
  • the capacitance value is denoted as C2
  • the conductive layer 3 and the conductive layer 4 form a capacitor 3
  • the capacitance The value is denoted as C3, capacitor 1
  • capacitor 2 and capacitor 3 are connected in parallel
  • the capacitor corresponding to D, the conductive layer 1 and the conductive layer 2 form a capacitor 1, the capacitance value is denoted as C1, the conductive layer 2 and the conductive layer 3 form a capacitor 2, the capacitance value is denoted as C2, the conductive layer 3 and the conductive layer Layer 4 forms a capacitor 3, the capacitance value is denoted as C3, the conductive layer 4 and the
  • the capacitors corresponding to the first external electrode A and the second external electrode D can also form a similar series-parallel structure, and the capacitors corresponding to the first external electrode B and the second external electrode C can also be similar.
  • the series-parallel structure will not be repeated here. Therefore, the laminated structure 1 can form capacitors with different capacitances.
  • first external electrode A is electrically connected to the conductive layer 1 and the conductive layer 5
  • first external electrode B is electrically connected to the conductive layer 3 and the conductive layer 5
  • second external electrode C is electrically connected to the conductive layer 2 and
  • the conductive layer 4 and the second external electrode D are also electrically connected to the conductive layer 4.
  • the conductive layer 1 and the conductive layer 2 form a capacitor 1
  • the capacitance is denoted as C1
  • the conductive layer 2 and the conductive layer 4 form a capacitor 2
  • the capacitance is denoted as C2
  • the capacitor 1 and the capacitor 2 are in parallel
  • the conductive layer 3 and the conductive layer 4 form a capacitor 3
  • the capacitance value is denoted as C3
  • the conductive layer 4 and the conductive layer 5 form
  • the capacitors corresponding to the first external electrode A and the second external electrode D can also form a similar series-parallel structure, and the capacitors corresponding to the first external electrode B and the second external electrode C can also be similar.
  • the series-parallel structure will not be repeated here. Therefore, the laminated structure 1 can form capacitors with different capacitances.
  • each first external electrode 230 in the at least one first external electrode 230 is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer; each second external electrode 230 in the at least one second external electrode 240 The electrode 240 is electrically connected to all even-numbered conductive layers in the n-layer conductive layer.
  • the capacitor 200 includes a laminated structure, denoted as laminated structure 2, and includes two first external electrodes and two second external electrodes, and the two first external electrodes are respectively denoted as first external electrodes.
  • a and the first external electrode B, the two second external electrodes are respectively denoted as the second external electrode C and the second external electrode D
  • the laminated structure 2 includes 5 conductive layers, 4 dielectric layers, and 5 conductive layers They are denoted as conductive layer 1, conductive layer 2, conductive layer 3, conductive layer 4, and conductive layer 5, respectively.
  • the four dielectric layers are denoted as dielectric layer 1, dielectric layer 2, dielectric layer 3, and dielectric layer 4, respectively.
  • the first external electrode A is electrically connected to the conductive layer 1, the conductive layer 3 and the conductive layer 5, the first external electrode B is also electrically connected to the conductive layer 1, the conductive layer 3 and the conductive layer 5.
  • Two external electrodes C are electrically connected to the conductive layer 2 and the conductive layer 4, and the second external electrode D is also electrically connected to the conductive layer 2 and the conductive layer 4, then for the first external electrode A and the second external electrode C
  • the conductive layer 1 and the conductive layer 2 form a capacitor 1
  • the capacitance value is denoted as C1
  • the conductive layer 2 and the conductive layer 3 form a capacitor 2
  • the capacitance value is denoted as C2
  • the conductive layer 3 and the conductive layer 4 forms a capacitor 3
  • the capacitance value is denoted as C3
  • the conductive layer 4 and the conductive layer 5 form a capacitor 4
  • the capacitance value is denoted as C4
  • the capacitors corresponding to the first external electrode A and the second external electrode D can also form a similar series-parallel structure, and the capacitors corresponding to the first external electrode B and the second external electrode C can also be similar.
  • the series-parallel structure will not be repeated here.
  • different stacked structures in the at least one stacked structure 220 can share the same first external electrode 230, and/or different stacked structures can share the same second external electrode 240.
  • different stacked structures in the at least one stacked structure 220 may not share any external electrodes, which is not limited in the embodiment of the present application.
  • a first external electrode 230 may be electrically connected to a part or all of the at least one laminated structure 220.
  • a second external electrode 240 may also be electrically connected. It is connected to part or all of the at least one stacked structure 220.
  • the capacitor 200 includes three stacked structures, a first external electrode P, a second external electrode Q, and a second external electrode Z.
  • the three stacked structures are denoted as stacked structure A and stacked structure B, respectively.
  • the first external electrode P is electrically connected to all odd-numbered conductive layers of the laminated structure A and all odd-numbered conductive layers of the laminated structure B
  • the second external electrode Q is electrically connected to all the even-numbered layers of the laminated structure A Conductive layer
  • the second external electrode Z is electrically connected to all even-numbered conductive layers of the laminated structure B
  • the first external electrode P and the second external electrode Q form an equivalent capacitor 1
  • the capacitance value is denoted as C1
  • the The first external electrode P and the second external electrode Z form an equivalent capacitor 2
  • the capacitance is denoted as C2.
  • the i-th conductive layer includes a film layer portion 30 and a trench portion 40, and the i-th conductive layer trench group 20 is disposed in the film portion of the i-th conductive layer 30 and does not enter the trench portion 40 of the i-th conductive layer.
  • the laminated structure 220 may include two conductive layers, such as the first conductive layer 221 and the second conductive layer shown in FIG. 2 222, and two dielectric layers, such as the first dielectric layer 223 and the second dielectric layer 224 shown in FIG. 2.
  • the first dielectric layer 223 is disposed between the semiconductor substrate 210 and the first conductive layer 221
  • the second dielectric layer 224 is disposed between the first conductive layer 221 and the second conductive layer 222 between. As shown in FIG.
  • the first conductive layer 221 includes a film layer portion 30 and a trench portion 40, the first conductive layer 221 is formed with a first conductive layer trench group 20, and the first conductive layer trench group 20 is disposed on the film portion 30 of the first conductive layer 221 and does not enter the trench portion 40 of the first conductive layer.
  • the laminated structure 220 may include three conductive layers, such as the first conductive layer 221 and the second conductive layer shown in FIG.
  • the first dielectric layer 224 is disposed between the semiconductor substrate 210 and the first conductive layer 221
  • the second dielectric layer 225 is disposed between the first conductive layer 221 and the second conductive layer 222
  • the third dielectric layer 226 is disposed between the second conductive layer 222 and the third conductive layer 223.
  • the first conductive layer 221 includes a film layer portion 30 and a trench portion 40, the first conductive layer 221 is formed with a first conductive layer trench group 20, and the first conductive layer trench group 20 is disposed on the film portion 30 of the first conductive layer 221 and does not enter the trench portion 40 of the first conductive layer;
  • the second conductive layer 222 includes the film portion 30 and the trench portion 40, the second The conductive layer 222 is formed with a second conductive layer trench group 20, and the second conductive layer trench group 20 is disposed on the film portion 30 of the second conductive layer 222 and does not enter the trench of the second conductive layer ⁇ 40 ⁇ Slot section 40.
  • the thickness of the film portion of the first conductive layer 221 ranges from 10 nm to 20 ⁇ m.
  • the thickness of the film portions of different conductive layers in the n-layer conductive layer may be the same or different.
  • the number and/or size of the conductive layer trenches included in different conductive layers in the n-layer conductive layer are the same.
  • the number and/or size of the conductive layer trenches included in different conductive layers in the n-layer conductive layer may also be different.
  • a plurality of substrate trenches included in the substrate trench group 10 are distributed in an array, and/or, the i-th conductive layer trench group
  • the plurality of conductive layer trenches included in 20 are distributed in an array.
  • the size of the plurality of substrate trenches included in the substrate trench group 10 is smaller than a first threshold, and/or, the i-th conductive layer
  • the size of the plurality of conductive layer trenches included in the trench group 20 is smaller than the second threshold.
  • the first threshold is equal to the second threshold, for example, the first threshold may be 1 ⁇ m, and the second threshold may also be 1 ⁇ m. Therefore, the plurality of substrate trenches and the plurality of conductive layer trenches may use the same etching parameters to reduce the difficulty of manufacturing the capacitor.
  • the first threshold may also be greater than or less than the second threshold, that is, the multiple substrate trenches may be individually set with countable parameters.
  • the i-th conductive layer includes a film layer portion 30 and a trench portion 40, and the i-th conductive layer trench group 20 is disposed in the film portion of the i-th conductive layer 30 and the groove portion 40.
  • the laminated structure 220 may include two conductive layers, such as the first conductive layer 221 and the second conductive layer shown in FIG. 4 222, and two dielectric layers, such as the first dielectric layer 223 and the second dielectric layer 224 shown in FIG. 4.
  • the first dielectric layer 223 is disposed between the semiconductor substrate 210 and the first conductive layer 221
  • the second dielectric layer 224 is disposed between the first conductive layer 221 and the second conductive layer 222 between. As shown in FIG.
  • the first conductive layer 221 includes a film layer portion 30 and a trench portion 40, the first conductive layer 221 is formed with a first conductive layer trench group 20, and the first conductive layer trench group 20 is provided on the film portion 30 and the trench portion 40 of the first conductive layer 221.
  • the substrate trench group 10 includes at least one first substrate trench 11, and the second conductive layer of the n-layer conductive layer is also disposed in the first substrate trench Within 11.
  • the size of the first substrate trench is greater than the third threshold.
  • the third threshold may be 100 nm.
  • the substrate trench group 10 further includes at least one second substrate trench 12 disposed around the first substrate trench 11, and only the n-layer conductive layer The first conductive layer is disposed in the second substrate trench 12.
  • the first conductive layer is disposed in the second substrate trench 12 to increase the capacitance of the capacitor formed by the semiconductor substrate 210 and the first conductive layer 221.
  • the size of the second substrate trench 12 is smaller than the size of the first substrate trench 11, and/or the depth of the second substrate trench 12 is smaller than that of the first substrate trench 11 depth.
  • the second substrate trench 12 can be formed by etching simultaneously with the first substrate trench 11 to reduce the etching process.
  • the conductive layers in different stacked structures in the at least one stacked structure 220 may be in an electrically isolated state, as shown in FIGS. 2 and 3; the at least one stacked layer The conductive layers in the different laminated structures in the structure 220 may also be in an electrical connection state, as shown in FIGS. 4 and 5.
  • the semiconductor substrate 210 is formed of a material with a resistivity less than a threshold, or the surface of the semiconductor substrate 210 is formed with a heavily doped conductive layer or a conductive region with a resistivity less than the threshold. . That is, the semiconductor substrate 210 is conductive, or the region of the semiconductor substrate 210 that is in contact with the stacked structure 220 is conductive.
  • the semiconductor substrate 210 is formed of a material with a resistivity less than the threshold, it can be considered that the semiconductor substrate 210 is a heavily doped low resistivity substrate; the surface of the semiconductor substrate 210 is formed with a heavily doped resistor.
  • a conductive layer with a rate less than the threshold can be considered as a heavily doped low-resistivity conductive layer formed on the surface of the semiconductor substrate 210; a conductive region with a heavily doped resistivity less than the threshold is formed on the surface of the semiconductor substrate 210.
  • the surface of the semiconductor substrate 210 is formed with a heavily doped low-resistivity conductive region.
  • the semiconductor substrate 210 is a heavily doped low-resistivity substrate, and the at least one substrate trench group 10 is disposed in the semiconductor substrate 210.
  • a heavily doped low-resistivity conductive layer is formed on the upper surface of the semiconductor substrate 210 and the inner surface of the at least one substrate trench group 10.
  • a heavily doped low-resistivity conductive region is formed on the surface of the semiconductor substrate 210, and the at least one substrate trench group 10 is disposed in the conductive region.
  • a material with a resistivity less than the threshold can be considered as a conductive material.
  • the semiconductor substrate 210 in the stacked structure 220 is electrically connected to the first external electrode 230, then the semiconductor substrate 210 is electrically connected to the second external electrode 240.
  • the semiconductor substrate 210 is electrically connected to the first external electrode 230.
  • the conductive layer closest to the semiconductor substrate 210 in the laminated structure 220 is electrically connected to the first external electrode 230, and the semiconductor substrate 210 is electrically connected to the second external electrode 240.
  • the first external electrode 230 and/or the second external electrode 240 are electrically connected to the conductive layer in the n-layer conductive layer through the interconnection structure 250.
  • the interconnection structure 250 includes at least one insulating layer 251 and a conductive via structure 252, and the conductive via structure 252 penetrates the at least one insulating layer 251 to electrically connect the conductive layers in the n-layer conductive layer. As shown in FIGS. 2 to 5, the interconnect structure 250 is disposed above the laminated structure 220.
  • the at least one insulating layer 251 may also be referred to as an intermetal dielectric layer (IMD) or an interlayer dielectric layer (ILD).
  • the conductive via structure 252 may also be referred to as a conductive channel.
  • the at least one insulating layer 251 covers the laminated structure 220, and the at least one insulating layer 251 can fill the cavity or gap formed in the laminated structure 220 to improve the structural integrity and integrity of the capacitor. Mechanical stability.
  • the material of the at least one insulating layer 251 may be an organic polymer material, including polyimide, Parylene, benzocyclobutene (BCB), etc.; or Some inorganic materials, including spin-on glass (SOG), undoped silicon glass (USG), boro-silicate glass (BSG), phosphor-silicate glass (phospho-silicate glass, PSG), boro-phospho-silicate glass (BPSG), silicon oxide synthesized from Tetraethyl Orthosilicate (TEOS), silicon oxide, nitride, ceramic; it can also be the above materials A combination or stack of layers.
  • SOG spin-on glass
  • USG undoped silicon glass
  • BSG boro-silicate glass
  • phosphor-silicate glass phospho-silicate glass
  • PSG boro-phospho-silicate glass
  • BPSG boro-phospho-silicate glass
  • the material of the conductive via structure 252 may be made of a low-resistivity conductive material, such as heavily doped polysilicon, tungsten, Ti, TiN, Ta, TaN.
  • the shape and number of the conductive via structure 252 may be specifically determined according to the manufacturing process of the capacitor 200, which is not limited in the embodiment of the present application.
  • the stacked structure 220 is provided with a step structure, and the step structure is provided with an etch stop layer 50 formed of an insulating material, as shown in FIG. 10, or the step structure A side wall 51 made of insulating material is provided at the edge, as shown in FIG. 11.
  • the etch stop layer 50 may be one of the aforementioned at least one insulating layer 251.
  • the side wall 51 may be one or a part of the at least one insulating layer 251 described above.
  • the etch stop layer 50 is more resistant to etching than other insulating layers in the at least one insulating layer 251.
  • the bottom of the conductive via structure 252 can stay at a different position.
  • a dry or wet process is used to remove part of the etch stop layer 50 exposed at the bottom of the conductive via structure 252 so that the conductive via structure 252 penetrates the etch stop layer 50.
  • the etch stop layer 50 provided on the step structure can enhance the electrical insulation between adjacent conductive layers in the stacked structure 220, and strengthen the first conductive layer and the conductive layer in the stacked structure 220. Electrical insulation between the semiconductor substrates 210.
  • the sidewall 51 formed of insulating material is arranged at the edge of the step structure to enhance the electrical insulation between adjacent conductive layers in the laminated structure 220, and to enhance the conductivity of the first layer in the laminated structure 220. The electrical insulation between the layer and the semiconductor substrate 210.
  • the etch stop layer 50 or the sidewall 51 may be silicon oxide, silicon nitride, or silicon-containing glass (Undoped Silicon Glass (Undoped Silicon Glass)) deposited by a chemical vapor deposition (Chemical Vapor Deposition, CVD) process.
  • Glass, USG boro-silicate glass (BSG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG); it can also be atomic layer deposition ( Atomic layer deposition (ALD) deposited alumina; or sprayed, spin-coated spin-on glass (SOG), polyimide (Polyimide), etc.; it can also be a combination of the above materials.
  • the at least one first external electrode 230 and the at least one second external electrode 240 are disposed above the laminated structure 220.
  • the capacitor 200 further includes: an electrode layer disposed above the laminated structure 220, the electrode layer including at least one first conductive region and at least one second conductive region that are separated from each other, and the first conductive region forms The first external electrode 230 and the second conductive area form the second external electrode 240, as shown in FIGS. 2 to 5. That is, the at least one first external electrode 230 and the at least one second external electrode 240 can be formed by one etching, which reduces the etching steps.
  • the electrode layer is disposed above the interconnect structure 250, and the first external electrode 230 is electrically connected to the semiconductor substrate 210 and the stacked structure through the conductive via structure 252
  • the even-numbered conductive layers in 220, the second external electrode 240 is electrically connected to the odd-numbered conductive layers in the stacked structure 220 through the conductive via structure 252.
  • the semiconductor substrate 210 may not be provided with the at least one substrate trench group 10, that is, the first conductive layer of the n-layer conductive layer is provided on the semiconductor substrate 210.
  • the semiconductor substrate 210 may not be provided with the at least one substrate trench group 10, that is, the first conductive layer of the n-layer conductive layer is provided on the semiconductor substrate 210.
  • Figure 12 As shown in Figure 12.
  • trench capacitors are fabricated separately in the semiconductor substrate and the conductive layer, and the process of fabricating a single capacitor can be reused, which reduces the alignment accuracy requirements of the multilayer conductive layer, and can be used without increasing the difficulty of the process. Further improve the capacitance density of the capacitor.
  • the capacitors of the embodiments of the present application are described above, and the method for preparing the capacitors of the embodiments of the present application is described below.
  • the method for preparing a capacitor of the embodiment of the present application can prepare the capacitor of the foregoing embodiment of the present application, and the following embodiments and related descriptions in the foregoing embodiments may refer to each other.
  • FIG. 13 is a schematic flowchart of a method for manufacturing a capacitor according to an embodiment of the present application, but these steps or operations are only examples, and the embodiment of the present application may also perform other operations or modifications of each operation in FIG. 13.
  • FIG. 13 shows a schematic flowchart of a method 300 for manufacturing a capacitor according to an embodiment of the present application. As shown in FIG. 13, the manufacturing method 300 of the capacitor includes:
  • Step 310 preparing at least one substrate trench group on the semiconductor substrate, the substrate trench group entering the semiconductor substrate downward from the upper surface of the semiconductor substrate;
  • Step 320 preparing at least one stacked structure, each stacked structure including n conductive layers and m dielectric layers, and the first conductive layer of the n conductive layers is disposed above the semiconductor substrate and the substrate trench
  • the i-th conductive layer in the n-layer conductive layer is formed with an i-th conductive layer trench group
  • the i+1-th conductive layer in the n-layer conductive layer is arranged above the i-th conductive layer
  • the n conductive layer and the m dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, m, n, i are positive integers, and n ⁇ 2, 1 ⁇ i ⁇ n-1;
  • Step 330 preparing at least one first external electrode and at least one second external electrode, wherein the first external electrode is electrically connected to a portion of the n-layer conductive layer, and the second external electrode is electrically connected to the n-layer
  • the other part of the conductive layer in the conductive layer, and the adjacent conductive layer of each conductive layer in the part of the conductive layer in the laminated structure includes at least one conductive layer in the other part of the conductive layer.
  • the capacitors shown in FIGS. 2 to 5 can be prepared based on the above steps 310-330.
  • each material layer in steps 310-330 refers to the surface substantially parallel to the upper surface of the substrate, and the inner surface of each material layer refers to the upper surface of the material layer in the trench.
  • the upper surface and the inner surface can be regarded as a whole.
  • the depth of the substrate trench group 10 is less than the thickness of the semiconductor substrate 210. That is, the substrate trench group 10 does not penetrate the semiconductor substrate 210.
  • the above step 310 may use photolithography and deep reactive ion etching processes to form the at least one substrate trench group 10 on the semiconductor substrate 210.
  • the substrate trenches included in the substrate trench group 10 may be one or more of vias, trenches, pillars, and walls.
  • the above step 310 may prepare at least one substrate trench group 10 as shown in FIG. 14a on the semiconductor substrate 210, or at least one substrate trench group 10 as shown in FIG. 14b on the semiconductor substrate 210.
  • at least one substrate trench group 10 as shown in FIG. 14c can also be prepared on the semiconductor substrate 210.
  • a capacitor prepared based on at least one substrate trench group 10 shown in FIG. 14a may at least include but not limited to the following features:
  • the i-th conductive layer includes a film layer portion 30 and a groove portion 40.
  • the i-th conductive layer groove set 20 is disposed in the film portion 30 of the i-th conductive layer and does not enter the i-th conductive layer.
  • the thickness of the film portion of the first conductive layer ranges from 10 nm to 20 ⁇ m;
  • the number and/or size of the conductive layer trenches included in different conductive layers in the n-layer conductive layer are the same.
  • the number and/or size of the conductive layer trenches included in different conductive layers in the n-layer conductive layer may also be different;
  • the plurality of substrate trenches included in the substrate trench group 10 are distributed in an array, and/or, the plurality of conductive layer trenches included in the i-th conductive layer trench group 20 are distributed in an array;
  • the size of the plurality of substrate trenches included in the substrate trench group 10 is smaller than the first threshold, and/or the size of the plurality of conductive layer trenches included in the i-th conductive layer trench group 20 is smaller than the second Threshold.
  • the first threshold may be 1 ⁇ m
  • the second threshold may also be 1 ⁇ m.
  • a capacitor prepared based on at least one substrate trench group 10 as shown in FIGS. 14b and 14c may at least include but not limited to the following features:
  • the i-th conductive layer includes a film layer portion 30 and a trench portion 40, and the i-th conductive layer trench group 20 is disposed on the film portion 30 and the trench portion 40 of the i-th conductive layer;
  • the substrate trench group 10 includes at least one first substrate trench 11, and the second conductive layer of the n-layer conductive layer is also disposed in the first substrate trench 11;
  • the size of the first substrate trench is greater than a third threshold, for example, the third threshold may be 100 nm;
  • the substrate trench group 10 further includes at least one second substrate trench 12 disposed around the first substrate trench 11, and only the first conductive layer of the n-layer conductive layer is disposed on the second substrate trench 11 In the substrate trench 12.
  • the semiconductor substrate 210 is formed of a material with a resistivity less than a threshold, or the surface of the semiconductor substrate 210 is formed with a heavily doped conductive layer or a conductive region with a resistivity less than the threshold.
  • the semiconductor substrate 210 may be as shown in FIGS. 6-9.
  • the semiconductor substrate 210 is electrically connected to the second external electrode 240.
  • the semiconductor substrate 210 is electrically connected to the first external electrode 230.
  • the semiconductor substrate 210 is formed of a material with a resistivity less than a threshold value as an example for description.
  • the foregoing step 330 may specifically be: preparing an electrode layer above the laminated structure 220, the electrode layer including at least one first conductive region and at least one second conductive region that are separated from each other, and the first conductive region forms the The first external electrode 230, and the second conductive area forms the second external electrode 240.
  • the method 300 further includes:
  • the interconnection structure 250 is prepared so that the first external electrode 230 and/or the second external electrode 240 are electrically connected to the conductive layer of the n-layer conductive layer through the interconnection structure 250.
  • the interconnect structure 250 includes at least one insulating layer 251 and a conductive via structure 252, and the conductive via structure 252 penetrates the at least one insulating layer 251 to be electrically connected to the conductive layer in the n-layer conductive layer .
  • the stacked structure 220 is provided with a stepped structure, and an etch stop layer 50 formed of an insulating material is provided on the stepped structure, as shown in FIG. 10, or an edge of the stepped structure is provided with an insulating material.
  • the formed side wall 51 is shown in FIG. 11.
  • the etch stop layer 50 may be one of the above-mentioned at least one insulating layer 251.
  • the side wall 51 may be one or a part of the at least one insulating layer 251 described above.
  • the first external electrode 230 is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer
  • the second external electrode 240 is electrically connected to all even-numbered conductive layers in the n-layer conductive layer.
  • different stacked structures in the at least one stacked structure 220 share the same first external electrode 230, and/or different stacked structures share the same second external electrode 240.
  • the laminated structure 220 includes: a first conductive layer 221, a second conductive layer 222, a first dielectric layer 223, and a Two dielectric layers 224.
  • the capacitor 200 as shown in FIG. 2 can be prepared in the following manner:
  • the first dielectric layer 223 is deposited on the upper surface of the semiconductor substrate 210 and the inner surface of the substrate trench group 10, and then, on the upper surface of the first dielectric layer 223
  • the first conductive layer 221 is deposited on the upper surface and the inner surface, as shown in FIG. 14d.
  • the first conductive layer 221 is etched to form a first conductive layer trench group 20 in the first conductive layer 221, and the first conductive layer trench group 20 is disposed on the first layer.
  • the film portion 30 of the conductive layer 221 does not enter the trench portion 40 of the first conductive layer 221, as shown in FIG. 14e.
  • the second dielectric layer 224 is deposited on the upper surface of the first conductive layer 221 and the inner surface of the first conductive layer trench group 20, and on the upper and inner surfaces of the second dielectric layer 224
  • the second conductive layer 222 is shown in FIG. 14f.
  • a photolithography process is used to perform multi-step photolithography to form a stepped structure in the stacked structure 220, as shown in FIG. 14g.
  • an insulating layer 251 is deposited on the stacked structure 220, and the insulating layer 251 covers the stacked structure 220.
  • a photolithography process is used to deposit the corresponding semiconductor substrate 210, the first conductive layer 221, The position of the second conductive layer 222 opens a number of vias 60 penetrating the insulating layer 251, as shown in FIG. 14h, and then a conductive material is deposited in the vias 60 to form a conductive via structure 252, as shown in FIG. 14i Shown.
  • the insulating layer 251 and the conductive via structure 252 constitute the interconnect structure 250.
  • an electrode layer is deposited on the upper surface of the interconnect structure 250, and a plurality of external electrodes are formed by photolithography, so that the capacitor 200 as shown in FIG. 2 is prepared.
  • the capacitor 200 as shown in FIG. 4 can be prepared in the following manner:
  • the first dielectric layer 223 is deposited on the upper surface of the semiconductor substrate 210 and the inner surface of the substrate trench group 10, and then, on the upper surface of the first dielectric layer 223
  • the first conductive layer 221 is deposited on the upper surface and the inner surface, as shown in FIG. 14j.
  • the first conductive layer 221 is etched to form a first conductive layer trench group 20 in the first conductive layer 221, and the first conductive layer trench group 20 is disposed on the first layer.
  • the film portion 30 and the trench portion 40 of the conductive layer 221 are as shown in FIG. 14k.
  • the second dielectric layer 224 is deposited on the upper surface of the first conductive layer 221 and the inner surface of the first conductive layer trench group 20, and on the upper and inner surfaces of the second dielectric layer 224
  • the second conductive layer 222 is shown in FIG. 14l.
  • a photolithography process is used to perform multi-step photolithography to form a step structure in the stacked structure 220, as shown in FIG. 14m.
  • an insulating layer 251 is deposited on the stacked structure 220, and the insulating layer 251 covers the stacked structure 220.
  • a photolithography process is used to deposit the corresponding semiconductor substrate 210, the first conductive layer 221, The position of the second conductive layer 222 opens a number of via holes 60 penetrating the insulating layer 251, and then a conductive material is deposited in the via holes 60 to form a conductive via structure 252, the insulating layer 251 and the conductive via hole
  • the structure 252 constitutes the interconnect structure 250, as shown in FIG. 14n.
  • an electrode layer is deposited on the upper surface of the interconnect structure 250, and a plurality of external electrodes are formed by photolithography, thereby fabricating the capacitor 200 as shown in FIG. 4.
  • the method for preparing the capacitor 200 as shown in FIG. 4 can be referred to, and the preparation as shown in FIG.
  • the description of the capacitor 200 is omitted here.
  • the process of manufacturing a single capacitor can be reused, reducing the alignment accuracy requirements of the multilayer conductive layer, The capacitance density of the capacitor can be further improved without increasing the difficulty of the process.
  • FIG. 2 a capacitor as shown in FIG. 2 is made in this embodiment.
  • the capacitor manufacturing method in this embodiment can also be used to manufacture capacitors as shown in FIG. 3, FIG. 4, FIG. 5, and FIG. 12.
  • the difference is only in the laminated structure and the arrangement of the semiconductor substrate. It's concise, so I won't repeat it here.
  • Step 1 Choose a semiconductor substrate.
  • the semiconductor substrate is a silicon wafer, including monocrystalline silicon, polycrystalline silicon, and amorphous silicon; other semiconductor wafers may also be used, such as SiC, GaN, GaAs and other compound semiconductor wafers of group III-V elements; It may also include an oxide layer and a bonding layer, such as a silicon-on-insulator (SOI) wafer.
  • SOI silicon-on-insulator
  • Step 2 Using photolithography and deep reactive ion etching processes to fabricate a first trench array on the semiconductor substrate.
  • the trench includes a hole (Via), a groove (Trench), a pillar (Pillar), and a wall (Wall).
  • Step 3 Set up a first capacitor on the surface of the first trench array, including a first plate layer, a first dielectric layer and a second plate layer.
  • the first dielectric layer electrically isolates the first electrode plate layer and the second electrode plate layer.
  • the first electrode plate layer is arranged on the surface of the first groove array.
  • doping can be performed on the surface of the first trench array to form a p++-type or n++-type low-resistivity conductive region.
  • a low-resistivity conductive material is deposited on the surface of the first trench array, for example, TiN and/or TaN and/or Pt are deposited by an ALD process, or a CVD process is used to deposit heavily doped polysilicon, metallic tungsten, and carbon materials .
  • a first dielectric layer is provided on the first plate layer.
  • a second plate layer is deposited on the first dielectric layer. It should be noted that the second electrode plate layer fills the first trench array and forms a film layer with a certain thickness (between 10 nanometers and 20 microns) on the upper surface of the semiconductor substrate.
  • Step 4 Using photolithography and deep reactive ion etching processes, a second trench array is fabricated on the second electrode plate layer.
  • the depth of the second trench array is smaller than the thickness of the second electrode plate layer on the surface of the semiconductor substrate.
  • Step 5 Set a second capacitor on the surface of the second trench array, including a second electrode plate layer, a second dielectric layer and a third electrode plate layer.
  • the first and second dielectric layers may be silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, or metal oxynitride.
  • silicon dioxide, silicon nitride, SiON, or high dielectric constant materials including Al2O3, HfO2, ZrO2, TiO2, Y2O3, La2O3, HfSiO4, LaAlO3, SrTiO3, LaLuO3, etc.
  • the dielectric layer may be one layer or include multiple stacked layers, and may be one material or a combination of multiple materials.
  • the second and third electrode plate layers are heavily doped polysilicon deposited by a CVD process; they can also be a laminated combination of low-resistivity conductive materials and other materials.
  • Low-resistivity conductive materials include carbon materials, or aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), iridium (Ir)
  • Various metals such as, rhodium (Rh) can also be compounds with low resistivity such as titanium nitride and tantalum nitride.
  • Deposition methods include ALD, CVD, physical vapor deposition (PVD), electroplating and so on.
  • Step 6 Fabricate interconnection structures and electrodes, and connect the first capacitor and the second capacitor in parallel. Wherein, at least one electrode is electrically connected to the first and third electrode plate layers, and at least one electrode is electrically connected to the second electrode plate layer.
  • the interconnection structure includes at least one layer of insulating material as an interlayer dielectric layer (ILD).
  • the deposited insulating material can also be used as an etch stop layer, or used to make a spacer at the edge of a step to strengthen the electrical insulation between adjacent plate layers.
  • the insulating material can be silicon oxide, silicon nitride, silicon-containing glass (USG, BSG, PSG, BPSG) deposited by CVD process; it can also be aluminum oxide deposited by ALD; or sprayed, spin-coated SOG, Polyimide, etc.

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Abstract

本申请实施例提供一种电容器及其制作方法，电容器包括：半导体衬底，包括至少一个衬底沟槽组；至少一个叠层结构，每个叠层结构包括n层导电层和m层电介质层，n层导电层中的第一层导电层设置于半导体衬底上方和衬底沟槽组内，n层导电层中的第i层导电层形成有第i导电层沟槽组，n层导电层中的第i+1层导电层设置于第i层导电层的上方和第i导电层沟槽组内，m、n、i为正整数，且n≥2，1≤i≤n-1；至少一个第一外接电极，电连接至n层导电层中的一部分导电层；至少一个第二外接电极，电连接至n层导电层中的另一部分导电层，一部分导电层中的每层导电层在叠层结构中相邻的导电层包括有另一部分导电层中的至少一个导电层。

Description

电容器及其制作方法 技术领域
本申请涉及电容器领域，并且更具体地，涉及电容器及其制作方法。
背景技术
电容器在电路中可以起到旁路、滤波、去耦等作用，是保证电路正常运转的不可或缺的一部分。随着现代电子系统不断向多功能、高集成、低功耗、微型化发展，传统的多层陶瓷电容(Multi-layer Ceramic Capacitors，MLCC)已经难以满足应用端日益严苛的小体积、高容量的需求。如何制备小体积、高容量的电容器，成为一个亟待解决的技术问题。
发明内容
本申请实施例提供一种电容器及其制作方法，能够制备小体积、高容值密度的电容器。
第一方面，提供了一种电容器，所述电容器包括：
半导体衬底，包括至少一个衬底沟槽组，所述衬底沟槽组自所述半导体衬底的上表面向下进入所述半导体衬底；
至少一个叠层结构，每个叠层结构包括n层导电层和m层电介质层，所述n层导电层中的第一层导电层设置于所述半导体衬底上方和所述衬底沟槽组内，所述n层导电层中的第i层导电层形成有第i导电层沟槽组，所述n层导电层中的第i+1层导电层设置于所述第i层导电层的上方和所述第i导电层沟槽组内，所述n层导电层和所述m层电介质层形成导电层与电介质层彼此相邻的结构，m、n、i为正整数，且n≥2，1≤i≤n-1；
至少一个第一外接电极，所述第一外接电极电连接至所述n层导电层中的一部分导电层；
至少一个第二外接电极，所述第二外接电极电连接至所述n层导电层中的另一部分导电层，所述一部分导电层中的每层导电层在所述叠层结构中相邻的导电层包括有所述另一部分导电层中的至少一个导电层。
在一些可能的实现方式中，所述第i层导电层包括膜层部分和沟槽部分，所述第i导电层沟槽组设置于所述第i层导电层的所述膜层部分且未进入所 述第i层导电层的所述沟槽部分。
在一些可能的实现方式中，所述第一层导电层的所述膜层部分的厚度范围为10nm～20μm。
在一些可能的实现方式中，所述n层导电层中不同导电层所包括的导电层沟槽的数量和/或尺寸相同。
在一些可能的实现方式中，所述n层导电层中不同导电层所包括的导电层沟槽的数量和/或尺寸不同。
在一些可能的实现方式中，所述衬底沟槽组所包括的多个衬底沟槽呈阵列分布，和/或，所述第i导电层沟槽组所包括的多个导电层沟槽呈阵列分布。
在一些可能的实现方式中，所述衬底沟槽组所包括的多个衬底沟槽的尺寸小于第一阈值，和/或，所述第i导电层沟槽组所包括的多个导电层沟槽的尺寸小于第二阈值。
在一些可能的实现方式中，所述第一阈值等于所述第二阈值。
在一些可能的实现方式中，所述每个叠层结构包括第一层导电层、第二层导电层、第一层电介质层和第二层电介质层；其中，
所述第一层电介质层设置于所述半导体衬底与所述第一层导电层之间，所述第二层电介质层设置于所述第一层导电层与所述第二层导电层之间；
所述第一层导电层包括所述膜层部分和所述沟槽部分，所述第一层导电层形成有第一导电层沟槽组，所述第一导电层沟槽组设置于所述第一层导电层的所述膜层部分且未进入所述第一层导电层的所述沟槽部分，所述第二层导电层设置于所述第一层导电层的上方和所述第一导电层沟槽组内。
在一些可能的实现方式中，所述每个叠层结构包括第一层导电层、第二层导电层、第三层导电层、第一层电介质层、第二层电介质层和第三层电介质层；其中，
所述第一层电介质层设置于所述半导体衬底与所述第一层导电层之间，所述第二层电介质层设置于所述第一层导电层与所述第二层导电层之间，所述第三层电介质层设置于所述第二层导电层与所述第三层导电层之间；
所述第一层导电层包括所述膜层部分和所述沟槽部分，所述第一层导电层形成有第一导电层沟槽组，所述第一导电层沟槽组设置于所述第一层导电层的所述膜层部分且未进入所述第一层导电层的所述沟槽部分，所述第二层导电层设置于所述第一层导电层的上方和所述第一导电层沟槽组内；
所述第二层导电层包括膜层部分和沟槽部分，所述第二层导电层形成有第二导电层沟槽组，所述第二导电层沟槽组设置于所述第二层导电层的膜层部分且未进入所述第二层导电层的沟槽部分，所述第三层导电层设置于所述第二层导电层的上方和所述第二导电层沟槽组内。
在一些可能的实现方式中，所述第i层导电层包括膜层部分和沟槽部分，所述第i导电层沟槽组设置于所述第i层导电层的所述膜层部分和所述沟槽部分。
在一些可能的实现方式中，所述衬底沟槽组包括至少一个第一衬底沟槽，所述n层导电层中的第二层导电层也设置于所述第一衬底沟槽内。
在一些可能的实现方式中，所述第一衬底沟槽的尺寸大于第三阈值。
在一些可能的实现方式中，所述衬底沟槽组还包括设置于所述第一衬底沟槽的周围的至少一个第二衬底沟槽，所述n层导电层中仅所述第一层导电层设置于所述第二衬底沟槽内。
在一些可能的实现方式中，所述第二衬底沟槽的尺寸小于所述第一衬底沟槽的尺寸，和/或，所述第二衬底沟槽的深度小于所述第一衬底沟槽的深度。
在一些可能的实现方式中，所述每个叠层结构包括第一层导电层、第二层导电层、第一层电介质层和第二层电介质层；其中，
所述第一层电介质层设置于所述半导体衬底与所述第一层导电层之间，所述第二层电介质层设置于所述第一层导电层与所述第二层导电层之间；
所述第一层导电层包括所述膜层部分和所述沟槽部分，所述第一层导电层形成有第一导电层沟槽组，所述第一导电层沟槽组设置于所述第一层导电层的所述膜层部分和所述第一层导电层的所述沟槽部分，所述第二层导电层设置于所述第一层导电层的上方和所述第一导电层沟槽组内。
在一些可能的实现方式中，所述叠层结构中设置有台阶结构，所述台阶结构上设置有由绝缘材料形成的刻蚀停止层，或者，所述台阶结构边缘处设置有由绝缘材料形成的边墙。
在一些可能的实现方式中，所述半导体衬底由电阻率小于阈值的材料形成，或者，所述半导体衬底的表面形成有重掺杂的电阻率小于阈值的导电层或者导电区域。
在一些可能的实现方式中，
所述叠层结构中距离所述半导体衬底最近的导电层电连接所述第一外 接电极，所述半导体衬底电连接所述第二外接电极；或者
所述叠层结构中距离所述半导体衬底最近的导电层电连接所述第二外接电极，所述半导体衬底电连接所述第一外接电极。
在一些可能的实现方式中，所述电容器还包括：电极层，设置于所述叠层结构的上方，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。
在一些可能的实现方式中，所述第一外接电极和/或所述第二外接电极通过互联结构电连接至所述n层导电层中的导电层。
在一些可能的实现方式中，所述互联结构包括至少一层绝缘层和导电通孔结构，所述导电通孔结构贯穿所述至少一层绝缘层，以至电连接所述n层导电层中的导电层。
在一些可能的实现方式中，所述第一外接电极电连接至所述n层导电层中的所有奇数层导电层，所述第二外接电极电连接至所述n层导电层中的所有偶数层导电层。
在一些可能的实现方式中，所述至少一个叠层结构中不同叠层结构共用同一个所述第一外接电极，和/或，不同叠层结构共用同一个所述第二外接电极。
在一些可能的实现方式中，所述导电层包括以下中的至少一层：
重掺杂多晶硅层，金属硅化物层，碳层，导电聚合物层，铝层，铜层，钨层，钛层，钽层，铂层，镍层，钌层，铱层，铑层，氮化钽层，氮化钛层，氮化铝钛层，氮化硅钽层，氮化碳钽层。
在一些可能的实现方式中，所述电介质层包括以下中的至少一层：
硅的氧化物层，硅的氮化物层，硅的氮氧化物层，金属的氧化物层，金属的氮化物层，金属的氮氧化物层。
第二方面，提供了一种电容器的制作方法，包括：
在半导体衬底上制备至少一个衬底沟槽组，所述衬底沟槽组自所述半导体衬底的上表面向下进入所述半导体衬底；
制备至少一个叠层结构，每个叠层结构包括n层导电层和m层电介质层，所述n层导电层中的第一层导电层设置于所述半导体衬底上方和所述衬底沟槽组内，所述n层导电层中的第i层导电层形成有第i导电层沟槽组，所述 n层导电层中的第i+1层导电层设置于所述第i层导电层的上方和所述第i导电层沟槽组内，所述n层导电层和所述m层电介质层形成导电层与电介质层彼此相邻的结构，m、n、i为正整数，且n≥2，1≤i≤n-1；
制备至少一个第一外接电极和至少一个第二外接电极，其中，所述第一外接电极电连接至所述n层导电层中的一部分导电层，所述第二外接电极电连接至所述n层导电层中的另一部分导电层，所述一部分导电层中的每层导电层在所述叠层结构中相邻的导电层包括有所述另一部分导电层中的至少一个导电层。
在一些可能的实现方式中，所述第i层导电层包括膜层部分和沟槽部分，所述第i导电层沟槽组设置于所述第i层导电层的所述膜层部分且未进入所述第i层导电层的所述沟槽部分。
在一些可能的实现方式中，所述第一层导电层的所述膜层部分的厚度范围为10nm～20μm。
在一些可能的实现方式中，所述n层导电层中不同导电层所包括的导电层沟槽的数量和/或尺寸相同。
在一些可能的实现方式中，所述n层导电层中不同导电层所包括的导电层沟槽的数量和/或尺寸不同。
在一些可能的实现方式中，所述衬底沟槽组所包括的多个衬底沟槽呈阵列分布，和/或，所述第i导电层沟槽组所包括的多个导电层沟槽呈阵列分布。
在一些可能的实现方式中，所述衬底沟槽组所包括的多个衬底沟槽的尺寸小于第一阈值，和/或，所述第i导电层沟槽组所包括的多个导电层沟槽的尺寸小于第二阈值。
在一些可能的实现方式中，所述第一阈值等于所述第二阈值。
在一些可能的实现方式中，所述叠层结构包括第一层电介质层、第一层导电层、第二层电介质层、第二层导电层；
所述制备叠层结构，包括：
在所述半导体衬底上表面和所述衬底沟槽组内表面沉积第一层电介质层；
在所述第一层电介质层的上表面和内表面沉积所述第一层导电层；
对所述第一层导电层进行刻蚀处理，以在所述第一层导电层中形成第一导电层沟槽组，所述第一导电层沟槽组设置于所述第一层导电层的所述膜层 部分且未进入所述第一层导电层的所述沟槽部分；
在所述第一层导电层的上表面和所述第一导电层沟槽组内表面沉积所述第二电介质层；
在所述第二层电介质层的上表面和内表面沉积所述第二层导电层。
在一些可能的实现方式中，所述第i层导电层包括膜层部分和沟槽部分，所述第i导电层沟槽组设置于所述第i层导电层的所述膜层部分和所述沟槽部分。
在一些可能的实现方式中，所述衬底沟槽组包括至少一个第一衬底沟槽，所述n层导电层中的第二层导电层也设置于所述第一衬底沟槽内。
在一些可能的实现方式中，所述第一衬底沟槽的尺寸大于第三阈值。
在一些可能的实现方式中，所述衬底沟槽组还包括设置于所述第一衬底沟槽的周围的至少一个第二衬底沟槽，所述n层导电层中仅所述第一层导电层设置于所述第二衬底沟槽内。
在一些可能的实现方式中，所述第二衬底沟槽的尺寸小于所述第一衬底沟槽的尺寸，和/或，所述第二衬底沟槽的深度小于所述第一衬底沟槽的深度。
在一些可能的实现方式中，所述叠层结构包括第一层电介质层、第一层导电层、第二层电介质层、第二层导电层；
所述制备叠层结构，包括：
在所述半导体衬底上表面和所述衬底沟槽组内表面沉积第一层电介质层；
在所述第一层电介质层的上表面和内表面沉积所述第一层导电层；
对所述第一层导电层进行刻蚀处理，以在所述第一层导电层中形成第一导电层沟槽组，所述第一导电层沟槽组设置于所述第一层导电层的所述膜层部分和所述沟槽部分；
在所述第一层导电层的上表面和所述第一导电层沟槽组内表面沉积所述第二电介质层；
在所述第二层电介质层的上表面和内表面沉积所述第二层导电层。
在一些可能的实现方式中，所述叠层结构中设置有台阶结构，所述台阶结构上设置有由绝缘材料形成的刻蚀停止层，或者，所述台阶结构边缘处设置有由绝缘材料形成的边墙。
在一些可能的实现方式中，所述半导体衬底由电阻率小于阈值的材料形 成，或者，所述半导体衬底的表面形成有重掺杂的电阻率小于阈值的导电层或者导电区域。
在一些可能的实现方式中，
所述叠层结构中距离所述半导体衬底最近的导电层电连接所述第一外接电极，所述半导体衬底电连接所述第二外接电极；或者
所述叠层结构中距离所述半导体衬底最近的导电层电连接所述第二外接电极，所述半导体衬底电连接所述第一外接电极。
在一些可能的实现方式中，所述制备至少一个第一外接电极和至少一个第二外接电极，包括：
在所述叠层结构上方制备电极层，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。
在一些可能的实现方式中，所述方法还包括：
制备互联结构，以使所述第一外接电极和/或所述第二外接电极通过所述互联结构电连接至所述n层导电层中的导电层。
在一些可能的实现方式中，所述互联结构包括至少一层绝缘层和导电通孔结构，所述导电通孔结构贯穿所述至少一层绝缘层，以电连接至所述n层导电层中的导电层。
在一些可能的实现方式中，所述第一外接电极电连接至所述n层导电层中的所有奇数层导电层，所述第二外接电极电连接至所述n层导电层中的所有偶数层导电层。
在一些可能的实现方式中，所述至少一个叠层结构中不同叠层结构共用同一个所述第一外接电极，和/或，不同叠层结构共用同一个所述第二外接电极。
因此，在本申请实施例中，在半导体衬底和导电层中分别制作沟槽式电容器，可以重复使用制作单个电容的工艺，降低多层导电层对准精度要求，能够在不增加工艺难度的情况下进一步提高电容器的容值密度。
附图说明
图1是本申请提供的一种电容器的示意性结构图。
图2是根据本申请实施例的一种电容器的示意性结构图。
图3是根据本申请实施例的又一种电容器的示意性结构图。
图4是根据本申请实施例的再一种电容器的示意性结构图。
图5是根据本申请实施例的再一种电容器的示意性结构图。
图6是根据本申请实施例的一种半导体衬底的示意性结构图。
图7是根据本申请实施例的又一种半导体衬底的示意性结构图。
图8是根据本申请实施例的再一种半导体衬底的示意性结构图。
图9是根据本申请实施例的再一种半导体衬底的示意性结构图。
图10是根据本申请实施例的刻蚀停止层的示意性结构图。
图11是根据本申请实施例的边墙的示意性结构图。
图12是根据本申请实施例的再一种电容器的示意性结构图。
图13是根据本申请实施例的一种电容器的制作方法的示意性流程图。
图14a至图14n是本申请实施例的一种电容器的制作方法的示意图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
应理解，本申请实施例的电容器在电路中可以起到旁路、滤波、去耦等作用。
本申请实施例所述的电容器可以是3D硅电容器，3D硅电容器是一种基于半导体晶圆加工技术的新型电容器。与传统的MLCC(多层陶瓷电容)相比，3D硅电容器具有小尺寸、高精度、高稳定性、长寿命等优点。其基本的加工流程需要先在晶圆或衬底上加工出高深宽比的深孔(Via)、沟槽(Trench)、柱状(Pillar)、墙状(Wall)等3D结构，接着在3D结构表面沉积绝缘薄膜和低电阻率导电材料依次制作电容的下电极、电介质层和上电极。
借助于先进的半导体加工工艺，制作超薄型、高可靠性的电容器已经成为可能。为了提高容值密度，现有3D硅电容器一般采用多层堆叠的技术方案，如图1所示。通过在3D结构表面制作垂直堆叠的多个电容器，再利用金属互联结构将多个电容器并联，可以有效提高电容密度。
具体如图1所示，衬底110为低电阻率衬底，衬底110上形成有沟槽1和沟槽2，衬底110上表面、沟槽1和沟槽2内沉积有第一电介质层120，第一电介质层120上表面和内表面沉积有第一导电层130，第一导电层130上表面和内表面沉积有第二电介质层140，第二电介质层140上表面和内表 面沉积有第二导电层150。
衬底110与第一导电层130形成电容器的容值为C 1，第一导电层130与第二导电层150形成电容器的容值为C 2，电容器C 1和电容器C 2并联形成的等效电容器的容值为C total，其中，
Figure PCTCN2019094619-appb-000001
然而，由于沟槽1和沟槽2中需要沉积多个导电层，因此沟槽开口较大，由此导致单位面积内的沟槽数量较少，进而使得容值有限。进一步地，由于几何效应，垂直堆叠的多个电容器的容值逐渐减小，由多层导电层堆叠带来的容值密度增益实际有限。并且现有方案工艺难度大，需要严格管控沉积、刻蚀的均匀性，还要精准的多层对准。由此，导致产品良率降低。
在此背景下，本申请提出了一种新型的电容器的结构和制作方法，可以提高电容器的容值密度。
以下，结合图2至图12，详细介绍本申请实施例的电容器。
应理解，图2至图12中的电容器仅仅只是示例，电容器所包括的叠层结构的数量并不局限于图2至图12中的电容器所示，可以根据实际需要确定。同时叠层结构所包括的导电层的数量以及电介质的数量仅仅只是示例，叠层结构所包括的导电层的数量以及电介质层的数量并不局限于图2至图12中的电容器所示，可以根据实际需要灵活设置。
需要说明的是，为便于理解，在以下示出的实施例中，对于不同实施例中示出的结构中，相同的结构采用相同的附图标记，并且为了简洁，省略对相同结构的详细说明。
图2是本申请一个实施例的电容器200的一种可能的结构图。如图2所示，该电容器200包括半导体衬底210、至少一个叠层结构220、至少一个第一外接电极230、至少一个第二外接电极240。
具体地，如图2所示，在该电容器200中，该半导体衬底210包括至少一个衬底沟槽组10，该衬底沟槽组10自该半导体衬底210的上表面向下进入该半导体衬底210；该叠层结构220包括n层导电层和m层电介质层，该n层导电层中的第一层导电层设置于该半导体衬底210上方和该衬底沟槽组10内，该n层导电层中的第i层导电层形成有第i导电层沟槽组20，该n层导电层中的第i+1层导电层设置于该第i层导电层的上方和该第i导电层沟槽组20内，该n层导电层和该m层电介质层形成导电层与电介质层彼此相邻的结构，m、n、i为正整数，且n≥2，1≤i≤n-1；该第一外接电极230电 连接至该n层导电层中的一部分导电层；该第二外接电极240电连接至该n层导电层中的另一部分导电层，该一部分导电层中的每层导电层在该叠层结构中相邻的导电层包括有该另一部分导电层中的至少一个导电层。
需要说明的是，该衬底沟槽组10可以包括多个衬底沟槽，该第i导电层沟槽组20可以包括多个导电层沟槽。
可选地，该衬底沟槽组10中的多个衬底沟槽中不同的衬底沟槽的横截面的形状可以相同，也可以不同。
需要说明的是，本申请实施例中图2是沿着衬底纵向的截面。
在本申请实施例中，该衬底沟槽组10所包括的衬底沟槽的深宽可以根据实际需要灵活设置。优选地，该衬底沟槽组10所包括的衬底沟槽具有高深宽比(High aspect ratio)。同理，该第i导电层沟槽组20所包括的多个导电层沟槽的深宽可以根据实际需要灵活设置。优选地，该第i导电层沟槽组20所包括的多个导电层沟槽具有高深宽比。
需要说明的是，在本申请实施例中，该衬底沟槽组10所包括的衬底沟槽可以为横截面上长和宽尺寸相差较小的孔，或者也可以为长和宽尺寸相差较大的沟槽，或者还可以是柱状(Pillar)或墙状(Wall)3D结构。同理，该第i导电层沟槽组20所包括的多个导电层沟槽可以为横截面上长和宽尺寸相差较小的孔，或者也可以为长和宽尺寸相差较大的沟槽，或者还可以是柱状或墙状3D结构。这里横截面可以理解为与半导体衬底210表面平行的截面，而图2中则是沿着半导体衬底210纵向的截面。
在本申请实施例中，该n层导电层中相邻的两个导电层通过电介质层电隔离，以及m和n的具体数值可以根据实际需要灵活配置，只需满足该n层导电层中相邻两个导电层之间电隔离。
例如，在该半导体衬底210不参与形成电容器200的电极板的情况下，该叠层结构220中的第一层导电层可以直接设置在该半导体衬底210的上表面和该衬底沟槽组10内，即n＝m+1。
又例如，在该半导体衬底210参与形成电容器200的电极板的情况下，该叠层结构220中的第一层导电层与该半导体衬底210之间需要设置电介质层，以隔离该第一层导电层和该半导体衬底210，即n＝m。
应理解，本申请实施例中外接电极也可以称之为焊盘或者外接焊盘。
在本申请实施例中，在半导体衬底和导电层中分别制作沟槽式电容器， 可以重复使用制作单个电容的工艺，降低多层导电层对准精度要求，能够在不增加工艺难度的情况下进一步提高电容器的容值密度。
可选地，在本申请实施例中，该半导体衬底210可以为硅晶圆，包括单晶硅、多晶硅、不定形硅。该半导体衬底210也可以是别的半导体衬底，包括SOI晶圆，碳化硅(SiC)、氮化镓(GaN)、砷化镓(GaAs)等III-V族元素的化合物半导体晶圆；或者是玻璃衬底；或者是有机聚合物衬底；或者表面包含外延层、氧化层、掺杂层、键合层的衬底。
需要注意的是，在本申请实施例中，该半导体衬底210的厚度也可以根据实际需要灵活设置，例如，在该半导体衬底210的厚度因太厚而不能满足需求时，可以对该半导体衬底210进行减薄处理。
可选地，该第一外接电极230和该第二外接电极240的材料可以是金属，例如铜、铝等。该第一外接电极230和该第二外接电极240还可以包含低电阻率的Ti，TiN，Ta，TaN层作为黏附层和/或阻挡层；还可能包含位于外接电极表面的一些金属层，例如Ni、Pd(钯)、Au、Sn(锡)、Ag，用于后续打线或焊接工艺。
可选地，本申请实施例中，该导电层包括以下中的至少一层：
重掺杂多晶硅层，金属硅化物层，碳层，导电聚合物层，铝层，铜层，钨层，钛层，钽层，铂层，镍层，钌层，铱层，铑层，氮化钽层，氮化钛层，氮化铝钛层，氮化硅钽层，氮化碳钽层。
也就是说，该叠层结构220中的导电层的材料可以是重掺杂多晶硅，金属硅化物(silicide)，碳，导电的聚合物，铝(Al)、钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、铂(Pt)、钌(Ru)、铱(Ir)、铑(Rh)、镍(Ni)等金属，氮化钽(TaN)、氮化钛(TiN)、氮化铝钛(TiAlN)、氮化硅钽(TaSiN)、氮化碳钽(TaCN)等低电阻率化合物，或者上述材料的组合、叠层结构。具体导电材料和层厚可根据电容器的容值、频率特性、损耗等需求来调整。当然，该叠层结构220中的导电层还可以包括一些其他的导电材料，本申请实施例对此不作限定。
可选地，本申请实施例中，该电介质层包括以下中的至少一层：
硅的氧化物层，硅的氮化物层，硅的氮氧化物层，金属的氧化物层，金属的氮化物层和金属的氮氧化物层。
也就是说，该叠层结构220中的电介质层的材料可以是硅的氧化物，硅 的氮化物，硅的氮氧化物，金属的氧化物，金属的氮化物，金属的氮氧化物。例如SiO 2，SiN，SiON，或者高介电常数(high-k)材料，包括Al 2O 3，HfO 2，ZrO 2，TiO 2，Y 2O 3，La 2O 3，HfSiO 4，LaAlO 3，SrTiO 3，LaLuO 3等。该叠层结构220中的电介质层可以是一层或包含多个叠层，可以是一种材料或多种材料的组合、混合。具体绝缘材料和层厚可根据电容器的容值、频率特性、损耗等需求来调整。当然，该叠层结构220中的电介质层还可以包括一些其他的绝缘材料，本申请实施例对此不作限定。
需要说明的是，在该叠层结构220中，该m层电介质层的顺序是：在半导体衬底210上，与半导体衬底210的距离从小到大的顺序。同理，该n层导电层的顺序是：在半导体衬底210上，与半导体衬底210的距离从小到大的顺序。
在本申请实施例中，该至少一个叠层结构220中的每个叠层结构可以对应至少一个第一外接电极230和至少一个第二外接电极240。
需要说明的是，在本申请实施例中，由于该第一外接电极230电连接至该n层导电层中的一部分导电层；该第二外接电极240电连接至该n层导电层中的另一部分导电层，该一部分导电层中的每个导电层在该叠层结构220中相邻的导电层包括有该另一部分导电层中的至少一个导电层。因此，针对不同的第一外接电极230和第二外接电极240，该叠层结构220可以形成具有不同容值的电容器。
作为一个示例，假设该电容器200包括一个叠层结构，记为叠层结构1，以及包括2个第一外接电极和2个第二外接电极，2个第一外接电极分别记为第一外接电极A和第一外接电极B，2个第二外接电极分别记为第二外接电极C和第二外接电极D，以及该叠层结构1包括5层导电层和4层电介质层，5层导电层依次分别记为导电层1、导电层2、导电层3、导电层4和导电层5，4层电介质层依次分别记为电介质层1、电介质层2、电介质层3和电介质层4。
若该第一外接电极A电连接该导电层1和该导电层3，该第一外接电极B电连接该导电层1、该导电层3和该导电层5，该第二外接电极C电连接该导电层2和该导电层4，该第二外接电极D也电连接该导电层2和该导电层4，则针对该第一外接电极A与该第二外接电极C对应的电容器，该导电层1与该导电层2形成电容器1，容值记为C1，该导电层2与该导电层3形 成电容器2，容值记为C2，该导电层3与该导电层4形成电容器3，容值记为C3，电容器1、电容器2和电容器3并联，其等效电容i的容值记为Ci，则Ci＝C1+C2+C3；则针对该第一外接电极B与该第二外接电极D对应的电容器，该导电层1与该导电层2形成电容器1，容值记为C1，该导电层2与该导电层3形成电容器2，容值记为C2，该导电层3与该导电层4形成电容器3，容值记为C3，该导电层4与该导电层5形成电容器4，容值记为C4，电容器1、电容器2、电容器3和电容器4并联，其等效电容j的容值记为Cj，则Cj＝C1+C2+C3+C4。当然，针对该第一外接电极A与该第二外接电极D对应的电容器也可以形成类似的串并联结构，针对该第一外接电极B与该第二外接电极C对应的电容器也可以形成类似的串并联结构，在此不再赘述。因此，该叠层结构1可以形成具有不同容值的电容器。
若该第一外接电极A电连接该导电层1和该导电层5，该第一外接电极B电连接该导电层3和该导电层5，该第二外接电极C电连接该导电层2和该导电层4，该第二外接电极D也电连接该导电层4，则针对该第一外接电极A与该第二外接电极C对应的电容器，该导电层1与该导电层2形成电容器1，容值记为C1，该导电层2与该导电层4形成电容器2，容值记为C2，电容器1和电容器2并联，其等效电容i的容值记为Ci，则Ci＝C1+C2；则针对该第一外接电极B与该第二外接电极D对应的电容器，该导电层3与该导电层4形成电容器3，容值记为C3，该导电层4与该导电层5形成电容器4，容值记为C4，电容器3和电容器4并联，其等效电容j的容值记为Cj，则Cj＝C3+C4。当然，针对该第一外接电极A与该第二外接电极D对应的电容器也可以形成类似的串并联结构，针对该第一外接电极B与该第二外接电极C对应的电容器也可以形成类似的串并联结构，在此不再赘述。因此，该叠层结构1可以形成具有不同容值的电容器。
可选地，该至少一个第一外接电极230中每个第一外接电极230电连接至该n层导电层中的所有奇数层导电层；该至少一个第二外接电极240中每个第二外接电极240电连接至该n层导电层中的所有偶数层导电层。从而可以充分发挥叠层结构增加电容器的容值密度的效果。
作为一个示例，假设该电容器200包括一个叠层结构，记为叠层结构2，以及包括2个第一外接电极和2个第二外接电极，2个第一外接电极分别记为第一外接电极A和第一外接电极B，2个第二外接电极分别记为第二外接 电极C和第二外接电极D，以及该叠层结构2包括5层导电层和4层电介质层，5层导电层依次分别记为导电层1、导电层2、导电层3、导电层4和导电层5，4层电介质层依次分别记为电介质层1、电介质层2、电介质层3和电介质层4。
若该第一外接电极A电连接该导电层1、该导电层3和该导电层5，该第一外接电极B也电连接该导电层1、该导电层3和该导电层5，该第二外接电极C电连接该导电层2和该导电层4，该第二外接电极D也电连接该导电层2和该导电层4，则针对该第一外接电极A与该第二外接电极C对应的电容器，该导电层1与该导电层2形成电容器1，容值记为C1，该导电层2与该导电层3形成电容器2，容值记为C2，该导电层3与该导电层4形成电容器3，容值记为C3，该导电层4与该导电层5形成电容器4，容值记为C4，电容器1、电容器2、电容器3和电容器4并联，其等效电容i的容值记为Ci，则Ci＝C1+C2+C3+C4；则针对该第一外接电极B与该第二外接电极D对应的电容器，该导电层1与该导电层2形成电容器1，容值记为C1，该导电层2与该导电层3形成电容器2，容值记为C2，该导电层3与该导电层4形成电容器3，容值记为C3，该导电层4与该导电层5形成电容器4，容值记为C4，电容器1、电容器2、电容器3和电容器4并联，其等效电容j的容值记为Cj，则Cj＝C1+C2+C3+C4。当然，针对该第一外接电极A与该第二外接电极D对应的电容器也可以形成类似的串并联结构，针对该第一外接电极B与该第二外接电极C对应的电容器也可以形成类似的串并联结构，在此不再赘述。
可选地，该至少一个叠层结构220中不同叠层结构可以共用同一个第一外接电极230，和/或，不同叠层结构共用同一个第二外接电极240。当然，该至少一个叠层结构220中不同叠层结构也可以不共用任何外接电极，本申请实施例对此不作限定。
也就是说，在本申请实施例中，一个第一外接电极230可以电连接至该至少一个叠层结构220中的部分或者全部叠层结构220，同理，一个第二外接电极240也可以电连接至该至少一个叠层结构220中的部分或者全部叠层结构220。
作为一个示例，假设该电容器200包括3个叠层结构、第一外接电极P、第二外接电极Q和第二外接电极Z，3个叠层结构分别记为叠层结构A和叠 层结构B，
若该第一外接电极P电连接该叠层结构A的所有奇数层导电层和该叠层结构B的所有奇数层导电层，该第二外接电极Q电连接该叠层结构A的所有偶数层导电层，该第二外接电极Z电连接该叠层结构B的所有偶数层导电层，则该第一外接电极P与该第二外接电极Q形成等效电容器1，容值记为C1，该第一外接电极P与该第二外接电极Z形成等效电容器2，容值记为C2。
可选地，在本申请实施例中，该第i层导电层包括膜层部分30和沟槽部分40，该第i导电层沟槽组20设置于该第i层导电层的该膜层部分30且未进入该第i层导电层的该沟槽部分40。
可选地，在一个实施例中，n＝2，m＝2，即该叠层结构220可以包括2层导电层，例如图2中示出的第一层导电层221和第二层导电层222，以及2层电介质层，例如图2中示出的第一层电介质层223和第二层电介质层224。该第一层电介质层223设置于该半导体衬底210与该第一层导电层221之间，该第二层电介质层224设置于该第一层导电层221与该第二层导电层222之间。如图2所示，第一层导电层221包括膜层部分30和沟槽部分40，该第一层导电层221形成有第一导电层沟槽组20，以及该第一导电层沟槽组20设置于该第一层导电层221的膜层部分30且未进入该第一层导电层的沟槽部分40。
可选地，在另一个实施例中，n＝3，m＝3，即该叠层结构220可以包括3层导电层，例如图3中示出的第一层导电层221、第二层导电层222和第三层导电层223，以及3层电介质层，例如图3中示出的第一层电介质层224、第二层电介质层225和第三层电介质层226。该第一层电介质层224设置于该半导体衬底210与该第一层导电层221之间，该第二层电介质层225设置于该第一层导电层221与该第二层导电层222之间，该第三层电介质层226设置于该第二层导电层222与该第三层导电层223之间。如图3所示，第一层导电层221包括膜层部分30和沟槽部分40，该第一层导电层221形成有第一导电层沟槽组20，以及该第一导电层沟槽组20设置于该第一层导电层221的膜层部分30且未进入该第一层导电层的沟槽部分40；第二层导电层222包括膜层部分30和沟槽部分40，该第二层导电层222形成有第二导电层沟槽组20，以及该第二导电层沟槽组20设置于该第二层导电层222的膜 层部分30且未进入该第二层导电层的沟槽部分40。
可选地，在如图2和图3所示的实施例中，该第一层导电层221的膜层部分的厚度范围为10nm～20μm。可选地，在该n层导电层中不同导电层的膜层部分的厚度可以相同，也可以不同。例如，在该n层导电层中，第一层导电层的厚度＞第二层导电层的厚度＞…＞第n层导电层的厚度。
可选地，在如图2和图3所示的实施例中，该n层导电层中不同导电层所包括的导电层沟槽的数量和/或尺寸相同。当然，该n层导电层中不同导电层所包括的导电层沟槽的数量和/或尺寸也可以不同。
可选地，在如图2和图3所示的实施例中，该衬底沟槽组10所包括的多个衬底沟槽呈阵列分布，和/或，该第i导电层沟槽组20所包括的多个导电层沟槽呈阵列分布。
可选地，在如图2和图3所示的实施例中，该衬底沟槽组10所包括的多个衬底沟槽的尺寸小于第一阈值，和/或，该第i导电层沟槽组20所包括的多个导电层沟槽的尺寸小于第二阈值。
可选地，该第一阈值等于该第二阈值，例如，该第一阈值可以为1μm，该第二阈值也可以为1μm。从而该多个衬底沟槽可以与该多个导电层沟槽采用相同的刻蚀参数，以降低电容器的制备难度。
当然，该第一阈值也可以大于或者小于该第二阈值，即该多个衬底沟槽可以单独设置可数参数。
可选地，在本申请实施例中，该第i层导电层包括膜层部分30和沟槽部分40，该第i导电层沟槽组20设置于该第i层导电层的该膜层部分30和该沟槽部分40。
可选地，在一个实施例中，n＝2，m＝2，即该叠层结构220可以包括2层导电层，例如图4中示出的第一层导电层221和第二层导电层222，以及2层电介质层，例如图4中示出的第一层电介质层223和第二层电介质层224。该第一层电介质层223设置于该半导体衬底210与该第一层导电层221之间，该第二层电介质层224设置于该第一层导电层221与该第二层导电层222之间。如图4所示，第一层导电层221包括膜层部分30和沟槽部分40，该第一层导电层221形成有第一导电层沟槽组20，以及该第一导电层沟槽组20设置于该第一层导电层221的膜层部分30和沟槽部分40。
可选地，如图4所示，该衬底沟槽组10包括至少一个第一衬底沟槽11， 该n层导电层中的第二层导电层也设置于该第一衬底沟槽11内。
可选地，该第一衬底沟槽的尺寸大于第三阈值。例如，该第三阈值可以为100nm。
可选地，如图5所示，该衬底沟槽组10还包括设置于该第一衬底沟槽11的周围的至少一个第二衬底沟槽12，该n层导电层中仅该第一层导电层设置于该第二衬底沟槽12内。
需要说明的是，该第一层导电层设置于该第二衬底沟槽12内，可以增加该半导体衬底210与该第一层导电层221所形成的电容器的容值。
可选地，该第二衬底沟槽12的尺寸小于该第一衬底沟槽11的尺寸，和/或，该第二衬底沟槽12的深度小于该第一衬底沟槽11的深度。
需要说明的是，该第二衬底沟槽12可以与该第一衬底沟槽11同步刻蚀形成，以减少刻蚀工艺。
可选地，在本申请实施例中，该至少一个叠层结构220中不同的叠层结构中的导电层之间可以处于电隔离状态，如图2和图3所示；该至少一个叠层结构220中不同的叠层结构中的导电层之间也可以处于电连接状态，如图4和图5所示。
可选地，在本申请实施例中，该半导体衬底210由电阻率小于阈值的材料形成，或者，该半导体衬底210的表面形成有重掺杂的电阻率小于阈值的导电层或者导电区域。也即，该半导体衬底210导电，或者，该半导体衬底210中与该叠层结构220接触的区域导电。
需要说明的是，该半导体衬底210由电阻率小于阈值的材料形成即可认为该半导体衬底210为重掺杂低电阻率衬底；该半导体衬底210的表面形成有重掺杂的电阻率小于阈值的导电层即可认为该半导体衬底210的表面形成有重掺杂低电阻率导电层；该半导体衬底210的表面形成有重掺杂的电阻率小于阈值的导电区域即可认为该半导体衬底210的表面形成有重掺杂低电阻率导电区域。
例如，如图6所示，该半导体衬底210为重掺杂低电阻率衬底，该至少一个衬底沟槽组10设置于该半导体衬底210中。
又例如，如图7所示，该半导体衬底210的上表面和该至少一个衬底沟槽组10内表面形成有重掺杂低电阻率导电层。
再例如，如图8和图9所示，该半导体衬底210的表面形成有重掺杂低 电阻率导电区域，该至少一个衬底沟槽组10设置于该导电区域中。
需要说明的是，电阻率小于阈值的材料即可认为是导电材料。
可选地，若该叠层结构220中距离该半导体衬底210最近的导电层电连接该第一外接电极230，则该半导体衬底210电连接该第二外接电极240。
可选地，若该叠层结构220中距离该半导体衬底210最近的导电层电连接该第二外接电极240，则该半导体衬底210电连接该第一外接电极230。
例如图2至图5所示，该叠层结构220中距离该半导体衬底210最近的导电层电连接该第一外接电极230，以及该半导体衬底210电连接该第二外接电极240。
可选地，在本申请实施例中，该第一外接电极230和/或该第二外接电极240通过互联结构250电连接至该n层导电层中的导电层。
可选地，该互联结构250包括至少一层绝缘层251和导电通孔结构252，该导电通孔结构252贯穿该至少一层绝缘层251，以电连接该n层导电层中的导电层。如图2至图5所示，该互联结构250设置于该叠层结构220的上方。
需要说明的是，该至少一层绝缘层251也可以称之为金属间介质层(IMD)或者层间介质层(ILD)。该导电通孔结构252也可以称之为导电通道。
可选地，该至少一层绝缘层251包覆该叠层结构220，以及该至少一层绝缘层251可以填充该叠层结构220内形成的空腔或者空隙，以提升电容器的结构完整性和机械稳定性。
可选地，该至少一层绝缘层251的材料可以是有机的聚合物材料，包括聚酰亚胺(Polyimide)，帕里纶(Parylene)，苯并环丁烯(BCB)等；也可以是一些无机材料，包括旋转涂布玻璃(Spin on glass，SOG)，未掺杂硅玻璃(Undoped Silicon Glass，USG)，硼硅玻璃(boro-silicate glass，BSG)，磷硅玻璃(phospho-silicateglass，PSG)，硼磷硅玻璃(boro-phospho-silicateglass，BPSG)，由四乙氧基硅烷(Tetraethyl Orthosilicate，TEOS)合成的硅氧化物，硅的氧化物、氮化物，陶瓷；还可以是上述材料的组合或者叠层。
可选地，该导电通孔结构252的材料可以由低电阻率导电材料构成，例如重掺杂多晶硅，钨，Ti，TiN，Ta，TaN。
应理解，该导电通孔结构252的形状和数量可以根据该电容器200的制作工艺具体确定，本申请实施例对此不作限定。
可选地，在本申请实施例中，该叠层结构220中设置有台阶结构，该台阶结构上设置有由绝缘材料形成的刻蚀停止层50，如图10所示，或者，该台阶结构边缘处设置有由绝缘材料形成的边墙51，如图11所示。
可选地，该刻蚀停止层50可以是上述至少一层绝缘层251中的一层。该边墙51可以是上述至少一层绝缘层251中的一层或者一部分。
应理解，该刻蚀停止层50相对于该至少一层绝缘层251中的其他绝缘层更耐刻蚀，在刻蚀导电通孔结构252时，可以将导电通孔结构252的底部停留在不同深度的刻蚀停止层上，再利用干法或者湿法工艺去除导电通孔结构252底部露出的部分刻蚀停止层50，以使导电通孔结构252贯穿该刻蚀停止层50。
需要说明的是，该台阶结构上设置的刻蚀停止层50可以加强该叠层结构220中相邻导电层之间的电绝缘性，以及加强该叠层结构220中的第一层导电层与半导体衬底210之间的电绝缘性。同理，该台阶结构边缘处设置有由绝缘材料形成的边墙51可以加强该叠层结构220中相邻导电层之间的电绝缘性，以及加强该叠层结构220中的第一层导电层与半导体衬底210之间的电绝缘性。
可选地，该刻蚀停止层50或该边墙51可以是化学气相淀积(Chemical Vapor Deposition，CVD)工艺沉积的氧化硅、氮化硅、含硅玻璃(未掺杂硅玻璃(Undoped Silicon Glass，USG)、硼硅玻璃(boro-silicate glass，BSG)、磷硅玻璃(phospho-silicateglass，PSG)、硼磷硅玻璃(boro-phospho-silicateglass，BPSG))；还可以是原子层沉积(Atomic layer deposition，ALD)沉积的氧化铝；或者是喷涂、旋涂的旋转涂布玻璃(Spin on glass，SOG)、聚酰亚胺(Polyimide)等；还可以是上述材料的组合。
可选地，在一些实施例中，该至少一个第一外接电极230和该至少一个第二外接电极240设置于该叠层结构220的上方。可选地，该电容器200还包括：电极层，设置于该叠层结构220的上方，该电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，该第一导电区域形成该第一外接电极230，该第二导电区域形成该第二外接电极240，具体如图2至图5所示。也即，该至少一个第一外接电极230和该至少一个第二外接电极240可以通过一次刻蚀形成，减少了刻蚀步骤。
具体地，如图2至图5所示，该电极层设置于该互联结构250的上方， 该第一外接电极230通过该导电通孔结构252电连接至该半导体衬底210和该叠层结构220中的偶数层导电层，该第二外接电极240通过该导电通孔结构252电连接至该叠层结构220中的奇数层导电层。
可选地，在本申请实施例中，该半导体衬底210也可以不设置该至少一个衬底沟槽组10，即该n层导电层中的第一层导电层设置于该半导体衬底210的上方，如图12所示。
应理解，除了该半导体衬底210中未设置该至少一个衬底沟槽组10之外，图12和图2的其他设置相同，为了简洁，不再赘述。
在本申请实施例中，在半导体衬底和导电层中分别制作沟槽式电容器，可以重复使用制作单个电容的工艺，降低多层导电层对准精度要求，能够在不增加工艺难度的情况下进一步提高电容器的容值密度。
以上描述了本申请实施例的电容器，下面描述本申请实施例的制备电容器的方法。本申请实施例的制备电容器的方法可以制备前述本申请实施例的电容器，下述实施例和前述实施例中的相关描述可以相互参考。
以下，结合图13，详细介绍本申请实施例的电容器的制作方法。
应理解，图13是本申请实施例的电容器的制作方法的示意性流程图，但这些步骤或操作仅是示例，本申请实施例还可以执行其他操作或者图13中的各个操作的变形。
图13示出了根据本申请实施例的电容器的制作方法300的示意性流程图。如图13所示，该电容器的制作方法300包括：
步骤310，在半导体衬底上制备至少一个衬底沟槽组，该衬底沟槽组自该半导体衬底的上表面向下进入该半导体衬底；
步骤320，制备至少一个叠层结构，每个叠层结构包括n层导电层和m层电介质层，该n层导电层中的第一层导电层设置于该半导体衬底上方和该衬底沟槽组内，该n层导电层中的第i层导电层形成有第i导电层沟槽组，该n层导电层中的第i+1层导电层设置于该第i层导电层的上方和该第i导电层沟槽组内，该n层导电层和该m层电介质层形成导电层与电介质层彼此相邻的结构，m、n、i为正整数，且n≥2，1≤i≤n-1；
步骤330，制备至少一个第一外接电极和至少一个第二外接电极，其中，该第一外接电极电连接至该n层导电层中的一部分导电层，该第二外接电极电连接至该n层导电层中的另一部分导电层，该一部分导电层中的每层导电 层在该叠层结构中相邻的导电层包括有该另一部分导电层中的至少一个导电层。
具体地，基于上述步骤310-330可以制备如图2至图5所示的电容器。
应理解，步骤310-330中所述各材料层的上表面是指该材料层与衬底上表面基本平行的表面，而各材料层的内表面是指位于沟槽内材料层的上表面，上表面和内表面可以视为一个整体。
需要说明的是，该衬底沟槽组10的深度小于该半导体衬底210的厚度。也即该衬底沟槽组10未贯穿该半导体衬底210。
可选地，上述步骤310可以使用光刻和深反应离子刻蚀工艺，在该半导体衬底210上制作该至少一个衬底沟槽组10。
该衬底沟槽组10所包括的衬底沟槽可以是孔(Via)、槽(Trench)、柱(Pillar)、墙(Wall)中的一种或者多种。
可选地，上述步骤310可以在该半导体衬底210上制备如图14a所示的至少一个衬底沟槽组10，也可以在该半导体衬底210上制备如图14b所示的至少一个衬底沟槽组10，还可以在该半导体衬底210上制备如图14c所示的至少一个衬底沟槽组10。
可选地，在基于如图14a所示的至少一个衬底沟槽组10制备的电容器(如图2和图3所示的电容器200)可以至少包括但不限于如下特征：
该第i层导电层包括膜层部分30和沟槽部分40，该第i导电层沟槽组20设置于该第i层导电层的该膜层部分30且未进入该第i层导电层的该沟槽部分40；
该第一层导电层的膜层部分的厚度范围为10nm～20μm；
该n层导电层中不同导电层所包括的导电层沟槽的数量和/或尺寸相同。当然，该n层导电层中不同导电层所包括的导电层沟槽的数量和/或尺寸也可以不同；
该衬底沟槽组10所包括的多个衬底沟槽呈阵列分布，和/或，该第i导电层沟槽组20所包括的多个导电层沟槽呈阵列分布；
该衬底沟槽组10所包括的多个衬底沟槽的尺寸小于第一阈值，和/或，该第i导电层沟槽组20所包括的多个导电层沟槽的尺寸小于第二阈值。例如，该第一阈值可以为1μm，该第二阈值也可以为1μm。
可选地，在基于如图14b和图14c所示的至少一个衬底沟槽组10制备 的电容器(如图4和图5所示的电容器200)可以至少包括但不限于如下特征：
该第i层导电层包括膜层部分30和沟槽部分40，该第i导电层沟槽组20设置于该第i层导电层的该膜层部分30和该沟槽部分40；
该衬底沟槽组10包括至少一个第一衬底沟槽11，该n层导电层中的第二层导电层也设置于该第一衬底沟槽11内；
该第一衬底沟槽的尺寸大于第三阈值，例如，该第三阈值可以为100nm；
该衬底沟槽组10还包括设置于该第一衬底沟槽11的周围的至少一个第二衬底沟槽12，该n层导电层中仅该第一层导电层设置于该第二衬底沟槽12内。
可选地，该半导体衬底210由电阻率小于阈值的材料形成，或者，该半导体衬底210的表面形成有重掺杂的电阻率小于阈值的导电层或者导电区域。例如该半导体衬底210可以如图6至图9所示。
在该叠层结构220中距离该半导体衬底210最近的导电层电连接该第一外接电极230的情况下，该半导体衬底210电连接该第二外接电极240。
在该叠层结构220中距离该半导体衬底210最近的导电层电连接该第二外接电极240的情况下，该半导体衬底210电连接该第一外接电极230。
以下以该半导体衬底210由电阻率小于阈值的材料形成为例进行说明。
可选地，上述步骤330具体可以是：在该叠层结构220上方制备电极层，该电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，该第一导电区域形成该第一外接电极230，该第二导电区域形成该第二外接电极240。
可选地，该方法300还包括：
制备互联结构250，以使该第一外接电极230和/或该第二外接电极240通过该互联结构250电连接至该n层导电层中的导电层。
可选地，该互联结构250包括至少一层绝缘层251和导电通孔结构252，该导电通孔结构252贯穿该至少一层绝缘层251，以电连接至该n层导电层中的导电层。
可选地，该叠层结构220中设置有台阶结构，该台阶结构上设置有由绝缘材料形成的刻蚀停止层50，如图10所示，或者，该台阶结构边缘处设置有由绝缘材料形成的边墙51，如图11所示。该刻蚀停止层50可以是上述至 少一层绝缘层251中的一层。该边墙51可以是上述至少一层绝缘层251中的一层或者一部分。
可选地，该第一外接电极230电连接至该n层导电层中的所有奇数层导电层，该第二外接电极240电连接至该n层导电层中的所有偶数层导电层。
可选地，该至少一个叠层结构220中不同叠层结构共用同一个该第一外接电极230，和/或，不同叠层结构共用同一个该第二外接电极240。
可选地，在本申请实施例中，假设m＝2，n＝2，即该叠层结构220包括：第一层导电层221、第二层导电层222、第一层电介质层223、第二层电介质层224。
具体地，在该半导体衬底210上制备了如图14a所示的至少一个衬底沟槽组10的情况下，可以通过如下方式制备如图2所示的电容器200：
首先，在如图14a所示的结构中，在该半导体衬底210上表面和该衬底沟槽组10内表面沉积该第一层电介质层223，接着，在该第一层电介质层223的上表面和内表面沉积该第一层导电层221，如图14d所示。然后，对该第一层导电层221进行刻蚀处理，以在该第一层导电层221中形成第一导电层沟槽组20，该第一导电层沟槽组20设置于该第一层导电层221的膜层部分30且未进入该第一层导电层221的沟槽部分40，如图14e所示。再然后，在该第一层导电层221的上表面和该第一导电层沟槽组20内表面沉积该第二电介质层224，以及在该第二层电介质层224的上表面和内表面沉积该第二层导电层222，如图14f所示。再然后，利用光刻工艺进行多步光刻，以在该叠层结构220中形成台阶结构，如图14g所示。再然后，在该叠层结构220上沉积一层绝缘层251，该绝缘层251包覆该叠层结构220，接着，利用光刻工艺，在对应半导体衬底210、第一层导电层221、第二层导电层222的位置打开若干穿透该绝缘层251的导通孔60，如图14h所示，接着在导通孔60中沉积导电材料，以形成导电通孔结构252，如图14i所示。该绝缘层251和该导电通孔结构252构成该互联结构250。最后，在互联结构250上表面沉积电极层，并光刻形成多个外接电极，从而，制备如图2所示的电容器200。
具体地，在该半导体衬底210上制备了如图14b所示的至少一个衬底沟槽组10的情况下，可以通过如下方式制备如图4所示的电容器200：
首先，在如图14b所示的结构中，在该半导体衬底210上表面和该衬底 沟槽组10内表面沉积该第一层电介质层223，接着，在该第一层电介质层223的上表面和内表面沉积该第一层导电层221，如图14j所示。然后，对该第一层导电层221进行刻蚀处理，以在该第一层导电层221中形成第一导电层沟槽组20，该第一导电层沟槽组20设置于该第一层导电层221的膜层部分30和沟槽部分40，如图14k所示。再然后，在该第一层导电层221的上表面和该第一导电层沟槽组20内表面沉积该第二电介质层224，以及在该第二层电介质层224的上表面和内表面沉积该第二层导电层222，如图14l所示。再然后，利用光刻工艺进行多步光刻，以在该叠层结构220中形成台阶结构，如图14m所示。再然后，在该叠层结构220上沉积一层绝缘层251，该绝缘层251包覆该叠层结构220，接着，利用光刻工艺，在对应半导体衬底210、第一层导电层221、第二层导电层222的位置打开若干穿透该绝缘层251的导通孔60，接着在导通孔60中沉积导电材料，以形成导电通孔结构252，该绝缘层251和该导电通孔结构252构成该互联结构250，如图14n所示。最后，在互联结构250上表面沉积电极层，并光刻形成多个外接电极，从而，制备如图4所示的电容器200。
具体地，在该半导体衬底210上制备了如图14c所示的至少一个衬底沟槽组10的情况下，可以参考制备如图4所示的电容器200的方式，制备如图5所示的电容器200，为了简洁，在此不再赘述。
因此，在本申请实施例提供的电容器的制作方法中，通过在半导体衬底和导电层中分别制作沟槽式电容器，可以重复使用制作单个电容的工艺，降低多层导电层对准精度要求，能够在不增加工艺难度的情况下进一步提高电容器的容值密度。
下面结合一个具体地实施例对本申请的电容器的制作方法作进一步说明。为了便于理解，在该实施例中制作如图2所示的电容器。当然，利用该实施例中的电容器的制作方法还可以制作如图3、图4、图5和图12所示的电容器，只是在叠层结构、半导体衬底的设置等部分有所区别，为了简洁，在此不再赘述。
步骤一：选取半导体衬底。优选地，该半导体衬底为硅晶圆，包括单晶硅、多晶硅、不定形硅；也可以使用别的半导体晶圆，例如SiC、GaN、GaAs等III-V族元素的化合物半导体晶圆；还可以包含氧化层、键合层，例如绝缘衬底上的硅(Silicon-On-Insulator，SOI)晶圆。
步骤二：利用光刻和深反应离子刻蚀工艺，在半导体衬底上制作第一沟槽阵列。沟槽包括孔(Via)，槽(Trench)，柱(Pillar)，墙(Wall)。
步骤三：在第一沟槽阵列的表面设置第一电容，包括第一极板层、第一电介质层和第二极板层。其中，第一电介质层将第一极板层和第二极板层电隔离。
首先，在第一沟槽阵列表面设置第一极板层。有多种具体的实现方式：可以在第一沟槽阵列的表面进行掺杂，形成p++型或n++型的低电阻率导电区。或者，在第一沟槽阵列的表面沉积低电阻率导电材料，例如用ALD工艺沉积TiN和/或TaN和/或Pt等金属，或者用CVD工艺，沉积重掺杂多晶硅、金属钨、碳材料。此外，还也可以在步骤一直接选取重掺杂半导体衬底，或者先在半导体衬底形成重掺杂导电区再进行步骤二的光刻和刻蚀，则此步骤三可以省略。
接着，在第一极板层上设置第一电介质层。
最后，在第一电介质层上沉积第二极板层。需要注意的是，第二极板层将第一沟槽阵列填满，并在半导体衬底上表面形成一定厚度(介于10纳米和20微米之间)的膜层。
步骤四：利用光刻和深反应离子刻蚀工艺，在第二极板层上制作第二沟槽阵列。该第二沟槽阵列的深度小于在半导体衬底表面的第二极板层的厚度。
步骤五：在第二沟槽阵列的表面设置第二电容，包括第二极板层，第二电介质层和第三极板层。
需要注意的是，该第一、第二电介质层可以是硅的氧化物，硅的氮化物，硅的氮氧化物，金属的氧化物，金属的氮化物，金属的氮氧化物。例如二氧化硅，氮化硅，SiON，或者高介电常数材料，包括Al2O3，HfO2，ZrO2，TiO2，Y2O3，La2O3，HfSiO4，LaAlO3，SrTiO3，LaLuO3等。电介质层可以是一层或包含多个叠层，可以是一种材料或多种材料的组合。
优选地，该第二、第三极板层是CVD工艺沉积的重掺杂多晶硅；也可以是低电阻率导电材料和其余材料的叠层组合。低电阻率导电材料包括碳材料，或者是铝(Al)、钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、铂(Pt)、钌(Ru)、铱(Ir)、铑(Rh)等各类金属，也可以是氮化钛、氮化钽等低电阻率的化合物。沉积方法包括ALD、CVD、物理气相沉积(PVD)、电镀等。
步骤六：制作互联结构和电极，将第一电容和第二电容并联。其中，至 少一个电极电连接第一和第三极板层，至少一个电极电连接第二极板层。
需要说明的是，互联结构包含至少一层绝缘材料作为层间介质层(ILD)。在某些情况，沉积的绝缘材料还可以作为刻蚀停止层，或者用于制作台阶边缘处的边墙(spacer)，用于加强相邻极板层之间的电绝缘。该绝缘材料可以是CVD工艺沉积的氧化硅、氮化硅、含硅玻璃(USG、BSG、PSG、BPSG)；还可以是ALD沉积的氧化铝；或者是喷涂、旋涂的SOG、Polyimide等。
本领域普通技术人员可以意识到，以上结合附图详细描述了本申请的优选实施方式，但是，本申请并不限于上述实施方式中的具体细节，在本申请的技术构思范围内，可以对本申请的技术方案进行多种简单变型，这些简单变型均属于本申请的保护范围。
另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合，为了避免不必要的重复，本申请对各种可能的组合方式不再另行说明。
此外，本申请的各种不同的实施方式之间也可以进行任意组合，只要其不违背本申请的思想，其同样应当视为本申请所申请的内容。

Claims (49)

  1. 一种电容器，其特征在于，所述电容器包括：
    半导体衬底，包括至少一个衬底沟槽组，所述衬底沟槽组自所述半导体衬底的上表面向下进入所述半导体衬底；
    至少一个叠层结构，每个叠层结构包括n层导电层和m层电介质层，所述n层导电层中的第一层导电层设置于所述半导体衬底上方和所述衬底沟槽组内，所述n层导电层中的第i层导电层形成有第i导电层沟槽组，所述n层导电层中的第i+1层导电层设置于所述第i层导电层的上方和所述第i导电层沟槽组内，所述n层导电层和所述m层电介质层形成导电层与电介质层彼此相邻的结构，m、n、i为正整数，且n≥2，1≤i≤n-1；
    至少一个第一外接电极，所述第一外接电极电连接至所述n层导电层中的一部分导电层；
    至少一个第二外接电极，所述第二外接电极电连接至所述n层导电层中的另一部分导电层，所述一部分导电层中的每层导电层在所述叠层结构中相邻的导电层包括有所述另一部分导电层中的至少一个导电层。
  2. 根据权利要求1所述的电容器，其特征在于，所述第i层导电层包括膜层部分和沟槽部分，所述第i导电层沟槽组设置于所述第i层导电层的所述膜层部分且未进入所述第i层导电层的所述沟槽部分。
  3. 根据权利要求2所述的电容器，其特征在于，所述第一层导电层的所述膜层部分的厚度范围为10nm～20μm。
  4. 根据权利要求2或3所述的电容器，其特征在于，所述n层导电层中不同导电层所包括的导电层沟槽的数量和/或尺寸相同。
  5. 根据权利要求2或3所述的电容器，其特征在于，所述n层导电层中不同导电层所包括的导电层沟槽的数量和/或尺寸不同。
  6. 根据权利要求2至5中任一项所述的电容器，其特征在于，所述衬底沟槽组所包括的多个衬底沟槽呈阵列分布，和/或，所述第i导电层沟槽组所包括的多个导电层沟槽呈阵列分布。
  7. 根据权利要求2至6中任一项所述的电容器，其特征在于，所述衬底沟槽组所包括的多个衬底沟槽的尺寸小于第一阈值，和/或，所述第i导电层沟槽组所包括的多个导电层沟槽的尺寸小于第二阈值。
  8. 根据权利要求7所述的电容器，其特征在于，所述第一阈值等于所 述第二阈值。
  9. 根据权利要求2至8中任一项所述的电容器，其特征在于，所述每个叠层结构包括第一层导电层、第二层导电层、第一层电介质层和第二层电介质层；其中，
    所述第一层电介质层设置于所述半导体衬底与所述第一层导电层之间，所述第二层电介质层设置于所述第一层导电层与所述第二层导电层之间；
    所述第一层导电层包括所述膜层部分和所述沟槽部分，所述第一层导电层形成有第一导电层沟槽组，所述第一导电层沟槽组设置于所述第一层导电层的所述膜层部分且未进入所述第一层导电层的所述沟槽部分，所述第二层导电层设置于所述第一层导电层的上方和所述第一导电层沟槽组内。
  10. 根据权利要求2至8中任一项所述的电容器，其特征在于，所述每个叠层结构包括第一层导电层、第二层导电层、第三层导电层、第一层电介质层、第二层电介质层和第三层电介质层；其中，
    所述第一层电介质层设置于所述半导体衬底与所述第一层导电层之间，所述第二层电介质层设置于所述第一层导电层与所述第二层导电层之间，所述第三层电介质层设置于所述第二层导电层与所述第三层导电层之间；
    所述第一层导电层包括所述膜层部分和所述沟槽部分，所述第一层导电层形成有第一导电层沟槽组，所述第一导电层沟槽组设置于所述第一层导电层的所述膜层部分且未进入所述第一层导电层的所述沟槽部分，所述第二层导电层设置于所述第一层导电层的上方和所述第一导电层沟槽组内；
    所述第二层导电层包括膜层部分和沟槽部分，所述第二层导电层形成有第二导电层沟槽组，所述第二导电层沟槽组设置于所述第二层导电层的膜层部分且未进入所述第二层导电层的沟槽部分，所述第三层导电层设置于所述第二层导电层的上方和所述第二导电层沟槽组内。
  11. 根据权利要求1所述的电容器，其特征在于，所述第i层导电层包括膜层部分和沟槽部分，所述第i导电层沟槽组设置于所述第i层导电层的所述膜层部分和所述沟槽部分。
  12. 根据权利要求11所述的电容器，其特征在于，所述衬底沟槽组包括至少一个第一衬底沟槽，所述n层导电层中的第二层导电层也设置于所述第一衬底沟槽内。
  13. 根据权利要求12所述的电容器，其特征在于，所述第一衬底沟槽 的尺寸大于第三阈值。
  14. 根据权利要求12或13所述的电容器，其特征在于，所述衬底沟槽组还包括设置于所述第一衬底沟槽的周围的至少一个第二衬底沟槽，所述n层导电层中仅所述第一层导电层设置于所述第二衬底沟槽内。
  15. 根据权利要求14所述的电容器，其特征在于，所述第二衬底沟槽的尺寸小于所述第一衬底沟槽的尺寸，和/或，所述第二衬底沟槽的深度小于所述第一衬底沟槽的深度。
  16. 根据权利要求11至15中任一项所述的电容器，其特征在于，所述每个叠层结构包括第一层导电层、第二层导电层、第一层电介质层和第二层电介质层；其中，
    所述第一层电介质层设置于所述半导体衬底与所述第一层导电层之间，所述第二层电介质层设置于所述第一层导电层与所述第二层导电层之间；
    所述第一层导电层包括所述膜层部分和所述沟槽部分，所述第一层导电层形成有第一导电层沟槽组，所述第一导电层沟槽组设置于所述第一层导电层的所述膜层部分和所述第一层导电层的所述沟槽部分，所述第二层导电层设置于所述第一层导电层的上方和所述第一导电层沟槽组内。
  17. 根据权利要求1至16中任一项所述的电容器，其特征在于，所述叠层结构中设置有台阶结构，所述台阶结构上设置有由绝缘材料形成的刻蚀停止层，或者，所述台阶结构边缘处设置有由绝缘材料形成的边墙。
  18. 根据权利要求1至17中任一项所述的电容器，其特征在于，所述半导体衬底由电阻率小于阈值的材料形成，或者，所述半导体衬底的表面形成有重掺杂的电阻率小于阈值的导电层或者导电区域。
  19. 根据权利要求18所述的电容器，其特征在于，
    所述叠层结构中距离所述半导体衬底最近的导电层电连接所述第一外接电极，所述半导体衬底电连接所述第二外接电极；或者
    所述叠层结构中距离所述半导体衬底最近的导电层电连接所述第二外接电极，所述半导体衬底电连接所述第一外接电极。
  20. 根据权利要求1至19中任一项所述的电容器，其特征在于，所述电容器还包括：电极层，设置于所述叠层结构的上方，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。
  21. 根据权利要求1至20中任一项所述的电容器，其特征在于，所述第一外接电极和/或所述第二外接电极通过互联结构电连接至所述n层导电层中的导电层。
  22. 根据权利要求21所述的电容器，其特征在于，所述互联结构包括至少一层绝缘层和导电通孔结构，所述导电通孔结构贯穿所述至少一层绝缘层，以至电连接所述n层导电层中的导电层。
  23. 根据权利要求1至22中任一项所述的电容器，其特征在于，所述第一外接电极电连接至所述n层导电层中的所有奇数层导电层，所述第二外接电极电连接至所述n层导电层中的所有偶数层导电层。
  24. 根据权利要求1至23中任一项所述的电容器，其特征在于，所述至少一个叠层结构中不同叠层结构共用同一个所述第一外接电极，和/或，不同叠层结构共用同一个所述第二外接电极。
  25. 根据权利要求1至24中任一项所述的电容器，其特征在于，所述导电层包括以下中的至少一层：
    重掺杂多晶硅层，金属硅化物层，碳层，导电聚合物层，铝层，铜层，钨层，钛层，钽层，铂层，镍层，钌层，铱层，铑层，氮化钽层，氮化钛层，氮化铝钛层，氮化硅钽层，氮化碳钽层。
  26. 根据权利要求1至25中任一项所述的电容器，其特征在于，所述电介质层包括以下中的至少一层：
    硅的氧化物层，硅的氮化物层，硅的氮氧化物层，金属的氧化物层，金属的氮化物层，金属的氮氧化物层。
  27. 一种电容器的制作方法，其特征在于，包括：
    在半导体衬底上制备至少一个衬底沟槽组，所述衬底沟槽组自所述半导体衬底的上表面向下进入所述半导体衬底；
    制备至少一个叠层结构，每个叠层结构包括n层导电层和m层电介质层，所述n层导电层中的第一层导电层设置于所述半导体衬底上方和所述衬底沟槽组内，所述n层导电层中的第i层导电层形成有第i导电层沟槽组，所述n层导电层中的第i+1层导电层设置于所述第i层导电层的上方和所述第i导电层沟槽组内，所述n层导电层和所述m层电介质层形成导电层与电介质层彼此相邻的结构，m、n、i为正整数，且n≥2，1≤i≤n-1；
    制备至少一个第一外接电极和至少一个第二外接电极，其中，所述第一 外接电极电连接至所述n层导电层中的一部分导电层，所述第二外接电极电连接至所述n层导电层中的另一部分导电层，所述一部分导电层中的每层导电层在所述叠层结构中相邻的导电层包括有所述另一部分导电层中的至少一个导电层。
  28. 根据权利要求27所述的方法，其特征在于，所述第i层导电层包括膜层部分和沟槽部分，所述第i导电层沟槽组设置于所述第i层导电层的所述膜层部分且未进入所述第i层导电层的所述沟槽部分。
  29. 根据权利要求28所述的方法，其特征在于，所述第一层导电层的所述膜层部分的厚度范围为10nm～20μm。
  30. 根据权利要求28或29所述的方法，其特征在于，所述n层导电层中不同导电层所包括的导电层沟槽的数量和/或尺寸相同。
  31. 根据权利要求28或29所述的方法，其特征在于，所述n层导电层中不同导电层所包括的导电层沟槽的数量和/或尺寸不同。
  32. 根据权利要求28至31中任一项所述的方法，其特征在于，所述衬底沟槽组所包括的多个衬底沟槽呈阵列分布，和/或，所述第i导电层沟槽组所包括的多个导电层沟槽呈阵列分布。
  33. 根据权利要求28至32中任一项所述的方法，其特征在于，所述衬底沟槽组所包括的多个衬底沟槽的尺寸小于第一阈值，和/或，所述第i导电层沟槽组所包括的多个导电层沟槽的尺寸小于第二阈值。
  34. 根据权利要求33所述的方法，其特征在于，所述第一阈值等于所述第二阈值。
  35. 根据权利要求28至34中任一项所述的方法，其特征在于，所述叠层结构包括第一层电介质层、第一层导电层、第二层电介质层、第二层导电层；
    所述制备叠层结构，包括：
    在所述半导体衬底上表面和所述衬底沟槽组内表面沉积第一层电介质层；
    在所述第一层电介质层的上表面和内表面沉积所述第一层导电层；
    对所述第一层导电层进行刻蚀处理，以在所述第一层导电层中形成第一导电层沟槽组，所述第一导电层沟槽组设置于所述第一层导电层的所述膜层部分且未进入所述第一层导电层的所述沟槽部分；
    在所述第一层导电层的上表面和所述第一导电层沟槽组内表面沉积所述第二电介质层；
    在所述第二层电介质层的上表面和内表面沉积所述第二层导电层。
  36. 根据权利要求27所述的方法，其特征在于，所述第i层导电层包括膜层部分和沟槽部分，所述第i导电层沟槽组设置于所述第i层导电层的所述膜层部分和所述沟槽部分。
  37. 根据权利要求36所述的方法，其特征在于，所述衬底沟槽组包括至少一个第一衬底沟槽，所述n层导电层中的第二层导电层也设置于所述第一衬底沟槽内。
  38. 根据权利要求37所述的方法，其特征在于，所述第一衬底沟槽的尺寸大于第三阈值。
  39. 根据权利要求37或38所述的方法，其特征在于，所述衬底沟槽组还包括设置于所述第一衬底沟槽的周围的至少一个第二衬底沟槽，所述n层导电层中仅所述第一层导电层设置于所述第二衬底沟槽内。
  40. 根据权利要求39所述的方法，其特征在于，所述第二衬底沟槽的尺寸小于所述第一衬底沟槽的尺寸，和/或，所述第二衬底沟槽的深度小于所述第一衬底沟槽的深度。
  41. 根据权利要求36至40中任一项所述的方法，其特征在于，所述叠层结构包括第一层电介质层、第一层导电层、第二层电介质层、第二层导电层；
    所述制备叠层结构，包括：
    在所述半导体衬底上表面和所述衬底沟槽组内表面沉积第一层电介质层；
    在所述第一层电介质层的上表面和内表面沉积所述第一层导电层；
    对所述第一层导电层进行刻蚀处理，以在所述第一层导电层中形成第一导电层沟槽组，所述第一导电层沟槽组设置于所述第一层导电层的所述膜层部分和所述沟槽部分；
    在所述第一层导电层的上表面和所述第一导电层沟槽组内表面沉积所述第二电介质层；
    在所述第二层电介质层的上表面和内表面沉积所述第二层导电层。
  42. 根据权利要求27至41中任一项所述的方法，其特征在于，所述叠 层结构中设置有台阶结构，所述台阶结构上设置有由绝缘材料形成的刻蚀停止层，或者，所述台阶结构边缘处设置有由绝缘材料形成的边墙。
  43. 根据权利要求27至42中任一项所述的方法，其特征在于，所述半导体衬底由电阻率小于阈值的材料形成，或者，所述半导体衬底的表面形成有重掺杂的电阻率小于阈值的导电层或者导电区域。
  44. 根据权利要求43所述的方法，其特征在于，
    所述叠层结构中距离所述半导体衬底最近的导电层电连接所述第一外接电极，所述半导体衬底电连接所述第二外接电极；或者
    所述叠层结构中距离所述半导体衬底最近的导电层电连接所述第二外接电极，所述半导体衬底电连接所述第一外接电极。
  45. 根据权利要求27至44中任一项所述的方法，其特征在于，所述制备至少一个第一外接电极和至少一个第二外接电极，包括：
    在所述叠层结构上方制备电极层，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。
  46. 根据权利要求27至45中任一项所述的方法，其特征在于，所述方法还包括：
    制备互联结构，以使所述第一外接电极和/或所述第二外接电极通过所述互联结构电连接至所述n层导电层中的导电层。
  47. 根据权利要求46所述的方法，其特征在于，所述互联结构包括至少一层绝缘层和导电通孔结构，所述导电通孔结构贯穿所述至少一层绝缘层，以电连接至所述n层导电层中的导电层。
  48. 根据权利要求27至47中任一项所述的方法，其特征在于，所述第一外接电极电连接至所述n层导电层中的所有奇数层导电层，所述第二外接电极电连接至所述n层导电层中的所有偶数层导电层。
  49. 根据权利要求27至48中任一项所述的方法，其特征在于，所述至少一个叠层结构中不同叠层结构共用同一个所述第一外接电极，和/或，不同叠层结构共用同一个所述第二外接电极。
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